CHL8112_15 [INFINEON]
DIGITAL MULTI-PHASE BUCK CONTROLLER;
| 型号： | CHL8112_15 |
| 厂家： | 
Infineon |
| 描述： | DIGITAL MULTI-PHASE BUCK CONTROLLER |
| 文件： | 总2页 (文件大小：102K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRODUCT BRIEF
PRELIMINARY
CHL8112A/B
DIGITAL MULTI-PHASE BUCK CONTROLLER
The I2C/PMBus interface can communicate with up to 16
CHL8112A/B based VR loops. Device configuration and
fault parameters are easily defined using the CHiL Intuitive
Power Designer (IPD) GUI and stored in on-chip NVM.
FEATURES
5-phase dual output PWM Controller
Phases are flexibly assigned between Loops 1 & 2
AMD® SVI/G34 & Memory MPoL modes
The CHL8112A/B provides extensive OVP, UVP, OCP and
OTP fault protection and includes thermistor based
temperature sensing with VRHOT signal.
Dual OCP support for I-spike enhanced AMD CPUs
SMB_Alert Pin for Servers
PMBus Address pin or Variable Gate Drive (CHL8112A)
2nd Temperature Sense (CHL8112B)
The CHL8112A/B also includes numerous features like
register diagnostics for fast design cycles and platform
differentiation, truly simplifying VRD design and enabling
fastest time-to-market with its “set-and-forget” methodology.
Overclocking & Gaming Mode with Vmax setting
Switching frequency from 200kHz to 1.2MHz per phase
CHiL Efficiency Shaping Features including Variable
Gate Drive (CHL8112A only), Dynamic Phase Control
Programmable 1-phase or 2-phase for Light Loads and
Active Diode Emulation for Very Light Loads
40
39
38
37
36
35
34
33
32
31
1
2
30
29
28
27
26
25
24
23
22
21
RCSP_L2
RCSM_L2
VCC
RCSP
RCSM
VCC
CHiL Adaptive Transient Algorithm (ATA) on both loops
minimizes output bulk capacitors and system cost
Designed for use with coupled inductors
3
Auto-Phase Detection with auto-compensation
Per-Loop Fault Protection: OVP, UVP, OCP, OTP, CFP
4
VSEN_L2
VRTN_L2
PWM5
VSEN
VRTN
RRES
TSEN
V18A
CHL8112A/B
5
I2C/SMBus/PMBus system interface for telemetry of
Temperature, Voltage, Current & Power for both loops
40 Pin 6x6 QFN
Top View
6
Non-Volatile Memory (NVM) for custom configuration
Compatible with CHiL ATL and 3.3V tri-state Drivers
+3.3V supply voltage; 0ºC to 85ºC ambient operation
Pb-Free, RoHS, 6x6 40 pin QFN package
7
PWM4
PWM3
8
VR_READY1
/
PWM2
9
PWRGD2
Notes
1 Pin definition in MPoL mode
2 Pin definition in AMD mode
41 GND
VR_READY_L21
PWM1
10
/ PWROK2
DESCRIPTION
11
12
13
14
15
16
17
18
19
20
The CHL8112A/B are dual-loop digital multi-phase buck
controllers that drive up to 5 phases. The CHL8112A/B is
fully AMD® SVI compliant on both loops and provides a Vtt
tracking function for DDR memory.
NVM storage saves pins and enables a small package size.
The CHL8112A/B includes the CHiL Efficiency Shaping
Technology to deliver exceptional efficiency at minimum
cost across the entire load range. CHiL Variable Gate Drive
optimizes the MOSFET gate drive voltage as a function of
real-time load current. CHiL Dynamic Phase Control
adds/drops active phases based upon load current. The
CHL8112A/B can be configured to enter 1-phase operation
and active diode emulation mode automatically or by
command.
Figure 1. CHL8112A & CHL8112B Packages
APPLICATIONS
CHiL’s unique Adaptive Transient Algorithm (ATA), based
on proprietary non-linear digital PWM algorithms, minimizes
output bulk capacitors. In addition, a coupled inductor mode,
with phases added/dropped in pairs, enables further
improvement in transient response and form factor.
AMD® SVI based systems
DDR Memory with Vtt tracking
Overclocked & Gaming platforms
Trademarks and registered trademarks are the property of the respective
owners.
One Highwood Drive, Tewksbury, MA 01876
Tel: +1(978)-640-0011
www.chilsemi.com
© 2010 CHiL Semiconductor Corp. All rights reserved
Page 1 of 2
PB0012 Rev. 0.04, August 25, 2010
CHL8112A/B
PRODUCT BRIEF
DIGITAL MULTI-PHASE BUCK CONTROLLER
TYPICAL APPLICATIONS BLOCK DIAGRAMS
12V
CHL8510
HiGate
Switch
Boot
Vcc
HVCC
LVCC
PWM
GND
1
V_CPU_L1
RCSP
Rseries
V_VGD
CCS
L
O
A
D
RTh
RCS
LoGate
21
Rseries
PWM1
ISEN1
IRTN1
2
39
40
RCSM
VCC
3
28
+3.3V
12V
CHL8510
HiGate
Boot
Vcc
4
HVCC
LVCC
PWM
GND
Switch
V_VGD
VSEN
VRTN
RRES
5
6
LoGate
22
37
38
PWM 2
ISEN2
IRTN2
7
8
TSEN
12V
RTh2
CHL8510
HiGate
Switch
Boot
Vcc
HVCC
LVCC
PWM
GND
CHL8112A
V_VGD
V18A
LoGate
23
35
36
PWM3
ISEN3
IRTN3
9
VR_RDY_L11/PWRGD2
VR_RDY_L21/PWROK2
10
+12V
12V
RVIN_1
CHL8510
HiGate
11
Boot
Vcc
VINSEN
HVCC
LVCC
Switch
RVIN_2
V_VGD
PWM
GND
LoGate
24
33
34
PWM4
ISEN4
IRTN4
17
18
19
NC1/VFIXEN2
NC1/SVD2
NC1/SVC2
VR_HOT#1/
15
16
VRHOT_ICRIT#2
12V
From
System
EN
CHL8510
HiGate
Switch
Boot
Vcc
HVCC
LVCC
V_CPU_L2
V_VGD
+3.3V
L
O
A
D
PWM
GND
LoGate
25
31
32
PWM5
ISEN5
IRTN5
17
18
19
SMB_ALERT#
SMB_DIO
SMB_CLK
RCSP_L2
30
Rseries
CCS
RTh
RCS
12V
Rseries
29
CHL8510
HiGate
RCSM_L2
Boot
Vcc
HVCC
LVCC
PWM
GND
Switch
20
VAR_GATE_
PM_ADDR
27
26
V_VGD
LoGate
VSEN_L2
VRTN_L2
Optional Variable
Gate Drive Circuit
Notes
1 Pin definition in MPoL mode
2 Pin definition in AMD mode
GND
ORDERING INFORMATION
CHL8112 -
Package
QFN
QFN
QFN
QFN
Tape & Reel Qty
Part Number
3000
3000
3000
3000
CHL8112A-00CRT1
CHL8112A-xxCRT2
CHL8112B-00CRT1
CHL8112B-xxCRT2
T: Tape & Reel
Package type
R : QFN
Notes
Operating Temperature
C: Commercial Standard
1. For unprogrammed/default parts, use configuration
file 00. Unprogrammed parts will not start up until
programmed in order to insure a safe power up.
2. -xx indicates a customer specific configuration file
xx: Configuration file
Part
A: CHL8112A
B: CHL8112B
Page 2 of 2
PB0012
Rev. 0.04, August 25, 2010
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