C167SR [INFINEON]
16-Bit CMOS Single-Chip Microcontroller; 16位CMOS单芯片微控制器
| 型号： | C167SR |
| 厂家： | 
Infineon |
| 描述： | 16-Bit CMOS Single-Chip Microcontroller |
| 文件： | 总66页 (文件大小：677K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Microcomputer Components
16-Bit CMOS Single-Chip Microcontroller
C167SR
Data Sheet 06.95 Advance Information
Edition 06.95
Ausgabe 06.95
Published by Siemens AG,
Bereich Halbleiter, Marketing-
Kommunikation, Balanstraße 73,
81541 München
Herausgegeben von Siemens AG,
Bereich Halbleiter, Marketing-
Kommunikation, Balanstraße 73,
81541 München
© Siemens AG 1995.
All Rights Reserved.
© Siemens AG 1995.
Alle Rechte vorbehalten.
Attention please!
Wichtige Hinweise!
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for components, not for applications, pro-
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Terms of delivery and rights to change design
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Packing
Verpackung
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1
1
Critical components of the Semiconductor
Kritische Bauelemente des Bereichs Halblei-
Group of Siemens AG, may only be used in
life-support devices or systems with the ex-
press written approval of the Semiconductor
Group of Siemens AG.
ter der Siemens AG dürfen nur mit ausdrückli-
cher schriftlicher Genehmigung des Bereichs
Halbleiter der Siemens AG in lebenserhalten-
2
2
den Geräten oder Systemen eingesetzt wer-
den.
1 A critical component is a component used
in a life-support device or system whose
failure can reasonably be expected to
cause the failure of that life-support de-
vice or system, or to affect its safety or ef-
fectiveness of that device or system.
1 Ein kritisches Bauelement ist ein in einem
lebenserhaltenden Gerät oder System ein-
gesetztes Bauelement, bei dessen Ausfall
berechtigter Grund zur Annahme besteht,
daß das lebenserhaltende Gerät oder Sy-
stem ausfällt bzw. dessen Sicherheit oder
Wirksamkeit beeinträchtigt wird.
2 Life support devices or systems are in-
tended (a) to be implanted in the human
body, or (b) to support and/or maintain
and sustain human life. If they fail, it is
reasonable to assume that the health of
the user may be endangered.
2 Lebenserhaltende Geräte und Systeme
sind (a) zur chirurgischen Einpflanzung in
den menschlichen Körper gedacht, oder
(b) unterstützen bzw. erhalten das
menschliche Leben. Sollten sie ausfallen,
besteht berechtigter Grund zur Annahme,
daß die Gesundheit des Anwenders ge-
fährdet werden kann.
C167SR
Revision History:
Original Version: 06.95 (Advance Information)
Previous Releases:
Data Sheet C167 06.94
Page
31
Subjects (changes compared to C167)
Register PICON added
VILS, VIHS, HYS, IOV added.
RRST, IRWH, IRWL, IALEL, IALEH, IP6H, test cond. IOZx changed.
36
36
37
IP6L, ICC, IID changed.
37
ICC, IID typical values added
ADC specification changed.
PLL description added.
External Clock Drive specification changed.
t14, t15, t16, t17, t22, t39, t46 changed.
t47 changed.
39
41...43
44
46
47
52
t14, t15, t16, t17, t20, t21, t22 changed.
t39, t46, t47, t55 changed.
t53 changed to t68.
53
56, 57
58
t36 changed.
61
t63 changed.
C16x-Family of
High-Performance CMOS 16-Bit Microcontrollers
C167SR
Advance Information
C167SR 16-Bit Microcontroller
● High Performance 16-bit CPU with 4-Stage Pipeline
● 100 ns Instruction Cycle Time at 20 MHz CPU Clock
● 500 ns Multiplication (16 × 16 bit), 1 µs Division (32 / 16 bit)
● Enhanced Boolean Bit Manipulation Facilities
● Additional Instructions to Support HLL and Operating Systems
● Register-Based Design with Multiple Variable Register Banks
● Single-Cycle Context Switching Support
● Clock Generation via on-chip PLL or via direct clock input
● Up to 16 MBytes Linear Address Space for Code and Data
● 2 KBytes On-Chip Internal RAM (IRAM)
● 2 KBytes On-Chip Extension RAM (XRAM)
● Programmable External Bus Characteristics for Different Address Ranges
● 8-Bit or 16-Bit External Data Bus
● Multiplexed or Demultiplexed External Address/Data Buses
● Five Programmable Chip-Select Signals
● Hold- and Hold-Acknowledge Bus Arbitration Support
● 1024 Bytes On-Chip Special Function Register Area
● Idle and Power Down Modes
● 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event
Controller (PEC)
● 16-Priority-Level Interrupt System with 56 Sources, Sample-Rate down to 50 ns
● 16-Channel 10-bit A/D Converter with 9.7 µs Conversion Time
● Two 16-Channel Capture/Compare Units
● 4-Channel PWM Unit
● Two Multi-Functional General Purpose Timer Units with 5 Timers
● Two Serial Channels (Synchronous/Asynchronous and High-Speed-Synchronous)
● Programmable Watchdog Timer
● Up to 111 General Purpose I/O Lines, partly with Selectable Input Thresholds and Hysteresis
● Supported by a Wealth of Development Tools like C-Compilers, Macro-Assembler Packages,
Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers,
Programming Boards
● On-Chip Bootstrap Loader
● 144-Pin MQFP Package (EIAJ)
This document describes the SAB-C167SR-LM, the SAF-C167SR-LM and the SAK-C167SR-LM.
For simplicity all versions are referred to by the term C167SR throughout this document.
Semiconductor Group
1
06.95
C167SR
C167SR
Revision History:
Original Version: 06.95 (Advance Information)
Previous Releases:
Data Sheet C167 06.94
Page
31
Subjects (changes compared to C167)
Register PICON added
VILS, VIHS, HYS, IOV added.
RRST, IRWH, IRWL, IALEL, IALEH, IP6H, test cond. IOZx changed.
36
36
37
IP6L, ICC, IID changed.
37
ICC, IID typical values added
ADC specification changed.
PLL description added.
External Clock Drive specification changed.
t14, t15, t16, t17, t22, t39, t46 changed.
t47 changed.
39
41...43
44
46
47
52
t14, t15, t16, t17, t20, t21, t22 changed.
t39, t46, t47, t55 changed.
t53 changed to t68.
53
56, 57
58
t36 changed.
61
t63 changed.
Semiconductor Group
2
C167SR
Introduction
The C167SR is a new derivative of the Siemens C16x Family of full featured single-chip CMOS
microcontrollers. It combines high CPU performance (up to 10 million instructions per second) with
high peripheral functionality and enhanced IO-capabilities. It also provides on-chip high-speed RAM
and clock generation via PLL.
C167SR
Figure 1
Logic Symbol
Ordering Information
Type
Ordering Code
Package
Function
SAB-C167SR-LM Q67121-C952
P-MQFP-144-1
16-bit microcontroller with
2 × 2 KByte RAM
Temperature range 0 to + 70 ˚C
SAF-C167SR-LM Q67121-C953
P-MQFP-144-1
P-MQFP-144-1
16-bit microcontroller with
2 × 2 KByte RAM
Temperature range – 40 to + 85 ˚C
SAK-C167SR-LM
C
16-bit microcontroller with
2 × 2 KByte RAM
Temperature range – 40 to + 125 ˚C
Semiconductor Group
3
C167SR
Pin Configuration
(top view)
C167SR
Figure 2
Semiconductor Group
4
C167SR
Pin Definitions and Functions
Symbol Pin
Input (I)
Function
Number Output (O)
P6.0 -
P6.7
1 -
8
I/O
Port 6 is an 8-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-
impedance state. Port 6 outputs can be configured as push/
pull or open drain drivers.
The following Port 6 pins also serve for alternate functions:
1
...
5
6
7
8
O
...
O
I
O
O
P6.0
...
P6.4
P6.5
P6.6
P6.7
CS0
...
CS4
HOLD
HLDA
BREQ
Chip Select 0 Output
...
Chip Select 4 Output
External Master Hold Request Input
Hold Acknowledge Output
Bus Request Output
P8.0 -
P8.7
9 -
16
I/O
Port 8 is an 8-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-
impedance state. Port 8 outputs can be configured as push/
pull or open drain drivers. The input threshold of Port 8 is
selectable (TTL or special).
The following Port 8 pins also serve for alternate functions:
9
...
16
I/O
...
I/O
P8.0
...
P8.7
CC16IO CAPCOM2: CC16 Cap.-In/Comp.Out
... ...
CC23IO CAPCOM2: CC23 Cap.-In/Comp.Out
P7.0 -
P7.7
19 -
26
I/O
Port 7 is an 8-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-
impedance state. Port 7 outputs can be configured as push/
pull or open drain drivers. The input threshold of Port 7 is
selectable (TTL or special).
The following Port 7 pins also serve for alternate functions:
19
...
O
...
P7.0
...
POUT0
...
PWM Channel 0 Output
...
22
23
...
O
I/O
...
P7.3
P7.4
...
POUT3
PWM Channel 3 Output
CC28IO CAPCOM2: CC28 Cap.-In/Comp.Out
... ...
CC31IO CAPCOM2: CC31 Cap.-In/Comp.Out
26
I/O
P7.7
Semiconductor Group
5
C167SR
Pin Definitions and Functions (cont’d)
Symbol Pin
Input (I)
Function
Number Output (O)
P5.0 -
P5.15
27 - 36
39 - 44
I
I
Port 5 is a 16-bit input-only port with Schmitt-Trigger
characteristics. The pins of Port 5 also serve as the (up to 16)
analog input channels for the A/D converter, where P5.x
equals ANx (Analog input channel x), or they serve as timer
inputs:
39
40
41
42
43
44
I
I
I
I
I
I
P5.10
P5.11
P5.12
P5.13
P5.14
P5.15
T6EUD
T5EUD
T6IN
T5IN
T4EUD
T2EUD
GPT2 Timer T6 Ext.Up/Down Ctrl.Input
GPT2 Timer T5 Ext.Up/Down Ctrl.Input
GPT2 Timer T6 Count Input
GPT2 Timer T5 Count Input
GPT1 Timer T4 Ext.Up/Down Ctrl.Input
GPT1 Timer T2 Ext.Up/Down Ctrl.Input
P2.0 -
P2.15
47 - 54
57 - 64
I/O
Port 2 is a 16-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-
impedance state. Port 2 outputs can be configured as push/
pull or open drain drivers. The input threshold of Port 2 is
selectable (TTL or special).
The following Port 2 pins also serve for alternate functions:
47
...
54
57
I/O
...
I/O
I/O
I
...
I/O
I
P2.0
...
P2.7
P2.8
CC0IO
...
CC7IO
CC8IO
EX0IN
...
CAPCOM: CC0 Cap.-In/Comp.Out
...
CAPCOM: CC7 Cap.-In/Comp.Out
CAPCOM: CC8 Cap.-In/Comp.Out,
Fast External Interrupt 0 Input
...
...
64
...
P2.15
CC15IO CAPCOM: CC15 Cap.-In/Comp.Out,
EX7IN
T7IN
Fast External Interrupt 7 Input
CAPCOM2 Timer T7 Count Input
I
Semiconductor Group
6
C167SR
Pin Definitions and Functions (cont’d)
Symbol Pin Input (I) Function
Number Output (O)
P3.0 -
P3.13,
P3.15
65 - 70, I/O
73 - 80, I/O
Port 3 is a 15-bit (P3.14 is missing) bidirectional I/O port. It is
bit-wise programmable for input or output via direction bits.
For a pin configured as input, the output driver is put into high-
impedance state. Port 3 outputs can be configured as push/
pull or open drain drivers. The input threshold of Port 3 is
selectable (TTL or special).
81
I/O
The following Port 3 pins also serve for alternate functions:
65
66
67
68
69
70
I
O
I
O
I
I
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
T0IN
CAPCOM Timer T0 Count Input
GPT2 Timer T6 Toggle Latch Output
GPT2 Register CAPREL Capture Input
GPT1 Timer T3 Toggle Latch Output
GPT1 Timer T3 Ext.Up/Down Ctrl.Input
GPT1 Timer T4 Input for
T6OUT
CAPIN
T3OUT
T3EUD
T4IN
Count/Gate/Reload/Capture
73
74
I
I
P3.6
P3.7
T3IN
T2IN
GPT1 Timer T3 Count/Gate Input
GPT1 Timer T2 Input for
Count/Gate/Reload/Capture
75
76
77
78
79
I/O
I/O
O
I/O
O
O
I/O
O
P3.8
P3.9
P3.10
P3.11
P3.12
MRST
MTSR
T×D0
R×D0
BHE
SSC Master-Rec./Slave-Transmit I/O
SSC Master-Transmit/Slave-Rec. O/I
ASC0 Clock/Data Output (Asyn./Syn.)
ASC0 Data Input (Asyn.) or I/O (Syn.)
Ext. Memory High Byte Enable Signal,
Ext. Memory High Byte Write Strobe
SSC Master Clock Outp./Slave Cl. Inp.
WRH
SCLK
80
81
P3.13
P3.15
CLKOUT System Clock Output (=CPU Clock)
P4.0 -
P4.7
85 - 92
I/O
Port 4 is an 8-bit bidirectional I/O port. It is bit-wise
programmable for input or output via direction bits. For a pin
configured as input, the output driver is put into high-
impedance state.
In case of an external bus configuration, Port 4 can be used to
output the segment address lines:
85
...
89
...
O
...
O
...
O
P4.0
...
P4.4
..
A16
...
A20
:
Least Significant Segment Addr. Line
...
Least Significant Segment Addr. Line
:
92
P4.7
A23
Most Significant Segment Addr. Line
RD
95
O
External Memory Read Strobe. RD is activated for every
external instruction or data read access.
Semiconductor Group
7
C167SR
Pin Definitions and Functions (cont’d)
Symbol Pin
Input (I)
Function
Number Output (O)
WR/
WRL
96 O
External Memory Write Strobe. In WR-mode this pin is
activated for every external data write access. In WRL-mode
this pin is activated for low byte data write accesses on a 16-
bit bus, and for every data write access on an 8-bit bus. See
WRCFG in register SYSCON for mode selection.
READY 97
I
Ready Input. When the Ready function is enabled, a high
level at this pin during an external memory access will force
the insertion of memory cycle time waitstates until the pin
returns to a low level.
ALE
EA
98
99
O
I
Address Latch Enable Output. Can be used for latching the
address into external memory or an address latch in the
multiplexed bus modes.
External Access Enable pin. A low level at this pin during and
after Reset forces the C167SR to begin instruction execution
out of external memory. A high level forces execution out of
the internal ROM. ROMless versions must have this pin tied
to ‘0’.
PORT0:
P0L.0 -
P0L.7,
P0H.0 - 108,
P0H.7 111-117
I/O
PORT0 consists of the two 8-bit bidirectional I/O ports P0L
and P0H. It is bit-wise programmable for input or output via
direction bits. For a pin configured as input, the output driver
is put into high-impedance state.
In case of an external bus configuration, PORT0 serves as
the address (A) and address/data (AD) bus in multiplexed bus
modes and as the data (D) bus in demultiplexed bus modes.
Demultiplexed bus modes:
100 -
107
Data Path Width:
P0L.0 - P0L.7:
P0H.0- P0H.7:
8-bit
D0 - D7
I/O
16-bit
D0 - D7
D8 - D15
Multiplexed bus modes:
Data Path Width:
P0L.0 - P0L.7:
P0H.0 - P0H.7:
8-bit
AD0 - AD7
A8 - A15
16-bit
AD0 - AD7
AD8 - AD15
Semiconductor Group
8
C167SR
Pin Definitions and Functions (cont’d)
Symbol Pin Input (I) Function
Number Output (O)
PORT1:
P1L.0 -
P1L.7,
P1H.0 - 128 -
P1H.7
I/O
118 -
125
PORT1 consists of the two 8-bit bidirectional I/O ports P1L
and P1H. It is bit-wise programmable for input or output via
direction bits. For a pin configured as input, the output driver
is put into high-impedance state. PORT1 is used as the 16-bit
address bus (A) in demultiplexed bus modes and also after
switching from a demultiplexed bus mode to a multiplexed
bus mode.
135
The following PORT1 pins also serve for alternate functions:
132
133
134
135
I
I
I
I
P1H.4
P1H.5
P1H.6
P1H.7
CC24IO CAPCOM2: CC24 Capture Input
CC25IO CAPCOM2: CC25 Capture Input
CC26IO CAPCOM2: CC26 Capture Input
CC27IO CAPCOM2: CC27 Capture Input
XTAL1
XTAL2
138
I
XTAL1:
Input to the oscillator amplifier and input to the
internal clock generator
Output of the oscillator amplifier circuit.
137
O
XTAL2:
To clock the device from an external source, drive XTAL1,
while leaving XTAL2 unconnected. Minimum and maximum
high/low and rise/fall times specified in the AC Characteristics
must be observed.
RSTIN
140
I
Reset Input with Schmitt-Trigger characteristics. A low level at
this pin for a specified duration while the oscillator is running
resets the C167SR. An internal pullup resistor permits power-
on reset using only a capacitor connected to VSS.
RSTOUT 141
O
I
Internal Reset Indication Output. This pin is set to a low level
when the part is executing either a hardware-, a software- or a
watchdog timer reset. RSTOUT remains low until the EINIT
(end of initialization) instruction is executed.
NMI
142
Non-Maskable Interrupt Input. A high to low transition at this
pin causes the CPU to vector to the NMI trap routine. When
the PWRDN (power down) instruction is executed, the NMI
pin must be low in order to force the C167SR to go into power
down mode. If NMI is high, when PWRDN is executed, the
part will continue to run in normal mode.
If not used, pin NMI should be pulled high externally.
VAREF
VAGND
VPP
37
38
84
–
–
–
Reference voltage for the A/D converter.
Reference ground for the A/D converter.
Flash programming voltage. This pin accepts the
programming voltage for flash versions of the C167SR.
Note: This pin is not connected (NC) on non-flash versions.
Semiconductor Group
9
C167SR
Pin Definitions and Functions (cont’d)
Symbol Pin
Input (I)
Function
Number Output (O)
VCC
17, 46,
56, 72,
82, 93,
109,
–
Digital Supply Voltage:
+ 5 V during normal operation and idle mode.
≥ 2.5 V during power down mode.
126,
136, 144
VSS
18, 45,
55, 71,
83, 94,
110,
–
Digital Ground.
127,
139, 143
Semiconductor Group
10
C167SR
Functional Description
The architecture of the C167SR combines advantages of both RISC and CISC processors and of
advanced peripheral subsystems in a very well-balanced way. The following block diagram gives an
overview of the different on-chip components and of the advanced, high bandwidth internal bus
structure of the C167SR.
Note: All time specifications refer to a CPU clock of 20 MHz
(see definition in the AC Characteristics section).
Figure 3
Block Diagram
Semiconductor Group
11
C167SR
Memory Organization
The memory space of the C167SR is configured in a Von Neumann architecture which means that
code memory, data memory, registers and I/O ports are organized within the same linear address
space which includes 16 MBytes. The entire memory space can be accessed bytewise or wordwise.
Particular portions of the on-chip memory have additionally been made directly bitaddressable.
The C167SR is prepared to incorporate on-chip mask-programmable ROM or Flash Memory for
code or constant data. Currently no ROM is integrated.
2 KBytes of on-chip Internal RAM are provided as a storage for user defined variables, for the
system stack, general purpose register banks and even for code. A register bank can consist of up
to 16 wordwide (R0 to R15) and/or bytewide (RL0, RH0, …, RL7, RH7) so-called General Purpose
Registers (GPRs).
1024 bytes (2 × 512 bytes) of the address space are reserved for the Special Function Register
areas (SFR space and ESFR space). SFRs are wordwide registers which are used for controlling
and monitoring functions of the different on-chip units. Unused SFR addresses are reserved for
future members of the C16x family.
2 KBytes of on-chip Extension RAM (XRAM) are provided to store user data, user stacks or code.
The XRAM is accessed like external memory and therefore cannot be used for the system stack or
for register banks and is not bitadressable. The XRAM allows 16-bit accesses with maximum
speed.
In order to meet the needs of designs where more memory is required than is provided on chip, up
to 16 MBytes of external RAM and/or ROM can be connected to the microcontroller.
External Bus Controller
All of the external memory accesses are performed by a particular on-chip External Bus Controller
(EBC). It can be programmed either to Single Chip Mode when no external memory is required, or
to one of four different external memory access modes, which are as follows:
– 16-/18-/20-/24-bit Addresses, 16-bit Data, Demultiplexed
– 16-/18-/20-/24-bit Addresses, 16-bit Data, Multiplexed
– 16-/18-/20-/24-bit Addresses, 8-bit Data, Multiplexed
– 16-/18-/20-/24-bit Addresses, 8-bit Data, Demultiplexed
In the demultiplexed bus modes, addresses are output on PORT1 and data is input/output on
PORT0. In the multiplexed bus modes both addresses and data use PORT0 for input/output.
Important timing characteristics of the external bus interface (Memory Cycle Time, Memory Tri-
State Time, Length of ALE and Read Write Delay) have been made programmable to allow the user
the adaption of a wide range of different types of memories. In addition, different address ranges
may be accessed with different bus characteristics. Up to 5 external CS signals can be generated
in order to save external glue logic. Access to very slow memories is supported via a particular
‘Ready’ function. A HOLD/HLDA protocol is available for bus arbitration.
For applications which require less than 16 MBytes of external memory space, this address space
can be restricted to 1 MByte, 256 KByte or to 64 KByte. In this case Port 4 outputs four, two or no
address lines at all. It outputs all 8 address lines, if an address space of 16 MBytes is used.
Semiconductor Group
12
C167SR
Central Processing Unit (CPU)
The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit
(ALU) and dedicated SFRs. Additional hardware has been spent for a separate multiply and divide
unit, a bit-mask generator and a barrel shifter.
Based on these hardware provisions, most of the C167SR’s instructions can be executed in just one
machine cycle which requires 100 ns at 20-MHz CPU clock. For example, shift and rotate
instructions are always processed during one machine cycle independent of the number of bits to
be shifted. All multiple-cycle instructions have been optimized so that they can be executed very
fast as well: branches in 2 cycles, a 16 × 16 bit multiplication in 5 cycles and a 32-/16 bit division in
10 cycles. Another pipeline optimization, the so-called ‘Jump Cache’, allows reducing the execution
time of repeatedly performed jumps in a loop from 2 cycles to 1 cycle.
Figure 4
CPU Block Diagram
Semiconductor Group
13
C167SR
The CPU disposes of an actual register context consisting of up to 16 wordwide GPRs which are
physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the
base address of the active register bank to be accessed by the CPU at a time. The number of
register banks is only restricted by the available internal RAM space. For easy parameter passing,
a register bank may overlap others.
A system stack of up to 2048 bytes is provided as a storage for temporary data. The system stack
is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP)
register. Two separate SFRs, STKOV and STKUN, are implicitly compared against the stack
pointer value upon each stack access for the detection of a stack overflow or underflow.
The high performance offered by the hardware implementation of the CPU can efficiently be utilized
by a programmer via the highly efficient C167SR instruction set which includes the following
instruction classes:
– Arithmetic Instructions
– Logical Instructions
– Boolean Bit Manipulation Instructions
– Compare and Loop Control Instructions
– Shift and Rotate Instructions
– Prioritize Instruction
– Data Movement Instructions
– System Stack Instructions
– Jump and Call Instructions
– Return Instructions
– System Control Instructions
– Miscellaneous Instructions
The basic instruction length is either 2 or 4 bytes. Possible operand types are bits, bytes and words.
A variety of direct, indirect or immediate addressing modes are provided to specify the required
operands.
Semiconductor Group
14
C167SR
Interrupt System
With an interrupt response time within a range from just 250 ns to 600 ns (in case of internal
program execution), the C167SR is capable of reacting very fast to the occurence of non-
deterministic events.
The architecture of the C167SR supports several mechanisms for fast and flexible response to
service requests that can be generated from various sources internal or external to the
microcontroller. Any of these interrupt requests can be programmed to being serviced by the
Interrupt Controller or by the Peripheral Event Controller (PEC).
In contrast to a standard interrupt service where the current program execution is suspended and
a branch to the interrupt vector table is performed, just one cycle is ‘stolen’ from the current CPU
activity to perform a PEC service. A PEC service implies a single byte or word data transfer between
any two memory locations with an additional increment of either the PEC source or the destination
pointer. An individual PEC transfer counter is implicity decremented for each PEC service except
when performing in the continuous transfer mode. When this counter reaches zero, a standard
interrupt is performed to the corresponding source related vector location. PEC services are very
well suited, for example, for supporting the transmission or reception of blocks of data. The C167SR
has 8 PEC channels each of which offers such fast interrupt-driven data transfer capabilities.
A separate control register which contains an interrupt request flag, an interrupt enable flag and an
interrupt priority bitfield exists for each of the possible interrupt sources. Via its related register, each
source can be programmed to one of sixteen interrupt priority levels. Once having been accepted
by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For
the standard interrupt processing, each of the possible interrupt sources has a dedicated vector
location.
Fast external interrupt inputs are provided to service external interrupts with high precision
requirements. These fast interrupt inputs feature programmable edge detection (rising edge, falling
edge or both edges).
Software interrupts are supported by means of the ‘TRAP’ instruction in combination with an
individual trap (interrupt) number.
The following table shows all of the possible C167SR interrupt sources and the corresponding
hardware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers:
Note: Three nodes in the table (X-Peripheral nodes) are prepared to accept interrupt requests from
integrated X-Bus peripherals. Nodes, where no X-Peripherals are connected, may be used
to generate software controlled interrupt requests by setting the respective XPnIR bit.
Semiconductor Group
15
C167SR
Source of Interrupt or
PEC Service Request
Request
Flag
Enable
Flag
Interrupt
Vector
Vector
Location
Trap
Number
CAPCOM Register 0
CAPCOM Register 1
CAPCOM Register 2
CAPCOM Register 3
CAPCOM Register 4
CAPCOM Register 5
CAPCOM Register 6
CAPCOM Register 7
CAPCOM Register 8
CAPCOM Register 9
CAPCOM Register 10
CAPCOM Register 11
CAPCOM Register 12
CAPCOM Register 13
CAPCOM Register 14
CAPCOM Register 15
CAPCOM Register 16
CAPCOM Register 17
CAPCOM Register 18
CAPCOM Register 19
CAPCOM Register 20
CAPCOM Register 21
CAPCOM Register 22
CAPCOM Register 23
CAPCOM Register 24
CAPCOM Register 25
CAPCOM Register 26
CAPCOM Register 27
CAPCOM Register 28
CAPCOM Register 29
CAPCOM Register 30
CAPCOM Register 31
CAPCOM Timer 0
CC0IR
CC0IE
CC0INT
CC1INT
CC2INT
CC3INT
CC4INT
CC5INT
CC6INT
CC7INT
CC8INT
CC9INT
CC10INT
CC11INT
CC12INT
CC13INT
CC14INT
CC15INT
CC16INT
CC17INT
CC18INT
CC19INT
CC20INT
CC21INT
CC22INT
CC23INT
CC24INT
CC25INT
CC26INT
CC27INT
CC28INT
CC29INT
CC30INT
CC31INT
T0INT
00’0040
00’0044
00’0048
10
11
12
13
14
15
16
17
18
19
H
H
H
H
H
H
H
H
H
H
H
H
H
CC1IR
CC1IE
CC2IR
CC2IE
CC3IR
CC3IE
00’004C
H
CC4IR
CC4IE
00’0050
00’0054
00’0058
H
CC5IR
CC5IE
H
H
CC6IR
CC6IE
CC7IR
CC7IE
00’005C
H
CC8IR
CC8IE
00’0060
00’0064
00’0068
H
CC9IR
CC9IE
H
H
CC10IR
CC11IR
CC12IR
CC13IR
CC14IR
CC15IR
CC16IR
CC17IR
CC18IR
CC19IR
CC20IR
CC21IR
CC22IR
CC23IR
CC24IR
CC25IR
CC26IR
CC27IR
CC28IR
CC29IR
CC30IR
CC31IR
T0IR
CC10IE
CC11IE
CC12IE
CC13IE
CC14IE
CC15IE
CC16IE
CC17IE
CC18IE
CC19IE
CC20IE
CC21IE
CC22IE
CC23IE
CC24IE
CC25IE
CC26IE
CC27IE
CC28IE
CC29IE
CC30IE
CC31IE
T0IE
1A
1B
H
H
00’006C
H
00’0070
00’0074
00’0078
1C
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
1D
H
H
1E
1F
00’007C
00’00C0
00’00C4
00’00C8
H
H
H
H
30
31
32
33
34
35
36
37
38
39
00’00CC
H
00’00D0
00’00D4
00’00D8
H
H
H
00’00DC
H
00’00E0
00’00E4
00’00E8
H
H
H
3A
3B
H
00’00EC
H
H
00’00E0
3C
H
H
00’0110
00’0114
00’0118
00’0080
44
45
46
20
H
H
H
H
H
H
H
H
Semiconductor Group
16
C167SR
Source of Interrupt or
PEC Service Request
Request
Flag
Enable
Flag
Interrupt
Vector
Vector
Location
Trap
Number
CAPCOM Timer 1
CAPCOM Timer 7
CAPCOM Timer 8
GPT1 Timer 2
T1IR
T7IR
T8IR
T2IR
T3IR
T4IR
T5IR
T6IR
T1IE
T1INT
00’0084
21
H
H
T7IE
T7INT
00’00F4
00’00F8
3D
H
H
H
H
H
H
H
H
H
H
H
H
H
T8IE
T8INT
3E
T2IE
T2INT
00’0088
22
23
24
25
26
27
28
29
GPT1 Timer 3
T3IE
T3INT
00’008C
H
GPT1 Timer 4
T4IE
T4INT
00’0090
00’0094
00’0098
H
GPT2 Timer 5
T5IE
T5INT
H
H
GPT2 Timer 6
T6IE
T6INT
GPT2 CAPREL Register CRIR
A/D Conversion Complete ADCIR
CRIE
CRINT
ADCINT
ADEINT
S0TINT
S0TBINT
S0RINT
S0EINT
SCTINT
SCRINT
SCEINT
PWMINT
XP0INT
XP1INT
XP2INT
XP3INT
00’009C
H
H
H
H
ADCIE
ADEIE
S0TIE
S0TBIE
S0RIE
S0EIE
SCTIE
SCRIE
SCEIE
PWMIE
XP0IE
XP1IE
XP2IE
XP3IE
00’00A0
00’00A4
00’00A8
A/D Overrun Error
ASC0 Transmit
ASC0 Transmit Buffer
ASC0 Receive
ASC0 Error
ADEIR
S0TIR
S0TBIR
S0RIR
S0EIR
SCTIR
SCRIR
SCEIR
PWMIR
XP0IR
XP1IR
XP2IR
XP3IR
2A
H
H
00’011C
47
H
00’00AC
2B
H
H
00’00B0
00’00B4
00’00B8
2C
2D
H
H
H
H
H
H
H
H
H
H
SSC Transmit
H
H
SSC Receive
2E
SSC Error
00’00BC
2F
3F
H
PWM Channel 0...3
X-Peripheral Node
X-Peripheral Node
X-Peripheral Node
PLL Unlock
00’00FC
H
00’0100
00’0104
00’0108
40
41
42
43
H
H
H
00’010C
H
Semiconductor Group
17
C167SR
The C167SR also provides an excellent mechanism to identify and to process exceptions or error
conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware traps cause immediate
non-maskable system reaction which is similar to a standard interrupt service (branching to a
dedicated vector table location). The occurence of a hardware trap is additionally signified by an
individual bit in the trap flag register (TFR). Except when another higher prioritized trap service is in
progress, a hardware trap will interrupt any actual program execution. In turn, hardware trap
services can normally not be interrupted by standard or PEC interrupts.
The following table shows all of the possible exceptions or error conditions that can arise during run-
time:
Exception Condition
Trap
Flag
Trap
Vector
Vector
Location
Trap
Number
Trap
Priority
Reset Functions:
Hardware Reset
Software Reset
Watchdog Timer Overflow
RESET
RESET
RESET
00’0000
00’0000
00’0000
00
00
00
III
III
III
H
H
H
H
H
H
Class A Hardware Traps:
Non-Maskable Interrupt
Stack Overflow
NMI
STKOF
STKUF
NMITRAP 00’0008
STOTRAP 00’0010
STUTRAP 00’0018
02
04
06
II
II
II
H
H
H
H
H
H
Stack Underflow
Class B Hardware Traps:
Undefined Opcode
Protected Instruction
Fault
UNDOPC BTRAP
00’0028
00’0028
0A
0A
I
I
H
H
H
H
PRTFLT
BTRAP
Illegal Word Operand
Access
ILLOPA
BTRAP
00’0028
0A
I
H
H
Illegal Instruction Access
Illegal External Bus
Access
ILLINA
ILLBUS
BTRAP
BTRAP
00’0028
00’0028
0A
0A
I
I
H
H
H
H
Reserved
[2C – 3C ] [0B – 0F ]
H H H H
Software Traps
Any
Any
Current
TRAP Instruction
[00’0000 – [00 – 7F ] CPU
H H H
00’01FC ]
Priority
H
in steps
of 4
H
Semiconductor Group
18
C167SR
Capture/Compare (CAPCOM) Units
The CAPCOM units support generation and control of timing sequences on up to 32 channels with
a maximum resolution of 400 ns (at 20-MHz system clock). The CAPCOM units are typically used
to handle high speed I/O tasks such as pulse and waveform generation, pulse width modulation
(PMW), Digital to Analog (D/A) conversion, software timing, or time recording relative to external
events.
Four 16-bit timers (T0/T1, T7/T8) with reload registers provide two independent time bases for the
capture/compare register array.
The input clock for the timers is programmable to several prescaled values of the internal system
clock, or may be derived from an overflow/underflow of timer T6 in module GPT2. This provides a
wide range of variation for the timer period and resolution and allows precise adjustments to the
application specific requirements. In addition, external count inputs for CAPCOM timers T0 and T7
allow event scheduling for the capture/compare registers relative to external events.
Both of the two capture/compare register arrays contain 16 dual purpose capture/compare
registers, each of which may be individually allocated to either CAPCOM timer T0 or T1 (T7 or T8,
respectively), and programmed for capture or compare function. Each register has one port pin
associated with it which serves as an input pin for triggering the capture function, or as an output pin
(except for CC24...CC27) to indicate the occurence of a compare event.
When a capture/compare register has been selected for capture mode, the current contents of the
allocated timer will be latched (‘capture’d) into the capture/compare register in response to an
external event at the port pin which is associated with this register. In addition, a specific interrupt
request for this capture/compare register is generated. Either a positive, a negative, or both a
positive and a negative external signal transition at the pin can be selected as the triggering event.
The contents of all registers which have been selected for one of the five compare modes are
continuously compared with the contents of the allocated timers. When a match occurs between the
timer value and the value in a capture/compare register, specific actions will be taken based on the
selected compare mode.
Compare Modes
Function
Mode 0
Interrupt-only compare mode;
several compare interrupts per timer period are possible
Mode 1
Mode 2
Mode 3
Pin toggles on each compare match;
several compare events per timer period are possible
Interrupt-only compare mode;
only one compare interrupt per timer period is generated
Pin set ‘1’ on match; pin reset ‘0’ on compare time overflow;
only one compare event per timer period is generated
Double
Register Mode
Two registers operate on one pin; pin toggles on each compare match;
several compare events per timer period are possible.
Semiconductor Group
19
C167SR
*)
*) 12 outputs on CAPCOM2
Figure 5
CAPCOM Unit Block Diagram
Semiconductor Group
20
C167SR
PWM Module
The Pulse Width Modulation Module can generate up to four PWM output signals using edge-
aligned or center-aligned PWM. In addition the PWM module can generate PWM burst signals and
single shot outputs. The frequency range of the PWM signals covers 4.8 Hz to 1 MHz (referred to
a CPU clock of 20 MHz), depending on the resolution of the PWM output signal. The level of the
output signals is selectable and the PWM module can generate interrupt requests.
General Purpose Timer (GPT) Unit
The GPT unit represents a very flexible multifunctional timer/counter structure which may be used
for many different time related tasks such as event timing and counting, pulse width and duty cycle
measurements, pulse generation, or pulse multiplication.
The GPT unit incorporates five 16-bit timers which are organized in two separate modules, GPT1
and GPT2. Each timer in each module may operate independently in a number of different modes,
or may be concatenated with another timer of the same module.
Each of the three timers T2, T3, T4 of module GPT1 can be configured individually for one of three
basic modes of operation, which are Timer, Gated Timer, and Counter Mode. In Timer Mode, the
input clock for a timer is derived from the CPU clock, divided by a programmable prescaler, while
Counter Mode allows a timer to be clocked in reference to external events.
Pulse width or duty cycle measurement is supported in Gated Timer Mode, where the operation of
a timer is controlled by the ‘gate’ level on an external input pin. For these purposes, each timer has
one associated port pin (TxIN) which serves as gate or clock input. The maximum resolution of the
timers in module GPT1 is 400 ns (@ 20-MHz CPU clock).
The count direction (up/down) for each timer is programmable by software or may additionally be
altered dynamically by an external signal on a port pin (TxEUD) to facilitate e. g. position tracking.
Timers T3 and T4 have output toggle latches (TxOTL) which change their state on each timer over-
flow/underflow. The state of these latches may be output on port pins (TxOUT) e. g. for time out
monitoring of external hardware components, or may be used internally to clock timers T2 and T4
for measuring long time periods with high resolution.
In addition to their basic operating modes, timers T2 and T4 may be configured as reload or capture
registers for timer T3. When used as capture or reload registers, timers T2 and T4 are stopped. The
contents of timer T3 is captured into T2 or T4 in response to a signal at their associated input pins
(TxIN). Timer T3 is reloaded with the contents of T2 or T4 triggered either by an external signal or
by a selectable state transition of its toggle latch T3OTL. When both T2 and T4 are configured to
alternately reload T3 on opposite state transitions of T3OTL with the low and high times of a PWM
signal, this signal can be constantly generated without software intervention.
With its maximum resolution of 200 ns (@ 20 MHz), the GPT2 module provides precise event
control and time measurement. It includes two timers (T5, T6) and a capture/reload register
(CAPREL). Both timers can be clocked with an input clock which is derived from the CPU clock via
a programmable prescaler or with external signals. The count direction (up/down) for each timer is
programmable by software or may additionally be altered dynamically by an external signal on a
port pin (TxEUD). Concatenation of the timers is supported via the output toggle latch (T6OTL) of
timer T6, which changes its state on each timer overflow/underflow.
Semiconductor Group
21
C167SR
The state of this latch may be used to clock timer T5, or it may be output on a port pin (T6OUT). The
overflows/underflows of timer T6 can additionally be used to clock the CAPCOM timers T0 or T1,
and to cause a reload from the CAPREL register. The CAPREL register may capture the contents
of timer T5 based on an external signal transition on the corresponding port pin (CAPIN), and timer
T5 may optionally be cleared after the capture procedure. This allows absolute time differences to
be measured or pulse multiplication to be performed without software overhead.
Figure 6
Block Diagram of GPT1
Semiconductor Group
22
C167SR
Figure 7
Block Diagram of GPT2
Watchdog Timer
The Watchdog Timer represents one of the fail-safe mechanisms which have been implemented to
prevent the controller from malfunctioning for longer periods of time.
The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in the time
interval until the EINIT (end of initialization) instruction has been executed. Thus, the chip’s start-up
procedure is always monitored. The software has to be designed to service the Watchdog Timer
before it overflows. If, due to hardware or software related failures, the software fails to do so, the
Watchdog Timer overflows and generates an internal hardware reset and pulls the RSTOUT pin low
in order to allow external hardware components to be reset.
The Watchdog Timer is a 16-bit timer, clocked with the system clock divided either by 2 or by 128.
The high byte of the Watchdog Timer register can be set to a prespecified reload value (stored in
WDTREL) in order to allow further variation of the monitored time interval. Each time it is serviced
by the application software, the high byte of the Watchdog Timer is reloaded. Thus, time intervals
between 25 µs and 420 ms can be monitored (@ 20 MHz). The default Watchdog Timer interval
after reset is 6.55 ms (@ 20 MHz).
Semiconductor Group
23
C167SR
A/D Converter
For analog signal measurement, a 10-bit A/D converter with 16 multiplexed input channels and a
sample and hold circuit has been integrated on-chip. It uses the method of successive
approximation. The sample time (for loading the capacitors) and the conversion time is
programmable and can so be adjusted to the external circuitry.
Overrun error detection/protection is provided for the conversion result register (ADDAT): either an
interrupt request will be generated when the result of a previous conversion has not been read from
the result register at the time the next conversion is complete, or the next conversion is suspended
in such a case until the previous result has been read.
For applications which require less than 16 analog input channels, the remaining channel inputs can
be used as digital input port pins.
The A/D converter of the C167SR supports four different conversion modes. In the standard Single
Channel conversion mode, the analog level on a specified channel is sampled once and converted
to a digital result. In the Single Channel Continuous mode, the analog level on a specified channel
is repeatedly sampled and converted without software intervention. In the Auto Scan mode, the
analog levels on a prespecified number of channels are sequentially sampled and converted. In the
Auto Scan Continuous mode, the number of prespecified channels is repeatedly sampled and
converted. In addition, the conversion of a specific channel can be inserted (injected) into a running
sequence without disturbing this sequence. This is called Channel Injection Mode.
The Peripheral Event Controller (PEC) may be used to automatically store the conversion results
into a table in memory for later evaluation, without requiring the overhead of entering and exiting
interrupt routines for each data transfer.
After each reset and also during normal operation the ADC automatically performs calibration
cycles. This automatic self-calibration constantly adjusts the converter to changing operating
conditions (e.g. temperature) and compensates process variations.
These calibration cycles are part of the conversion cycle, so they do not affect the normal operation
of the A/D converter.
Serial Channels
Serial communication with other microcontrollers, processors, terminals or external peripheral
components is provided by two serial interfaces with different functionality, an Asynchronous/
Synchronous Serial Channel (ASC0) and a High-Speed Synchronous Serial Channel (SSC).
ASC0 is upward compatible with the serial ports of the Siemens SAB 8051x microcontroller family
and support full-duplex asynchronous communication up to 625 KBaud and half-duplex
synchronous communication up to 2.5 Mbaud on the @ 20-MHz system clock.
The SSC allows half duplex synchronous communication up to 5 Mbaud @ 20-MHz system clock.
Two dedicated baud rate generators allow to set up all standard baud rates without oscillator tuning.
For transmission, reception, and erroneous reception 3 separate interrupt vectors are provided for
each serial channel.
Semiconductor Group
24
C167SR
In asynchronous mode, 8- or 9-bit data frames are transmitted or received, preceded by a start bit
and terminated by one or two stop bits. For multiprocessor communication, a mechanism to
distinguish address from data bytes has been included (8-bit data + wake up bit mode).
In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a shift clock
which is generated by the ASC0. The SSC transmits or receives characters of 2...16 bits length
synchronously to a shift clock which can be generated by the SSC (master mode) or by an external
master (slave mode). The SSC can start shifting with the LSB or with the MSB, while the ASC0
always shifts the LSB first.
A loop back option is available for testing purposes.
A number of optional hardware error detection capabilities has been included to increase the
reliability of data transfers. A parity bit can automatically be generated on transmission or be
checked on reception. Framing error detection allows to recognize data frames with missing stop
bits. An overrun error will be generated, if the last character received has not been read out of the
receive buffer register at the time the reception of a new character is complete.
Parallel Ports
The C167SR provides up to 111 I/O lines which are organized into eight input/output ports and one
input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise)
programmable as inputs or outputs via direction registers. The I/O ports are true bidirectional ports
which are switched to high impedance state when configured as inputs. The output drivers of five
I/O ports can be configured (pin by pin) for push/pull operation or open-drain operation via control
registers. During the internal reset, all port pins are configured as inputs.
The input threshold of Port 2, Port 3, Port 7 and Port 8 is selectable (TTL or CMOS like), where the
special CMOS like input threshold reduces noise sensitivity due to the input hysteresis. The input
threshold may be selected individually for each byte of the respective ports.
All port lines have programmable alternate input or output functions associated with them.
PORT0 and PORT1 may be used as address and data lines when accessing external memory,
while Port 4 outputs the additional segment address bits A23/19/17...A16 in systems where
segmentation is enabled to access more than 64 KBytes of memory.
Port 2, Port 8 and Port 7 are associated with the capture inputs or compare outputs of the CAPCOM
units and/or with the outputs of the PWM module.
Port 6 provides optional bus arbitration signals (BREQ, HLDA, HOLD) and chip select signals.
Port 3 includes alternate functions of timers, serial interfaces, the optional bus control signal BHE
and the system clock output (CLKOUT).
Port 5 is used for the analog input channels to the A/D converter or timer control signals.
All port lines that are not used for these alternate functions may be used as general purpose IO
lines.
Semiconductor Group
25
C167SR
Instruction Set Summary
The table below lists the instructions of the C167SR in a condensed way.
The various addressing modes that can be used with a specific instruction, the operation of the
instructions, parameters for conditional execution of instructions, and the opcodes for each
instruction can be found in the “C16x Family Instruction Set Manual”.
This document also provides a detailled description of each instruction.
Instruction Set Summary
Mnemonic
ADD(B)
Description
Bytes
2 / 4
2 / 4
2 / 4
2 / 4
2
Add word (byte) operands
ADDC(B)
SUB(B)
Add word (byte) operands with Carry
Subtract word (byte) operands
SUBC(B)
MUL(U)
DIV(U)
Subtract word (byte) operands with Carry
(Un)Signed multiply direct GPR by direct GPR (16-16-bit)
(Un)Signed divide register MDL by direct GPR (16-/16-bit)
(Un)Signed long divide reg. MD by direct GPR (32-/16-bit)
Complement direct word (byte) GPR
Negate direct word (byte) GPR
2
DIVL(U)
CPL(B)
2
2
NEG(B)
AND(B)
2
Bitwise AND, (word/byte operands)
Bitwise OR, (word/byte operands)
Bitwise XOR, (word/byte operands)
Clear direct bit
2 / 4
2 / 4
2 / 4
2
OR(B)
XOR(B)
BCLR
BSET
Set direct bit
2
BMOV(N)
BAND, BOR, BXOR
BCMP
Move (negated) direct bit to direct bit
AND/OR/XOR direct bit with direct bit
Compare direct bit to direct bit
4
4
4
BFLDH/L
Bitwise modify masked high/low byte of bit-addressable
direct word memory with immediate data
4
CMP(B)
CMPD1/2
CMPI1/2
PRIOR
Compare word (byte) operands
2 / 4
2 / 4
2 / 4
2
Compare word data to GPR and decrement GPR by 1/2
Compare word data to GPR and increment GPR by 1/2
Determine number of shift cycles to normalize direct
word GPR and store result in direct word GPR
SHL / SHR
ROL / ROR
ASHR
Shift left/right direct word GPR
2
2
2
Rotate left/right direct word GPR
Arithmetic (sign bit) shift right direct word GPR
Semiconductor Group
26
C167SR
Instruction Set Summary (cont’d)
Mnemonic
MOV(B)
Description
Bytes
Move word (byte) data
2 / 4
MOVBS
Move byte operand to word operand with sign extension
Move byte operand to word operand. with zero extension
Jump absolute/indirect/relative if condition is met
Jump absolute to a code segment
2 / 4
MOVBZ
2 / 4
4
JMPA, JMPI, JMPR
JMPS
4
J(N)B
Jump relative if direct bit is (not) set
4
JBC
Jump relative and clear bit if direct bit is set
Jump relative and set bit if direct bit is not set
Call absolute/indirect/relative subroutine if condition is met
Call absolute subroutine in any code segment
4
JNBS
4
CALLA, CALLI, CALLR
CALLS
4
4
PCALL
Push direct word register onto system stack and call
absolute subroutine
4
TRAP
Call interrupt service routine via immediate trap number
Push/pop direct word register onto/from system stack
2
2
4
PUSH, POP
SCXT
Push direct word register onto system stack und update
register with word operand
RET
Return from intra-segment subroutine
Return from inter-segment subroutine
2
2
2
RETS
RETP
Return from intra-segment subroutine and pop direct
word register from system stack
RETI
Return from interrupt service subroutine
Software Reset
2
4
4
4
SRST
IDLE
Enter Idle Mode
PWRDN
Enter Power Down Mode
(supposes NMI-pin being low)
SRVWDT
DISWDT
EINIT
Service Watchdog Timer
4
Disable Watchdog Timer
4
Signify End-of-Initialization on RSTOUT-pin
Begin ATOMIC sequence
4
ATOMIC
EXTR
2
Begin EXTended Register sequence
Begin EXTended Page (and Register) sequence
Begin EXTended Segment (and Register) sequence
Null operation
2
EXTP(R)
EXTS(R)
NOP
2 / 4
2 / 4
2
Semiconductor Group
27
C167SR
Special Function Registers Overview
The following table lists all SFRs which are implemented in the C167SR in alphabetical order.
Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the Extended
SFR-Space (ESFRs) are marked with the letter “E” in column “Physical Address”.
An SFR can be specified via its individual mnemonic name. Depending on the selected addressing
mode, an SFR can be accessed via its physical address (using the Data Page Pointers), or via its
short 8-bit address (without using the Data Page Pointers).
Special Function Registers Overview
Name
Physical 8-Bit
Address Address
Description
Reset
Value
ADCIC
b FF98
CC
A/D Converter End of Conversion Interrupt
Control Register
0000
H
H
H
ADCON
ADDAT
ADDAT2
b FFA0
D0
A/D Converter Control Register
A/D Converter Result Register
A/D Converter 2 Result Register
Address Select Register 1
Address Select Register 2
Address Select Register 3
Address Select Register 4
0000
0000
0000
0000
0000
0000
0000
0000
H
H
H
H
H
H
H
H
H
H
FEA0
50
H
H
F0A0 E 50
H
H
ADDRSEL1 FE18
0C
H
H
H
H
H
ADDRSEL2 FE1A
0D
H
ADDRSEL3 FE1C
0E
0F
H
H
H
ADDRSEL4 FE1E
ADEIC
b FF9A
CD
A/D Converter Overrun Error Interrupt Control
Register
H
BUSCON0 b FF0C
86
Bus Configuration Register 0
Bus Configuration Register 1
Bus Configuration Register 2
Bus Configuration Register 3
Bus Configuration Register 4
GPT2 Capture/Reload Register
CAPCOM Register 0
0XX0
H
H
H
BUSCON1 b FF14
BUSCON2 b FF16
BUSCON3 b FF18
8A
8B
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
8C
8D
H
BUSCON4 b FF1A
H
H
CAPREL
CC0
FE4A
25
40
H
H
H
H
FE80
b FF78
FE82
H
CC0IC
CC1
BC
CAPCOM Register 0 Interrupt Control Register
CAPCOM Register 1
H
H
H
41
H
H
CC1IC
CC2
b FF7A
BD
42
CAPCOM Register 1 Interrupt Control Register
CAPCOM Register 2
H
H
FE84
H
CC2IC
b FF7C
BE
CAPCOM Register 2 Interrupt Control Register
H
Semiconductor Group
28
C167SR
Special Function Registers Overview (cont’d)
Name
Physical 8-Bit
Address Address
Description
Reset
Value
CC3
FE86
43
CAPCOM Register 3
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
CC3IC
CC4
b FF7E
BF
CAPCOM Register 3 Interrupt Control Register
CAPCOM Register 4
H
H
H
H
H
H
H
H
H
FE88
44
H
CC4IC
CC5
b FF80
C0
45
CAPCOM Register 4 Interrupt Control Register
CAPCOM Register 5
FE8A
H
H
CC5IC
CC6
b FF82
C1
46
CAPCOM Register 5 Interrupt Control Register
CAPCOM Register 6
H
FE8C
H
H
CC6IC
CC7
b FF84
C2
47
CAPCOM Register 6 Interrupt Control Register
CAPCOM Register 7
H
FE8E
b FF86
H
H
CC7IC
CC8
C3
48
CAPCOM Register 7 Interrupt Control Register
CAPCOM Register 8
H
FE90
H
H
H
CC8IC
CC9
b FF88
FE92
C4
49
CAPCOM Register 8 Interrupt Control Register
CAPCOM Register 9
H
H
CC9IC
CC10
CC10IC
CC11
CC11IC
CC12
CC12IC
CC13
CC13IC
CC14
CC14IC
CC15
CC15IC
CC16
CC16IC
CC17
b FF8A
C5
CAPCOM Register 9 Interrupt Control Register
CAPCOM Register 10
H
H
H
H
FE94
4A
C6
b FF8C
CAPCOM Register 10 Interrupt Control Register 0000
CAPCOM Register 11 0000
CAPCOM Register 11 Interrupt Control Register 0000
CAPCOM Register 12 0000
CAPCOM Register 12 Interrupt Control Register 0000
CAPCOM Register 13 0000
CAPCOM Register 13 Interrupt Control Register 0000
CAPCOM Register 14 0000
CAPCOM Register 14 Interrupt Control Register 0000
CAPCOM Register 15 0000
CAPCOM Register 15 Interrupt Control Register 0000
CAPCOM Register 16 0000
CAPCOM Register 16 Interrupt Control Register 0000
H
H
H
H
FE96
b FF8E
4B
C7
4C
C8
4D
C9
H
H
H
H
H
H
H
H
H
FE98
b FF90
FE9A
H
b FF92
H
FE9C
4E
CA
H
H
H
b FF94
H
H
FE9E
4F
H
b FF96
CB
30
H
H
FE60
H
b F160 E B0
H
H
FE62
31
CAPCOM Register 17
0000
H
H
Semiconductor Group
29
C167SR
Special Function Registers Overview (cont’d)
Name
Physical 8-Bit
Address Address
Description
Reset
Value
CC17IC
CC18
b F162 E B1
CAPCOM Register 17 Interrupt Control Register 0000
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
FE64
32
CAPCOM Register 18
CAPCOM Register 18 Interrupt Control Register 0000
CAPCOM Register 19 0000
CAPCOM Register 19 Interrupt Control Register 0000
CAPCOM Register 20 0000
CAPCOM Register 20 Interrupt Control Register 0000
CAPCOM Register 21 0000
CAPCOM Register 21 Interrupt Control Register 0000
CAPCOM Register 22 0000
CAPCOM Register 22 Interrupt Control Register 0000
CAPCOM Register 23 0000
CAPCOM Register 23 Interrupt Control Register 0000
CAPCOM Register 24 0000
CAPCOM Register 24 Interrupt Control Register 0000
CAPCOM Register 25 0000
CAPCOM Register 25 Interrupt Control Register 0000
CAPCOM Register 26 0000
CAPCOM Register 26 Interrupt Control Register 0000
CAPCOM Register 27 0000
CAPCOM Register 27 Interrupt Control Register 0000
CAPCOM Register 28 0000
CAPCOM Register 28 Interrupt Control Register 0000
CAPCOM Register 29 0000
CAPCOM Register 29 Interrupt Control Register 0000
CAPCOM Register 30 0000
CAPCOM Register 30 Interrupt Control Register 0000
CAPCOM Register 31 0000
CAPCOM Register 31 Interrupt Control Register 0000
0000
H
CC18IC
CC19
b F164 E B2
H
H
H
FE66
33
H
CC19IC
CC20
b F166 E B3
H
H
H
FE68
34
H
CC20IC
CC21
b F168 E B4
H
H
H
FE6A
35
H
CC21IC
CC22
b F16A E B5
H
H
H
FE6C
36
H
CC22IC
CC23
b F16C E B6
H
H
H
FE6E
37
H
CC23IC
CC24
b F16E E B7
H
H
H
FE70
38
H
CC24IC
CC25
b F170 E B8
H
H
H
FE72
39
H
CC25IC
CC26
b F172 E B9
H
H
H
FE74
3A
H
CC26IC
CC27
b F174 E BA
H
H
H
FE76
3B
H
CC27IC
CC28
b F176 E BB
H
H
FE78
3C
H
H
CC28IC
CC29
b F178 E BC
H
H
H
H
H
FE7A
3D
H
CC29IC
CC30
b F184 E C2
H
FE7C
3E
H
CC30IC
CC31
b F18C E C6
H
H
H
FE7E
3F
H
CC31IC
b F194 E CA
H H
Semiconductor Group
30
C167SR
Special Function Registers Overview (cont’d)
Name
Physical 8-Bit
Address Address
Description
Reset
Value
CCM0
CCM1
CCM2
CCM3
CCM4
CCM5
CCM6
CCM7
CP
b FF52
b FF54
b FF56
b FF58
b FF22
b FF24
b FF26
b FF28
A9
CAPCOM Mode Control Register 0
CAPCOM Mode Control Register 1
CAPCOM Mode Control Register 2
CAPCOM Mode Control Register 3
CAPCOM Mode Control Register 4
CAPCOM Mode Control Register 5
CAPCOM Mode Control Register 6
CAPCOM Mode Control Register 7
CPU Context Pointer Register
0000
0000
0000
0000
0000
0000
0000
0000
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
AA
AB
H
H
AC
H
91
92
93
94
08
H
H
H
H
H
FE10
FC00
H
H
CRIC
CSP
b FF6A
B5
GPT2 CAPREL Interrupt Control Register
0000
H
H
H
H
H
H
H
H
H
FE08
04
CPU Code Segment Pointer Register (read only) 0000
H
DP0L
DP0H
DP1L
DP1H
DP2
b F100 E 80
P0L Direction Control Register
00
00
00
00
H
H
H
H
H
b F102 E 81
P0H Direction Control Register
H
b F104 E 82
P1L Direction Control Register
H
b F106 E 83
P1H Direction Control Register
H
b FFC2
b FFC6
E1
Port 2 Direction Control Register
0000
0000
H
H
H
H
H
H
H
H
DP3
E3
E5
E7
E9
Port 3 Direction Control Register
H
DP4
b FFCA
b FFCE
Port 4 Direction Control Register
00
00
00
00
H
H
H
H
H
H
H
H
H
H
H
H
DP6
Port 6 Direction Control Register
DP7
b FFD2
b FFD6
Port 7 Direction Control Register
DP8
EB
Port 8 Direction Control Register
H
DPP0
DPP1
DPP2
DPP3
EXICON
MDC
MDH
MDL
FE00
FE02
FE04
FE06
00
01
02
03
CPU Data Page Pointer 0 Register (10 bits)
CPU Data Page Pointer 1 Register (10 bits)
CPU Data Page Pointer 2 Register (10 bits)
CPU Data Page Pointer 3 Register (10 bits)
External Interrupt Control Register
CPU Multiply Divide Control Register
CPU Multiply Divide Register – High Word
CPU Multiply Divide Register – Low Word
0000
0001
0002
0003
0000
0000
0000
0000
H
H
H
H
H
H
H
H
H
H
H
H
b F1C0 E E0
H
H
H
H
H
b FF0E
87
06
07
H
FE0C
H
H
FE0E
Semiconductor Group
31
C167SR
Special Function Registers Overview (cont’d)
Name
Physical 8-Bit
Address Address
Description
Reset
Value
ODP2
ODP3
ODP6
ODP7
ODP8
ONES
P0L
b F1C2 E E1
Port 2 Open Drain Control Register
Port 3 Open Drain Control Register
Port 6 Open Drain Control Register
Port 7 Open Drain Control Register
Port 8 Open Drain Control Register
Constant Value 1’s Register (read only)
Port 0 Low Register (Lower half of PORT0)
Port 0 High Register (Upper half of PORT0)
Port 1 Low Register (Lower half of PORT1)
Port 1 High Register (Upper half of PORT1)
Port 2 Register
0000
0000
H
H
H
H
H
H
H
b F1C6 E E3
H
b F1CE E E7
00
00
00
H
H
H
H
b F1D2 E E9
H
b F1D6 E EB
H
H
FF1E
8F
FFFF
H
H
H
H
H
H
H
b FF00
b FF02
b FF04
b FF06
80
81
82
83
00
00
00
00
H
H
H
H
H
H
H
H
P0H
P1L
P1H
P2
b FFC0
b FFC4
b FFC8
E0
E2
E4
0000
H
H
H
H
H
H
H
H
P3
Port 3 Register
0000
H
P4
Port 4 Register (8 bits)
00
H
P5
b FFA2
D1
Port 5 Register (read only)
XXXX
H
H
H
H
P6
b FFCC
E6
E8
Port 6 Register (8 bits)
00
00
00
H
H
H
H
P7
b FFD0
b FFD4
Port 7 Register (8 bits)
H
P8
EA
Port 8 Register (8 bits)
H
H
PECC0
PECC1
PECC2
PECC3
PECC4
PECC5
PECC6
PECC7
PICON
PP0
FEC0
FEC2
FEC4
FEC6
FEC8
60
61
62
63
64
65
66
67
PEC Channel 0 Control Register
PEC Channel 1 Control Register
PEC Channel 2 Control Register
PEC Channel 3 Control Register
PEC Channel 4 Control Register
PEC Channel 5 Control Register
PEC Channel 6 Control Register
PEC Channel 7 Control Register
Port Input Threshold Control Register
PWM Module Period Register 0
PWM Module Period Register 1
PWM Module Period Register 2
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
FECA
H
FECC
H
H
FECE
F1C4 E E2
H
H
F038 E 1C
H
H
H
H
PP1
F03A E 1D
H
PP2
F03C E 1E
H
Semiconductor Group
32
C167SR
Special Function Registers Overview (cont’d)
Name
Physical 8-Bit
Address Address
Description
Reset
Value
PP3
PSW
PT0
PT1
PT2
PT3
PW0
PW1
PW2
PW3
F03E E 1F
PWM Module Period Register 3
CPU Program Status Word
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
b FF10
88
H
F030 E 18
PWM Module Up/Down Counter 0
PWM Module Up/Down Counter 1
PWM Module Up/Down Counter 2
PWM Module Up/Down Counter 3
PWM Module Pulse Width Register 0
PWM Module Pulse Width Register 1
PWM Module Pulse Width Register 2
PWM Module Pulse Width Register 3
PWM Module Control Register 0
PWM Module Control Register 1
PWM Module Interrupt Control Register
H
F032 E 19
H
F034 E 1A
H
H
H
H
H
F036 E 1B
H
FE30
FE32
FE34
FE36
18
19
H
H
H
H
H
H
1A
H
H
H
H
1B
PWMCON0 b FF30
PWMCON1 b FF32
98
99
PWMIC
RP0H
b F17E E BF
H H
b F108 E 84
System Startup Configuration Register (Rd. only) XX
H
H
H
S0BG
FEB4
5A
Serial Channel 0 Baud Rate Generator Reload
Register
0000
H
H
H
S0CON
S0EIC
b FFB0
D8
Serial Channel 0 Control Register
0000
H
H
H
H
H
H
b FF70
B8
Serial Channel 0 Error Interrupt Control Register 0000
H
S0RBUF
FEB2
59
Serial Channel 0 Receive Buffer Register
(read only)
XX
H
H
S0RIC
b FF6E
B7
Serial Channel 0 Receive Interrupt Control
Register
0000
H
H
H
S0TBIC
S0TBUF
S0TIC
b F19C E CE
Serial Channel 0 Transmit Buffer Interrupt Control 0000
Register
H
H
H
FEB0
58
Serial Channel 0 Transmit Buffer Register
(write only)
00
H
H
H
H
H
b FF6C
B6
Serial Channel 0 Transmit Interrupt Control
Register
0000
H
H
SP
FE12
09
CPU System Stack Pointer Register
SSC Baudrate Register
FC00
H
H
SSCBR
F0B4 E 5A
0000
0000
H
H
H
SSCCON b FFB2
D9
SSC Control Register
H
H
H
Semiconductor Group
33
C167SR
Special Function Registers Overview (cont’d)
Name
Physical 8-Bit
Address Address
Description
Reset
Value
SSCEIC
SSCRB
SSCRIC
SSCTB
SSCTIC
STKOV
STKUN
b FF76
BB
SSC Error Interrupt Control Register
SSC Receive Buffer (read only)
0000
H
H
H
F0B2 E 59
XXXX
H
H
H
b FF74
BA
SSC Receive Interrupt Control Register
SSC Transmit Buffer (write only)
SSC Transmit Interrupt Control Register
CPU Stack Overflow Pointer Register
CPU Stack Underflow Pointer Register
CPU System Configuration Register
CAPCOM Timer 0 Register
0000
0000
0000
H
H
H
F0B0 E 58
H
H
H
H
b FF72
B9
0A
0B
H
H
H
H
H
H
FE14
FA00
H
H
H
H
FE16
FC00
H
1)
SYSCON b FF12
89
28
0xx0
H
T0
FE50
0000
H
H
H
T01CON b FF50
A8
CAPCOM Timer 0 and Timer 1 Control Register 0000
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
T0IC
T0REL
T1
b FF9C
CE
CAPCOM Timer 0 Interrupt Control Register
CAPCOM Timer 0 Reload Register
CAPCOM Timer 1 Register
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
H
H
H
H
FE54
FE52
2A
H
29
H
T1IC
T1REL
T2
b FF9E
CF
CAPCOM Timer 1 Interrupt Control Register
CAPCOM Timer 1 Reload Register
GPT1 Timer 2 Register
H
H
H
H
H
H
FE56
FE40
2B
H
20
H
T2CON
T2IC
T3
b FF40
b FF60
A0
B0
GPT1 Timer 2 Control Register
GPT1 Timer 2 Interrupt Control Register
GPT1 Timer 3 Register
H
H
H
FE42
21
H
H
H
T3CON
T3IC
T4
b FF42
b FF62
A1
GPT1 Timer 3 Control Register
GPT1 Timer 3 Interrupt Control Register
GPT1 Timer 4 Register
H
H
H
B1
FE44
22
H
H
H
T4CON
T4IC
T5
b FF44
b FF64
A2
B2
GPT1 Timer 4 Control Register
GPT1 Timer 4 Interrupt Control Register
GPT2 Timer 5 Register
H
H
H
FE46
23
H
H
H
T5CON
T5IC
T6
b FF46
b FF66
A3
B3
GPT2 Timer 5 Control Register
GPT2 Timer 5 Interrupt Control Register
GPT2 Timer 6 Register
H
H
H
FE48
24
A4
H
H
T6CON
b FF48
GPT2 Timer 6 Control Register
H
Semiconductor Group
34
C167SR
Special Function Registers Overview (cont’d)
Name
Physical 8-Bit
Address Address
Description
Reset
Value
T6IC
T7
b FF68
B4
GPT2 Timer 6 Interrupt Control Register
CAPCOM Timer 7 Register
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
H
H
H
H
H
H
H
H
H
H
H
H
H
H
F050 E 28
H
T78CON b FF20
90
CAPCOM Timer 7 and 8 Control Register
CAPCOM Timer 7 Interrupt Control Register
CAPCOM Timer 7 Reload Register
CAPCOM Timer 8 Register
H
T7IC
b F17A E BE
H
H
T7REL
T8
F054 E 2A
H
H
F052 E 29
H
H
T8IC
b F17C E BF
CAPCOM Timer 8 Interrupt Control Register
CAPCOM Timer 8 Reload Register
Trap Flag Register
H
H
T8REL
TFR
F056 E 2B
H
H
b FFAC
D6
H
H
H
H
WDT
FEAE
57
Watchdog Timer Register (read only)
Watchdog Timer Control Register
X-Peripheral 0 Interrupt Control Register
X-Peripheral 1 Interrupt Control Register
X-Peripheral 2 Interrupt Control Register
PLL Interrupt Control Register
H
2)
WDTCON
XP0IC
XP1IC
XP2IC
XP3IC
ZEROS
FFAE
D7
000X
H
H
H
H
H
H
H
H
H
b F186 E C3
0000
0000
0000
0000
0000
H
b F18E E C7
H
b F196 E CB
H
H
H
H
b F19E E CF
H
b FF1C
8E
Constant Value 0’s Register (read only)
H
1)
The system configuration is selected during reset.
Bit WDTR indicates a watchdog timer triggered reset.
2)
Note: The Interrupt Control Registers XPnIC are prepared to control interrupt requests from
integrated X-Bus peripherals. Nodes, where no X-Peripherals are connected, may be used
to generate software controlled interrupt requests by setting the respective XPnIR bit.
Semiconductor Group
35
C167SR
Absolute Maximum Ratings
Ambient temperature under bias (TA):
SAB-C167SR-LM............................................................................................................0 to + 70 ˚C
SAF-C167SR-LM....................................................................................................... – 40 to + 85 ˚C
SAK-C167SR-LM..................................................................................................... – 40 to + 125 ˚C
Storage temperature (TST)........................................................................................ – 65 to + 150 ˚C
Voltage on VCC pins with respect to ground (VSS) ..................................................... – 0.5 to + 6.5 V
Voltage on any pin with respect to ground (VSS).................................................– 0.5 to VCC + 0.5 V
Input current on any pin during overload condition.................................................. – 10 to + 10 mA
Absolute sum of all input currents during overload condition.............................................. |100 mA|
Power dissipation..................................................................................................................... 1.5 W
Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability. During overload conditions (VIN > VCC or VIN < VSS) the
voltage on pins with respect to ground (VSS) must not exceed the values defined by the
Absolute Maximum Ratings.
Parameter Interpretation
The parameters listed in the following partly represent the characteristics of the C167SR and partly
its demands on the system. To aid in interpreting the parameters right, when evaluating them for a
design, they are marked in column “Symbol”:
CC (Controller Characteristics):
The logic of the C167SR will provide signals with the respective timing characteristics.
SR (System Requirement):
The external system must provide signals with the respective timing characteristics to the C167SR.
Semiconductor Group
36
C167SR
DC Characteristics
CC = 5 V ± 10 %;
TA = 0 to + 70 ˚C
V
VSS = 0 V;
for SAB-C167SR-LM
f
CPU = 20 MHz;
Reset active
TA = – 40 to + 85 ˚C for SAF-C167SR-LM
TA = – 40 to + 125 ˚C for SAK-C167SR-LM
Parameter
Symbol
Limit Values
Unit Test Condition
min.
max.
Input low voltage
(TTL)
VIL SR – 0.5
0.2 VCC
– 0.1
V
V
V
–
–
–
Input low voltage
(Special Threshold)
VILS SR – 0.5
2.0
Input high voltage, all except
RSTIN and XTAL1 (TTL)
VIH SR 0.2 VCC
VCC + 0.5
+ 0.9
Input high voltage RSTIN
Input high voltage XTAL1
VIH1 SR 0.6 VCC
VIH2 SR 0.7 VCC
VCC + 0.5
VCC + 0.5
VCC + 0.5
V
V
V
–
–
–
Input high voltage
(Special Threshold)
VIHS SR 0.8 VCC
– 0.2
Input Hysteresis
(Special Threshold)
HYS
400
–
mV
V
–
Output low voltage
(PORT0, PORT1, Port 4, ALE, RD,
WR, BHE, CLKOUT, RSTOUT)
VOL CC –
VOL1 CC –
0.45
IOL = 2.4 mA
Output low voltage
(all other outputs)
0.45
–
V
V
IOL1 = 1.6 mA
Output high voltage
VOH CC 0.9 VCC
IOH = – 500 µA
(PORT0, PORT1, Port 4, ALE, RD,
WR, BHE, CLKOUT, RSTOUT)
2.4
IOH = – 2.4 mA
1)
Output high voltage
(all other outputs)
VOH1 CC 0.9 VCC
–
V
V
I
OH = – 250 µA
2.4
IOH = – 1.6 mA
Input leakage current (Port 5)
Input leakage current (all other)
Overload current
IOZ1 CC –
IOZ2 CC –
IOV SR –
±200
±500
±5
nA
nA
mA
kΩ
µA
µA
µA
µA
µA
0.45V < VIN < VCC
0.45V < VIN < VCC
5) 8)
RSTIN pullup resistor
RRST CC 50
250
– 40
–
–
4)
2)
Read/Write inactive current
IRWH
IRWL
IALEL
IALEH
IP6H
–
VOUT = 2.4 V
VOUT = VOLmax
VOUT = VOLmax
VOUT = 2.4 V
VOUT = 2.4 V
4)
3)
2)
3)
2)
Read/Write active current
– 500
–
4)
ALE inactive current
40
4)
ALE active current
500
–
–
4)
Port 6 inactive current
– 40
Semiconductor Group
37
C167SR
Parameter
Symbol
Limit Values
max.
Unit Test Condition
min.
4)
3)
Port 6 active current
IP6L
– 500
–
–
µA
µA
µA
µA
pF
VOUT = VOL1max
4)
2)
PORT0 configuration current
IP0H
– 10
–
VIN = VIHmin
3)
IP0L
– 100
VIN = VILmax
XTAL1 input current
IIL
CC –
± 20
10
0 V < VIN < VCC
5)
Pin capacitance
CIO CC –
f = 1 MHz
TA = 25 ˚C
(digital inputs/outputs)
Power supply current
ICC
IID
–
–
–
20 +
5 × fCPU
mA
mA
µA
RSTIN = VIL2
6)
fCPU in [MHz]
Idle mode supply current
20 +
2 × fCPU
RSTIN = VIH1
fCPU in [MHz]
6)
7)
Power-down mode supply current IPD
100
VCC = 5.5 V
Notes
1)
This specification is not valid for outputs which are switched to open drain mode. In this case the respective
output will float and the voltage results from the external circuitry.
2)
3)
4)
The maximum current may be drawn while the respective signal line remains inactive.
The minimum current must be drawn in order to drive the respective signal line active.
This specification is only valid during Reset, or during Hold- or Adapt-mode. Port 6 pins are only affected, if
they are used for CS output and the open drain function is not enabled.
5)
6)
Not 100 % tested, guaranteed by design characterization.
The supply current is a function of the operating frequency. This dependency is illustrated in the figure below.
These parameters are tested at VCCmax and 20 MHz CPU clock with all outputs disconnected and all inputs at
VIL or VIH.
7)
8)
This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to
0.1 V or at VCC – 0.1 V to VCC, VREF = 0 V, all outputs (including pins configured as outputs) disconnected.
Overload conditions occur if the standard operatings conditions are exceeded, ie. the voltage on any pin
exceeds the specified range (i.e. VOV > VCC + 0.5 V or VOV < VSS – 0.5 V). The absolute sum of input overload
currents on all port pins may not exceed 50 mA.
Semiconductor Group
38
C167SR
Figure 8
Supply/Idle Current as a Function of Operating Frequency
Semiconductor Group
39
C167SR
A/D Converter Characteristics
VCC = 5 V ± 10 %;
VSS = 0 V
TA = 0 to + 70 ˚C
for SAB-C167SR-LM
TA = – 40 to + 85 ˚C for SAF-C167SR-LM
TA = – 40 to + 125 ˚C for SAK-C167SR-LM
4.0 V ≤ VAREF ≤ VCC + 0.1 V; VSS – 0.1 V ≤ VAGND ≤ VSS + 0.2 V
Parameter
Symbol
Limit Values
Unit Test Condition
min.
max.
VAREF
2 tSC
1)
Analog input voltage range
Sample time
VAIN SR VAGND
V
2) 4)
3) 4)
tS
tC
CC –
CC –
Conversion time
14 tCC +
tS + 4TCL
5)
Total unadjusted error
TUE CC –
± 2
LSB
6) 7)
tCC in [ns]
Internal resistance of reference
voltage source
RAREF SR –
tCC / 165 kΩ
– 0.25
2) 7)
tS in [ns]
Internal resistance of analog
source
RASRC SR –
tS / 330
– 0.25
kΩ
7)
ADC input capacitance
CAIN CC –
33
pF
Sample time and conversion time of the C167SR’s ADC are programmable. The table below should
be used to calculate the above timings.
ADCON.15|14 Conversion Clock tCC
(ADCTC)
ADCON.13|12 Sample Clock tSC
(ADSTC)
00
01
10
11
TCL × 24
00
01
10
11
tCC
Reserved, do not use
TCL × 96
t
t
t
CC × 2
CC × 4
CC × 8
TCL × 48
Semiconductor Group
40
C167SR
Notes
1)
VAIN may exceed VAGND or VAREF up to the absolute maximum ratings. However, the conversion result in these
cases will be X000H or X3FFH, respectively.
2)
3)
During the sample time the input capacitance CI can be charged/discharged by the external source. The
internal resistance of the analog source must allow the capacitance to reach its final voltage level within tS.
After the end of the sample time tS, changes of the analog input voltage have no effect on the conversion result.
Values for the sample clock tSC depend on programming and can be taken from the table above.
This parameter includes the sample time tS, the time for determining the digital result and the time to load the
result register with the conversion result.
Values for the conversion clock tCC depend on programming and can be taken from the table above.
4)
5)
This parameter depends on the ADC control logic. It is not a real maximum value, but rather a fixum.
TUE is tested at VAREF = 5.0 V, VAGND = 0 V, VCC = 4.9 V. It is guaranteed by design characterization for all other
voltages within the defined voltage range.
The specified TUE is guaranteed only if an overload condition (see IOV specification) occurs on maximum 2 not
selected analog input pins and the absolute sum of input overload currents on all analog input pins does not
exceed 10 mA.
During the reset calibration sequence the maximum TUE may be ± 4 LSB.
6)
7)
During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal
resistance of the reference voltage source must allow the capacitance to reach its respective voltage level
within tCC. The maximum internal resistance results from the programmed conversion timing.
Not 100 % tested, guaranteed by design characterization.
Semiconductor Group
41
C167SR
Testing Waveforms
AC inputs during testing are driven at 2.4 V for a logic ‘1’ and 0.4 V for a logic ‘0’.
Timing measurements are made at VIH min for a logic ‘1’ and VIL max for a logic ‘0’.
Figure 9
Input Output Waveforms
For timing purposes a port pin is no longer floating when a 100 mV change from load
voltageoccurs,butbeginstofloatwhena100mVchangefromtheloadedVOH/VOL leveloccurs
(IOH/IOL = 20 mA).
Figure 10
Float Waveforms
Semiconductor Group
42
C167SR
AC Characteristics
Definition of Internal Timing
The internal operation of the C167SR is controlled by the internal CPU clock fCPU. Both edges of the
CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations.
The specification of the external timing (AC Characteristics) therefore depends on the time between
two consecutive edges of the CPU clock, called “TCL” (see figure below).
Phase Locked Loop Operation
f
XTAL
CPU
f
TCLTCL
TCLTCL
Direct Clock Drive
f
XTAL
CPU
f
Figure 11
Generation Mechanisms for the CPU Clock
The CPU clock signal can be generated via different mechanisms. The duration of TCLs and their
variation (and also the derived external timing) depends on the used mechanism to generate fCPU
.
This influence must be regarded when calculating the timings for the C167SR.
Direct Drive
When pin P0.15 (P0H.7) is low (‘0’) during reset the on-chip phase locked loop is disabled and the
CPU clock is directly driven from the oscillator with the input clock signal.
The frequency of fCPU directly follows the frequency of fXTAL so the high and low time of fCPU (i.e. the
duration of an individual TCL) is defined by the duty cycle of the input clock fXTAL
.
The timings listed below that refer to TCLs therefore must be calculated using the minimum TCL
that is possible under the respective circumstances. This minimum value can be calculated via the
following formula:
TCLmin = 1/fXTAL × DCmin
(DC = duty cycle)
For two consecutive TCLs the deviation caused by the duty cycle of fXTAL is compensated so the
duration of 2TCL is always 1/fXTAL. The minimum value TCLmin therefore has to be used only once for
timings that require an odd number of TCLs (1,3,...). Timings that require an even number of TCLs
(2,4,...) may use the formula 2TCL = 1/fXTAL
.
Note: The address float timings in Multiplexed bus mode (t11 and t45) use the maximum duration of
TCL (TCLmax = 1/fXTAL × DCmax) instead of TCLmin.
Semiconductor Group
43
C167SR
Phase Locked Loop
When pin P0.15 (P0H.7) is high (‘1’) during reset the on-chip phase locked loop is enabled and
provides the CPU clock. The PLL multiplies the input frequency by 4 (i.e. fCPU = fXTAL × 4). With every
fourth transition of fXTAL the PLL circuit synchronizes the CPU clock to the input clock. This
synchronization is done smoothely, i.e. the CPU clock frequency does not change abruptly.
Due to this adaptation to the input clock the frequency of fCPU is constantly adjusted so it is locked
to fXTAL. The slight variation causes a jitter of fCPU which also effects the duration of individual TCLs.
The timings listed in the AC Characteristics that refer to TCLs therefore must be calculated using the
minimum TCL that is possible under the respective circumstances.
The actual minimum value for TCL depends on the jitter of the PLL. As the PLL is constantly
adjusting its output frequency so it corresponds to the applied input frequency (crystal or oscillator)
the relative deviation for periods of more than one TCL is lower than for one single TCL (see formula
and figure below).
For a period of N × TCL the minimum value is computed using the corresponding deviation D :
N
TCLmin = TCLNOM × (1 – D / 100)
D = ± (4 – N /15) [%],
N
N
where N = number of consecutive TCLs
and 1 ≤ N ≤ 40.
So for a period of 3 TCLs (i.e. N = 3): D = 4 – 3/15 = 3.8 %,
3
and TCLmin = TCLNOM × (1 – 3.8 / 100) = TCLNOM × 0.962 (24.1 nsec @ fCPU = 20 MHz).
This is especially important for bus cycles using waitstates and eg. for the operation of timers, serial
interfaces, etc. For all slower operations and longer periods (e.g. pulse train generation or
measurement, lower baudrates, etc.) the deviation caused by the PLL jitter is neglectible.
Figure 12
Approximated Maximum PLL Jitter
Semiconductor Group
44
C167SR
AC Characteristics
External Clock Drive XTAL1
VCC = 5 V ± 10 %;
VSS = 0 V
TA = 0 to + 70 ˚C
for SAB-C167SR-LM
TA = – 40 to + 85 ˚C for SAF-C167SR-LM
TA = – 40 to + 125 ˚C for SAK-C167SR-LM
Parameter
Symbol
Direct Drive 1:1
PLL 1:4
max.
Unit
min.
tOSC SR 50
max.
1000
–
min.
200
10
10
–
Oscillator period
High time
333
–
ns
ns
ns
ns
ns
1) 2)
t1
t2
t3
t4
SR 23
SR 23
SR –
SR –
1) 2)
Low time
–
–
2)
2)
Rise time
10
10
10
2)
2)
Fall time
10
–
1)
For temperatures above TA = +85 ˚C the minimum value for t1 and t2 is 25 ns.
2)
The clock input signal must reach the defined levels VIL and VIH2
.
Figure 13
External Clock Drive XTAL1
Semiconductor Group
45
C167SR
Memory Cycle Variables
The timing tables below use three variables which are derived from the BUSCONx registers and
represent the special characteristics of the programmed memory cycle. The following table
describes, how these variables are to be computed.
Description
Symbol Values
ALE Extension
tA
tC
tF
TCL × <ALECTL>
Memory Cycle Time Waitstates
Memory Tristate Time
2TCL × (15 – <MCTC>)
2TCL × (1 – <MTTC>)
AC Characteristics
Multiplexed Bus
V
CC = 5 V ± 10 %;
VSS = 0 V
for SAB-C167SR-LM
TA = 0 to + 70 ˚C
TA = – 40 to + 85 ˚C for SAF-C167SR-LM
TA = – 40 to + 125 ˚C for SAK-C167SR-LM
CL (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF
CL (for Port 6, CS) = 100 pF
ALE cycle time = 6 TCL + 2tA + tC + tF (150 ns at 20-MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock
= 20 MHz
Variable CPU Clock
1/2TCL = 1 to 20 MHz
Unit
min.
CC 15 + tA
max.
min.
max.
ALE high time
t5
t6
–
–
–
–
TCL – 10 + tA
TCL – 15 + tA
TCL – 10 + tA
TCL – 10 + tA
–
–
–
–
ns
ns
ns
ns
CC
CC
CC
Address setup to ALE
Address hold after ALE
10 + tA
15 + tA
15 + tA
t7
t8
ALE falling edge to RD,
WR (with RW-delay)
t9
CC
ALE falling edge to RD,
WR (no RW-delay)
– 10 + tA
–
– 10 + tA
–
ns
ns
ns
ns
ns
t10 CC
t11 CC
Address float after RD,
WR (with RW-delay)
–
–
5
–
–
5
Address float after RD,
WR (no RW-delay)
30
–
TCL + 5
RD, WR low time
(with RW-delay)
t12 CC 40 + tC
t13 CC 65 + tC
2TCL – 10
+ tC
–
–
RD, WR low time
(no RW-delay)
–
3TCL – 10
+ tC
Semiconductor Group
46
C167SR
Parameter
Symbol
Max. CPU Clock
= 20 MHz
Variable CPU Clock
1/2TCL = 1 to 20 MHz
Unit
min.
max.
min.
max.
RD to valid data in
(with RW-delay)
t14 SR
t15 SR
t16 SR
t17 SR
t18 SR
t19 SR
–
–
–
–
0
–
30 + tC
–
–
–
–
0
–
2TCL – 20
+ tC
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RD to valid data in
(no RW-delay)
55 + tC
3TCL – 20
+ tC
ALE low to valid data in
55
+ tA + tC
3TCL – 20
+ tA + tC
Address to valid data in
70
+ 2tA + tC
4TCL – 30
+ 2tA + tC
Data hold after RD
rising edge
–
–
Data float after RD
Data valid to WR
Data hold after WR
35 + tF
2TCL – 15
+ tF
t22 SR 25 + tC
t23 CC 35 + tF
–
2TCL – 25
+ tC
–
–
2TCL – 15
+ tF
–
ALE rising edge after RD, t25 CC 35 + tF
WR
–
2TCL – 15
+ tF
–
Address hold after RD,
WR
t27 CC 35 + tF
t38 CC – 5 – tA
–
2TCL – 15
+ tF
–
ALE falling edge to CS
CS low to Valid Data In
10 – tA
– 5 – tA
10 – tA
ns
ns
t39 SR
–
55
–
3TCL – 20
+ tC + 2tA
+ tC + 2tA
CS hold after RD, WR
t40 CC 60 + tF
t42 CC 20 + tA
t43 CC – 5 + tA
–
3TCL – 15
+ tF
–
ns
ns
ns
ns
ns
ns
ALE fall. edge to RdCS,
WrCS (with RW delay)
–
TCL – 5
+ tA
–
ALE fall. edge to RdCS,
WrCS (no RW delay)
–
– 5
+ tA
–
Address float after RdCS, t44 CC
WrCS (with RW delay)
–
–
–
0
–
–
–
0
Address float after RdCS, t45 CC
WrCS (no RW delay)
25
TCL
RdCS to Valid Data In
(with RW delay)
t46 SR
25 + tC
2TCL – 25
+ tC
Semiconductor Group
47
C167SR
Parameter
Symbol
Max. CPU Clock
= 20 MHz
Variable CPU Clock
1/2TCL = 1 to 20 MHz
Unit
min.
max.
min.
max.
RdCS to Valid Data In
(no RW delay)
t47 SR
–
50 + tC
–
3TCL – 25
+ tC
ns
ns
ns
ns
RdCS, WrCS Low Time
(with RW delay)
t48 CC 40 + tC
t49 CC 65 + tC
t50 CC 35 + tC
–
–
–
2TCL – 10
+ tC
–
–
–
–
RdCS, WrCS Low Time
(no RW delay)
3TCL – 10
+ tC
Data valid to WrCS
2TCL – 15
+ tC
Data hold after RdCS
Data float after RdCS
t51 SR
t52 SR
0
–
–
0
–
ns
ns
30 + tF
2TCL – 20
+ tF
Address hold after
RdCS, WrCS
t54 CC 30 + tF
t56 CC 30 + tF
–
–
2TCL – 20
+ tF
–
ns
ns
Data hold after WrCS
2TCL – 20
–
+ tF
Semiconductor Group
48
C167SR
t5
t16
t25
ALE
CSx
t38
t39
t40
t17
t27
A23-A16
(A15-A8)
BHE
Address
t6
t7
t54
t19
t18
Read Cycle
BUS
Address
t8
Data In
t10
t14
t12
t46
t48
RD
t51
t44
t42
t52
RdCSx
Write Cycle
t23
BUS
Address
t8
Data Out
t56
t10
t22
WR,
WRL, WRH
t12
t44
t42
t50
WrCSx
t48
Figure 14-1
External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Normal ALE
Semiconductor Group 49
C167SR
t5
t16
t25
ALE
CSx
t38
t39
t40
t17
t27
A23-A16
(A15-A8)
BHE
Address
t6
t7
t54
t19
t18
Read Cycle
BUS
Address
Data In
t10
t8
t14
t12
t46
t48
RD
t51
t44
t42
t52
RdCSx
Write Cycle
t23
BUS
Address
Data Out
t56
t10
t8
t22
WR,
WRL, WRH
t12
t44
t42
t50
WrCSx
t48
Figure 14-2
External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Extended ALE
Semiconductor Group 50
C167SR
t5
t16
t25
ALE
CSx
t38
t39
t40
t17
t27
A23-A16
(A15-A8)
BHE
Address
t6
t7
t54
t19
t18
Read Cycle
BUS
Address
t9
Data In
t11
t15
t13
t47
t49
RD
t51
t43
t45
t52
RdCSx
Write Cycle
t23
BUS
Address
t9
Data Out
t56
t11
t22
WR,
WRL, WRH
t13
t50
t43
t45
WrCSx
t49
Figure 14-3
External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Normal ALE
Semiconductor Group 51
C167SR
t5
t16
t25
ALE
CSx
t38
t39
t40
t17
t27
A23-A16
(A15-A8)
BHE
Address
t6
t7
t54
t19
t18
Read Cycle
BUS
Address
t9
Data In
t11
t15
t13
t47
t49
RD
t51
t43
t45
t52
RdCSx
Write Cycle
t23
BUS
Address
t9
Data Out
t56
t11
t22
WR,
WRL, WRH
t13
t43
t45
t50
WrCSx
t49
Figure 14-4
External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Extended ALE
Semiconductor Group 52
C167SR
AC Characteristics
Demultiplexed Bus
VCC = 5 V ± 10 %;
VSS = 0 V
TA = 0 to + 70 ˚C
for SAB-C167SR-LM
TA = – 40 to + 85 ˚C for SAF-C167SR-LM
TA = – 40 to + 125 ˚C for SAK-C167SR-LM
CL (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF
CL (for Port 6, CS) = 100 pF
ALE cycle time = 4 TCL + 2tA + tC + tF (100 ns at 20-MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock
= 20 MHz
Variable CPU Clock
1/2TCL = 1 to 20 MHz
Unit
min.
CC 15 + tA
max.
min.
max.
ALE high time
t5
t6
–
–
–
TCL – 10 + tA
TCL – 15 + tA
–
–
–
ns
ns
ns
CC
CC
Address setup to ALE
10 + tA
15 + tA
t8
ALE falling edge to RD,
WR (with RW-delay)
TCL – 10
+ tA
t9
CC
ALE falling edge to RD,
WR (no RW-delay)
– 10 + tA
–
– 10
+ tA
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RD, WR low time
(with RW-delay)
t12 CC 40 + tC
t13 CC 65 + tC
–
2TCL – 10
+ tC
RD, WR low time
(no RW-delay)
–
3TCL – 10
+ tC
RD to valid data in
(with RW-delay)
t14 SR
t15 SR
t16 SR
t17 SR
t18 SR
–
–
–
–
0
–
–
30 + tC
55 + tC
–
–
–
–
0
–
–
2TCL – 20
+ tC
RD to valid data in
(no RW-delay)
3TCL – 20
+ tC
ALE low to valid data in
55
+ tA + tC
3TCL – 20
+ tA + tC
Address to valid data in
70
+ 2tA + tC
4TCL – 30
+ 2tA + tC
Data hold after RD
rising edge
–
–
Data float after RD rising t20 SR
35 + tF
2TCL – 15
+ 2tA + tF
1)
1)
edge (with RW-delay )
Data float after RD rising t21 SR
15 + tF
TCL – 10
+ 2tA + tF
1)
1)
edge (no RW-delay )
Data valid to WR
t22 CC 25 + tC
t24 CC 15 + tF
–
–
2TCL – 25
+ tC
–
Data hold after WR
TCL – 10 + tF
–
Semiconductor Group
53
C167SR
Parameter
Symbol
Max. CPU Clock
= 20 MHz
Variable CPU Clock
1/2TCL = 1 to 20 MHz
Unit
min.
max.
min.
max.
ALE rising edge after RD, t26 CC – 10 + tF
WR
–
– 10
+ tF
–
ns
ns
Address hold after RD,
WR
t28 CC 0 + tF
–
0
+ tF
–
ALE falling edge to CS
CS low to Valid Data In
t38 CC – 5 – tA
10 – tA
– 5 – tA
10 – tA
ns
ns
t39 SR
–
55
–
3TCL – 20
+ tC + 2tA
+ tC + 2tA
CS hold after RD, WR
t41 CC 10 + tF
t42 CC 20 + tA
–
–
TCL – 15
+ tF
–
–
ns
ns
ALE falling edge to
RdCS, WrCS (with RW-
delay)
TCL – 5
+ tA
ALE falling edge to
RdCS, WrCS (no RW-
delay)
t43 CC – 5 + tA
–
– 5
+ tA
–
ns
RdCS to Valid Data In
(with RW-delay)
t46 SR
t47 SR
–
–
25 + tC
–
–
2TCL – 25
+ tC
ns
ns
ns
ns
ns
RdCS to Valid Data In
(no RW-delay)
50 + tC
3TCL – 25
+ tC
RdCS, WrCS Low Time
(with RW-delay)
t48 CC 40 + tC
t49 CC 65 + tC
t50 CC 35 + tC
–
–
–
2TCL – 10
+ tC
–
–
–
–
RdCS, WrCS Low Time
(no RW-delay)
3TCL – 10
+ tC
Data valid to WrCS
2TCL – 15
+ tC
Data hold after RdCS
t51 SR
t53 SR
0
–
–
0
–
ns
ns
Data float after RdCS
(with RW-delay)
30 + tF
2TCL – 20
+ tF
Data float after RdCS
(no RW-delay)
t68 SR
–
5 + tF
–
TCL – 20
+ tF
ns
ns
ns
Address hold after
RdCS, WrCS
t55 CC – 10 + tF
t57 CC 10 + tF
–
–
– 10
+ tF
–
–
Data hold after WrCS
TCL – 15
+ tF
1)
RW-delay and tA refer to the next following bus cycle.
Semiconductor Group
54
C167SR
t5
t16
t26
ALE
CSx
t38
t39
t41
t17
t28
A23-A16
A15-A0
BHE
Address
t6
t55
t20
Read Cycle
BUS
(D15-D8)
D7-D0
t18
Data In
t8
t14
RD
t12
t46
t48
t51
t42
t53
RdCSx
Write Cycle
BUS
(D15-D8)
D7-D0
t24
Data Out
t57
t8
t22
WR,
WRL, WRH
t12
t42
t50
WrCSx
t48
Figure 15-1
External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Normal ALE
Semiconductor Group 55
C167SR
t5
t16
t39
t17
t26
ALE
CSx
t38
t41
t28
A23-A16
A15-A0
BHE
Address
t6
t55
t20
t18
Read Cycle
BUS
(D15-D8)
D7-D0
Data In
t8
t14
t12
t46
t48
RD
t51
t42
t53
RdCSx
Write Cycle
BUS
(D15-D8)
D7-D0
t24
Data Out
t57
t8
t22
WR,
WRL, WRH
t12
t42
t50
WrCSx
t48
Figure 15-2
External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Extended ALE
Semiconductor Group 56
C167SR
t5
t16
t26
ALE
CSx
t38
t39
t41
t17
t28
A23-A16
A15-A0
BHE
Address
t6
t55
t21
Read Cycle
BUS
(D15-D8)
D7-D0
t18
Data In
t9
t15
t13
t47
t49
RD
t51
t43
t68
RdCSx
Write Cycle
BUS
(D15-D8)
D7-D0
t24
Data Out
t57
t9
t22
WR,
WRL, WRH
t13
t50
t43
WrCSx
t49
Figure 15-3
External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Normal ALE
Semiconductor Group 57
C167SR
t5
t16
t39
t17
t26
ALE
CSx
t38
t41
t28
A23-A16
A15-A0
BHE
Address
t6
t55
t21
t18
Read Cycle
BUS
(D15-D8)
D7-D0
Data In
t9
t15
t13
t47
t49
RD
t51
t43
t68
RdCSx
Write Cycle
BUS
(D15-D8)
D7-D0
t24
Data Out
t57
t9
t22
WR,
WRL, WRH
t13
t43
t50
WrCSx
t49
Figure 15-4
External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Extended ALE
Semiconductor Group 58
C167SR
AC Characteristics
CLKOUT and READY
VCC = 5 V ± 10 %;
VSS = 0 V
TA = 0 to + 70 ˚C
for SAB-C167SR-LM
TA = – 40 to + 85 ˚C for SAF-C167SR-LM
TA = – 40 to + 125 ˚C for SAK-C167SR-LM
CL (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF
CL (for Port 6, CS) = 100 pF
Parameter
Symbol
Max. CPU Clock
= 20 MHz
Variable CPU Clock
1/2TCL = 1 to 20 MHz
Unit
min.
max.
min.
max.
CLKOUT cycle time
CLKOUT high time
CLKOUT low time
CLKOUT rise time
CLKOUT fall time
t29 CC 50
50
2TCL
TCL – 5
TCL – 10
–
2TCL
ns
ns
ns
ns
ns
ns
t30 CC
t31 CC
20
15
–
–
–
–
–
t32 CC
t33 CC
5
5
–
5
–
5
CLKOUT rising edge to
ALE falling edge
t34 CC 0 + tA
10 + tA
0 + tA
10 + tA
Synchronous READY
setup time to CLKOUT
t35 SR 15
–
–
–
–
–
0
15
–
ns
ns
ns
ns
ns
ns
Synchronous READY
hold time after CLKOUT
t36 SR
0
0
–
Asynchronous READY
low time
t37 SR 65
2TCL + 15
–
t58 SR
t59 SR
t60 SR
Asynchronous READY
15
0
15
0
–
1)
setup time
Asynchronous READY
hold time 1)
–
Async. READY hold time
after RD, WR high
(Demultiplexed Bus)2)
0
0
TCL – 25
+ 2tA + tF
+ 2tA + tF
2)
2)
Notes
1)
These timings are given for test purposes only, in order to assure recognition at a specific clock edge.
2)
Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values. This
adds even more time for deactivating READY.
The 2tA refer to the next following bus cycle.
Semiconductor Group
59
C167SR
READY
waitstate
6)
1)
MUX/Tristate
Running cycle
t32
t33
CLKOUT
ALE
t30
t34
t29
t31
7)
2)
Command
RD, WR
t35
t36
t35
t36
Sync
READY
3)
3)
4)
t58
t59
t58
t59
t60
Async
3)
3)
READY
t37
5)
see 6)
Figure 16
CLKOUT and READY
Notes
1)
Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS).
The leading edge of the respective command depends on RW-delay.
2)
3)
READY sampled HIGH at this sampling point generates a READY controlled waitstate,
READY sampled LOW at this sampling point terminates the currently running bus cycle.
4)
5)
READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or
WR).
If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT
(eg. because CLKOUT is not enabled), it must fulfill t37 in order to be safely synchronized. This is guaranteed,
if READY is removed in reponse to the command (see Note 4)).
6)
7)
Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may
be inserted here.
For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without
MTTC waitstate this delay is zero.
The next external bus cycle may start here.
Semiconductor Group
60
C167SR
AC Characteristics
External Bus Arbitration
VCC = 5 V ± 10 %;
VSS = 0 V
TA = 0 to + 70 ˚C
for SAB-C167SR-LM
TA = – 40 to + 85 ˚C for SAF-C167SR-LM
TA = – 40 to + 125 ˚C for SAK-C167SR-LM
CL (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF
CL (for Port 6, CS) = 100 pF
Parameter
Symbol
Max. CPU Clock
= 20 MHz
Variable CPU Clock
1/2TCL = 1 to 20 MHz
Unit
min.
max.
min.
max.
HOLD input setup time
to CLKOUT
t61 SR 20
–
20
–
ns
ns
ns
CLKOUT to HLDA high
or BREQ low delay
t62 CC
t63 CC
–
–
20
20
–
20
20
CLKOUT to HLDA low
or BREQ high delay
–
CSx release
t64 CC
t65 CC
–
20
25
20
25
–
20
25
20
25
ns
ns
ns
ns
CSx drive
– 5
–
– 5
–
t66 CC
t67 CC
Other signals release
Other signals drive
– 5
– 5
Semiconductor Group
61
C167SR
CLKOUT
HOLD
t61
t63
HLDA
1)
t62
2)
BREQ
t64
3)
CSx
(On P6.x)
t66
Other
Signals
1)
Figure 17
External Bus Arbitration, Releasing the Bus
Notes
1)
The C167SR will complete the currently running bus cycle before granting bus access.
This is the first possibility for BREQ to get active.
2)
3)
The CS outputs will be resistive high (pullup) after t64.
Semiconductor Group
62
C167SR
2)
CLKOUT
HOLD
t61
t62
HLDA
t62
t62
t63
1)
BREQ
t65
CSx
(On P6.x)
t67
Other
Signals
Figure 18
External Bus Arbitration, (Regaining the Bus)
Notes
1)
This is the last chance for BREQ to trigger the indicated regain-sequence.
Even if BREQ is activated earlier, the regain-sequence is initiated by HOLD going high.
Please note that HOLD may also be deactivated without the C167SR requesting the bus.
2)
The next C167SR driven bus cycle may start here.
Semiconductor Group
63
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