BTS770G [INFINEON]
TrilithIC Quad switch driver; TrilithIC四路开关驱动器
| 型号： | BTS770G |
| 厂家： | 
Infineon |
| 描述： | TrilithIC Quad switch driver |
| 文件： | 总17页 (文件大小：95K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TrilithIC
BTS 770 G
Overview
Features
• Quad switch driver
• Free configurable as bridge or quad-switch
• Optimized for DC motor management applications
• Ultra low RDS ON @ 25 °C:
High-side switch: typ.165 mΩ,
Low-side switch: typ. 55 mΩ
P-DSO-28-9
• Very high peak current capability
• Very low quiescent current
• Space- and thermal optimized power P-DSO-Package
• Load and GND-short-circuit-protected
• Operates up to 40 V
• Status flag diagnosis
• Overtemperature shut down with hysteresis
• Short-circuit detection and diagnosis
• Open-load detection and diagnosis
• C-MOS compatible inputs
• Internal clamp diodes
• Isolated sources for external current sensing
• Over- and under-voltage detection with hysteresis
Type
Ordering Code
Package
BTS 770 G
Q67007-A9254
P-DSO-28-9
Description
The BTS 770 G is a TrilithIC contains one double high-side switch and two low-side
switches in one P-DSO-28-9 -Package.
“Silicon instead of heatsink”
becomes true
The ultra low RDS ON of this device avoids powerdissipation. It saves costs in mechanical
construction and mounting and increases the efficiency.
The high-side switches are produced in the SIEMENS SMART SIPMOS® technology. It
is fully protected and contains the signal conditioning circuitry for diagnosis. (The
comparable standard high-side product is the BTS 611L1.)
Semiconductor Group
1
1999-01-07
BTS 770 G
For minimized RDS ON the two low-side switches are produced in the SIEMENS Millifet
logic level technology (The comparable standard product is the BUZ 101AL).
Each drain of these three chips is mounted on separated leadframes (see P-DSO-28-9
pin configuration). The sources of all four power transistors are connected to separate
pins.
So the BTS 770 G can be used in H-Bridge configuration as well as in any other switch
configuration.
Moreover, it is possible to add current sense resistors.
All these features open a broad range of automotive and industrial applications.
Semiconductor Group
2
1999-01-07
BTS 770 G
DL1
GL1
DL1
N.C.
1
2
3
4
28 DL1
27 SL1
26 SL1
25 DL1
LS-Lead Frame 1
DHVS
GND
5
6
24 DHVS
23 SH1
GH1
ST
7
8
9
22 SH1
21 SH2
20 SH2
19 DHVS
18 DL2
17 SL2
16 SL2
15 DL2
HS-Lead Frame
GH2
DHVS 10
N.C.
DL2
GL2
DL2
11
12
13
14
LS-Lead Frame 2
AEP02071
Figure 1 Pin Configuration (top view)
Semiconductor Group
3
1999-01-07
BTS 770 G
Pin Definitions and Functions
Pin No.
Symbol Function
1, 3, 25, 28
DL1
Drain of low-side switch1
Leadframe 1 1)
2
GL1
Gate of low-side switch1
not connected
4
N.C.
5, 10, 19, 24
DHVS
Drain of high-side switches and power supply voltage
Leadframe 2 1)
6
GND
GH1
ST
Ground
7
Gate of high-side switch1
Status of high-side switches; open Drain output
Gate of high-side switch2
not connected
8
9
GH2
N.C.
11
12, 14, 15, 18 DL2
Drain of low-side switch2
Leadframe 3 1)
13
GL2
SL2
SH2
SH1
SL1
Gate of low-side switch2
16, 17
20, 21
22, 23
26, 27
Source of low-side switch2
Source of high-side switch2
Source of high-side switch1
Source of low-side switch1
1)
To reduce the thermal resistance these pins are direct connected via metal bridges to the leadframe.
Bold type: Pin needs power wiring
Semiconductor Group
4
1999-01-07
BTS 770 G
DHVS
5, 10, 19, 24
8
7
ST
DST
C6V1
Diagnosis
Driver
Biasing and Protection
RI1
GH1
IN
OUT
3.5 kΩ
1
0
0
1
1
2
0
1
0
1
1
L
L
H
H
2
L
H
L
DI1
C6V1
RO1
RO2
20, 21
SH2
RI2
10 kΩ
10 kΩ
9
GH2
GND
GL1
GL2
3.5 kΩ
H
12, 14, 15, 18
22, 23
DI2
C6V1
DL2
SH1
6
1, 3, 25, 28
DL1
2
13
26, 27
16, 17
SL2
SL1
AEB02072
Figure 2 Block Diagram
Semiconductor Group
5
1999-01-07
BTS 770 G
Circuit Description
Input Circuit
The control inputs GH1,2 consist of TTL/CMOS compatible Schmitt-Triggers with
hysteresis. Buffer amplifiers are driven by these stages and convert the logic signal into
the necessary form for driving the power output stages.
The inputs GH1 and GH2 are connected to a standard N-channel logic level power-MOS
gate.
Output Stages
The output stages consist of an ultra low RDS ON Power-MOS H-Bridge. Protective circuits
make the outputs short circuit proof to ground and load short circuit proof. Positive and
negative voltage spikes, which occur when driving inductive loads, are limited by
integrated power clamp diodes.
Short Circuit Protection (valid only for the high-side switches)
The outputs are protected against
– output short circuit to ground, and
– overload (load short circuit).
An internal OP-Amp controls the Drain-Source-Voltage of the HS-Switches by
comparing the DS-Voltage-Drop with an internal reference voltage. Above this trippoint
the OP-Amp reduces the output current depending on the junction temperature and the
drop voltage.
In the case of overloaded high-side switches the status output is set to low.
If the HS-Switches are in OFF-state-Condition internal resistors RO1,2 from SH1,2 to GND
pull the voltage at SH1,2 to low values. On each output pin SH1 and SH2 an output
examiner circuit compares the output voltages with the internal reference voltage VEO.
This results in switching the status output to low. In H-Bridge condition this feature can
be used to protect the low-side switches against short circuit during the OFF-period.
Overtemperature Protection (valid only for the high-side-switches)
The chip also incorporates an overtemperature protection circuit with hysteresis which
switches off the output transistors and sets the status output to low.
Undervoltage-Lockout (UVLO)
When VS reaches the switch-on voltage VUVON the IC becomes active with a hysteresis.
The High-Side output transistors are switched off if the supply voltage VS drops below
the switch off value VUVOFF
.
Semiconductor Group
6
1999-01-07
BTS 770 G
Overvoltage-Lockout (OVLO)
When VS reaches the switch-off voltage VOVOFF the High-Side output transistors are
switched off with a hysteresis. The IC becomes active if the supply voltage VS drops
below the switch-on value VOVON
.
Open Load Detection
Open load is detected by current measurement. If the output current drops below an
internal fixed level the error flag is set with a delay.
Status Flag
Various errors as listed in the table “Diagnosis” are detected by switching the open drain
output ST to low.
Semiconductor Group
7
1999-01-07
BTS 770 G
Truthtable and Diagnosis (valid only for the High-Side-Switches)
Flag
GH1 GH2 SH1 SH2 ST Remarks
Inputs
Outputs
0
0
1
1
0
1
0
1
L
L
H
H
L
H
L
1
1
1
1
stand-by mode
switch2 active
switch1 active
both switches
active
Normal operation;
identical with functional truth table
H
Open load at high-side switch1
Open load at high-side switch2
0
0
1
0
1
X
0
1
X
0
0
1
Z
Z
H
L
H
X
L
1
1
0
1
1
0
H
X
Z
Z
H
detected
detected
detected
Short circuit to DHVS at high-side switch1
Short circuit to DHVS at high-side switch2
0
0
1
0
1
X
0
1
X
0
0
1
H
H
H
L
H
X
L
0
1
1
0
1
1
H
X
H
H
H
detected
Overtemperature high-side switch1
Overtemperature high-side switch2
Overtemperature both high-side switch
0
1
X
X
L
L
X
X
1
0
detected
detected
X
X
0
1
X
X
L
L
1
0
0
X
1
0
1
X
L
L
L
L
L
L
1
0
0
detected
detected
Over- and Under-Voltage
X
X
L
L
1
not detected
Inputs:
Outputs:
Status:
0 = Logic LOW
1 = Logic HIGH
X = don’t care
Z = Output in tristate condition
L = Output in sink condition
H = Output in source condition
X = Voltage level undefined
1 = No error
0 = Error
Semiconductor Group
8
1999-01-07
BTS 770 G
Electrical Characteristics
Absolute Maximum Ratings
– 40 °C < Tj < 150 °C
Parameter
Symbol Limit Values Unit Remarks
min. max.
High-Side-Switches (Pins DHVS, GH1,2 and SH1,2)
Supply voltage
HS-drain current
HS-input current
HS-input voltage
VS
– 0.3 43
V
A
–
IDHS
IGH
VGH
– 8
*
* internally limited
– 2
2
mA Pin GH1 and GH2
V Pin GH1 and GH2
– 10
16
Status Output ST
Status Output current
IST
– 5
5
mA Pin ST
Low-Side-Switches (Pins DL1,2, GL1,2 and SL1,2)
Break-down voltage
LS-drain current
LS-drain current
LS-drain current
lS-input voltage
V(BR)DSS 50
–
V
A
A
A
V
VGS = 0 V; ID <= 1 mA
IDLS
IDLS
IDLS
VGL
–
10
20
30
14
–
–
t < 1 ms; ν < 0.1
t < 0.1 ms; ν < 0.1
Pin GL1 and GL2
–
– 10
Temperatures
Junction temperature
Storage temperature
Tj
– 40
– 50
150
150
°C
°C
–
–
Tstg
Thermal Resistances (one HS-LS-Path active)
LS-junction case
HS-junction case
Junction ambient
RthjCLS
RthjCHS
Rthja
–
–
–
20
20
60
K/W measured to pin3 or 12
K/W measured to pin19
K/W –
Note: Maximum ratings are absolute ratings; exceeding any one of these values may
cause irreversible damage to the integrated circuit.
Semiconductor Group
9
1999-01-07
BTS 770 G
Operating Range
Parameter
Symbol Limit Values Unit
min. max.
Remarks
Supply voltage
VS
VUVOFF 34
V
After VS rising
above VUVON
Input voltages
VGH
VGL
IST
– 0.3 15
V
–
–
–
–
–
Input voltages
– 9
0
13
V
Output current
2
mA
°C
°C
HS-junction temperature
LS-junction temperature
TjHS
TjLS
– 40
– 40
150
150
Note: In the operating range the functions given in the circuit description are fulfilled.
Semiconductor Group
10
1999-01-07
BTS 770 G
Electrical Characteristics
SH1 = ISH2 = ISL1 = ISL2 = 0 A; – 40 °C < Tj < 150 °C; 8 V > VS > 18 V
I
unless otherwise specified
Parameter
Symbol
Limit Values
Unit Test Condition
min. typ. max.
Current Consumption
Quiescent current
IS
IS
–
–
16
–
30
35
µA
µA
GH1 = GH2 = L
VS = 13.2 V
Tj = 25 °C
Quiescent current
GH1 = GH2 = L
VS = 13.2 V
Supply current
Supply current
IS
IS
–
–
2
4
3.5
7
mA GH1 or GH2 = H
mA GH1 and GH2 = H
Under Voltage Lockout (UVLO)
Switch-ON voltage
Switch-OFF voltage
VUVON
–
5.4
4.3
1.1
7
–
–
V
V
V
VS increasing
VS decreasing
VUVOFF
3.5
–
Switch ON/OFF hysteresis VUVHY
VUVON – VUVOFF
Over Voltage Lockout (OVLO)
Switch-OFF voltage
Switch-ON voltage
VOVOFF
VOVON
36
35
–
38
43
–
V
V
V
VS increasing
VS decreasing
37.3
0.7
Switch OFF/ON hysteresis VOVHY
–
VOVOFF – VOVON
Short Circuit of Highside Switch to GND
Initial peak SC current
Initial peak SC current
Initial peak SC current
ISCP
ISCP
ISCP
8
10
8.5
5
13
11
7
A
A
A
Tj = – 40 °C
Tj = 25 °C
6.5
3.9
Tj = 150 °C
Semiconductor Group
11
1999-01-07
BTS 770 G
Electrical Characteristics (cont’d)
SH1 = ISH2 = ISL1 = ISL2 = 0 A; – 40 °C < Tj < 150 °C; 8 V > VS > 18 V
I
unless otherwise specified
Parameter
Symbol
Limit Values
Unit Test Condition
min. typ. max.
Short Circuit of Highside Switch to VS
OFF-state
examiner-voltage
VEO
RO
2
3
4
V
VGH = 0 V
Output pull-down-resistor
4
11
30
kΩ
–
Open Circuit Detection of Highside Switch
Detection current
IOCD
10
90
200
mA
–
Switching Times of Highside Switch
Switch-ON-time;
to 90% VSH
tON_H
–
–
0.2
0.4
ms
ms
resistive load
ISH = 1 A; VS = 12 V
Switch-OFF-time;
tOFF_H
0.15 0.4
resistive load
to 10% VSH
ISH = 1 A; VS = 12 V
Control Inputs of Highside Switches GH 1, 2
H-input voltage
VGHH
VGHL
VGHHY
IGHH
IGHL
–
2.8
2.3
0.5
60
25
3.5
–
3.5
–
V
–
L-input voltage
1.5
–
V
–
Input voltage hysterese
H-input current
–
V
–
20
1
90
50
6
µA
µA
kΩ
V
VGH = 5 V
VGH = 0.4 V
–
L-input current
Input series resistance
Zener limit voltage
RI
2.5
5.4
VGHZ
–
IGH = 1.6 mA
Status Flag Output ST of Highside Switch
Low output voltage
Leakage current
VSTL
ISTLK
VSTZ
–
0.25 0.6
V
IST = 1.6 mA
VST = 5 V
–
0.5
–
10
–
µA
V
Zener-limit-voltage
5.4
IST = 1.6 mA
Semiconductor Group
12
1999-01-07
BTS 770 G
Electrical Characteristics (cont’d)
SH1 = ISH2 = ISL1 = ISL2 = 0 A; – 40 °C < Tj < 150 °C; 8 V > VS > 18 V
I
unless otherwise specified
Parameter
Symbol
Limit Values
Unit Test Condition
min. typ. max.
Control Inputs of Lowside Switches GL1, 2
Gate-threshold-voltage
Transconductance
VGL(th)
gfs
0.8
–
1.6
5
2.5
–
V
S
VGL = VDSL;
IDL = 1 mA
DSL = 20 V;
V
IDL = 20 A
Switching Times of Lowside Switch
Switch-ON delay time;
VGS = 5 V; RGS = 50Ω
td_ON_L
tON_L
td_OFF_L
tOFF_L
–
–
–
–
25
40
ns
ns
ns
ns
resistive load
ISL = 1 A; VS = 12 V
Switch-ON time;
VGS = 5 V; RGS = 50Ω
95
140
190
115
resistive load
ISL = 1 A; VS = 12 V
Switch-OFF delay time;
VGS = 5 V; RGS = 50Ω
140
85
resistive load
ISL = 1 A; VS = 12 V
Switch-OFF time;
resistive load
VGS = 5 V; RGS = 50Ω
ISL = 1 A; VS = 12 V
Thermal Shutdown
Thermal shutdown junction TjSD
temperature
155
150
–
–
190
180
–
°C
°C
°C
–
Thermal switch-on junction TjSO
temperature
–
–
Temperature hysteresis
∆T
10
∆T = TjSD – TjSO
Semiconductor Group
13
1999-01-07
BTS 770 G
Electrical Characteristics (cont’d)
SH1 = ISH2 = ISL1 = ISL2 = 0 A; – 40 °C < Tj < 150 °C; 8 V > VS > 18 V
I
unless otherwise specified
Parameter
Symbol
Limit Values
Unit Test Condition
min. typ. max.
Output Stages
Leakage current
of highside switch
IHSLK
ILSLK
VFH
–
–
–
5
12
µA
µA
V
VGH = VSH = 0 V
Leakage current
of lowside switch
20
0.8
100
1.5
VGL = 0 V
VDS = 18 V
Clamp-diode
IFH = 3 A
of highside switch;
Forward-Voltage
Clamp-diode leakage-
current (IFH + ISH)
of highside switch
ILKCL
–
–
–
–
–
2
10
mA IFH = 3 A
Clamp-diode
of lowside switch;
forward-voltage
VFL
0.8
1.5
V
IFL = 3 A
Static drain-source
on-resistance
of highside switch
RDS ON H
RDS ON L
RDS ON
165 220 mΩ ISH = 1 A
Tj = 25 °C
Static drain-source
on-resistance
of lowside switch
45
–
65
mΩ ISL = 1 A;
VGL = 5 V
Tj = 25 °C
Static path on-resistance
500
mΩ
R
DS ON H + RDS ON L
;
ISH = 1 A
Note: The listed characteristics are ensured over the operating range of the integrated
circuit. Typical characteristics specify mean values expected over the production
spread. If not otherwise specified, typical characteristics apply at TA = 25 °C and
the given supply voltage.
Semiconductor Group
14
1999-01-07
BTS 770 G
Ι S
+ VS
CS
470nF
CL
100 µF
Ι FH1, 2
DHVS
Ι ST, Ι STLK
ST
8
5, 10, 19, 24
DST
C6V1
Diagnosis
Driver
Biasing and Protection
VDSH2
-VFH2
VDSH1
-VFH1
RI1
Ι GH1
GH1 7
IN
OUT
VST
VSTL
VSTZ
3.5 kΩ
1
0
0
1
1
2
0
1
0
1
1
L
2
L
DI1
C6V1
RO1
RO2
Ι SH2
20 SH2
21
RI2
L
H
H
H
L
H
Ι GH2
VUVON
VUVOFF
VOVON
VOVOFF
GH2
GND
9
6
10 kΩ
10 kΩ
VGH1
Ι DL2
Ι LKL
Ι SH1
3.5 kΩ
12, 14, 15, 18 DL2
DI2
C6V1
VGH2
22, 23 SH1
Ι GND
Ι LKCL1, 2
Ι DL1
Ι LKL
1, 3, DL1
25, 28
GL1 2
VGL1
VGL(th)1
VEO1
VDSL1
-VFL1
VEO2
VDSL2
-VFL2
GL2 13
VGL2
VGL(th)2
26, 27
SL1
16, 17
SL2
Ι SL1
Ι SL2
VDSH
VDSL
RDSONH
=
RDSONL =
AES02079
Ι SH
Ι SL
Figure 3 Test Circuit
HS-Source-Current Named during
Short Circuit
Named during
Open Circuit
Named during
Leakage-Cond.
ISH1,2
ISCP
IOCD
IHSLK
Semiconductor Group
15
1999-01-07
BTS 770 G
Watchdog
Reset
Q
I
VS = 12 V
TLE 4268G
DO1
D
GND
RQ
100 kΩ
CQ
22
CD
100nF
CS
22
F
µF
WD
R VCC
DHVS
RS
ST
8
5, 10, 19, 24
10 kΩ
DST
C6V1
Diagnosis
Driver
Biasing and Protection
RI1
GH1 7
IN
OUT
3.5 kΩ
1
0
0
1
1
2
0
1
0
1
1
L
L
H
H
2
L
H
L
DI1
C6V1
RO1
RO2
20 SH2
21
RI2
GH2 9
GND 6
GL1 2
10 kΩ
10 kΩ
µ
P
12, 14, 15, 18 DL2
22, 23 SH1
3.5 kΩ
H
DI2
C6V1
M1
1, 3, DL1
25, 28
GL2 13
26, 27
SL1
16, 17
SL2
AES02074
Figure 4 Application Circuit
Semiconductor Group
16
1999-01-07
BTS 770 G
Package Outlines
P-DSO-28-9
(Plastic Dual Small Outline Package)
0.35 x 45˚
1)
7.6 -0.2
+0.09
0.23
8˚ max
0.4 +0.8
10.3 ±0.3
1.27
0.35 +0.152)
0.1
0.2 28x
28
15
14
1
1)
18.1-0.4
Index Marking
1) Does not include plastic or metal protrusions of 0.15 max rer side
2) Does not include dambar protrusion of 0.05 max per side
GPS05123
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
Dimensions in mm
1999-01-07
SMD = Surface Mounted Device
Semiconductor Group
17
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