BTG7050-1EPL [INFINEON]
The BTG7050-1EPL, as part of the PROFET™ Load Guard family, is a single channel smart high-side power switch, providing protection functions and enhanced diagnostic capabilities. It is equipped with adjustable overcurrent limitation to offer high reliability for protecting the system: In case of a short circuit to ground, the PCB traces, connectors, as well as loads, can be protected. Furthermore, the BTG7050-1EPL has a capacitive load switching mode implemented to charge big capacitive loads and to reduce current peaks during switch on of capacitors. By these features, the device addresses different use cases for intelligent power distribution (load supply protection, wire protection and power supply protection) and a broad range of applications.;
| 型号： | BTG7050-1EPL |
| 厂家： | 
Infineon |
| 描述： | The BTG7050-1EPL, as part of the PROFET™ Load Guard family, is a single channel smart high-side power switch, providing protection functions and enhanced diagnostic capabilities. It is equipped with adjustable overcurrent limitation to offer high reliability for protecting the system: In case of a short circuit to ground, the PCB traces, connectors, as well as loads, can be protected. Furthermore, the BTG7050-1EPL has a capacitive load switching mode implemented to charge big capacitive loads and to reduce current peaks during switch on of capacitors. By these features, the device addresses different use cases for intelligent power distribution (load supply protection, wire protection and power supply protection) and a broad range of applications. PC |
| 文件： | 总52页 (文件大小：913K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
BTG7050-1EPL
Datasheet
™
PROFET Load Guard
Smart high-side power switch
Features
• High-side switch with diagnosis and embedded protection
™
• Part of PROFET Load Guard family
• Switch ON capability while inverse current condition (InverseON)
• Capacitive load switching mode
• Green product (RoHS compliant)
Potential applications
• Replaces electromechanical relays, fuses and discrete circuits
• Protection of system supply
• Main switch for ECU power supply
• Suitable for driving resistive, inductive and capacitive loads
• Suitable for driving heating elements
• Suitable for driving ADAS & AD modules, e.g. cameras, radar, ultrasonic, and LIDAR modules
• Suitable for driving sub modules, e.g. displays
Product validation
Qualified for automotive applications.
Product validation according to AEC-Q100, Grade 1.
Description
™
The PROFET Load Guard is a Smart High Side Switch, providing protection functions and enhanced diagnosis capabilities. The
device offers an adjustable current limitation to offer higher reliability for protecting the system. In case of an short circuit to
™
ground the PCB traces, connectors, as well as loads, can be protected. Furthermore, the PROFET Load Guard has an capacitive
load switching mode implemented to charge capacitors.
VBAT
ZWIRE
Optional
Logic Supply
CVS
CVSGND
T1
RGND
GND
VS
OCT
OUT
VDD
GPIO
GPIO
RIN
IN
RDEN
DEN
COUT
CVS2
DZ2
Optional
RES
ADC
RADC
RIS_PROT
IS
COUT
VSS
CSENSE
Optional
Logic GND
Power GND
Chassis GND
Further information in Chapter 9
Datasheet
www.infineon.com
Please read the sections "Important notice" and "Warnings" at the end of this document
Rev.1.00
2022-09-20
BTG7050-1EPL
Datasheet
Description
Parameter
Symbol
VS(OP)
Values
3 V
Minimum operating voltage
Minimum operating voltage (cranking)
Maximum operating voltage
VS(UV)
2.7 V
VS
28 V
Minimum overvoltage protection (TJ ≥ 25°C)
Maximum current in sleep mode (TJ ≤ 85°C)
Maximum operative current
VDS(CLAMP)_25
IVS(SLEEP)_85
IGND(ACTIVE)
RDS(ON)_25
RDS(ON)_150
IL(NOM)
35 V
0.5 µA
4.5 mA
50 mΩ
100 mΩ
3 A
Typical ON-state resistance (TJ = 25°C)
Maximum ON-state resistance (TJ = 150°C)
Nominal load current (TA = 85°C)
Typical current sense ratio at IL = IL(NOM)
Adjustable overcurrent limitation
kILIS
2030
ILIM
0.79 A - 8.86 A
Diagnostic features
• Proportional load current sense
• Open load in ON and OFF state
• Short circuit to ground and battery
Protection features
• Absolute and dynamic temperature protection with restart control
• Adjustable overcurrent limitation
• Overvoltage protection
Type
Package
Marking
BTG7050-1EPL
PG-TSDSO-14
7050-1L
Datasheet
2
Rev.1.00
2022-09-20
BTG7050-1EPL
Datasheet
Table of contents
Table of contents
Table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1
1.1
1.2
Block diagram and terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
2
2.1
2.2
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
3
3.1
3.2
3.3
3.3.1
3.3.2
General product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Functional range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
PCB setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Thermal impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4
4.1
I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Digital I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Input pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Diagnosis pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Analog I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Adjustable overcurrent threshold pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Electrical characteristics I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1.1
4.1.2
4.2
4.2.1
4.3
5
5.1
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Operation modes and transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Unsupplied . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Sleep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Inactive with diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Active with diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Active without diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Capacitive load switching mode with diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Capacitive load switching mode without diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Undervoltage on VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Electrical characteristics power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
5.1.1
5.1.1.1
5.1.1.2
5.1.1.3
5.1.1.4
5.1.1.5
5.1.1.6
5.1.1.7
5.1.1.8
5.2
5.3
6
6.1
6.2
6.2.1
6.2.2
Power Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Output ON-state resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Switching loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Switching resistive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Switching inductive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
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Datasheet
Table of contents
6.2.3
6.3
6.3.1
6.4
Switching capacitive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Advanced switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Inverse current behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Electrical characteristics power stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7
7.1
7.1.1
7.2
7.3
Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Adjustable overcurrent threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Overtemperature protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Protection and diagnosis in case of fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Retry strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Additional protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Reverse polarity protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Loss of battery and loss of load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Loss of ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Electrical characteristics protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.3.1
7.4
7.4.1
7.4.2
7.4.3
7.4.4
7.5
8
8.1
Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
SENSE signal truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Diagnosis in ON state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Current sense (kILIS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Fault current (IIS(FAULT)) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Diagnosis in OFF State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Open load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
OCT pin fault current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
SENSE timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Electrical characteristics diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.1.1
8.2
8.2.1
8.2.2
8.3
8.3.1
8.3.2
8.4
8.5
9
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
10
11
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Datasheet
1 Block diagram and terms
1
Block diagram and terms
1.1
Block diagram
VS
Supply voltage
monitoring
Channel
Overvoltage
protection
Voltage sensor
T
Overtemperature
Internal power
supply
Overvoltage
clamping
Gate control
+
Driver
Chargepump
Restart control
SENSE output
Overcurrent
logic
limitation
IS
Capacitive load
InverseON
switching
OUT
IN
DEN
OCT
Load current sense
ESD protection
+
I/O
Reverse polarity
protection and
GND circutry
GND
Figure 2
Block diagram of BTG7050-1EPL
Datasheet
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Datasheet
1 Block diagram and terms
1.2
Terms
Figure 3 shows all terms used in this data sheet, with associated convention for positive values.
IVS
VSIS
VDS
IIN
VS
IN
IDEN
VIN
DEN
IL
VS
IIS
OUT
VDEN
IS
IOCT
VIS
OCT
GND
VOCT
VOUT
IGND
Figure 3
Voltage and current convention
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2 Pin configuration
2
Pin configuration
2.1
Pin assignment
GND
IN
1
2
3
4
5
6
7
14
13
12
11
10
9
OUT
OUT
OUT
n.c.
DEN
IS
VS
n.c.
n.c.
OCT
RES
RES
RES
exposed pad
(bottom)
8
Figure 4
Pin configuration
2.2
Pin definitions and functions
Table 1
Pin definition
Pin
Symbol
Function
EP
VS (exposed
pad)
Supply Voltage
Battery voltage
1
2
GND
Ground
Ground connection for the internal logic
IN
Input Channel
Digital signal to switch ON the channel ("high" active)
If not used: Connect with a 10kΩ resistor either to GND pin or to module ground
3
DEN
Diagnostic Enable
Digital signal to enable device diagnosis ("high" active) and to clear the protection
counter
If not used: Connect with a 10kΩ resistor either to GND pin or to module ground
4
7
IS
SENSE current output
Analog/digital signal for diagnosis
If not used: Lef open
OCT
Adjustable overcurrent threshold
A resistor ROCT needs to be connected between OCT pin and GND pin to adjust the
overcurrent threshold
If not used: Threshold selection as described in Chapter 7.1.1
5, 6, 11
12-14
n.c.
Not connected, internally not bonded
OUT
Output
Protected high-side power output channel 1)
(table continues...)
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Datasheet
2 Pin configuration
Table 1
(continued) Pin definition
Pin
Symbol
Function
8-10
RES
RESERVED
It is recommended to connect these pins to VS or with a capacitor COUT to GND
1) All output pins of the channel must be connected together on the PCB. All pins of the output are internally
connected together. PCB traces have to be designed to withstand the maximum current which can flow.
Datasheet
8
Rev.1.00
2022-09-20
BTG7050-1EPL
Datasheet
3 General product characteristics
3
General product characteristics
Absolute maximum ratings
3.1
TJ = -40°C to +150°C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Table 2
Absolute maximum ratings
Parameter
Symbol
Min.
Values
Typ.
Unit
Note or condition
P-
Number
Max.
Supply pins
2)
Power supply voltage VS
-0.3
–
–
28
V
V
PRQ-34
PRQ-36
-
2)
Load dump voltage
VBAT(LD)
–
35
suppressed load dump
acc. to ISO16750-2
(2010). Ri = 2 Ω
2)
Supply voltage for
VBAT(SC)
0
–
–
–
24
16
V
V
PRQ-38
PRQ-40
short circuit protection
Setup acc. to AEC-
Q100-012
2)
Reverse polarity
voltage
-VBAT(REV)
t ≤ 2min
TA = +25°C
Setup as described
in Chapter 9
2)
Current through GND
pin
IGND
-50
–
50
mA
PRQ-44
RGND according
to Chapter 9
Logic & control pins (Digital Input = DI)
DI = IN, DEN
2) 1)
Current through DI pin IDI
-1
-1
–
–
2
mA
mA
PRQ-47
PRQ-48
2) 1)
Current through DI
pin - Reverse battery
condition
IDI(REV)
10
t ≤ 2 min
Analog & control pin (Analog Input = AI)
AI = OCT
2) 1)
Current through AI pin IAI
-1
-1
–
–
2
mA
mA
PRQ-60
PRQ-61
2) 1)
Current through AI
pin - Reverse battery
condition
IAI(REV)
10
t ≤ 2 min
(table continues...)
Datasheet
9
Rev.1.00
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BTG7050-1EPL
Datasheet
3 General product characteristics
Table 2
(continued) Absolute maximum ratings
Parameter
Symbol
Values
Typ.
Unit
Note or condition
P-
Number
Min.
Max.
IS pin
2)
Voltage at IS pin
VIS
-1.5
–
VS
V
PRQ-50
PRQ-52
IIS = 10 μA
2)
Current through IS Pin IIS
-25
–
IIS(SAT),M mA
AX
-
Temperatures
2)
Junction temperature TJ
-40
-55
–
–
+150
+150
°C
°C
PRQ-53
PRQ-54
-
2)
Storage temperature
TSTG
-
ESD susceptibility
2)
ESD Susceptibility all
pins (HBM)
VESD(HBM)
-2
-4
–
–
2
4
kV
kV
PRQ-55
PRQ-56
HBM3)
2)
ESD Susceptibility
OUTn vs GND and VS
connected (HBM)
VESD(HBM)_OUT
HBM3)
2)
ESD Susceptibility all
pins (CDM)
VESD(CDM)
-500
-750
–
–
500
750
V
V
PRQ-57
PRQ-58
CDM4)
2)
ESD Susceptibility
corner pins (CDM) -
(pins 1, 7, 8, 14)
VESD(CDM)_CRN
CDM4)
Power stage
2)
Maximum energy
dissipation - single
pulse
EAS
–
–
–
–
12
mJ
mJ
PRQ-766
PRQ-767
IL = 2⋅IL(NOM)
TJ(0) = 150°C
VS = 28 V
2)
Maximum energy
dissipation - repetitive
pulse
EAR
2.5
IL = IL(NOM)
TJ(0) = 85°C
VS = 13.5 V
1M cycles
2)
Load current
|IL|
–
–
ILIM,MAX
A
PRQ-768
–
1)
2)
3)
4)
Maximum VDI to be considered for Latch-Up tests: 5.5 V
Not subject to production test - specified by design
ESD susceptibility, Human Body Model “HBM”, according to AEC Q100-002
ESD susceptibility, Charged Device Model “CDM”, according to AEC Q100-011
Datasheet
10
Rev.1.00
2022-09-20
BTG7050-1EPL
Datasheet
3 General product characteristics
Notes
1.
Stresses above the ones listed here may cause permanent damage to the device. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Integrated protection functions are designed to prevent IC destruction under fault conditions described in
the datasheet. Fault conditions are considered as “outside” normal operating range. Protection functions
are not designed for continuous repetitive operation.
2.
3.2
Functional range
Table 3
Functional range
Symbol
Parameter
Values
Typ.
Unit
Note or condition
P-
Number
Min.
Max.
20
1)
Supply voltage range
for normal operation
VS(NOR)
4
13.5
V
V
PRQ-66
–
1)
2)
3)
Lower extended supply VS(EXT,LOW)
voltage range for
operation (normal)
2.7
–
4
PRQ-67
(parameter deviations
possible)
1)
Upper extended supply VS(EXT,UP)
voltage range for
20
–
–
28
V
PRQ-68
PRQ-69
3)
operation
(parameter deviations
possible)
1)
Junction temperature TJ
-40
+150
°C
–
1)
2)
Not subject to production test - specified by design
In case of VS voltage decreasing refer to the maximum voltage of VS(UV), in case of VS voltage increasing refer to the maximum voltage of
VS(OP)
3)
Protection functions still operative
Note
Within the functional or operating range, the IC operates as described in the circuit description. The electrical
characteristics are specified by the conditions given in the Electrical Characteristics tables.
3.3
Thermal resistance
Thermal resistance
Symbol
Table 4
Parameter
Values
Typ.
Unit
Note or condition
P-
Number
Min.
Max.
7.5
1)
2)
Thermal
Ψ
–
4.4
K/W
PRQ-623
JTOP
characterization
parameter junction-top
(table continues...)
Datasheet
11
Rev.1.00
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BTG7050-1EPL
Datasheet
3 General product characteristics
Table 4
(continued) Thermal resistance
Parameter
Symbol
Values
Typ.
Unit
Note or condition
P-
Number
Min.
Max.
8.6
1)
2)
Thermal resistance
junction-to-case
RthJC
–
–
5.1
K/W
PRQ-624
simulated at exposed
pad
1)
Thermal resistance
junction-to-ambient
RthJA
33.5
–
K/W
PRQ-625
2)
1)
2)
Not subject to production test - specified by design
According to JEDEC JESD51-2,-5,-7 at natural convection on FR4 2s2p board; the Product (Chip + Package) was simulated on a 76.2 ×
114.3 × 1.5 mm board with 2 inner copper layers (2 × 70 µm Cu, 2 × 35 µm Cu). Where applicable a thermal via array under the exposed
pad contacted the first inner copper layer. Simulation done at TA = 105°C, PDISSIPATION = 1 W
Note
This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go to
www.jedec.org.
3.3.1
PCB setup
70 µm modeled (traces, cooling area)
70 µm, 5% metalization*
*: means percentual Cu metalization on each layer
Figure 5
Figure 6
1s0p PCB cross section
70 µm modeled (traces)
35 µm, 90% metalization*
35 µm, 90% metalization*
70 µm, 5% metalization*
0.25mm ≤ A ≤ 0.5 mm
*: means percentual Cu metalization on each layer
2s2p PCB cross section
Datasheet
12
Rev.1.00
2022-09-20
BTG7050-1EPL
Datasheet
3 General product characteristics
PCB 1s0p + 600 mm² cooling
PCB 2s2p / 1s0p footprint
Figure 7
PCB setup for thermal simulations
Figure 8
Thermal vias on PCB for 2s2p PCB setup
Datasheet
13
Rev.1.00
2022-09-20
BTG7050-1EPL
Datasheet
3 General product characteristics
3.3.2
Thermal impedance
BTG7050-1EPL
100
10
1
2s2p
1s0p - 600 mm²
1s0p - 300 mm²
1s0p - footprint
0.1
0.0001
0.001
0.01
0.1
1
10
100
1000
Time (s)
Figure 9
Typical thermal impedance. PCB setup according to PCB setup
BTG7050-1EPL
130
120
110
100
90
1s0p - Ta = 105°C
80
70
60
50
40
30
0
100
200
300
400
500
600
Cooling area (mm²)
Figure 10
Thermal resistance on 1s0p PCB with various cooling surfaces
Datasheet
14
Rev.1.00
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BTG7050-1EPL
Datasheet
4 I/O pins
4
I/O pins
The device has two digital pins for direct control.
4.1
Digital I/O pins
Digital input (DI) pins = IN, DEN
4.1.1
Input pins
The input pin IN activates the output channel. The input circuitry is compatible with a 3.3 V and a 5 V microcontroller.
The electrical equivalent of the input circuitry is shown in Figure 11. In case the pin is not used, it must be connected
by a 10 kΩ resistor either to GND pin or to module ground.
VS
DI
VS(CLAMP)
IDI
IDI
ESD
VDI(CLAMP)
VDI
GND
IGND
Figure 11
Input circuitry
The logic thresholds for “low” and “high” states are defined by parameters VDI(TH) and VDI(HYS). The
relationship between these two values is shown in Figure 12.
VDI
VDI(TH),MAX
VDI(TH)
VDI(HYS)
VDI(TH),MIN
t
t
Internal channel
activation signal
0
x
1
x
0
Figure 12
Input threshold voltages and hysteresis
Datasheet
15
Rev.1.00
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BTG7050-1EPL
Datasheet
4 I/O pins
4.1.2
Diagnosis pins
The Diagnosis Enable (DEN) pin controls the diagnosis circuitry and the protection circuitry. When DEN pin is set to
“high”, the diagnosis is enabled (see Chapter 8.2 for more details). When it is set to “low”, the diagnosis is disabled (IS
pin is set to high impedance). See Figure 12 for more details.
The transition from “high” to “low” of DEN pin clears the protection latch of the channel depending on the logic state
of IN pin and DEN pulse length (see Chapter 7.3 for more details).
4.2
Analog I/O pins
Analog input (AI) pins = OCT
4.2.1
Adjustable overcurrent threshold pin
To be able to adjust the overcurrent limitation for the OUT pin, the device offers an OCT pin. The pin needs to be
connected to device ground via an external resistor ROCT. The adjustable current limit allows the flexibility to adjust
the overcurrent limitation as defined in Table 10. This improves the reliability of the system by limiting the inrush or
overload current. The electrical equivalent of the overcurrent pin circuit circuitry is shown in Figure 13.
VS
AI decoder
A
VOCT
AI
VS(CLAMP)
IOCT
ESD
VAI(CLAMP)
GND
Figure 13
Adjustable overcurrent threshold pin circuitry
4.3
Electrical characteristics I/O pins
VS = 4 V to 20 V, TJ = -40°C to +150°C
Unless otherwise specified typical values: VS = 13.5 V, TJ = 25°C
Digital input (DI) pins = IN, DEN
Analog input (AI) pins = OCT
Datasheet
16
Rev.1.00
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BTG7050-1EPL
Datasheet
4 I/O pins
Table 5
Electrical characteristics I/O pins
Parameter
Symbol
Values
Typ.
Unit
Note or condition
P-
Number
Min.
Max.
DI pins
Digital input voltage
threshold
VDI(TH)
0.8
1.3
2
–
V
V
See Figure 11 and
Figure 12
PRQ-76
PRQ-77
1)
Digital input clamping VDI(CLAMP1)
voltage
–
7
IDI = 1 mA
See Figure 11 and
Figure 12
Digital input clamping VDI(CLAMP2)
6.5
–
7.5
0.25
10
8.5
–
V
IDI = 2 mA
See Figure
11 and Figure 12
1)
PRQ-78
PRQ-80
PRQ-81
PRQ-82
voltage
Digital input hysteresis VDI(HYS)
V
See Figure 11 and
Figure 12
Digital input current
("high")
IDI(H)
2
25
25
µA
µA
VDI = 2 V
See Figure 11 and
Figure 12
Digital input current
("low")
IDI(L)
2
10
VDI = 0.8 V
See Figure 11 and
Figure 12
AI pins
1)
Analog input clamping VAI(CLAMP1)
voltage
–
7
–
V
PRQ-88
IOCT = 1 mA
See Figure 13
Analog input clamping VAI(CLAMP2)
6.5
7.5
0.5
8.5
V
V
IOCT = 2 mA
See Figure 13
1)
PRQ-630
PRQ-628
voltage
Analog overcurrent
voltage threshold
VOCT
0.44
0.56
IOCT,MIN ≤ IOCT ≤ IOCT,MAX
INn = "high" or DEN =
"high"
1)
Analog linear
IOCT
20
–
–
228
–
μA
μA
PRQ-89
PRQ-91
overcurrent range
INn = "high" or DEN =
"high"
2)
OCT short to device
ground detection
current
IOCT(SHORT2GND) 320
DEN = "high"
INn = "low"
(table continues...)
Datasheet
17
Rev.1.00
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BTG7050-1EPL
Datasheet
4 I/O pins
Table 5
(continued) Electrical characteristics I/O pins
Parameter
Symbol
Values
Typ.
Unit
Note or condition
P-
Number
Min.
Max.
2)
OCT open detection
current
IOCT(OPEN)
–
–
5
μA
PRQ-619
DEN = "high"
INn = "low"
1)
2)
Not subject to production test - specified by design
Functional test only
Datasheet
18
Rev.1.00
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BTG7050-1EPL
Datasheet
5 Power Supply
5
Power Supply
The device is supplied by VS, which is used to supply the internal logic as well as to supply the power output stages.
In case of an undervoltage condition, the device has an detection circuit, which prevents the activation of the power
output stage as well as the diagnosis.
5.1
Operation modes and transitions
Operation modes
5.1.1
The device has the following operation modes:
•
•
•
•
•
•
Sleep
Inactive with diagnosis
Active with diagnosis
Active without diagnosis
Capacitive load switching mode with diagnosis
Capacitive load switching mode without diagnosis
The transition between operation modes is determined according to these variables:
•
•
•
Logic level at IN pin
PWM signal at IN pin
Logic level at DEN pin
The state diagram including the possible transitions is shown in Figure 14. The behavior of the device as well as some
parameters may change independent from the operation mode of the device. Furthermore, due to the undervoltage
detection circuitry which monitors VS supply voltage, some changes within the same operation mode can be seen
accordingly.
Table 6 shows the correlation between operation modes, VS supply voltage, and the state of the most important
functions (channel status).
IN=“low“ & DEN=“low“
IN=“fVIN(CLS)“ & DEN=“high“
Power-up
Unsupplied
IN=“fVIN(CLS)“ & DEN=“high“
IN=“low“ & DEN=“high“
IN=“low“ & DEN=“low“
IN=“low“ & DEN=“low“
Inactive with Diag
Sleep
IN=“low“ & DEN=“high“
IN=“fVIN(CLS)“ & DEN=“low“
IN=“high“ & DEN=“high“
IN=“low“ & DEN=“low“
IN=“high“ &
DEN=“high“
IN=“low“ &
DEN=“high“
IN=“low“ &
DEN=“low“
IN=“high“ &
DEN=“low“
IN=“fVIN(CLS)“ &
IN=“high“ &
IN=“high“ & DEN=“high“
IN=“high“ & DEN=“low“
DEN=“high“
DEN=“low“
Capacitive Load
Switching with Diag
Capacitive Load
Switching without Diag
Active with Diag
Active without Diag
IN=“high“ &
DEN=“high“
IN=“fVIN(CLS)“ &
DEN=“low“
IN=“fVIN(CLS)“ & DEN=“high“
IN=“fVIN(CLS)“ & DEN=“low“
Figure 14
Table 6
Operation mode state diagram
Operation mode, device function and VS voltage
Operation mode
Function
Channels
Diagnosis
VS > VS(OP)
VS < VS(OP)
OFF
Sleep
OFF
OFF
OFF
(table continues...)
Datasheet
19
Rev.1.00
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BTG7050-1EPL
Datasheet
5 Power Supply
Table 6
(continued) Operation mode, device function and VS voltage
Operation mode
Function
Channels
Diagnosis
Channels
Diagnosis
Channels
Diagnosis
Channels
Diagnosis
Channels
Diagnosis
VS > VS(OP)
VS < VS(OP)
OFF
Inactive with diagnosis
OFF
ON
ON
ON
ON
OFF
ON
ON
ON
OFF
OFF
Active with diagnosis
OFF
OFF
Active without diagnosis
OFF
OFF
Capacitive load switching mode with
diagnosis
OFF
OFF
Capacitive load switching mode without
diagnosis
OFF
OFF
5.1.1.1
Unsupplied
In this state the device supply voltage is below the undervoltage threshold VS(UV)
.
5.1.1.2
Power-up
The power-up transition is entered when the supply voltage (VS) is applied to the device. The supply rises until it
exceeds the undervoltage threshold VS(OP)
.
5.1.1.3
Sleep
The device is in sleep mode when digital input (DI) pins are set to "low". While in sleep mode the current consumption
is at IVS(SLEEP). Overtemperature, overload protection and undervoltage mechanism are disabled. The device can go
in sleep mode only if the protection is not active (nRESTART(CR) = 0, TJ < TJ(ABS) and (TJ - TJ(REF)) < TJ(DYN) (including
hysteresis)), see Chapter 7.3.
5.1.1.4
Inactive with diagnosis
The device is in inactive with diagnosis mode while DEN pin is set to “high” and input pins are set to “low”. The
channels are OFF, therefore open load in OFF diagnosis is possible. Depending on the load condition, either a
fault current IIS(FAULT) or an open load in OFF current IIS(OLOFF) may be present at IS pin. During such condition, the
current consumption of the device is increased.
5.1.1.5
Active with diagnosis
Active with diagnosis mode is the normal operation mode of the device. The device enters active with diagnosis mode
for the channel when IN = "high" and DEN = "high", in this condition the output is switched ON with diagnosis. Device
current consumption is specified by parameter IGND(ACTIVE)
.
5.1.1.6
Active without diagnosis
The device is in active without diagnosis mode when IN = "high" and DEN = "low", in this condition the output is
switched ON without diagnosis.
5.1.1.7
Capacitive load switching mode with diagnosis
The device has a capacitive load switching mode implemented to drive capacitive loads. The capacitive load
switching mode with diagnosis can be activated with IN = "fVIN(CLS)" and DEN = "high", in this condition the output is
switched ON with diagnosis. Device current consumption is specified by parameter IGND(ACTIVE)
.
Datasheet
20
Rev.1.00
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BTG7050-1EPL
Datasheet
5 Power Supply
5.1.1.8
Capacitive load switching mode without diagnosis
The device is in capacitive load switching mode without diagnosis when IN = "fVIN(CLS)" and DEN = "low", in this
condition the output is switched ON without diagnosis.
5.2
Undervoltage on VS
Between VS(OP) and VS(UV) the undervoltage mechanism is triggered.
The power output stage follows the input logic as long as VS > VS(OP)
.
If the device is Active or in Capacitive Load Switching Mode, with or without Diagnosis and the supply voltage VS drops
below the undervoltage threshold VS(UV), the internal logic switches OFF the output channel.
VS
VS(OP)
VS(HYS)
VS(UV)
t
INn
t
VOUTn
t
Figure 15
VS undervoltage behavior
5.3
Electrical characteristics power supply
VS = 4 V to 20 V, TJ = -40°C to +150°C
Unless otherwise specified typical values: VS = 13.5 V, TJ = 25°C
Typical resistive loads connected to the outputs for testing (unless otherwise specified):
BTG7050-1EPL: RL = 4.7 Ω
Table 7
Electrical characteristics power supply
Parameter
Symbol
Values
Unit
Note or condition
P-
Number
Min.
Typ.
Max.
VS pin
Power supply
undervoltage
shutdown
VS(UV)
1.8
2.2
2.7
V
VS decreasing
INn = “high”
PRQ-98
From 0 ≤ VDS ≤ 0.5 V to
VDS ∼ VS
See Figure 15
(table continues...)
Datasheet
21
Rev.1.00
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BTG7050-1EPL
Datasheet
5 Power Supply
Table 7
(continued) Electrical characteristics power supply
Parameter
Symbol
Values
Typ.
Unit
Note or condition
P-
Number
Min.
2.1
Max.
Power supply
minimum operating
voltage
VS(OP)
2.5
3
–
V
VS increasing
INn = “high”
PRQ-99
From VDS ∼ VS to
0 ≤ VDS ≤ 0.5 V
See Figure 15
1)
Power supply
undervoltage
shutdown hysteresis
VS(HYS)
–
0.3
–
V
PRQ-100
PRQ-101
PRQ-776
VS(OP) - VS(UV)
See Figure 15
1)
Breakdown voltage
between GND and VS
pins in reverse battery
-VS(REV)
16
–
30
V
IGND(REV) = 7 mA
TJ = 150°C
1)
Power supply current IVS(SLEEP)_85
consumption in sleep
mode with loads at TJ
≤ 85°C
0.03
0.5
μA
VS = 20 V
VOUT = 0 V
IN = DEN = “low”
TJ ≤ 85°C
Power supply current IVS(SLEEP)_150
consumption in sleep
mode with loads at TJ
= 150°C
–
3.5
14
μA
VS = 20 V
VOUT = 0 V
IN = DEN = “low”
TJ = 150°C
PRQ-777
Operating current in
active with diagnosis
mode
IGND(ACTIVE)
–
–
3.7
1.8
4.5
2.2
mA
mA
VS = 20 V
IN = DEN = “high”
PRQ-778
PRQ-779
Operating current in
inactive with diagnosis
mode
IGND(INACTIVE)
VS = 20 V
INn = "low"
DEN = “high”
IOCT = IOCT,MAX
1)
Not subject to production test - specified by design
Datasheet
22
Rev.1.00
2022-09-20
BTG7050-1EPL
Datasheet
6 Power Stage
6
Power Stage
The high-side power stages are built using a N-channel vertical power MOSFET with charge pump.
6.1
Output ON-state resistance
The ON-state resistance RDS(ON) depends mainly on junction temperature TJ. Figure 16, shows the variation
of RDS(ON) across the whole TJ range. The value “2” on the y-axis corresponds to the maximum RDS(ON) measured
at TJ = 150°C.
RDS(ON) variation over TJ
2.20
2.00
1.80
1.60
1.40
1.20
1.00
0.80
0.60
0.40
0.20
0.00
Reference value:
"2" = RDS(ON),MAX @ 150
Typical
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
160
Junction Temperature (°C)
Figure 16
RDS(ON) variation factor
The behavior in reverse polarity is described in Chapter 7.4.1.
6.2
Switching loads
6.2.1
Switching resistive loads
When switching resistive loads, the switching times and slew rates shown in Figure 17 can be considered.
The switching energy values EON and EOFF are proportional to load resistance and times tON and tOFF
.
Datasheet
23
Rev.1.00
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BTG7050-1EPL
Datasheet
6 Power Stage
INn
VIN(TH)
VIN(HYS)
t
VOUTn
90% of VS
tON
tOFF(DELAY)
70% of VS
70% of VS
30% of VS
(dV/dt)OFF
(dV/dt)ON
30% of VS
10% of VS
tON(DELAY)
tOFF
t
t
PDMOS
EON
EOFF
Figure 17
Switching a resistive load
6.2.2
Switching inductive loads
When switching OFF inductive loads with high-side switches, the voltage VOUT drops below ground potential, because
the inductance intends to continue driving the current. To prevent the destruction of the device due to overvoltage, a
voltage clamp mechanism is implemented. The clamping structure limits the output voltage so that VDS ≤ VDS(CLAMP)
Chapter 6.2.2 shows a concept drawing of the implementation.
.
The clamping structure is active in all operation modes listed in Chapter 5.1.
VS
VSIS(CLAMP)
VDS(CLAMP)
VDS
VS(CLAMP)
VS
IS
IL
OUT
GND
VOUT
Figure 18
Output clamping concept
During demagnetization of inductive loads, energy has to be dissipated in the device. The energy can be calculated
with:
Datasheet
24
Rev.1.00
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BTG7050-1EPL
Datasheet
6 Power Stage
V − V
R · I
S
DS CLAMP
L
L
L
(1)
E = V
·
· ln 1 −
+ I
·
DS CLAMP
L
R
V − V
R
L
S
DS CLAMP
L
The maximum energy the device can sustain is limited by the thermal design. Please refer to Table 2 for the maximum
allowed values of EAS (single pulse energy) and EAR (repetitive energy).
6.2.3
Switching capacitive loads
When fVIN(CLS) is applied the device enters CLS mode afer tON_CLS(DELAY) as shown in Figure 19. A pumping mode is
applied to charge the capacitor while the overcurrent limitation is active using the overcurrent limitation setting as
set by the OCT pin, as shown in Figure 20. During CLS mode, protection and diagnosis functions are active.
fVIN(CLS)
INn
VIN(TH)
VIN(HYS)
t
nACT
0
nCLS(ACT)x = 1
0
t
VOUT
90% of VS
tON
tOFF_CLS(DELAY) tOFF(DELAY)
70% of VS
30% of VS
70% of VS
(dV/dt)ON
(dV/dt)OFF
30% of VS
10% of VS
tON_CLS(DELAY) tON(DELAY)
tOFF
t
Figure 19
Switching a capacitive load
When the device is in CLS mode, the dynamic overtemperature protection is reduced to TJ(DYN)_CLS with continuous
restart.
A transition from CLS mode to Active mode is performed automatically when VDS ≤ VDS(OLOFF)
.
On the contrary, when VDS > VDS(OLOFF), the CLS mode has to be lef afer a maximum time of tCLSx by setting input to
"low" or "high".
A transition from capacitive load switching mode to active mode shall be performed only if there is no short circuit at
the output. To distinguish between short circuit and normal load, a current sense measurement must be performed
before leaving. If the current measurement delivers an expected value, the transition from CLS mode to active mode
may be performed. If the current measurement delivers an open load value (no output current), it has to be assumed
that there is either an open load or a short circuit at the output. Additionally, a short circuit condition could be
excluded by an external voltage measurement at the output.
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Datasheet
6 Power Stage
INn
tCLSx
t
t
VOUTn
VDS(OLOFF)
IL
ILIM(ADJ)
IL
t
t
t
nACT
0
nCLS(ACT)x = 1
0
Operation
Mode
SLEEP
Capacitive Load Switching Mode
ACTIVE
Figure 20
Capacitive load switching activations
6.3
Advanced switching characteristics
Inverse current behavior
6.3.1
When VOUT > VS, a current IL(INV) flows into the power output transistor (see Figure 21). This condition is known as
“Inverse Current”.
If the channel is in OFF state, the current flows through the intrinsic body diode generating high power losses,
therefore, an increase of overall device temperature. This may lead to a switch OFF of unaffected channels due to
overtemperature. If the channel is in ON state, RDS(INV) can be expected and power dissipation in the output stage is
comparable to normal operation in RDS(ON)
.
During inverse current condition, the channel remains in ON or OFF state as long as |-IL| < |-IL(INV)|.
The feature of InverseON allows to switch ON the channel during Inverse Current condition as long as |-IL| < |-IL(INV)|,
see Figure 22.
Datasheet
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BTG7050-1EPL
Datasheet
6 Power Stage
VS
Power stage
control
INV
Comp.
Device logic
-ILn
VOUT > VS
OUTn
GND
Figure 21
Inverse current circuitry
CASE 1 : Power stage is on
Power stage control
CASE 2 : Power stage is off
Power stage control
„high“
„low“
IL
t
t
IL
t
t
NORMAL
NORMAL
NORMAL
NORMAL
INVERSE
ON
INVERSE
OFF
Power stage
Power stage
t
t
CASE 3 : Switch on during inverse current
Power stage control
CASE 4 : Switch off during inverse current
Power stage control
„low“
„high“
„high“
„low“
IL
IL
t
t
t
t
NORMAL
NORMAL
NORMAL
NORMAL
INVERSE
INVERSE
Power stage
Power stage
OFF
ON
ON
OFF
t
t
Figure 22
InverseON - Channel behavior in case of applied inverse current
6.4
Electrical characteristics power stage
VS = 4 V to 20 V, TJ = -40°C to +150°C
Unless otherwise specified typical values: VS = 13.5 V, TJ = 25°C
Datasheet
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BTG7050-1EPL
Datasheet
6 Power Stage
Typical resistive loads connected to the outputs for testing (unless otherwise specified):
BTG7050-1EPL: RL = 4.7 Ω
Table 8
Electrical characteristics power stage
Parameter
Symbol
Values
Typ.
Unit
Note or condition
P-
Number
Min.
Max.
Voltages
Drain to source
clamping voltage at TJ
= -40°C
VDS(CLAMP)_-40
33
36.5
38
42
V
V
IL = 5 mA
TJ = -40°C
See Chapter 6.2.2
1)
PRQ-110
PRQ-111
Drain to source
clamping voltage at TJ
≥ 25°C
VDS(CLAMP)_25
35
44
IL = 5 mA
TJ ≥ 25°C
See Chapter 6.2.2
Timings
Switch-ON delay
tON(DELAY)
tOFF(DELAY)
tON
10
10
50
30
70
130
160
210
220
µs
µs
µs
µs
VS = 13.5 V
PRQ-112
PRQ-113
PRQ-114
PRQ-115
VOUT = 10% VS
IOCT = IOCT,MAX
See Figure 17
Switch-OFF delay
Switch-ON time
50
VS = 13.5 V
VOUT = 90% VS
IOCT = IOCT,MAX
See Figure 17
130
100
VS = 13.5 V
VOUT = 90% VS
IOCT = IOCT,MAX
See Figure 17
Switch-OFF time
CLS activation delay
tOFF
VS = 13.5 V
VOUT = 10% VS
IOCT = IOCT,MAX
See Figure 17
tON_CLS(DELAY)
tOFF_CLS(DELAY)
ΔtSW
10
70
40
25
200
90
µs
µs
µs
VS = 13.5 V
IOCT = IOCT,MAX
See Figure 19
PRQ-664
PRQ-665
PRQ-116
CLS de-activation
delay
20
VS = 13.5 V
IOCT = IOCT,MAX
See Figure 19
Switch-ON/OFF
Matching - tON - tOFF
-60
90
VS = 13.5V
IOCT = IOCT,MAX
(table continues...)
Datasheet
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Datasheet
6 Power Stage
Table 8
(continued) Electrical characteristics power stage
Parameter
Symbol
Values
Typ.
Unit
Note or condition
P-
Number
Min.
Max.
Voltage slope
Switch-ON slew rate
(dV/dt)ON
(dV/dt)OFF
Δ(dV/dt)SW
0.16
0.27
-0.27
0
0.39
V/µs
V/µs
V/µs
VS = 13.5 V
IOCT = IOCT,MAX
VOUT = 30% to 70% of VS
PRQ-117
PRQ-118
PRQ-119
Switch-OFF slew rate
-0.39
-0.15
-0.16
0.15
VS = 13.5V
IOCT = IOCT,MAX
VOUT = 70% to 30% of VS
Slew rate matching -
(dV/dt)ON + (dV/dt)OFF
VS = 13.5V
IOCT = IOCT,MAX
CLS mode
2)
Input frequency
for capacitive load
switching mode
activation
fVIN(CLS)
22
30
38
kHz
–
PRQ-353
PRQ-354
DCVIN(CLS) = 50%
2)
Duty cycle for
capacitive load
switching mode
activation
DCVIN(CLS)
30%
50%
70%
fVIN(CLS) = 30 kHz
2)
Maximum time in CLS tCLS1
–
–
–
–
–
–
–
–
25
ms
PRQ-355
PRQ-813
PRQ-812
PRQ-814
mode
See Chapter 6.2.3
2)
Maximum time in CLS tCLS2
mode
90
ms
See Chapter 6.2.3
2)
Maximum number of
CLS mode activations
nCLS_ACT1
nCLS_ACT2
500
50
kcycles
kcycles
See Chapter 6.2.3
2)
Maximum number of
CLS mode activations
See Chapter 6.2.3
Output characteristics
2)
ON-state resistance at RDS(ON)_25
–
–
–
50
–
–
mΩ
mΩ
mΩ
PRQ-793
PRQ-794
PRQ-795
TJ = 25°C
TJ = 25°C
ON-state resistance at RDS(ON)_150
TJ = 150°C
100
110
TJ = 150°C
IL = 2 A
ON-state resistance in RDS(ON)_CRANK_15
–
TJ = 150°C
VS = 3.1 V
IL = 1 A
cranking at TJ = 150°C
0
(table continues...)
Datasheet
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BTG7050-1EPL
Datasheet
6 Power Stage
Table 8
(continued) Electrical characteristics power stage
Parameter
Symbol
Values
Typ.
Unit
Note or condition
P-
Number
Min.
Max.
2)
ON-state resistance in RDS(INV)_25
inverse current at TJ =
25°C
–
–
50
–
mΩ
PRQ-796
TJ = 25°C
VS = 13.5 V
IL = -2 A
See Figure 21
ON-state resistance in RDS(INV)_150
inverse current at TJ =
150°C
–
110
mΩ
TJ = 150°C
VS = 13.5 V
IL = -2 A
PRQ-797
See Figure 21
2)
Nominal load current IL(NOM)_85
per channel at TA =
85°C
–
–
3
–
A
PRQ-798
PRQ-799
TA = 85°C
TJ ≤ 150°C
2)
Output leakage current IL(OFF)_85
at TJ ≤ 85°C
0.01
0.5
μA
VOUT = 0 V
IN = "low"
TA ≤ 85°C
Output leakage current IL(OFF)_150
–
–
1.2
3
4
–
μA
VOUT = 0 V
IN = "low"
TA = 150°C
2)
PRQ-800
PRQ-801
at TJ = 150°C
Inverse Current
Capability
IL(INV)
A
VS < VOUT
IN = "high"
See Figure 21
Voltages
Drain source diode
voltage
|VDS(DIODE)
|
–
–
550
1.2
700
–
mV
mJ
IL = -190 mA
TJ = 150°C
2)
PRQ-802
PRQ-803
Switch-ON energy
EON
VS = 20V
See Figure 17
2)
Switch-OFF energy
EOFF
–
1.25
–
mJ
PRQ-804
VS = 20V
See Figure 17
1)
2)
Tested at TJ = 150°C
Not subject to production test - specified by design
Datasheet
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BTG7050-1EPL
Datasheet
7 Protection
7
Protection
The device is protected against overload, overtemperature and overvoltage.
Overtemperature and overload protection are operational in all operation modes, except when in sleep mode.
Overload protection is not active during inverse current condition.
Overtemperature and overload protection during inverse current condition is inactive on the channel which is in
inverse condition.
Overvoltage protection is active in all operation modes.
7.1
Overcurrent protection
7.1.1
Adjustable overcurrent threshold
The device is protected in case of overload and short circuit to ground.
The device offers an adjustable overcurrent limitation range from ILIM,MIN to ILIM,MAX. This feature offers
protection against overstress for the load as well as for the power output stage. In case of DMOS temperature
increase exceeding the device safe operating environment, overtemperature and dynamic temperature protection
mechanism will be triggered as shown in Figure 24 and Figure 25.
For the adjustment of the current limitation for both output channels, the following equation can be considered:
I
− ∆ I
LIM
LIM
I
= k
· I
+ ∆ I
wℎere,
I
=
(2)
(3)
LIM
ILIOCT
OCT
LIM
OCT
k
ILIOCT
To select the proper resistor value ROCT connected between the OCT pin and device ground, the following equation
can be considered:
V
I
· k
OCT
ILIOCT
R
=
OCT
− ∆ I
LIM
LIM
In case of an OCT pin open with the current not exceeding IOCT(OPEN) the device will set the current limit value to
ILIMOCT(OPEN). In case of an OCT pin short to ground with the current exceeding IOCT(SHORT2GND) the device will set the
current limit value to ILIMOCT(SHORT2GND). The behavior of how IOCT is related to ILIM is described in Figure 23. However,
due to the maximum rating of the allowed current through OCT pin IOCT, it is not recommended to shorten the OCT
pin to device GND. In the case of reverse battery condition, this could lead to violations of the maximum ratings,
therefore IAI(REV) needs to be considered.
Datasheet
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Datasheet
7 Protection
ILIM
ILIM,MAX
ILIMOCT(SHORT2GND)
∆ILIM03
kILIOCT03
∆ILIM02
kILIOCT02
∆ILIM01
kILIOCT01
ILIM,MIN
ILIMOCT(OPEN)
IOCT(OPEN) IOCT,MIN
IOCT,MAX IOCT(SHORT2GND)
IOCT
Figure 23
Adjustable overcurrent limitation behavior
7.2
Overtemperature protection
The device incorporates both an absolute (TJ(ABS)) and a dynamic (TJ(DYN)) temperature protection circuitry for each
channel.
An increase in junction temperature TJ above either one of the two thresholds (TJ(ABS) or TJ(DYN)) switches OFF
the overheated channel. The affected channel will perform automatic restart attempts. The channel remains
switched OFF until the junction temperature has reached the restart condition described in Table 9 according to
Chapter 7.3.1. If the number of automatic restart attempts exceeds nRESTART(CR),TYP, the affected channel latches OFF
to prevent destruction. The behavior is shown in Figure 24 and Figure 25. TJ(REF) is the reference temperature used for
dynamic temperature protection.
Datasheet
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BTG7050-1EPL
Datasheet
7 Protection
INn
t
t
DEN
IL
ILIM
t
t
TJ
TJ(ABS)
tIS(FAULT)_D
IIS
IIS(FAULT)
IIS = IL / kILIS
IL / kILIS
IIS < IIS(SAT),Min
t
t
Internal
counter
0
1
Figure 24
Overtemperature protection (absolute)
INn
t
t
DEN
IL
ILIM
t
t
TJ
TJ(ABS)
TJ(REF)
tIS(FAULT)_D
IIS
IIS(FAULT)
IL / kILIS
t
t
Internal
counter
0
1
2
Figure 25
Overtemperature protection (dynamic)
When the overtemperature protection circuitry allows the channel to be switched ON again, the retry strategy
described in Chapter 7.3 is followed.
7.3
Protection and diagnosis in case of fault
Any event that triggers overtemperature protection has two consequences:
Datasheet
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Datasheet
7 Protection
•
•
The affected channel switches OFF according to Chapter 7.3.1.
If the diagnosis is active for the affected channel, a current IIS(FAULT) is provided by IS pin (see Chapter 8.2.2 for
further details).
The channel can be switched ON again if all the protection mechanisms fulfill the “restart” conditions described
in Table 9 and nRESTART(CR) < nRESTART(CR),typ
.
Table 9
Protection "restart" condition
Switch OFF event
Fault condition
"Restart" condition
Overtemperature TJ ≥ TJ(ABS) or (TJ - TJ(REF)) ≥ TJ(DYN)
TJ < TJ(ABS) and (TJ - TJ(REF)) < TJ(DYN) (including hysteresis)
7.3.1
Retry strategy
When IN is set to “high”, the power output stage is switched ON. If a fault condition is detected the power output stage
is switched OFF. The device will apply the restart strategy and return to normal operation or latches OFF if the fault
remains to be present afer nRESTART(CR),TYP
.
The device has an internal retry counter nRESTART(CR) (one for each channel) to maximize the robustness in case of
fault.
The channel is allowed to switch ON for nRESTART(CR) times before switching OFF. Afer nRESTART(CR),TYP consecutive
“restart” cycles, the channel latches OFF. To de-latch the power output stage and reset the internal counter it is
necessary to set the input pin to “low” for a time longer than tDELAY(CR)
.
If the fault is no longer present and tDELAY(CR) is observed the device will enter normal operation. In case the fault is
still present, the device will trigger again the retry strategy.
The retry strategy is shown in Figure 26.
INn
t
Short
circuit to
ground
t
IL
ILIM
t
Internal
temperature
protection
t
t
t
tDELAY(CR)
Internal
counter
0
1
2
3
4
5
6
nRESTART(CR) +1
0
DEN
IIS(FAULT)
IIS
IL / kILIS
t
tsIS(DIAG)
tsIS(DIAG)
Figure 26
Retry strategy timing diagram
It is possible to “force” a reset of the internal counter without waiting for tDELAY(CR) by applying a pulse (rising edge
followed by a falling edge) to the DEN pin while IN pin is “low”. The pulse applied to DEN pin must have a duration
longer than tDEN(CR) to ensure a reset of the internal counter.
The timings are shown in Figure 27.
Datasheet
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Datasheet
7 Protection
INn
t
t
Short
circuit to
ground
IL
ILIM
t
t
t
t
Internal
temperature
protection
Internal
counter
0
1
2
3
4
5
6
nRESTART(CR) +1
0
1
2
3
4
5
6
nRESTART(CR) +1
0
DEN
tDEN(CR)
IIS(FAULT)
tDEN(CR)
IIS(FAULT)
tDEN(CR)
IIS(FAULT)
IIS
IL / kILIS
t
tsIS(DIAG)
Figure 27
Retry strategy timing diagram with forced reset
7.4
Additional protection
7.4.1
Reverse polarity protection
In reverse polarity condition (also known as reverse battery), power dissipation is caused by the intrinsic body diode
of the DMOS channel. Each ESD diode of the logic contributes to total power dissipation. The reverse current through
the output stages must be limited by the connected loads. The current through digital input pins has to be limited by
an external resistor (please refer to the absolute maximum ratings listed in Table 2 and to Application Information in
Chapter 9).
7.4.2
Overvoltage protection
In the case of supply voltages between VS(EXT,UP) and VBAT(LD), the output transistors are still operational and follow the
input pin.
In addition to the output clamp for inductive loads as described in Chapter 6.2.2, there is a clamp mechanism
available for overvoltage protection for the logic and the output channels, monitoring the voltage between VS and
GND pins (VS(CLAMP)).
7.4.3
Loss of battery and loss of load
The loss of connection to the battery or the load does not influence device robustness as long as load and wire
harness are purely resistive. In case of driving an inductive load, the energy stored in the inductance must be handled.
The device can handle the inductivity of the wire harness up to 10 µH with IL(NOM)_85.
In case of applications where currents and/or the aforementioned inductivity are exceeded, an external suppressor
diode (like diode DZ2 shown in Chapter 9) is recommended to handle the energy and to provide a well-defined path
for the load current.
Datasheet
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Datasheet
7 Protection
7.4.4
Loss of ground
It is recommended to have a resistor connected between any digital input pin and the microcontroller to ensure a
channel switch OFF in case of a loss of device ground event (as described in Chapter 9).
Note
In case any digital input pin is pulled to ground (either by a resistor or active) a parasitic ground path is present, which
could keep the device operational during a loss of device ground.
7.5
Electrical characteristics protection
VS = 4 V to 20 V, TJ = -40°C to +150°C
Unless otherwise specified typical values: VS = 13.5 V, TJ = 25°C
Typical resistive loads connected to the outputs for testing (unless otherwise specified):
BTG7050-1EPL: RL = 4.7 Ω
Table 10
Electrical characteristics protection
Parameter
Symbol
Values
Typ.
175
Unit
Note or condition
P-
Number
Min.
150
Max.
200
1) 2)
Thermal shutdown
temperature (absolute)
TJ(ABS)
°C
K
PRQ-174
PRQ-356
PRQ-357
PRQ-177
See Figure 24
3)
Thermal shutdown
hysteresis (absolute)
THYS(ABS)
TJ(DYN)
–
–
–
30
80
40
–
–
–
See Figure 24
3)
Thermal shutdown
temperature (dynamic)
K
See Figure 24
3)
Thermal shutdown
temperature (dynamic)
in capacitive load
switching mode
TJ(DYN)_CLS
K
Power supply clamping VS(CLAMP)_-40
33
35
36.5
38
42
44
V
V
IVS = 5 mA
TJ = -40°C
See Chapter 6.2.2
2)
PRQ-179
PRQ-184
voltage at TJ = -40°C
Power supply clamping VS(CLAMP)_25
voltage at TJ ≥ 25°C
IVS = 5 mA
TJ ≥ 25°C
See Chapter 6.2.2
1)
Automatic restarts in
case of fault afer
counter reset
nRESTART(CR)
tDELAY(CR)
tDEN(CR)
–
6
–
–
PRQ-186
PRQ-188
PRQ-190
See Figure 26
1)
Counter reset delay
time afer fault
condition
40
50
70
100
100
150
ms
µs
See Figure 26
3)
Minimum DEN pulse
duration for counter
reset
See Figure 27
(table continues...)
Datasheet
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Datasheet
7 Protection
Table 10
(continued) Electrical characteristics protection
Parameter
Symbol
Values
Typ.
Unit
Note or condition
P-
Number
Min.
Max.
Adjustable overcurrent limitation
3)
Adjustable overcurrent ILIM(ACCURACY)
limitation accuracy
(low)
-22.5%
–
+22.5%
–
PRQ-633
0.79 A ≤ ILIM < 1.67 A
VDS = 3 V
3)
Adjustable overcurrent ΔILIM01
limitation d-factor
(low)
Adjustable overcurrent kILIOCT01
limitation k-factor
(low)
–
0.102
34449
–
–
A
–
–
PRQ-646
PRQ-658
PRQ-644
0.79 A ≤ ILIM < 1.67 A
3)
–
–
0.79 A ≤ ILIM < 1.67 A
3)
Adjustable overcurrent ILIM(ACCURACY)
limitation accuracy
(medium)
-16%
+16%
1.67 A ≤ ILIM < 3.27 A
VDS = 3 V
3)
Adjustable overcurrent ΔILIM02
limitation d-factor
(medium)
–
-0.042
37301
–
–
A
–
–
PRQ-647
PRQ-659
PRQ-634
1.67 A ≤ ILIM < 3.27 A
3)
Adjustable overcurrent kILIOCT02
limitation k-factor
–
–
1.67 A ≤ ILIM < 3.27 A
(medium)
3)
Adjustable overcurrent ILIM(ACCURACY)
limitation accuracy
(high)
-18%
+18%
3.27 A ≤ ILIM ≤ 8.86 A
VDS = 3 V
3)
Adjustable overcurrent ΔILIM03
limitation d-factor
(high)
Adjustable overcurrent kILIOCT03
limitation k-factor
(high)
–
-0.374
40512
0.74
–
A
–
PRQ-648
PRQ-660
PRQ-661
PRQ-662
3.27 A ≤ ILIM ≤ 8.86 A
3)
–
–
3.27 A ≤ ILIM ≤ 8.86 A
4)
Current limitation
value in case OCT pin
open
ILIMOCT(OPEN)
0.52
0.97
11.5
A
A
IOCT ≤ IOCT(OPEN)
4)
Current limitation
ILIMOCT(SHORT2GND 7.45
9.48
value in case OCT pin
short to device ground
)
IOCT ≥ IOCT(SHORT2GND)
1)
2)
3)
4)
Functional test only
Tested at TJ = 150°C only
Not subject to production test - specified by design
Tested at TJ = -40°C only
Datasheet
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BTG7050-1EPL
Datasheet
8 Diagnosis
8
Diagnosis
For the purpose of diagnosis, the device provides a proportional sense current signal (IIS) at pin IS. In case of
disabled diagnostic (DEN pin set to “low”), IS pin becomes high impedance.
A sense resistor RSENSE must be connected between IS pin and module ground if the current sense diagnosis is used.
RSENSE value has to be higher than 820 Ω (or 400 Ω when a central Reverse Battery protection is present on the battery
feed) to limit the power losses in the sense circuitry.
A typical value is RSENSE = 1.2 kΩ.
Due to the internal connection between IS pin and VS supply voltage, it is not recommended to connect the IS pin to
the sense current output of other devices, if they are supplied by a different battery feed.
See Figure 28 for details as an overview.
VS
Channel
T
Overtemperature
IS Pin Control
Internal Counters
Logic
IN
OUT
DEN
IL / kILIS
+
VDS(kILIS_EN)
MUX
+
IIS(FAULT)
VDS(OLOFF)
IIS(OLOFF)
MUX
IS
Figure 28
Diagnosis block diagram
8.1
Overview
Table 11 gives a quick reference to the state of the IS pin during the device operation.
Table 11
SENSE signal as a function of application condition
Operation mode
Input level
DEN level
VOUT
Diagnostic output
Normal operation
LOW/OFF
HIGH
~ GND
Z
IIS(FAULT) if nRESTART(CR) > 0
(table continues...)
Datasheet
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Rev.1.00
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BTG7050-1EPL
Datasheet
8 Diagnosis
Table 11
(continued) SENSE signal as a function of application condition
Operation mode
Input level
DEN level
VOUT
Diagnostic output
Short circuit to GND
~ GND
Z
IIS(FAULT) if nRESTART(CR) > 0
Thermal shutdown
temperature (absolute)
Z
IIS(FAULT)
Thermal shutdown
temperature (dynamic)
Z
IIS(FAULT)
Short circuit to VS
= VS
IIS(OLOFF)
IIS(FAULT) if nRESTART(CR) > 0
Open load
< VS - VDS(OLOFF)
Z
1)
1)
> VS - VDS(OLOFF)
< VS - VDS(OLOFF)
> VS - VDS(OLOFF)
IIS(OLOFF) or IIS(FAULT)
if nRESTART(CR) > 0 for both cases
Overcurrent pin fault
IIS(OCT_PIN_FAULT)
IIS(OLOFF) or IS(FAULT)
if nRESTART(CR) > 0 for both cases
IS(OLOFF) or IS(FAULT) if nRESTART(CR) > 0
IIS = IL / kILIS
IIS(FAULT)
I
Inverse current
~ VINV = VOUT > VS
I
Normal operation
Short circuit to GND
HIGH/ON or
CLS
< VS - VDS(kILIS_EN)
~ GND
Z
Thermal shutdown
temperature (absolute)
IIS(FAULT)
Thermal shutdown
temperature (dynamic)
Z
IIS(FAULT)
Short circuit to VS
Open load
= VS
IIS < IL / kILIS
IIS = IIS(EN)
IIS = IIS(EN)
IIS(FAULT)
2)
~ VS
Inverse current
Current limitation
Underload
~ VINV = VOUT > VS
< VS
3)
~ VS
IIS(EN) < IIS < IL(NOM) / kILIS
All conditions
n.a.
LOW
n.a.
Z
1) With additional pull up resistor
2) The output current has to be smaller than IL(OL)
3) The output current has to be higher than IL(OL)
8.1.1
SENSE signal truth table
Diagnosis can be activated or deactivated using the DEN pin, Table 12.
Datasheet
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Datasheet
8 Diagnosis
Table 12
Diagnostic truth table
DEN
IS
"low"
"high"
Z
SENSE output
8.2
Diagnosis in ON state
A current proportional to the load current (IIS = IL/kILIS) is provided at pin IS when the following conditions are fulfilled:
•
•
•
The power output stage is switched ON with VDS < VDS(kILIS_EN)
The diagnosis is enabled for that channel
No fault (as described in Chapter 7.3) is present or was present and not cleared yet (see Chapter 8.2.2 for further
details)
As long as a fault is present or was present and not cleared yet a current IIS(FAULT) is provided at IS pin.
8.2.1
Current sense (kILIS)
IIS increases linearly with IL output current until it reaches the saturation current IIS(SAT). In case of open load at
the output stage (IL close to 0 A), the maximum sense current IIS(EN) (no load, diagnosis enabled) is specified. This
condition is shown in Figure 29. The center line represents the ideal kILIS, while the outer lines show the behavior of
a typical product. An external RC filter between IS pin and microcontroller ADC input pin is recommended to reduce
signal ripple and oscillations (a minimum time constant of 1 µs for the RC filter is recommended). The kILIS factor is
specified with limits that take into account effects due to temperature, supply voltage, and manufacturing process.
IIS
IIS(OL)
IIS(EN)
IL(OL)_4u
IL
Figure 29
Current sense ratio in open load at ON condition
8.2.2
Fault current (IIS(FAULT))
In case a fault is present and DEN is set to “high”, a current IIS(FAULT) is provided.
Datasheet
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BTG7050-1EPL
Datasheet
8 Diagnosis
The following situations may occur:
•
•
•
If the channel is ON and the number of restarts is less than “nRESTART(CR),TYP”, the current IIS(FAULT) is provided for a
time tIS(FAULT)_D afer the channel is allowed to restart, and thereafer IIS = IL/kILIS (as shown in Figure 30). During a
restart cycle the current IIS(FAULT) is provided each time the channel diagnosis is checked.
If the channel is ON and the number of restarts is equal to “nRESTART(CR),TYP”, the current IIS(FAULT) is provided
until the internal counter is reset. The internal counter can be cleared either by INn = "low" for tDELAY(CR) or by
INn = "low" and DEN pin pulse for tDEN(CR), as described in Chapter 7.3.1.
While the channel is OFF and the internal counter value is not reset, the current IIS(FAULT) is provided.
INn
t
IL
ILIM
t
Internal
counter
0
1
2
0
t
t
DEN
tIS(FAULT)_D
tDEN(CR)
IIS(FAULT)
IIS
IIS(FAULT)
IL / kILIS
t
Figure 30
IIS(FAULT) at load switching
Figure 31 adds the behavior of SENSE signal to the timing diagram seen in Figure 26, while Figure 32 shows the
relation between IIS = IL/kILIS, IIS(SAT) and IIS(FAULT)
.
Datasheet
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Datasheet
8 Diagnosis
INn
t
t
Short
circuit to
ground
IL
ILIM
t
t
t
t
Internal
temperature
protection
tDELAY(CR)
Internal
counter
0
1
2
3
4
5
6
nRESTART(CR) +1
0
DEN
IIS(FAULT)
IIS(FAULT)
IIS(FAULT)
IIS
IL / kILIS
t
tsIS(DIAG)
tsIS(DIAG)
tsIS(DIAG)
tsIS(DIAG)
Figure 31
SENSE behavior in fault condition
IIS
IIS(SAT),MAX
IIS(FAULT),MAX
IIS(SAT)
IIIS(FAULT)
IIS(SAT),MIN
IIS(FAULT),MIN
IL / kILIS
IL
Figure 32
SENSE behavior - overview
8.3
Diagnosis in OFF State
When a power output stage is in OFF state, the device can measure the output voltage and compare it with a
threshold voltage. In this way, using some additional external components (a pull-down resistor and a switchable
pull-up current source), it is possible to detect if the load is missing or if there is a short circuit to battery. If
a fault condition was detected by the device (the internal counter has a value different from the reset value, as
described in Chapter 8.2.2 a current IIS(FAULT) is provided by IS pin each time the channel diagnosis is checked
also in OFF state. Additionally, the device can measure if the OCT pin is open IOCT(OPEN) or shorted to device
ground IOCT(SHORT2GND). In case of an fault condition on the OCT pin IIS(OCT_PIN_FAULT) is provided. Figure 33 shows the
relationship between IIS(OLOFF), IIS(FAULT) and IIS(OCT_PIN_FAULT) as functions of VDS. The three currents do not overlap
making it always possible to differentiate between open load in OFF, OCT pin fault and fault condition.
Datasheet
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Datasheet
8 Diagnosis
IIS
IIS(FAULT)
IIS(OLOFF)
IIS(OCT_PIN_FAULT)
VDS(OLOFF)
VDS
Figure 33
IIS in OFF state
8.3.1
Open load current
In OFF state, while DEN pin is set to “high”, the VDS voltage is compared with a threshold voltage VDS(OLOFF). When the
diagnosis is active and VDS ≤ VDS(OLOFF), a current IIS(OLOFF) is provided by IS pin. If the load is properly connected and
there is no short circuit to battery, VDS ~ VS, therefore, VDS > VDS(OLOFF) the IS pin is set to high impedance.
It is necessary to wait a time tIS(OLOFF)_D between the falling edge of the input pin and the sensing at pin IS for Open
Load in OFF diagnosis to allow the internal comparator to settle. In Figure 34 the timings for an Open Load detection
are shown - the load is always disconnected.
INn
t
DEN
t
tIS(OLOFF)_D
~ VS
VOUT
VDS(OLOFF)
Load connected
t
t
IIS
IIS(OLOFF)
IIS(OL)_4u
Figure 34
Open load in OFF timings - load disconnection
8.3.2
OCT pin fault current
When the device is in Inactive with Diagnosis mode and the OCT pin is open or shorted to device ground
and VDS ≥ VDS(OLOFF), a current IIS(OCT_PIN_FAULT) is provided by IS pin. Figure 33 shows IIS(OCT_PIN_FAULT) as a function over
VDS
.
Datasheet
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Datasheet
8 Diagnosis
8.4
SENSE timings
Figure 35 and Figure 36 show the timing during settling tsIS(ON) and disabling tsIS(OFF) of the SENSE (including the case
of load change). As a proper signal cannot be established before the load current is stable (therefore before tON),
t
= t
+ t
(4)
sIS DIAG
sIS ON
ON
INn
DEN
IL
OFF
ON
OFF
t
t
tOFF
t
t
tsIS(OFF)
tsIS(OFF)
tsIS(LC)
tsIS(ON)
IIS
tsIS(DIAG)
Figure 35
SENSE settling/disabling timing
INn
DEN
IL
OFF
ON
OFF
t
t
tsIS(LC)_SLC
t
t
tsIS(ON)_SLC
tsIS(ON)
IIS
Figure 36
SENSE timing with small load current
8.5
Electrical characteristics diagnosis
VS = 4 V to 20 V, TJ = -40°C to +150°C
Unless otherwise specified typical values: VS = 13.5 V, TJ = 25°C
Typical resistive loads connected to the outputs for testing (unless otherwise specified):
BTG7050-1EPL: RL = 4.7 Ω
Datasheet
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Rev.1.00
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BTG7050-1EPL
Datasheet
8 Diagnosis
Table 13
Electrical characteristics diagnosis
Parameter
Symbol
Values
Typ.
Unit
Note or condition
P-
Number
Min.
4.4
Max.
15
1)
SENSE saturation
current
IIS(SAT)
–
mA
PRQ-215
VS = 6 V to 20 V
RSENSE = 1.2 kΩ
See Figure 32
SENSE leakage current IIS(OFF)
when disabled
–
–
0.01
0.2
0.5
2
µA
µA
DEN = "low"
IL ≥ IL(NOM)
VIS = 0 V
1)
PRQ-219
PRQ-221
SENSE leakage current IIS(EN)_85
when enabled at TJ ≤
85°C
TJ ≤ 85°C
DEN = "high"
IL = 0 A
See Figure 29
SENSE leakage current IIS(EN)_150
when enabled at TJ =
150°C
–
0.2
2
µA
TJ = 150°C
DEN = "high"
IL = 0 A
PRQ-223
See Figure 29
1)
Saturation voltage in
kILIS operation (VS-
VIS)
VSIS_k
–
–
0.5
0.5
1
1
V
V
PRQ-226
PRQ-682
VS = 5 V
IN = DEN = “high”
1)
Saturation voltage in
open load at OFF
diagnosis (VS-VIS)
VSIS_OL
VS = 5 V
IN = "low"
DEN = "high"
1)
Saturation voltage in
fault diagnosis (VS-VIS)
VSIS_F
–
–
0.5
0.5
1
1
V
V
PRQ-684
PRQ-686
VS = 5 V
IN = "low"
DEN = "high"
counter > 0
1)
Saturation voltage in
OCT pin fault diagnosis
(VS-VIS)
VSIS_OCT_F
VS = 5 V
IN = "low"
DEN = "high"
IOCT
= IOCT(SHORT2GND) or IOCT(
OPEN)
(table continues...)
Datasheet
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Datasheet
8 Diagnosis
Table 13
(continued) Electrical characteristics diagnosis
Parameter
Symbol
Values
Typ.
Unit
Note or condition
P-
Number
Min.
33
Max.
42
Power supply to IS pin VSIS(CLAMP)_-40
clamping voltage at TJ
=-40°C
36.5
V
IIS = 1mA
TJ = -40°C
See Chapter 6.2.2
2)
PRQ-294
Power supply to IS pin VSIS(CLAMP)_25
clamping voltage at TJ
≥ 25°C
35
38
44
V
PRQ-296
IIS = 1 mA
TJ ≥ 25°C
See Chapter 6.2.2
SENSE fault current
IIS(FAULT)
IIS(OLOFF)
4.4
1.9
5.5
2.5
10
mA
mA
See Chapter 8
See Chapter 8
PRQ-298
PRQ-306
SENSE open load in
OFF current
3.5
SENSE OCT pin FAULT IIS(OCT_PIN_FAULT) 0.2
1.2
1.7
–
mA
µs
See Figure 33
PRQ-621
PRQ-308
in OFF current
1)
SENSE delay time
at channel switch
ON afer last fault
condition
tIS(FAULT)_D
–
500
See Figure 30
SENSE open load in
OFF delay time
tIS(OLOFF)_D
70
185
300
µs
VDS < VDS(OLOFF) from
INn falling edge to
IIS = IIS(OLOFF),MIN ⋅ 0.9
PRQ-310
DEN = “high”
nRESTART(CR) = 0
See Figure 34
1)
VDS threshold for kILIS VDS(kILIS_EN)
0.8
1.3
1.2
1.8
1.4
2.3
V
V
PRQ-809
PRQ-313
enable
Open load VDS
detection threshold in
OFF state
VDS(OLOFF)
See Chapter 8.3
SENSE settling time
with nominal load
current stable
tsIS(ON)
–
–
5
–
20
60
µs
µs
IL = IL(NOM) from DEN
rising edge to IIS = IL/
(kILIS,MAX @ IL) ⋅ 0.9
PRQ-315
PRQ-317
See Figure 35
1)
SENSE settling time
with small load current
stable
tsIS(ON)_SLC
IL = IL01 from DEN rising
edge to IIS = IL/(kILIS,MAX
@ IL) ⋅ 0.9
See Figure 36
(table continues...)
Datasheet
46
Rev.1.00
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BTG7050-1EPL
Datasheet
8 Diagnosis
Table 13
(continued) Electrical characteristics diagnosis
Parameter
Symbol
Values
Typ.
Unit
Note or condition
P-
Number
Min.
Max.
20
1)
SENSE disable time
tsIS(OFF)
–
5
µs
PRQ-319
IL = IL(NOM)
From DEN falling edge
to IIS = IIS(OFF)
See Figure 35
1)
SENSE settling time
tsIS(LC)
–
–
5
20
µs
µs
PRQ-321
PRQ-323
afer load change
from IL = IL(NOM)/2 to IL =
IL(NOM)
See Figure 35
1)
SENSE settling time
afer load change with
small load current
tsIS(LC)_SLC
250
400
DEN = "high" from load
change to IIS = IL/(kILIS
@ IL) from IL(NOM) to IL01
See Figure 36
Open load output
current at IIS = 4 µA
IL(OL)_4u
2
9.5
17
mA
–
IIS = IIS(OL) = 4 µA
PRQ-580
PRQ-585
PRQ-588
PRQ-590
PRQ-594
PRQ-598
PRQ-601
PRQ-604
Current sense ratio at kILIS02
IL =IL02
-26%
2230
+26%
+23.5%
+20%
+10%
+9.5%
+6%
IL02 = 20 mA
IL04 = 50 mA
IL05 = 100 mA
IL08 = 250 mA
IL11 = 1 A
Current sense ratio at kILIS04
IL =IL04
-23.5% 2030
–
Current sense ratio at kILIS05
IL =IL05
-20%
-10%
2030
2030
–
Current sense ratio at kILIS08
IL =IL08
–
Current sense ratio at kILIS11
IL =IL11
-9.5% 2030
–
Current sense ratio at kILIS13
IL =IL13
-6%
-5%
2030
2030
–
IL13 = 2 A
Current sense ratio at kILIS15
IL =IL15
+5%
–
IL15 = 4 A
1)
2)
Not subject to production test - specified by design
Tested at TJ = 150°C
Datasheet
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BTG7050-1EPL
Datasheet
9 Application information
9
Application information
Note:
The following information is given as a hint for the implementation of the device only and shall not be
regarded as a description or warranty of a certain functionality, condition or quality of the device.
VBAT
ZWIRE
Optional
Logic Supply
CVS
CVSGND
T1
RGND
GND
VS
OCT
OUT
VDD
GPIO
GPIO
RIN
IN
RDEN
DEN
COUT
CVS2
DZ2
Optional
RES
ADC
RADC
RIS_PROT
IS
COUT
VSS
CSENSE
Optional
Logic GND
Power GND
Chassis GND
Figure 37
Table 14
Application diagram
Suggested component values
Value Purpose
Reference
RIN
4.7 kΩ
Protection of the microcontroller during overvoltage and reverse polarity.
Necessary to switch OFF the output during loss of ground
RDEN
ROCT
4.7 kΩ
Protection of the microcontroller during overvoltage and reverse polarity.
Necessary to switch OFF the output during loss of ground
2.2 kΩ - 25 kΩ
Adjustable overcurrent limitation resistor connected to device ground.
Protection of the device during overvoltage and reverse polarity
RPD
ROL
47 kΩ
Output polarization (pull-down). Ensures polarization of the outputs to
distinguish between open load and short to VS in OFF diagnosis
1.5 kΩ
Output polarization (pull-up). Ensure polarization of the output during open load
in OFF diagnosis
COUT
T1
10 nF
Protection of the output during ESD events and BCI
Switch the battery voltage for open load in OFF diagnosis
Filtering of voltage spikes on the battery line
BC 807
100 nF
CVS
(table continues...)
Datasheet
48
Rev.1.00
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BTG7050-1EPL
Datasheet
9 Application information
Table 14
(continued) Suggested component values
Purpose
Reference
CVSGND
DZ2
Value
47 nF
Buffer capacitor for fast transient
33V TVS Diode
Transient voltage suppressor diode. Protection during overvoltage and in case of
loss of battery while driving an inductive load
CVS2
–
Filtering/buffer capacitor located at VBAT connector
RSENSE
RIS_PROT
1.2 kΩ
SENSE resistor
4.7 kΩ
Protection during overvoltage, reverse polarity, loss of ground Value to be tuned
according to microcontroller specifications
DZ1
7 V Z-Diode
Protection of microcontroller during overvoltage
RADC
4.7 kΩ
Protection of microcontroller ADC input during overvoltage, reverse polarity, loss
of ground. Value to be tuned according to microcontroller specifications
CSENSE
RGND
220 pF
Sense signal filtering. A time constant (RADC ⋅ CSENSE) longer than 1 µs is
recommended
47 Ω
Protection in case of overvoltage and loss of battery while driving inductive
loads
•
•
Please contact us for information regarding the pin behavior assessment
For further information you may contact http://www.infineon.com
Datasheet
49
Rev.1.00
2022-09-20
BTG7050-1EPL
Datasheet
10 Package outlines
10
Package outlines
Figure 38
PG-TSDSO-14 dual small outline package dimensions
Figure 39
PG-TSDSO-14 dual small outline footprint dimensions
Note:
To meet the world-wide customer requirements for environmentally friendly products and to be
compliant with government regulations the device is available as a green product. Green products are
RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC
J-STD-020).
Further information on packages https://www.infineon.com/packages
Datasheet
50
Rev.1.00
2022-09-20
BTG7050-1EPL
Datasheet
11 Revision history
11
Revision history
Table 15
Revision history
Date of release
Document
version
Description of changes
Rev.1.00
2022-09-20
Initial Datasheet
Datasheet
51
Rev.1.00
2022-09-20
Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
Edition 2022-09-20
Published by
Infineon Technologies AG
81726 Munich, Germany
Important notice
Warnings
The information given in this document shall in no
event be regarded as a guarantee of conditions or
characteristics (“Beschaffenheitsgarantie”).
With respect to any examples, hints or any typical
values stated herein and/or any information regarding
the application of the product, Infineon Technologies
hereby disclaims any and all warranties and liabilities
of any kind, including without limitation warranties of
non-infringement of intellectual property rights of any
third party.
In addition, any information given in this document is
subject to customer’s compliance with its obligations
stated in this document and any applicable legal
requirements, norms and standards concerning
customer’s products and any use of the product of
Infineon Technologies in customer’s applications.
Due to technical requirements products may contain
dangerous substances. For information on the types
in question please contact your nearest Infineon
Technologies office.
Except as otherwise explicitly approved by Infineon
Technologies in
authorized representatives of Infineon Technologies,
Infineon Technologies’ products may not be used in
any applications where a failure of the product or
any consequences of the use thereof can reasonably
be expected to result in personal injury.
a written document signed by
©
2022 Infineon Technologies AG
All Rights Reserved.
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aspect of this document?
Email: erratum@infineon.com
Document reference
IFX-yhc1639672556452
The data contained in this document is exclusively
intended for technically trained staff. It is the
responsibility of customer’s technical departments to
evaluate the suitability of the product for the intended
application and the completeness of the product
information given in this document with respect to such
application.
相关型号：
BTG7050-2EPL
The BTG7050-2EPL, as part of the PROFET™ Load Guard family, is a dual channel smart high-side power switch, providing protection functions and enhanced diagnostic capabilities. It is equipped with adjustable overcurrent limitation to offer high reliability for protecting the system: In case of a short circuit to ground, the PCB traces, connectors, as well as loads, can be protected. Furthermore, the BTG7050-2EPL has a capacitive load switching mode implemented to charge big capacitive loads and to reduce current peaks during switch on of capacitors. By these features, the device addresses different use cases for intelligent power distribution (load supply protection, wire protection and power supply protection) and a broad range of applications.
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