BGSC2341ML10 [INFINEON]
BGSC2341ML10 is a versatile Integrated Circuit (IC) ideal for RF tuning applications such as tunable impedance matching, antenna tuning and tunable filtering. This IC integrates an 8-states tunable capacitor and an extremely low RON Single Pole Double Throw (SPDT) RF switch function; both controlled by on-chip MIPI 2.1 RFFE digital interface.;
| 型号： | BGSC2341ML10 |
| 厂家： | 
Infineon |
| 描述： | BGSC2341ML10 is a versatile Integrated Circuit (IC) ideal for RF tuning applications such as tunable impedance matching, antenna tuning and tunable filtering. This IC integrates an 8-states tunable capacitor and an extremely low RON Single Pole Double Throw (SPDT) RF switch function; both controlled by on-chip MIPI 2.1 RFFE digital interface. 光电二极管 |
| 文件： | 总22页 (文件大小：793K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
BGSC2341ML10
RF Digitally Tunable Capacitor + SPDT Switch
Features
• Designed for high-linearity applications
• Ultra low RON resistance of 0.87 Ω at each SPDT throw in ON state
• High operating RF Voltage handling 40 V
• 0.25-2.00 pF Tuning range at 1.8 GHz
• Operating frequencies: 0.4 - 3.8 GHz
• High ESD Robustness
• MIPI 2.1 RFFE compliant control interface
• 2 default USID selectable via USID_SEL pin
• Supply voltage range: 1.65 to 1.95 V
1.1x1.5mm2
• Small form factor 1.1 mm x 1.5 mm (MSL1, 260◦C per JEDEC J-STD-020)
• RoHS and WEEE compliant package
Potential Applications
• Impedance Tuning
• Antenna Tuning
• Inductance Tuning
Product Validation
Qualified for industrial applications according to the relevant tests of JEDEC47/20/22.
Block diagram
RFC
Voltage
ESD
Regulator
C1
SW1
SW2
VIO
MIPI
RFFE
SCLK
Drivers
SDAT
USID_SEL
Chargepump
ESD
GND
RF3 RF1
RF2
Final Data Sheet
www.infineon.com
Revision 2.3
2021-09-19
BGSC2341ML10
RF Digitally Tunable Capacitor + SPDT Switch
Table of Contents
Table of Contents
Table of Contents
1
2
1
Features
2
3
4
5
6
7
8
Maximum Ratings
3
DC Characteristics
4
RF Small Signal Characteristics
RF Large Signal Parameters
MIPI RFFE Specification
Application Information
Package Information
5
8
10
17
18
Final Data Sheet
1
Revision 2.3
2021-09-19
BGSC2341ML10
RF Digitally Tunable Capacitor + SPDT Switch
Features
1 Features
• Designed for high-linearity applications
• Ultra low RON resistance of 0.87 Ω at each SPDT throw in ON state
• High operating RF Voltage handling 40 V
• 0.25-2.00 pF Tuning range at 1.8 GHz
• Operating frequencies: 0.4 - 3.8 GHz
• High ESD Robustness
• MIPI 2.1 RFFE compliant control interface
• 2 default USID selectable via USID_SEL pin
• Supply voltage range: 1.65 to 1.95 V
•
Small form factor 1.1 mm x 1.5 mm (MSL1, 260◦C per JEDEC J-STD-020)
• RoHS and WEEE compliant package
Description
The BGSC2341ML10 is a versatile Integrated Circuit (IC) ideal for RF tuning applications such as tunable impedance matching,
antenna tuning, tunable filtering. This IC integrates a 8 states tunable capacitor and an extremely low Ron Single Pole
Double Throw (SPDT) RF switch function; both controlled by on-chip MIPI2.1 RFFE digital interface. Last but not the least, the
BGSC2341ML10 exhibits very good linearity in high RF power conditions and up to RF Voltage of 40 V which is a key attribute in
application like antenna tuning. It does not require any additional High Voltage Supply Controller IC and can be powered by a
single 1.8 V Power Supply at an extremely low current consumption level. With 1.1 mm x 1.5 mm package dimensions, it is a
compact solution fitting well to any small form factor mobile phone-like applications.
Product Name
Marking
Package
Ordering Information
BGSC2341ML10
C2
TSLP-10-2
BGSC 2341ML10 E6327
Final Data Sheet
2
Revision 2.3
2021-09-19
BGSC2341ML10
RF Digitally Tunable Capacitor + SPDT Switch
Maximum Ratings
2 Maximum Ratings
Spectrum
Analyser
(Hx Monitor)
50 Ohm
50 Ohm Transmission Line
SIGNAL
SOURCE
Power
Meter
RFC
Voltage
Regulator
ESD
C1
SW1
SW2
VIO
MIPI
RFFE
SCLK
SDAT
USID_SEL
Drivers
ESD
Chargepump
RF2
RF3 RF1
GND
Figure 1: RF operating voltage measurement configuration (Switches 1,2 OFF and C1-Tuner position in Isolation Mode)
Table 1: Maximum Ratings at TA = 25 ◦C, unless otherwise specified
Parameter
Symbol
Values
Unit Note / Test Condition
Min. Typ. Max.
1)
Frequency Range
Storage temperature range
RF input power
f
0.4
-55
–
–
–
–
3.8
150
39
GHz
TSTG
PRF_max
◦C
–
dBm Pulsed RF input duty cycle of
25 % and 4620 µs in ON-state,
measured per 3GPP TS 45.005
RF voltage
VRF_max
–
–
45
V
Short term peaks (1 µs in 0.1%
duty cycle), exceeding typical
linearity, RON and COFF param-
eters, in Isolation mode, test
condition schematic in Fig. 1
ESD robustness, CDM 3)
ESD robustness, HBM 4)
Junction temperature
Thermal resistance junction - soldering point RthJS
RFFE Supply Voltage
VESD
-1
-750
–
–
-0.5
-0.7
–
–
–
40
–
+1
+750
125
43
2.2
kV
V
CDM
VESD
HBM
Tj
◦C
K/W
V
–
–
–
–
VIO
VSCLK
RFFE Control Voltage Levels
,
–
VIO+0.7
V
VSDAT
,
(max. 2.2)
VUSID_SEL
1) Switch has a low-pass response. For higher frequencies, losses have to be considered for their impact on thermal heating. The DC voltage at RF ports VRFDC has
to be 0V.
2) Note: Consider any ripple voltages on top of VDD. A high RF ripple at the VDD can exceed the maximum ratings by VDD = VDC + VRipple
.
3) Field-Induced Charged-Device Model ANSI/ESDA/JEDEC JS-002. Simulates charging/discharging events that occur in production equipment and processes.
Potential for CDM ESD events occurs whenever there is metal-to-metal contact in manufacturing.
4) Human Body Model ANSI/ESDA/JEDEC JS-001 (R = 1,5 kΩ, C = 100 pF).
5) IEC 61000-4-2 (R = 330 Ω, C = 150 pF), contact discharge.
Attention: Stresses above the max. values listed here may cause permanent damage to the device. Maximum rat-
ings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit.
Exposure to conditions at or below absolute maximum rating but above the specified maximum operation conditions
may aꢀect device reliability and life time. Functionality of the device might not be given under these conditions.
Final Data Sheet
3
Revision 2.3
2021-09-19
BGSC2341ML10
RF Digitally Tunable Capacitor + SPDT Switch
DC Characteristics
3 DC Characteristics
Table 2: DC Characteristics at TA = −40 ◦C to 85 ◦C
Parameter
Symbol
Values
Unit
Note / Test Condition
Min.
1.65
Typ.
1.8
–
Max.
1.95
VIO
RFFE supply voltage
VIO
VIH
VIL
V
–
RFFE input high voltage1
RFFE input low voltage1
RFFE output high voltage1
RFFE output low voltage1
0.7*VIO
V
–
0
–
0.3*VIO
VIO
V
–
VOH
VOL
0.8*VIO
–
V
–
0
–
–
–
–
0.2*VIO
2
V
–
RFFE control input capacitance CCtrl
–
pF
µA
µA
–
1.7
65
9
110
VIO shutdown mode
Power up mode
RFFE supply current
IVIO
1SCLK and SDATA
Final Data Sheet
4
Revision 2.3
2021-09-19
BGSC2341ML10
RF Digitally Tunable Capacitor + SPDT Switch
RF Small Signal Characteristics
4 RF Small Signal Characteristics
RFC
SPDT
C-Tuner
DC ROFF
Ctune
RON
RF1
RF3
COFF
GND
GND
DC ROFF
RON
RF2
COFF
GND
GND
Figure 2: RF measurement equivalent circuit
Table 3: Parametric specifications of DC the equivalent circuit
Parameter
Symbol
Values
Unit
STATE / Notes
Min.
Typ.
Max.
SPDT
VIO = 1.65 − 1.95 V,
RON DC ON resistance
ROFF DC OFF resistance
RON
ROFF
0.66
77
0.87
110
1.08
133
Ω
KΩ
TA = −40 ◦C... + 85 ◦C
Final Data Sheet
5
Revision 2.3
2021-09-19
BGSC2341ML10
RF Digitally Tunable Capacitor + SPDT Switch
RF Small Signal Characteristics
Table 4: Parametric specifications of the RF equivalent circuit @ f= 900 MHz (1,2,3)
Parameter
Symbol
Values
Typ.
Unit
STATE / Notes
Min.
Max.
CP,ESD SHUNT capacitance
C-Tuner
CP,ESD
190
220
285
fF
Ctune State 0
Ctune State 1
Ctune State 2
Ctune State 3
Ctune State 4
Ctune State 5
Ctune State 6
Ctune State 7
C0
C1
C2
C3
C4
C5
C6
C7
245
440
635
260
460
665
285
520
750
970
1210
1430
1675
2000
245
fF
fF
fF
fF
fF
fF
fF
fF
fF
VIO = 1.65 − 1.95 V,
TA = 25◦C
835
870
1030
1220
1435
1685
175
1075
1280
1500
1775
205
CP,tune SHUNT capacitance
SPDT
CP,tune
COFF OFF capacitance
COFF
CP,RF
185
120
200
165
225
225
fF
fF
CP,RF SHUNT capacitance
1) Network analyser input power: PIN = 0 dBm
2) On application board without any matching components.
3) This C-tuner has a monotonic behaviour: C value will increase if programming a growing C state and decrease if programming a decreasing C state.
Table 5: Parametric specifications of the RF equivalent circuit @ f= 1.8 GHz (1,2,3)
Parameter
Symbol
Values
Typ.
215
Unit
STATE / Notes
Min.
200
Max.
270
CP,ESD SHUNT capacitance
C-Tuner
CP,ESD
fF
Ctune State 0
Ctune State 1
Ctune State 2
Ctune State 3
Ctune State 4
Ctune State 5
Ctune State 6
Ctune State 7
C0
C1
C2
C3
C4
C5
C6
C7
250
460
670
900
1110
1350
1595
1855
160
270
500
725
1000
1200
1475
1750
2000
185
300
560
810
1100
1360
1650
1950
2300
230
fF
fF
fF
fF
fF
fF
fF
fF
fF
VIO = 1.65 − 1.95 V,
TA = 25◦C
CP,tune SHUNT capacitance
SPDT
CP,tune
COFF OFF capacitance
COFF
CP,RF
185
110
205
155
230
265
fF
fF
CP,RF SHUNT capacitance
1) Network analyser input power: PIN = 0 dBm
2) On application board without any matching components.
3) This C-tuner has a monotonic behaviour: C value will increase if programming a growing C state and decrease if programming a decreasing C state.
Final Data Sheet
6
Revision 2.3
2021-09-19
BGSC2341ML10
RF Digitally Tunable Capacitor + SPDT Switch
RF Small Signal Characteristics
Table 6: Parametric specifications of the RF equivalent circuit @ f= 2.7 GHz (1,2,3)
Parameter
Symbol
Values
Typ.
Unit
STATE / Notes
Min.
Max.
CP,ESD SHUNT capacitance
C-Tuner
CP,ESD
205
225
260
fF
Ctune State 0
Ctune State 1
Ctune State 2
Ctune State 3
Ctune State 4
Ctune State 5
Ctune State 6
Ctune State 7
C0
C1
C2
C3
C4
C5
C6
C7
260
500
755
1050
1275
1590
1940
2345
155
290
550
840
1180
1400
1800
2200
2660
180
320
610
935
1300
1610
2000
2460
3240
210
fF
fF
fF
fF
fF
fF
fF
fF
fF
VIO = 1.65 − 1.95 V,
TA = 25◦C
CP,tune SHUNT capacitance
SPDT
CP,tune
COFF OFF capacitance
COFF
CP,RF
190
120
215
155
250
185
fF
fF
CP,RF SHUNT capacitance
1) Network analyser input power: PIN = 0 dBm
2) On application board without any matching components.
3) This C-tuner has a monotonic behaviour: C value will increase if programming a growing C state and decrease if programming a decreasing C state.
Final Data Sheet
7
Revision 2.3
2021-09-19
BGSC2341ML10
RF Digitally Tunable Capacitor + SPDT Switch
RF Large Signal Parameters
5 RF Large Signal Parameters
Table 7: RF large signal specifications at TA = −40 .. + 85 ◦C, unless otherwise specified
Parameter
Symbol
Values
Typ.
–
Unit
Note / Test Condition
Min.
–
Max.
40
RF operating voltage
VRF_peak
V
In Isolation mode, test condition
schematic in Fig. 1 for H2/H3 < -
35dBm @ 50Ω, TA = 25 ◦C
Harmonic Generation up to 12.75 GHz(1,2)
All RF Ports - Second Order Har- PH2
monics
-
-
-
-
-
-
–
-71
-65
-79
-39
-50
-46
-51
dBm
dBm
dBm
dBm
dBm
dBm
dBm
25 dBm,f0 = 824 MHz
25 dBm,f0 = 824 MHz
35 dBm,f0 = 824 MHz
35 dBm, f0 = 824 MHz
AllRFPorts-ThirdOrderHarmon- PH3
ics
-84
-44
-56
-48
-52
-87
All RF Ports - Second Order Har- PH2
monics
AllRFPorts-ThirdOrderHarmon- PH3
ics
All RF Ports - Second Order Har- PH2
monics
33 dBm,f0 = 1800 MHz,
TA = 25 ◦C
AllRFPorts-ThirdOrderHarmon- PH3
ics
33 dBm,f0 = 1800 MHz,
TA = 25 ◦C
26 dBm ,f0 = 663 MHz, TA = 25 ◦C
All RF Ports
PHx
-65
Intermodulation Distortion IMD2 (1,2)
IIP2, low
IIP2, high
IIP2,l
IIP2,h
100
100
111
116
–
–
dBm
dBm
IIP2 conditions Table 8
IIP3 conditions Table 9
Intermodulation Distortion IMD3 (1,2)
IIP3
IIP3
70
73
–
dBm
1) Terminating Port Impedance: Z0 = 50 Ω
2) On application board without any matching components
Table 8: IIP2 conditions table
Band
In-BandFrequency Blocker Frequency 1 Blocker Power 1
Blocker Frequency 2 Blocker Power 2
[MHz]
2140
[MHz]
1950
[dBm]
20
[MHz]
190
[dBm]
-15
Band 1 Low
Band 1 High 2140
Band 5 Low 881.5
Band 5 High 881.5
1950
20
4090
45
-15
836.5
836.5
20
-15
20
1718
-15
Final Data Sheet
8
Revision 2.3
2021-09-19
BGSC2341ML10
RF Digitally Tunable Capacitor + SPDT Switch
RF Large Signal Parameters
Table 9: IIP3 conditions table
Band
In-BandFrequency Blocker Frequency 1 Blocker Power 1
Blocker Frequency 2 Blocker Power 2
[MHz]
2140
[MHz]
1950
[dBm]
20
[MHz]
1760
[dBm]
-15
Band 1
Band 5
881.5
836.5
20
791.5
-15
Final Data Sheet
9
Revision 2.3
2021-09-19
BGSC2341ML10
RF Digitally Tunable Capacitor + SPDT Switch
MIPI RFFE Specification
6 MIPI RFFE Specification
Warning: Register_0 and Register_1 RF switch control bits are identical. Writing both Registers Register_0 and Reg-
ister_1 simultaneously will lead to undefined behavior. The unused register (Register_0 or Register_1) must remain
0x00.
The MIPI RFFE interface is working in systems following the ’MIPI Alliance Specification for RF Front-End Control Interface
version 2.1 - 18 December 2017’, the ’MIPI Alliance Errata 01 for MIPI RFFE Specification version 2.1 - 24 February 2019’, and the
’Qualcomm RFFE Vendor specification 80-N7876-1 Rev. W.’
Table 10: MIPI Features
Feature
Supported Comment
MIPI RFFE 2.1 standard
Yes
Yes
Yes
Backward compatible to MIPI 2.0 standard
Register 0 write command sequence
Register read and write command sequence
Extended register read and write command sequence Yes
Masked write command sequence Yes
Indicated as MW in below register mapping tables
Up to 26 MHz for read and write
Support for standard frequency range operations for Yes
SCLK
Support for extended frequency range operations for Yes
SCLK
Up to 52 MHz for write
Half speed read
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Up to 26 MHz
Up to 26 MHz
Full speed read
Full speed write
Longer Reach RFFE Bus Length Feature
Programmable driver strength
Programmable Group SID
Programmable USID
Up to 80 pF
Trigger functionality
Extended Triggers and Trigger Masks
Broadcast / GSID write to PM TRIG register
Reset
Via VIO, PM TRIG or soꢀware register
Status / error sum register
Extended product ID register
Revision ID register
Group SID register
USID_SEL pin
See Table 14
Table 11: Startup Behavior
Feature
State
Comment
Power status
Low power
Lower power mode aꢀer start-up
Default power mode is HIGH
Trigger function
Final Data Sheet
Enabled
Enabled aꢀer start-up. Programmable via behavior control register
10
Revision 2.3
2021-09-19
BGSC2341ML10
RF Digitally Tunable Capacitor + SPDT Switch
MIPI RFFE Specification
Table 12: Switching Time Behavior
Parameter
Symbol
Values
Typ.
6.5
Unit
STATE / Notes
Min.
–
Max.
13
Power Up Settling Time
tPUP
µs
Time from Power Up plus Switch
command 50% last SCLK falling
edge to 90% RF-Signal,
see Fig. 3
SW1, SW2 SPST Switching Time
C1 C-Tuner Switching Time
tST
–
–
10.5
9.5
16
17
µs
µs
Time switching between RF
states 50% last SCLK falling
edge to 90% RF-Signal,
see Fig. 3
SW1,SW2
tST
C1
VDD+IO
1)
>120ns
tPUP
tST
<50ns
SCLK 52MHz
Power Up
SDATA
Switch A
Command
Switch B
Command
Command
90%
RF Path A
90%
RF Path B
1)
timing starts @ VIO > VIOmin (1.65V) and ends @ SDATA /SCLK < VILmax (0.3 x VIO
)
Figure 3: BGSC2341ML10 Switching Time Behavior
Final Data Sheet
11
Revision 2.3
2021-09-19
BGSC2341ML10
RF Digitally Tunable Capacitor + SPDT Switch
MIPI RFFE Specification
Table 13: Register Mapping, Table I
Register
Address
Register Name
Data Function
Bits
Description
Default
Broadcast_ID
Support
Trigger
Support
R/W
0x00
0x01
0x1C
REGISTER_0
7:0
7:0
7
MODE_CTRL
RF Switches and C-Tuner Control
00000000
No
No
Yes
Yes
Trigger 0-10
Yes
R/W
MW
R/W
MW
R/W
MW
REGISTER_1
PM_TRIG
MODE_CTRL
RF Switches and C-Tuner Control
00000000
Trigger 0-10
No
PWR_MODE(1)
Operation Mode
PWR_MODE(0)
State Bit Vector
0: Normal operation (ACTIVE)
1: Low Power Mode (LOW POWER)
0: No action (ACTIVE)
1
6
0
1: Powered Reset (STARTUP to ACTIVE
to LOW POWER)
5
4
3
TRIGGER_MASK_2
TRIGGER_MASK_1
TRIGGER_MASK_0
0: Data masked (held in shadow REG)
0
0
0
No
1: Datanotmasked(readyfortransferto
active REG)
0: Data masked (held in shadow REG)
1: Datanotmasked(readyfortransferto
active REG)
0: Data masked (held in shadow REG)
1: Datanotmasked(readyfortransferto
active REG)
2
1
TRIGGER_2
TRIGGER_1
TRIGGER_0
PRODUCT_ID
0: No action (data held in shadow REG)
1: Data transferred to active REG
0
Yes
0: No action (data held in shadow REG)
1: Data transferred to active REG
0
0
0: No action (data held in shadow REG)
1: Data transferred to active REG
0
0x1D
0x1E
0x1F
PRODUCT_ID
MAN_ID
7:0
This is a read-only register. However,
during the programming of the USID a
write command sequence is performed
on this register, even though the write
does not change its value.
01001101
No
No
No
No
R
R
7:0
7:4
3:0
MANUFACTURER_ID [7:0]
MANUFACTURER_ID [11:8]
USID[1:0]
This is a read-only register. However,
during the programming of the USID, a
write command sequence is performed
on this register, even though the write
does not change its value.
00011010
MAN_USID
These bits are read-only. However, dur-
ing the programming of the USID, a
write command sequence is performed
on this register even though the write
does not change its value.
01
USID_SEL pin
See
No
No
R/W
Tab. 10
Final Data Sheet
12
Revision 2.3
2021-09-19
BGSC2341ML10
RF Digitally Tunable Capacitor + SPDT Switch
MIPI RFFE Specification
Table 14: Register Mapping, Table II
Register
Address
Register Name
Data Function
Bits
Description
Default
Broadcast_ID
Support
Trigger
Support
R/W
0x20
EXT_PRODUCT_ID 7:0
EXT_PRODUCT_ID
Extension to PRODUCT_ID in register
0x1D. This is a read-only register. How-
ever, during the programming of the
USID a write command sequence is per-
formedonthisregister, eventhoughthe
write does not change its value.
00000000
No
No
R
0x21
0x22
0x23
REV_ID
GSID
7:4
3:0
7:4
3:0
7
MAIN_REVISION
SUB_REVISION
GSID0[3:0]
Chip main revision
0001
0000
0000
0000
0
No
No
Yes
No
No
No
R
Chip sub revision
Primary Group Slave ID.
Secondary Group Slave ID.
R/W
R/W
GSID1[3:0]
UDR_RST
UDR_RST
Reset all configurable non-RFFE Re-
served registers to default values.
0: Normal operation
1: Soꢀware reset
6:0
7
RESERVED
Reserved for future use
Reserved for future use
0000000
0x24
ERR_SUM
RESERVED
0
0
No
No
R
6
COMMAND_FRAME_PARITY_ERR
Command Sequence received with par-
ity error − discard command.
Command length error.
5
4
3
2
1
COMMAND_LENGTH_ERR
ADDRESS_FRAME_PARITY_ERR
DATA_FRAME_PARITY_ERR
READ_UNUSED_REG
0
0
0
0
0
0
Address frame with parity error.
Data frame with parity error.
Read command to an invalid address.
Write command to an invalid address.
WRITE_UNUSED_REG
BID_GID_ERR
0
Read command with a BROADCAST_ID
or GROUP_ID.
0x2B
BUS_LD
7:4
3:0
RESERVED
Reserved for future use
0x0
0x4
No
No
R/W
BUS_LD[3:0]
Set approximate bus load, default 50 pF
0x8-0xF: Spare
Final Data Sheet
13
Revision 2.3
2021-09-19
BGSC2341ML10
RF Digitally Tunable Capacitor + SPDT Switch
MIPI RFFE Specification
Table 15: Register Mapping, Table III
Register
Address
Register Name
Data Function
Bits
Description
Default
Broadcast_ID
Support
Trigger
Support
R/W
0x2D
EXT_TRIG_MASK
7
6
5
4
3
2
1
TRIGGER_MASK_10
0: Data writes to registers tied to
EXT_TRIGGER_10 are masked. Data
is held in shadow registers until the
EXT_TRIGGER_10 bit is set to 1.
1
No
No
R/W
1: Data writes to registers tied to
EXT_TRIGGER_10 are not masked. Data
writes go directly to the active registers.
MW
TRIGGER_MASK_9
TRIGGER_MASK_8
TRIGGER_MASK_7
TRIGGER_MASK_6
TRIGGER_MASK_5
TRIGGER_MASK_4
TRIGGER_MASK_3
0: Data writes to registers tied to
EXT_TRIGGER_9 are masked. Data
is held in shadow registers until the
EXT_TRIGGER_9 bit is set to 1.
1
1
1
1
1
1
1
1: Data writes to registers tied to
EXT_TRIGGER_9 are not masked. Data
writes go directly to the active registers.
0: Data writes to registers tied to
EXT_TRIGGER_8 are masked. Data
is held in shadow registers until the
EXT_TRIGGER_8 bit is set to 1.
1: Data writes to registers tied to
EXT_TRIGGER_8 are not masked. Data
writes go directly to the active registers.
0: Data writes to registers tied to
EXT_TRIGGER_7 are masked. Data
is held in shadow registers until the
EXT_TRIGGER_7 bit is set to 1.
1: Data writes to registers tied to
EXT_TRIGGER_7 are not masked. Data
writes go directly to the active registers.
0: Data writes to registers tied to
EXT_TRIGGER_6 are masked. Data
is held in shadow registers until the
EXT_TRIGGER_6 bit is set to 1.
1: Data writes to registers tied to
EXT_TRIGGER_6 are not masked. Data
writes go directly to the active registers.
0: Data writes to registers tied to
EXT_TRIGGER_5 are masked. Data
is held in shadow registers until the
EXT_TRIGGER_5 bit is set to 1.
1: Data writes to registers tied to
EXT_TRIGGER_5 are not masked. Data
writes go directly to the active registers.
0: Data writes to registers tied to
EXT_TRIGGER_4 are masked. Data
is held in shadow registers until the
EXT_TRIGGER_4 bit is set to 1.
1: Data writes to registers tied to
EXT_TRIGGER_4 are not masked. Data
writes go directly to the active registers.
0
0: Data writes to registers tied to
EXT_TRIGGER_3 are masked. Data
is held in shadow registers until the
EXT_TRIGGER_3 bit is set to 1.
1: Data writes to registers tied to
EXT_TRIGGER_3 are not masked. Data
writes go directly to the active registers.
Final Data Sheet
14
Revision 2.3
2021-09-19
BGSC2341ML10
RF Digitally Tunable Capacitor + SPDT Switch
MIPI RFFE Specification
Table 16: Register Mapping, Table IV
Register
Address
Register Name
Data Function
Bits
Description
Default
Broadcast_ID
Support
Trigger
Support
R/W
R/W
MW
0x2E
EXT_TRIG
7
6
5
4
3
2
1
TRIGGER_10
TRIGGER_9
TRIGGER_8
TRIGGER_7
TRIGGER_6
TRIGGER_5
TRIGGER_4
TRIGGER_3
0: No action. Data is held in shadow reg-
isters.
0
Yes
No
1: Data is transferred from shadow reg-
isters to active registers for refisters tied
to EXT_TRIGGER_10
0: No action. Data is held in shadow reg-
isters.
0
0
0
0
0
0
0
1: Data is transferred from shadow reg-
isters to active registers for refisters tied
to EXT_TRIGGER_9
0: No action. Data is held in shadow reg-
isters.
1: Data is transferred from shadow reg-
isters to active registers for refisters tied
to EXT_TRIGGER_8
0: No action. Data is held in shadow reg-
isters.
1: Data is transferred from shadow reg-
isters to active registers for refisters tied
to EXT_TRIGGER_7
0: No action. Data is held in shadow reg-
isters.
1: Data is transferred from shadow reg-
isters to active registers for refisters tied
to EXT_TRIGGER_6
0: No action. Data is held in shadow reg-
isters.
1: Data is transferred from shadow reg-
isters to active registers for refisters tied
to EXT_TRIGGER_5
0: No action. Data is held in shadow reg-
isters.
1: Data is transferred from shadow reg-
isters to active registers for refisters tied
to EXT_TRIGGER_4
0
0: No action. Data is held in shadow reg-
isters.
1: Data is transferred from shadow reg-
isters to active registers for refisters tied
to EXT_TRIGGER_3
Final Data Sheet
15
Revision 2.3
2021-09-19
BGSC2341ML10
RF Digitally Tunable Capacitor + SPDT Switch
MIPI RFFE Specification
Table 17: USID_SEL Selection
Address
USID_SEL6=0110
USID_SEL9=1001
Symbol
Addr6
Configuration
default
Ext. Condition at USID_SEL Port
ground
to VIO
Addr9
default
RFC
RFC
10
NC
10
NC
1
2
3
4
9
RF1
1
2
3
4
9
RF1
RF3
RF3
RF2
RF2
8
7
6
8
7
6
USID_SEL
USID_SEL
GND
GND
SCLK
SCLK
VIO
5
5
VIO
SDAT
SDAT
Addr9=1001
Addr6=0110
Figure 4: BGSC2341ML10 USID_SEL Pin Configuration
Table 18: Switch MIPI Control Combinations (truth table) 1)
REGISTER_0 :C-Tuner control register
State
0
1
Mode
Ctune State 0
Ctune State 1
D7
X
X
X
X
X
X
X
X
X
X
X
X
D6
X
D5
0
0
0
0
0
0
0
0
0
0
0
0
D4
X
X
X
X
X
X
X
X
0
0
1
D3
X
X
X
X
X
X
X
X
0
1
D2
0
0
0
0
1
D1
0
0
1
D0
0
1
X
2
Ctune State 2
X
0
1
3
Ctune State 3
X
1
4
5
Ctune State 4
Ctune State 5
X
0
0
1
0
1
X
1
6
7
Ctune State 6
Ctune State 7
X
1
0
1
X
1
1
8
9
10
11
SPDT ALL OFF
SPDT RF SW1 ON
SPDT RF SW2 ON
SPDT RF SW1,SW2 ON
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
X
1
1)measured according to the measurement set-up of Fig. 2
Combination of any state here above mentioned in Table 15 can be programmed in one single MIPI sequence. As an example,
programmation of RF1 ON RF2 ON C tuner in state 1 can be done in one MIPI data frame with register 0x1=0bxx011001.
Final Data Sheet
16
Revision 2.3
2021-09-19
BGSC2341ML10
RF Digitally Tunable Capacitor + SPDT Switch
Application Information
7 Application Information
Pin Configuration and Function
RFC
10
NC
1
9
RF1
SW1
SW2
RF3
2
C1
RF2
8
7
6
GND
USID_SEL
VIO
3
4
SCLK
5
SDAT
Figure 5: BGSC2341ML10 Pin Configuration (top view)
Table 19: Pin Definition and Function of BGSC2341ML10 in Swap Configuration:USID=0111
Pin No.
1
Name
NC
Pin Type
-
Function
Not Connected
2
3
4
5
6
7
8
9
10
RF3
I/O
I/O
I
Input/Output Tunable Capacitor Port
Ground
GND
SCLK
SDAT
VIO
MIPI Control Signal SCLOCK(Default)
MIPI Control Signal SDATA(Default)
MIPI/DC Voltage Supply
I/O
I
USID_SEL
RF2
I
USID_SEL hardware pin for USID selection (see Table.17)
Input/Output RF Switch 2
Input/Output RF Switch 1
Input/Output RF Common Port
I/O
I/O
I/O
RF1
RFC
Table 20: ESD robustness, System Level Test (SLT)
Parameter
Symbol
Values
Typ.
–
Unit
Note / Test Condition
Min.
-8 2)
Max.
+8 2)
ESD SLT 1)
VESD
kV
RF vs system GND, with 27 nH shunt inductor
SLT
1) IEC 61000-4-2 (R = 330 Ω, C = 150 pF), contact discharge.
2) For RFC path only.
Final Data Sheet
17
Revision 2.3
2021-09-19
BGSC2341ML10
RF Digitally Tunable Capacitor + SPDT Switch
Package Information
8 Package Information
ꢀꢁꢂꢂꢁꢃ ꢄꢅꢆꢇ
Figure 6: TSLP-10-2 Package Outline (top, side and bottom views)
Pin 1 marking
Date code (YW)
Type code
TSLP-10-2 MK
Figure 7: Marking Specification (top view): Date code digits Y and W defined in Table 21/22
Final Data Sheet
18
Revision 2.3
2021-09-19
BGSC2341ML10
RF Digitally Tunable Capacitor + SPDT Switch
Package Information
Table 21: Year date code marking - digit "Y"
Year
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
"Y"
0
1
2
3
4
5
6
7
8
9
Year
"Y"
0
1
2
3
4
5
6
7
8
9
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
Table 22: Week date code marking - digit "W"
Week
"W"
A
B
C
D
E
Week
12
13
14
15
16
17
18
19
"W"
N
P
Q
R
S
T
U
V
W
Y
Week
23
24
25
26
27
28
29
30
31
32
33
"W"
4
5
6
7
a
b
c
d
e
f
Week
34
35
36
37
38
39
40
41
42
43
"W"
h
j
k
l
n
p
q
r
Week
45
46
47
48
49
50
"W"
v
x
y
z
8
9
2
3
1
2
3
4
5
6
7
8
9
10
11
F
G
H
J
K
L
51
52
20
21
22
s
t
u
Z
g
44
Final Data Sheet
19
Revision 2.3
2021-09-19
BGSC2341ML10
RF Digitally Tunable Capacitor + SPDT Switch
Package Information
ꢙꢈꢁꢅꢍꢃꢇꢆ ꢋꢍꢆꢎꢂꢉ ꢏꢇꢋꢐ ꢎꢇꢏ
ꢖꢑꢗ ꢑꢒꢘꢕ
ꢑꢒꢓ
ꢑꢒꢓ
ꢑꢒꢓ
ꢖꢑꢗ ꢑꢒꢘꢕ
ꢀꢍꢆꢎꢂꢉ ꢏꢇꢋꢐ
ꢑꢒꢓ
ꢀꢁꢂꢃꢄꢅꢆ ꢇꢈꢂꢉꢁꢊꢉꢂꢋ
ꢌꢍꢈꢈꢂꢉ
Figure 8: Footprint Recommendation
ꢁꢂꢃ
ꢀ
ꢄꢅꢆ ꢇ
ꢈꢉꢊꢋꢅꢆꢌ
ꢇꢂꢍ
Figure 9: TSLP-10-2 Carrier Tape
Final Data Sheet
20
Revision 2.3
2021-09-19
BGSC2341ML10
RF Digitally Tunable Capacitor + SPDT Switch
Revision History
Page or Item
Subjects (major changes since previous revision)
Revision 2.3, 2021-09-19
4th version of the final datasheet
with update in Table 4-6 (capacitance performance) and Table 18 (truth table)
Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
IMPORTANT NOTICE
Theinformationgiveninthisdocumentshallinnoevent For further information on technology, delivery terms
Edition 2021-09-19
Published by
Infineon Technologies AG
81726 Munich, Germany
be regarded as a guarantee of conditions or characteris- and conditions and prices, please contact the nearest
tics ("Beschaꢁenheitsgarantie"). With respect to any ex- Infineon Technologies Oꢁice (www.infineon.com).
amples, hints or any typical values stated herein and/or
any information regarding the application of the prod-
uct, Infineon Technologies hereby disclaims any and all
warranties and liabilities of any kind, including without
limitationwarrantiesofnon-infringementofintellectual
property rights of any third party. In addition, any infor-
mation given in this document is subject to customer’s
WARNINGS
Due to technical requirements products may contain
dangerous substances. For information on the types
in question please contact your nearest Infineon Tech-
nologies oꢁice.
c
ꢀ 2021 Infineon Technologies AG.
All Rights Reserved.
compliance with its obligations stated in this document Except as otherwise explicitly approved by Infineon
and any applicable legal requirements, norms and stan- Technologies in a written document signed by autho-
dards concerning customer’s products and any use of rized representatives of Infineon Technologies, Infineon
the product of Infineon Technologies in customer’s ap- Technologies products may not be used in any applica-
plications. The data contained in this document is ex- tionswhereafailureoftheproductoranyconsequences
clusively intended for technically trained staꢁ. It is the of the use thereof can reasonably be expected to result
responsibility of customer’s technical departments to in personal injury.
Do you have a question about any
aspect of this document?
Email: erratum@infineon.com
Document reference
Doc_Number
evaluate the suitability of the product for the intended
application and the completeness of the product infor-
mation given in this document with respect to such ap-
plication.
Final Data Sheet
21
Revision 2.3
2021-09-19
相关型号：
©2020 ICPDF网 联系我们和版权申明