AUIRS2332J_15_技术文档

September 3rd, 2012

Automotive Grade

AUIRS2332J

3-PHASE BRIDGE DRIVER IC

Product Summary

Features

•

Floating channel designed for bootstrap operation

V_OFFSET

≤ 600V

10 – 20V

Fully operational to +600 V

Tolerant to negative transient voltage – dV/dt immune

Gate drive supply range from 10 V to 20 V

Undervoltage lockout for all channels

Over-current shutdown turns off all six drivers

Independent half-bridge drivers

Matched propagation delay for all channels

3.3 V logic compatible

Outputs out of phase with inputs

Cross-conduction prevention logic

Integrated Operational Amplifier

RoHS Compliant

V_OUT

I_o+& I _o-(typical)

t_ON& t_OFF(typical)

Deadtime (typical)

250mA & 500mA

540ns

850ns

Package Options

Automotive qualified*

Typical Applications

•

Automotive Body electronics

3 phase motor control

Pumps and fans

44-Lead PLCC w/o 12 Leads

Typical Connection Diagram

AUIRS2332J

Table of Contents

Page

Description

3

Qualification Information

Absolute Maximum Ratings

Recommended Operating Conditions

Dynamic Electrical Characteristics

Static Electrical Characteristics

Functional Block Diagram

Input/Output Pin Equivalent Circuit Diagram

Lead Definitions

4

5

6

7 - 8

8

9

10

Lead Assignments

10

Application Information and Additional Details

Parameter Temperature Trends

Package Details

11 - 25

26 - 29

30 - 31

32

Part Marking Information

Ordering Information

32

Important Notice

33

2

AUIRS2332J

Description

The AUIRS2332J is a high voltage, high speed power MOSFET and IGBT driver with three independent high and low side

referenced output channels. Proprietary HVIC technology enables ruggedized monolithic construction. Logic inputs are

compatible with CMOS or LSTTL outputs, down to 3.3V logic. A ground-referenced operational amplifier provides analog

feedback of bridge current via an external current sense resistor. A current trip function which terminates all six outputs is

also derived from this resistor. An open drain FAULT signal indicates if an over-current or undervoltage shutdown has

occurred. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction.

Propagation delays are matched to simplify use at high frequencies. The floating channel can be used to drive N-channel

power MOSFET or IGBT in the high side configuration which operates up to 600 volts.

3

AUIRS2332J

Qualification Information^†

Automotive

(per AEC-Q100^††)

Qualification Level

Comments: This family of ICs has passed an Automotive

qualification. IR’s Industrial and Consumer qualification

level is granted by extension of the higher Automotive level.

MSL3^†††245°C

(per IPC/JEDEC J-STD-020)

Moisture Sensitivity Level

Class M2 (Pass +/-200V)

(per AEC-Q100-003)

Machine Model

Class H1C (Pass +/-1500V)

ESD

Human Body Model

(

)

per AEC-Q100-002

Class C4 (+/-1000V)

(per AEC-Q100-011)

Class II, Level A

(per AEC-Q100-004)

Yes

Charged Device Model

IC Latch-Up Test

RoHS Compliant

†

Qualification standards can be found at International Rectifier’s web site http://www.irf.com/

†† Exceptions (if any) to AEC-Q100 requirements are noted in the qualification report.

††† Higher MSL ratings may be available for the specific package types listed here. Please contact your

International Rectifier sales representative for further information.

4

AUIRS2332J

Absolute Maximum Ratings

Absolute maximum ratings indicate sustained limits beyond which permanent damage to the device may occur.

These are stress ratings only, functional operation of the device at these or any other condition beyond those

indicated in the “Recommended Operating Condition” is not implied. Exposure to absolute maximum-rated

conditions for extended periods may affect device reliability. All voltage parameters are absolute voltages

referenced to V_SOunless otherwise stated in the table. The thermal resistance and power dissipation ratings are

measured under board mounted and still air conditions.

Symbol

Definition

Min.

Max.

Units

V_B1,2,3

High Side Floating Supply Voltage

-0.3

620

V_S1,2,3

V_HO1,2,3

V_CC

High Side Floating Offset Voltage

High Side Floating Output Voltage

Low Side and Logic Fixed Supply Voltage

Logic Ground

V_B1,2,3- 20

V_S1,2,3- 0.3

-0.3

V_B1,2,3+ 0.3

20

V_SS

V_CC- 20

-0.3

V_CC+ 0.3

V_LO1,2,3

Low Side Output Voltage

V

(V_SS+ 15) or

(V_CC+ 0.3)

Whichever is

lower

_______ ______

Logic Input Voltage ( HIN1,2,3, LIN1,2,3 & ITRIP)

V_SS-0.3

V_IN

V_FLT

FAULT Output Voltage

V_SS-0.3

V_CC+0.3

V_CAO

Operational Amplifier Output Voltage

V_CA-

Operational Amplifier Inverting Input Voltage

Allowable Offset Supply Voltage Transient

V_SS-0.3

—

V_CC+0.3

50

dV_S/dt

V/ns

W

P_D

Package Power Dissipation @ TA ≤ +25 °C

Thermal Resistance, Junction to Ambient

Thermal Resistance, Junction to Case

—

---

2.0

63

Rth_JA

Rth_JC

°C/W

21.95

°C/ W

T_J

T_S

T_L

Junction Temperature

—

-55

—

150

300

Storage Temperature

°C

Lead Temperature (soldering, 10 seconds)

5

AUIRS2332J

Recommended Operating Conditions

The Input/Output logic timing diagram is shown in figure 1. For proper operation the device should be used within the

recommended conditions. All voltage parameters are absolute voltage referenced to V_SO.The V_Soffset rating is

tested with all supplies biased at 15V differential.

Symbol

Definition

Min.

Max.

Units

V_B1,2,3

V_S1,2,3

High Side Floating Supply Voltage

Static High side floating offset voltage

Transient High side floating offset voltage

High Side Floating Output Voltage

Low Side and Logic Fixed Supply Voltage

Logic Ground

V_S1,2,3+10

V_S1,2,3+20

600

V_SO-8 (Note1)

V_St1,2,3

-50 (Note2)

V_S1,2,3

600

V_HO1,2,3

V_B1,2,3

V_CC

V_SS

10

-5

20

5

V

V_LO1,2,3

V_IN

Low Side Output Voltage

0

V_CC

V_SS+ 5

V_CC

Logic Input Voltage (HIN1,2,3, LIN1,2,3 & ITRIP)

FAULT Output Voltage

V_SS

-40

V_FLT

V_CAO

V_CA-

T_A

Operational Amplifier Output Voltage

Operational Amplifier Inverting Input Voltage

Ambient temperature

V_SS+ 5

125

°C

Note 1: Logic operational for V_Sof (V_SO-8 V) to (V_SO+600 V). Logic state held for V_Sof (V_SO-8 V) to (V_SO– V_{BS .}

)

Note 2: Operational for transient negative VS of VSS - 50 V with a 50 ns pulse width. Guaranteed by design. Refer

to the Application Information section of this datasheet for more details.

Note 3: CAO input pin is internally clamped with a 5.2 V zener diode.

Dynamic Electrical Characteristics

Unless otherwise noted, these specifications apply for an operating junction temperature range of -40°C ≤

Tj ≤125°C with bias conditions V_BIAS(V_CC, V_BS1,2,3) = 15 V, C_L= 1000 pF.

Symbol

Definition

Min Typ Max Units

Test Conditions

t_on

t_off

t _r

Turn-on propagation delay

Turn-off propagation delay

Turn-on rise time

400 540

700

145

55

V_S1,2,3= 0 V to 600 V

—

80

40

V_S1,2,3= 0 V

t _f

Turn-off fall time

ITRIP to Output Shutdown Propagation

delay

t_itrip

400 625

400

350 550

325

920

t_bl

t_flt

ITRIP Blanking Time

—

870

—

ns

ITRIP to FAULT Indication Delay

Input Filter Time (All Six Inputs)

LIN1,2,3 to FAULT Clear Time

t_{flt, in}

—

t_fltclr

DT

5300 8500 13700

500 850 1100

Deadtime:

V_IN= 0 V & 5 V without

external deadtime

MDT

Deadtime matching:

—

145

V_IN= 0 V & 5 V without

external deadtime larger than DT

MT

PM

Delay matching time (t_ON, t _OFF

Pulse width distortion

)

50

75

PM input 10 µs

SR+

SR-

Operational Amplifier Slew Rate (+)

Operational Amplifier Slew Rate (-)

5

10

—

1 V input step

V/µs

2.4

3.2

6

AUIRS2332J

NOTE: For high side PWM, HIN pulse width must be > 1.5 usec

Static Electrical Characteristics

Unless otherwise noted, these specifications apply for an operating junction temperature range of -40°C ≤

Tj ≤ 125°C with bias conditions of V_BIAS(V_CC, V_BS1,2,3) = 15 V, V_SO1,2,3= V_SS. The V_IN,V_THand I_INparameters are

referenced to V_SSand are applicable to all six logic input leads: HIN1,2,3 & LIN1,2,3. The V_Oand I_Oparameters are

referenced to V_SO1,2,3and are applicable to the respective output leads: HO1,2,3 or LO1,2,3.

Symbol

Definition

Min Typ Max Units Test Conditions

V_IH

V_IL

Logic “0” input Voltage (OUT = LO)

Logic “1” input Voltage (OUT = HI)

ITRIP Input Positive Going Threshold

—

2.2

—

V

0.8

V_IT,TH+

400 490 580

V_IN= 0 V, I_O= 20 mA

V_IN= 5 V, I_O= 20 mA

V_B= V_S= 600 V

V_IN= 0 V or 4 V

V_IN= 0 V

V_OH

V_OL

I_LK

High Level Output Voltage, V_BIAS- V_O

Low Level Output Voltage, V_O

Offset Supply Leakage Current

Quiescent V_BSSupply Current

Quiescent V_CCSupply Current

—

1150

400

50

mV

—

µA

I_QBS

I_QCC

I_IN+

I_IN-

I_ITRIP+

I_ITRIP-

37

4.5

50

6.2

mA

Logic “1” Input Bias Current (OUT =HI)

Logic “0” Input Bias Current (OUT = LO)

“High” ITRIP Bias Current

-450 -300 -100

-350 -220 -100

—

V_IN= 0 V

V_IN= 4 V

ITRIP = 4 V

ITRIP = 0 V

µA

nA

5

—

10

30

“LOW” ITRIP Bias Current

V

_BSSupply Undervoltage

V_BSUV+

V_BSUV-

V_CCUV+

V_CCUV-

7.5

7.1

8.3

8

8.3

7.9

8.9

8.6

9.2

8.8

9.7

9.4

Positive Going Threshold

V_BSSupply Undervoltage

Negative Going Threshold

V_CCSupply Undervoltage

Positive going Threshold

V

_CCSupply Undervoltage

Negative Going Threshold

V_CCUVH

V_BSUVH

R_{on, FLT}

Hysteresis

—

0.3

0.4

55

—

75

Hysteresis

FAULT Low On-Resistance

Ω

V_O= 0 V, V_IN= 0 V

PW ≤ 10 us

V_O= 15 V, V_IN= 5 V

I_O+

I_O-

Output High Short Circuit Pulsed Current

Output Low Short Circuit Pulsed Current

—

-250 -180

mA

375 500

—

PW ≤ 10 us

V_OS

I_CA-

Operational Amplifier Input Offset Voltage

CA- Input Bias Current

—

20

100

mV

nA

V_SO= 0.2 V

V_CA-= 1 V

Operational Amplifier Common Mode

Rejection Ratio

Operational Amplifier Power Supply

Rejection Ratio

Operational Amplifier High Level Output

Voltage

Operational Amplifier Low Level Output

Voltage

CMRR

PSRR

—

4.8

—

1

80

75

5.2

—

V_SO= 0.1 V & 5 V

dB

V_SO= 0.2 V

V_CC= 9.7 V & 20 V

V_OH,AMP

V_OL,AMP

I_SRC,AMP

I_SNK,AMP

5.6

40

-4

V

V_CA-= 0 V, V_SO=1 V

V_CA-= 1 V, V_SO=0 V

mV

V_CA-= 0 V, V_SO=1 V

V_CAO= 4 V

V_CA-= 1 V, V_SO=0 V

V_CAO= 2 V

Operational Amplifier Output Source Current

Operational Amplifier Output Sink Current

-7

mA

2.1

—

7

AUIRS2332J

Operational Amplifier Output High Short Circuit

Current

Operational Amplifier Output Low Short Circuit

Current

V_CA-= 0 V, V_SO=5 V

V_CAO= 0 V

V_CA-= 5 V, V_SO=0 V

V_CAO= 5 V

I_O+,AMP

I_O-,AMP

-30

—

-10

4

—

Functional Block Diagram

8

AUIRS2332J

Input/Output Pin Equivalent Circuit Diagram:

V_CC

ESD

Diode

50 KOhm

250 Ohm

HIN₁₂₃

LIN₁₂₃

,

20V

ESD

Diode

5V

V_SS

V_CC

ESD

Diode

250 Ohm

ITRIP

ESD

Diode

5V

1 MOhm

V_SS

9

AUIRS2332J

V_B123

ESD

Diode

20V

HO₁₂₃

ESD

Diode

V_S123

10

AUIRS2332J

Lead Definitions

Symbol

Description

HIN1,2,3

LIN1,2,3

FAULT

Logic input for high side gate driver outputs (HO1,2,3), out of phase

Logic input for low side gate driver output (LO1,2,3), out of phase

Indicates over-current or undervoltage lockout (low side) has occurred, negative logic

Low side and logic fixed supply

V_CC

ITRIP

CAO

Input for over-current shutdown

Output of current amplifier

CA-

Negative input of current amplifier

Logic Ground

V_SS

V_B1,2,3

HO1,2,3

V_S1,2,3

LO1,2,3

V_SO

High side floating supply

High side gate drive output

High side floating supply return

Low side gate drive output

Low side return and positive input of current amplifier

#Leas7, #11, #13, #15, #17, #20, #21 are N.C.

Lead Assignments

Leads num. 7, 11, 13, 15, 17, 20 and 21 are N.C.

11

AUIRS2332J

Application Information and Additional Details

Information regarding the following topics are included as subsections within this section of the datasheet.

•

IGBT/MOSFET Gate Drive

Switching and Timing Relationships

Deadtime

Matched Propagation Delays

Input Logic Compatibility

Undervoltage Lockout Protection

Shoot-Through Protection

Fault Reporting

Over-Current Protection

Over-Temperature Shutdown Protection

Truth Table: Undervoltage lockout, ITRIP

Advanced Input Filter

Short-Pulse / Noise Rejection

Integrated Bootstrap Functionality

Bootstrap Power Supply Design

Separate Logic and Power Grounds

Negative V_STransient SOA

DC- bus Current Sensing

PCB Layout Tips

Additional Documentation

IGBT/MOSFET Gate Drive

The AUIRS2332J HVIC is designed to drive up to six MOSFET or IGBT power devices. Figures 1 and 2 illustrate several

parameters associated with the gate drive functionality of the HVIC. The output current of the HVIC, used to drive the gate of

the power switch, is defined as I_O. The voltage that drives the gate of the external power switch is defined as V_HOfor the

high-side power switch and V_LOfor the low-side power switch; this parameter is sometimes generically called V_OUTand in this

case does not differentiate between the high-side or low-side output voltage.

V_B

(or V_CC

)

(or V_CC)

I_O+

HO

(or LO)

+

I_O-

V_HO(or V_LO)

-

V_S

(or COM)

Figure 1: HVIC sourcing current

Figure 2: HVIC sinking current

12

AUIRS2332J

Switching and Timing Relationships

The relationship between the input and output signals of the AUIRS2332J are illustrated below in Figures 3. From these

figures, we can see the definitions of several timing parameters (i.e., PW_IN, PW_OUT, t_ON, t_OFF, t_R, and t_F) associated with this

device.

LINx

(or HINx)

50%

PW_IN

t_OFFt_F

t_ONt_R

PW_OUT

90%

10%

90%

10%

LOx

(or HOx)

Figure 3: Switching time waveforms

The following two figures illustrate the timing relationships of some of the functionalities of the AUIRS2332J. These

functionalities are described in further detail later in this document.

During interval A of Figure 4, the HVIC has received the command to turn-on both the high- and low-side switches at the

same time; as a result, the shoot-through protection of the HVIC has prevented this condition and both the high- and low-side

output are held in the off state.

Interval B of Figures 4 shows that the signal on the ITRIP input pin has gone from a low to a high state; as a result, all of the

gate drive outputs have been disabled (i.e., see that HOx has returned to the low state; LOx is also held low) and a fault is

reported by the FAULT output transitioning to the low state. Once the ITRIP input has returned to the low state, the fault

condition is latched until the all LINx become high.

B

A

HIN1,2,3

LIN1,2,3

ITRIP

FAULT

HO1,2,3

LO1,2,3

Figure 4: Input/output timing diagram

13

AUIRS2332J

Deadtime

This HVIC features integrated deadtime protection circuitry. The deadtime for this IC is fixed; other ICs within IR’s HVIC

portfolio feature programmable deadtime for greater design flexibility. The deadtime feature inserts a time period (a minimum

deadtime) in which both the high- and low-side power switches are held off; this is done to ensure that the power switch being

turned off has fully turned off before the second power switch is turned on. This minimum deadtime is automatically inserted

whenever the external deadtime is shorter than DT; external deadtimes larger than DT are not modified by the gate driver.

Figure 5 illustrates the deadtime period and the relationship between the output gate signals.

The deadtime circuitry of the AUIRS2332J is matched with respect to the high- and low-side outputs of a given channel;

additionally, the deadtimes of each of the three channels are matched.

Figure 5: Illustration of deadtime

Matched Propagation Delays

The AUIRS2332J HVIC is designed with propagation delay matching circuitry. With this feature, the IC’s response at the

output to a signal at the input requires approximately the same time duration (i.e., t_ON, t_OFF) for both the low-side channels and

the high-side channels. Additionally, the propagation delay for each low-side channel is matched when compared to the

other low-side channels and the propagation delays of the high-side channels are matched with each other. The propagation

turn-on delay (t_ON) of the AUIRS2332J is matched to the propagation turn-on delay (t_OFF).

Input Logic Compatibility

The inputs of this IC are compatible with standard CMOS and TTL outputs. The AUIRS2332J has been designed to be

compatible with 3.3 V and 5 V logic-level signals. The AUIRS2332J features an integrated 5.2 V Zener clamp on the HIN,

LIN, and ITRIP pins. Figure 6 illustrates an input signal to the AUIRS2332J, its input threshold values, and the logic state of

the IC as a result of the input signal.

14

AUIRS2332J

Figure 6: HIN & LIN input thresholds

Undervoltage Lockout Protection

This IC provides undervoltage lockout protection on both the V_CC(logic and low-side circuitry) power supply and the V_BS

(high-side circuitry) power supply. Figure 7 is used to illustrate this concept; V_CC(or V_BS) is plotted over time and as the

waveform crosses the UVLO threshold (V_CCUV+/-or V_BSUV+/-) the undervoltage protection is enabled or disabled.

Upon power-up, should the V_CCvoltage fail to reach the V_CCUV+threshold, the IC will not turn-on. Additionally, if the V_CC

voltage decreases below the V_CCUV-threshold during operation, the undervoltage lockout circuitry will recognize a fault

condition and shutdown the high- and low-side gate drive outputs, and the FAULT pin will transition to the low state to inform

the controller of the fault condition.

Upon power-up, should the V_BSvoltage fail to reach the V_BSUVthreshold, the IC will not turn-on. Additionally, if the V_BSvoltage

decreases below the V_BSUVthreshold during operation, the undervoltage lockout circuitry will recognize a fault condition, and

shutdown the high-side gate drive outputs of the IC.

The UVLO protection ensures that the IC drives the external power devices only when the gate supply voltage is sufficient to

fully enhance the power devices. Without this feature, the gates of the external power switch could be driven with a low

voltage, resulting in the power switch conducting current while the channel impedance is high; this could result in very high

conduction losses within the power device and could lead to power device failure.

Figure 7: UVLO protection

Shoot-Through Protection

15

AUIRS2332J

The AUIRS2332J is equipped with shoot-through protection circuitry (also known as cross-conduction prevention circuitry).

Figure 8 shows how this protection circuitry prevents both the high- and low-side switches from conducting at the same time.

Table 1 illustrates the input/output relationship of the devices in the form of a truth table. Note that the AUIRS2332J has

inverting inputs (the output is out-of-phase with its respective input).

Figure 8: Illustration of shoot-through protection circuitry

AUIRS2332J

HIN

0

LIN

0

HO

0

LO

0

1

0

1

0

1

0

Table 1: Input/output truth table

Fault Reporting

The AUIRS2332J provides an integrated fault reporting output. There are two situations that would cause the HVIC to report

a fault via the FAULT pin. The first is an undervoltage condition of V_CCand the second is if the ITRIP pin recognizes a fault.

Once the fault condition occurs, the FAULT pin is internally pulled to V_SSand the fault condition is latched. The fault output

stays in the low state until the fault condition has been removed by all LINx set to high state. Once the fault is removed, the

voltage on the FAULT pin will return to V_CC

.

Over-Current Protection

The AUIRS2332J HVICs are equipped with an ITRIP input pin. This functionality can be used to detect over-current events in

the DC- bus. Once the HVIC detects an over-current event through the ITRIP pin, the outputs are shutdown, a fault is

reported through the FAULT pin.

The level of current at which the over-current protection is initiated is determined by the resistor network (i.e., R₀, R₁, and R₂)

connected to ITRIP as shown in Figure 9, and the ITRIP threshold (V_IT,TH+). The circuit designer will need to determine the

maximum allowable level of current in the DC- bus and select R₀, R₁, and R₂such that the voltage at node V_Xreaches the

over-current threshold (V_IT,TH+) at that current level.

V_IT,TH+= R₀I_DC-(R₁/(R₁+R₂))

16

AUIRS2332J

V

cc

A

U

I

HIN(x3)

LIN(x3)

V (x3)

B

HO(x3)

R

S

2

3

2

J

FAULT

V (x3)

S

LO(x3)

COM

ITRIP

V

SS

R

1

R

2

R₀

IDC-

Figure 9: Programming the over-current protection

For example, a typical value for resistor R₀could be 50 mΩ. The voltage of the ITRIP pin should not be allowed to exceed 5

V; if necessary, an external voltage clamp may be used.

Over-Temperature Shutdown Protection

The ITRIP input of the AUIRS2332J can also be used to detect over-temperature events in the system and initiate a

shutdown of the HVIC (and power switches) at that time. In order to use this functionality, the circuit designer will need to

design the resistor network as shown in Figure 10 and select the maximum allowable temperature.

This network consists of a thermistor and two standard resistors R₃and R₄. As the temperature changes, the resistance of

the thermistor will change; this will result in a change of voltage at node V_X. The resistor values should be selected such the

voltage V_Xshould reach the threshold voltage (V_IT,TH+) of the ITRIP functionality by the time that the maximum allowable

temperature is reached. The voltage of the ITRIP pin should not be allowed to exceed 5 V.

When using both the over-current protection and over-temperature protection with the ITRIP input, OR-ing diodes (e.g.,

DL4148) can be used. This network is shown in Figure 11; the OR-ing diodes have been labeled D₁and D₂.

Figure 10: Programming over-temperature protection Figure 11: Using over-current protection and over-temperature

protection

Truth Table: Undervoltage lockout and ITRIP

17

AUIRS2332J

Table 2 provides the truth table for the AUIRS2332J. The first line shows that the UVLO for V_CChas been tripped; the FAULT

output has gone low and the gate drive outputs have been disabled.

is not latched in this case and when V_CCis greater

V_CCUV

than

, the FAULT output returns to the high impedance state.

V_CCUV

The second case shows that the UVLO for V_BShas been tripped and that the high-side gate drive outputs have been

disabled. After V_BSexceeds the , HO will stay low until the HVIC input receives a new falling transition of HIN.

V_BSUVthreshold

The third case shows the normal operation of the HVIC. The fourth case illustrates that the ITRIP trip threshold has been

reached and that the gate drive outputs have been disabled and a fault has been reported through the fault pin. The fault

output stays in the low state until the fault condition has been removed by all LINx set to high state. Once the fault is

removed, the voltage on the FAULT pin will return to V_CC

.

VCC

VBS

---

ITRIP

---

0 V

>V_ITRIP

FAULT

LO

0

LIN

0

HO

0

HIN

0

<

UVLO V_CC

UVLO V_BS

Normal operation

ITRIP fault

0

V_CCUV

15 V

<

High impedance

0

V_BSUV

15 V

Table 2: AUIRS2332J UVLO, ITRIP & FAULT truth table

Advanced Input Filter

The advanced input filter allows an improvement in the input/output pulse symmetry of the HVIC and helps to reject noise

spikes and short pulses. This input filter has been applied to the HIN and LIN. The working principle of the new filter is shown

in Figures 12 and 13.

Figure 12 shows a typical input filter and the asymmetry of the input and output. The upper pair of waveforms (Example 1)

shows an input signal with a duration much longer then t_FIL,IN; the resulting output is approximately the difference between the

input signal and t_FIL,IN

.

The lower pair of waveforms (Example 2) show an input signal with a duration slightly longer then

t_FIL,IN; the resulting output is approximately the difference between the input signal and t_FIL,IN

.

Figure 13 shows the advanced input filter and the symmetry between the input and output. The upper pair of waveforms

(Example 1) show an input signal with a duration much longer then t_FIL,IN; the resulting output is approximately the same

duration as the input signal. The lower pair of waveforms (Example 2) show an input signal with a duration slightly longer

then t_FIL,IN; the resulting output is approximately the same duration as the input signal.

Figure 12: Typical input filter

Figure 13: Advanced input filter

Short-Pulse / Noise Rejection

18

AUIRS2332J

This device’s input filter provides protection against short-pulses (e.g., noise) on the input lines. If the duration of the input

signal is less than t_FIL,IN, the output will not change states. Example 1 of Figure 14 shows the input and output in the low state

with positive noise spikes of durations less than t_FIL,IN; the output does not change states. Example 2 of Figure 19 shows the

input and output in the high state with negative noise spikes of durations less than t_FIL,IN; the output does not change states.

Figure 14: Noise rejecting input filters

Figures 15 and 16 present lab data that illustrates the characteristics of the input filters while receiving ON and OFF pulses.

The input filter characteristic is shown in Figure 15; the left side illustrates the narrow pulse ON (short positive pulse)

characteristic while the left shows the narrow pulse OFF (short negative pulse) characteristic. The x-axis of Figure 20 shows

the duration of PW_IN, while the y-axis shows the resulting PW_OUTduration. It can be seen that for a PW_INduration less than

t_FIL,IN, that the resulting PW_OUTduration is zero (e.g., the filter rejects the input signal/noise). We also see that once the PW_IN

duration exceed t_FIL,IN, that the PW_OUTdurations mimic the PW_INdurations very well over this interval with the symmetry

improving as the duration increases. To ensure proper operation of the HVIC, it is suggested that the input pulse width for

the high-side inputs be ≥ 500 ns.

The difference between the PW_OUTand PW_INsignals of both the narrow ON and narrow OFF cases is shown in Figure 16;

the careful reader will note the scale of the y-axis. The x-axis of Figure 21 shows the duration of PW_IN, while the y-axis shows

the resulting PW_OUT–PW_INduration. This data illustrates the performance and near symmetry of this input filter.

Figure 15: AUIRS2332J input filter characteristic

19

AUIRS2332J

Figure 16: Difference between the input pulse and the output pulse

Separate Logic and Power Grounds

The AUIRS2332J has separate logic and power ground pin (V_SSand VSO respectively) to eliminate some of the noise

problems that can occur in power conversion applications. Current sensing shunts are commonly used in many applications

for power inverter protection (i.e., over-current protection), and in the case of motor drive applications, for motor current

measurements. In these situations, it is often beneficial to separate the logic and power grounds.

Figure 19 shows a HVIC with separate V_SSand VSO pins and how these two grounds are used in the system. The V_SSis

used as the reference point for the logic and over-current circuitry; V_Xin the figure is the voltage between the ITRIP pin and

the V_SSpin. Alternatively, the VSO pin is the reference point for the low-side gate drive circuitry. The output voltage used to

drive the low-side gate is V_LO-VSO; the gate-emitter voltage (V_GE) of the low-side switch is the output voltage of the driver

minus the drop across R_G,LO

.

DC+ BUS

D_BS

V_B

(x3)

V_CC

C_BS

HO

R_G,HO

(x3)

V_S

(x3)

V_S1

V_S2

V_S3

LO

(x3)

R_G,LO

ITRIP

+

V_GE1

V_GE2

V_GE3

-

V_SS

COM

R₂

R₀

+

R₁

V_X

-

DC- BUS

Figure 19: Separate V_SSand VSO (COM) pins

Negative V_STransient SOA

20

AUIRS2332J

A common problem in today’s high-power switching converters is the transient response of the switch node’s voltage as the

power switches transition on and off quickly while carrying a large current. A typical 3-phase inverter circuit is shown in

Figure 20; here we define the power switches and diodes of the inverter.

If the high-side switch (e.g., the IGBT Q1 in Figures 21 and 22) switches off, while the U phase current is flowing to an

inductive load, a current commutation occurs from high-side switch (Q1) to the diode (D2) in parallel with the low-side switch

of the same inverter leg. At the same instance, the voltage node V_S1, swings from the positive DC bus voltage to the negative

DC bus voltage.

Figure 20: Three phase inverter

DC+ BUS

Q1

ON

I_U

V_S1

D2

Q2

OFF

DC- BUS

Figure 21: Q1 conducting

Figure 22: D2 conducting

Also when the V phase current flows from the inductive load back to the inverter (see Figures 23 and 24), and Q4 IGBT

switches on, the current commutation occurs from D3 to Q4. At the same instance, the voltage node, V_S2, swings from the

positive DC bus voltage to the negative DC bus voltage.

21

AUIRS2332J

Figure 23: D3 conducting

Figure 24: Q4 conducting

However, in a real inverter circuit, the V_Svoltage swing does not stop at the level of the negative DC bus, rather it swings

below the level of the negative DC bus. This undershoot voltage is called “negative V_Stransient”.

The circuit shown in Figure 25 depicts one leg of the three phase inverter; Figures 26 and 27 show a simplified illustration of

the commutation of the current between Q1 and D2. The parasitic inductances in the power circuit from the die bonding to the

PCB tracks are lumped together in L_Cand L_Efor each IGBT. When the high-side switch is on, V_S1is below the DC+ voltage

by the voltage drops associated with the power switch and the parasitic elements of the circuit. When the high-side power

switch turns off, the load current momentarily flows in the low-side freewheeling diode due to the inductive load connected to

V_S1(the load is not shown in these figures). This current flows from the DC- bus (which is connected to the VSO pin of the

HVIC) to the load and a negative voltage between V_S1and the DC- Bus is induced (i.e., the VSO pin of the HVIC is at a

higher potential than the V_Spin).

Figure 25: Parasitic Elements

Figure 26: V_Spositive

Figure 27: V_Snegative

In a typical motor drive system, dV/dt is typically designed to be in the range of 3-5 V/ns. The negative V_Stransient voltage

can exceed this range during some events such as short circuit and over-current shutdown, when di/dt is greater than in

normal operation.

International Rectifier’s HVICs have been designed for the robustness required in many of today’s demanding applications.

An indication of the AUIRS2332J’s robustness can be seen in Figure 28, where there is represented the AUIRS2332J Safe

Operating Area at V_BS=15V based on repetitive negative V_Sspikes. A negative V_Stransient voltage falling in the grey area

(outside SOA) may lead to IC permanent damage; viceversa unwanted functional anomalies or permanent damage to the IC

do not appear if negative Vs transients fall inside SOA.

At V_BS=15V in case of -V_Stransients greater than -16.5 V for a period of time greater than 50 ns; the HVIC will hold by design

the high-side outputs in the off state for 4.5 µs.

22

AUIRS2332J

Figure 28: Negative V_Stransient SOA for AUIRS2332J

Even though the AUIRS2332J has been shown able to handle these large negative V_Stransient conditions, it is highly

recommended that the circuit designer always limit the negative V_Stransients as much as possible by careful PCB layout and

component use.

DC- bus Current Sensing

A ground referenced current signal amplifier has been included so that the current in the return leg of the DC bus may be

monitored. A typical circuit configuration is provided in Fig.29. The signal coming from the shunt resistor is amplified by the

ratio (R1+R2)/R2. Additional details can be found on Design Tip DT 92-6. This design tip is available at www.irf.com.

Figure 29: Current amplifier typical configuration

In the following Figures 30, 31, 32, 33 the configurations used to measure the operational amplifier characteristics are shown.

23

AUIRS2332J

15

V

V_CC

1V

CA-

CAO

0V

50pF

V

SS

SO

V

T1

1V

0V

T2

90%

V

10%

V

T1

V

T2

SR

-

+

SR

Figure 30: Operational Amplifier Slew rate measurement

Figure 31: Operational Amplifier Input Offset Voltage

measurement

15V

V

CC

-

CA

CAO

V

SO

V

SS

at V

_CAO2at V

0.1V

=1.1V

Measure V

=

SO

CAO1

V

(V_CAO1–0.1V)–(V_CAO2–1.1V)

1V

(dB)

LOG

*

CMRR -20

=

Figure 32: Operational Amplifier Common mode rejection

measurement

Figure 33: Operational Amplifier Power supply rejection

measurement

PCB Layout Tips

Distance between high and low voltage components: It’s strongly recommended to place the components tied to the floating

voltage pins (V_Band V_S) near the respective high voltage portions of the device. The AUIRS2332J in the PLCC44 package

has had some unused pins removed in order to maximize the distance between the high voltage and low voltage pins.

Please see the Case Outline PLCC44 information in this datasheet for the details.

Ground Plane: In order to minimize noise coupling, the ground plane should not be placed under or near the high voltage

floating side.

Gate Drive Loops: Current loops behave like antennas and are able to receive and transmit EM noise (see Figure 34). In

order to reduce the EM coupling and improve the power switch turn on/off performance, the gate drive loops must be reduced

as much as possible. Moreover, current can be injected inside the gate drive loop via the IGBT collector-to-gate parasitic

24

AUIRS2332J

capacitance. The parasitic auto-inductance of the gate loop contributes to developing a voltage across the gate-emitter, thus

increasing the possibility of a self turn-on effect.

Figure 34: Antenna Loops

Supply Capacitor: It is recommended to place a bypass capacitor (C_IN) between the V_CCand V_SSpins. This connection is

shown in Figure 35. A ceramic 1 µF ceramic capacitor is suitable for most applications. This component should be placed as

close as possible to the pins in order to reduce parasitic elements.

V

cc

HIN(x3)

LIN(x3)

V (x3)

B

HO(x3)

FAULT

V (x3)

S

LO(x3)

COM

ITRIP

V

SS

R

1

R

2

R₀

IDC-

Figure 35: Supply capacitor

Routing and Placement: Power stage PCB parasitic elements can contribute to large negative voltage transients at the switch

node; it is recommended to limit the phase voltage negative transients. In order to avoid such conditions, it is recommended

to 1) minimize the high-side emitter to low-side collector distance, and 2) minimize the low-side emitter to negative bus rail

stray inductance. However, where negative V_Sspikes remain excessive, further steps may be taken to reduce the spike.

This includes placing a resistor (5 Ω or less) between the V_Spin and the switch node (see Figure 36), and in some cases

using a clamping diode between V_SSand V_S(see Figure 37). See DT04-4 at www.irf.com for more detailed information.

25

AUIRS2332J

Figure 36: V_Sresistor

Figure 37: V_Sclamping diode

Additional Documentation

Several technical documents related to the use of HVICs are available at www.irf.com; use the Site Search function and

the document number to quickly locate them. Below is a short list of some of these documents.

DT97-3: Managing Transients in Control IC Driven Power Stages

AN-1123: Bootstrap Network Analysis: Focusing on the Integrated Bootstrap Functionality

DT04-4: Using Monolithic High Voltage Gate Drivers

AN-978: HV Floating MOS-Gate Driver ICs

26

AUIRS2332J

Parameter Temperature Trends

Figures illustrated in this chapter provide information on the experimental performance of the AUIRS2332J

HVIC. The line plotted in each figure is generated from actual lab data. A large number of individual samples

were tested at three temperatures (-40 ºC, 25 ºC, and 125 ºC) in order to generate the experimental curve. The

line consists of three data points (one data point at each of the tested temperatures) that have been connected

together to illustrate the understood trend. The individual data points on the Typ. curve were determined by

calculating the averaged experimental value of the parameter (for a given temperature).

Figure 38. Turn-on propagation delay vs. temperature

Figure 39. Turn-off propagation delay vs. temperature

Figure 40. Turn-on rise time vs. temperature

Figure 41. Turn-off fall time vs. temperature

27

AUIRS2332J

Figure 42. ITRIP to output shutdown propagation delay vs.

temperature

Figure 43. ITRIP to FAULT’ indication delay vs.

temperature

Figure 44. Dead time vs. temperature

Figure 45. Offset supply leakage current vs. temperature

Figure 46. Quiescent V_CCsupply current vs. temperature

Figure 47. Quiescent V_BSsupply current vs. temperature

28

AUIRS2332J

Figure 48. High level output voltage vs. temperature

Figure 49. Low level output voltage vs. temperature

Figure 50. V_CCsupply undervoltage positive going

threshold vs. temperature

Figure 51. V_CCsupply undervoltage negative going

threshold vs. temperature

Figure 53. V_BSsupply undervoltage negative going

threshold vs. temperature

Figure 52. V_BSsupply undervoltage positive going

threshold vs. temperature

29

AUIRS2332J

Figure 54. ITRIP input positive going threshold vs.

temperature

Figure 55. Op-amp input offset voltage vs. temperature

Figure 56. Op-amp high level output voltage vs. temperature

30

AUIRS2332J

Case Outlines

31

AUIRS2332J

Package Land Pattern

32

AUIRS2332J

Tape and Reel Details: PLCC44

LOADED TAPE FEED DIRECTION

A

B

H

D

F

C

NOTE : CONTROLLING

DIMENSION IN MM

E

G

CARRIER TAPE DIMENSION FOR 44PLCC

Metric

Imperial

Code

A

B

C

D

E

F

G

H

Min

23.90

3.90

31.70

14.10

17.90

2.00

Max

24.10

4.10

32.30

14.30

18.10

n/a

Min

0.94

Max

0.948

0.161

1.271

0.562

0.712

n/a

0.153

1.248

0.555

0.704

0.078

0.059

1.50

1.60

0.062

F

D

B

C

A

E

G

H

REEL DIMENSIONS FOR 44PLCC

Metric

Imperial

Max

Code

A

B

C

D

Min

329.60

20.95

12.80

1.95

Max

330.25

21.45

13.20

2.45

Min

12.976

0.824

0.503

0.767

3.858

n/a

13.001

0.844

0.519

0.096

4.015

1.511

1.409

1.303

E

F

98.00

n/a

102.00

38.4

G

34.7

35.8

1.366

1.283

H

32.6

33.1

33

AUIRS2332J

Part Marking Information

Ordering Information

Standard Pack

Base Part Number

Package Type

Complete Part Number

Form

Quantity

Tube/Bulk

27

AUIRS2332J

PLCC44

AUIRS2332J

Tape and Reel

500

AUIRS2332JTR

34

AUIRS2332J

IMPORTANT NOTICE

Unless specifically designated for the automotive market, International Rectifier Corporation and its

subsidiaries (IR) reserve the right to make corrections, modifications, enhancements, improvements, and other

changes to its products and services at any time and to discontinue any product or services without notice. Part

numbers designated with the “AU” prefix follow automotive industry and / or customer specific requirements

with regards to product discontinuance and process change notification. All products are sold subject to IR’s

terms and conditions of sale supplied at the time of order acknowledgment.

IR warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with IR’s standard warranty. Testing and other quality control techniques are used to the extent IR

deems necessary to support this warranty. Except where mandated by government requirements, testing of all

parameters of each product is not necessarily performed.

IR assumes no liability for applications assistance or customer product design. Customers are responsible for

their products and applications using IR components. To minimize the risks with customer products and

applications, customers should provide adequate design and operating safeguards.

Reproduction of IR information in IR data books or data sheets is permissible only if reproduction is without

alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction

of this information with alterations is an unfair and deceptive business practice. IR is not responsible or liable

for such altered documentation. Information of third parties may be subject to additional restrictions.

Resale of IR products or serviced with statements different from or beyond the parameters stated by IR for that

product or service voids all express and any implied warranties for the associated IR product or service and is

an unfair and deceptive business practice. IR is not responsible or liable for any such statements.

IR products are not designed, intended, or authorized for use as components in systems intended for surgical

implant into the body, or in other applications intended to support or sustain life, or in any other application in

which the failure of the IR product could create a situation where personal injury or death may occur. Should

Buyer purchase or use IR products for any such unintended or unauthorized application, Buyer shall indemnify

and hold International Rectifier and its officers, employees, subsidiaries, affiliates, and distributors harmless

against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or

indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if

such claim alleges that IR was negligent regarding the design or manufacture of the product.

Only products certified as military grade by the Defense Logistics Agency (DLA) of the US Department of

Defense, are designed and manufactured to meet DLA military specifications required by certain military,

aerospace or other applications. Buyers acknowledge and agree that any use of IR products not certified by

DLA as military-grade, in applications requiring military grade products, is solely at the Buyer’s own risk and

that they are solely responsible for compliance with all legal and regulatory requirements in connection with

such use.

IR products are neither designed nor intended for use in automotive applications or environments unless the

specific IR products are designated by IR as compliant with ISO/TS 16949 requirements and bear a part

number including the designation “AU”. Buyers acknowledge and agree that, if they use any non-designated

products in automotive applications, IR will not be responsible for any failure to meet such requirements.

For technical support, please contact IR’s Technical Assistance Center

http://www.irf.com/technical-info/

WORLD HEADQUARTERS:

101 N. Sepulveda Blvd., El Segundo, California 90245

Tel: (310) 252-7105

35

Revision History

Date

Comment

Jul. 7, 2010

Converted from industrial datasheet

Typ Application section updated in front page.

July 28, 2010 Logic block diagram modified because UVVcc is not latched.

Added Input Output equivalent circuit diagram

May 6, 2011

Added tri-temp graphs; updated qual info page and table of contents. Formated to AU DS format

Ton and toff typ values changed from 500ns to 540ns.Tf typ from 35ns to 40ns

DT typ from 700ns to 850ns.Iqbs typ from 30uA to 37uA; Iqcc typ from 4.0uA to 4.5uA.

ITRIP to Output Shutdown Propagation delay typ from 660ns to 625ns. VOH max from 1V to 1.1V.

VCCUV+ typ from 9V to 8.9V; VCCUV- from 8.7V to 8.6V. VBSUV+ typ from 8.35V to 8.3V; VCCUV- from

7.95V to 7.9V.

May 11, 2011

Iin+ min changed from -400 to -450; Iin- min changed from -300 to -350; Io- min changed from

May 11, 2011 420 to 375; Tr max changed from 125 to 145; MDT max change from 140 to 145; VOH max

changed from 1.1 to 1.15.

May 13, 2011 Changed formula in Figure 31

May 17, 2011 Updated CDM class

Rth_JC

June 7, 2011 Added

June 24, 2011 Updated disclaimer

August 30^th,

Updated Case Outline (more readable) and added Package Land Pattern

2012

September, 3^rd, Added NC (not connected) in lead assignment figure and text.

2012

Package Land Pattern updated

* Qualification standards can be found on IR’s web site www.irf.com


型号：	AUIRS2332J_15
厂家：	Infineon
描述：	Floating channel designed for bootstrap operation
文件：	总36页 (文件大小：1181K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AUIRS2332J_15 [INFINEON]

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