AUIRS211S [INFINEON]
SINGLE CHANNEL DRIVER;
| 型号： | AUIRS211S |
| 厂家： | 
Infineon |
| 描述： | SINGLE CHANNEL DRIVER 驱动 |
| 文件： | 总21页 (文件大小：659K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Automotive Grade
AUIRS211(7,8)S
SINGLE CHANNEL DRIVER
Features
Product Summary
Floating channel designed for bootstrap operation
Topology
VOFFSET
Single High Side
≤ 600 V
Fully operational to +600 V
Tolerant to negative transient voltage - dV/dt immune
Gate drive supply range from 10 V to 20 V
Undervoltage lockout
CMOS Schmitt-triggered inputs with pull-down
(AUIRS2117) or pull-up (AUIRS2118)
Output in phase with input (AUIRS2117) or out of
Phase with input (AUIRS2118)
VOUT
10 V – 20 V
Io+ & I o- (typical)
290 mA & 600 mA
140 ns & 140 ns
tON & tOFF (typical)
Leadfree, RoHS compliant
Automotive qualified*
Package Options
Typical Applications
Direct/Piezo injection
BLDC Motor Drive
MOSFET and IGBT drivers
8-Lead SOIC
Typical Connection Diagram
Up to 600 V
VB
Vcc
IN
Vcc
IN
HO
VS
TO
LOAD
COM
AUIRS2117
Up to 600 V
VB
Vcc
IN
Vcc
IN
HO
VS
TO
LOAD
COM
(Refer to Lead Assignments for correct pin configuration). This/These
diagram(s) show electrical connections only. Please refer to our
Application Notes and Design Tips for proper circuit board layout.
AUIRS2118
1
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AUIRS211(7,8)S
Table of Contents
Page
Description
3
Qualification Information
Absolute Maximum Ratings
Recommended Operating Conditions
Static Electrical Characteristics
Dynamic Electrical Characteristics
Functional Block Diagram
Input/Output Pin Equivalent Circuit Diagram
Lead Definitions
4
5
5
6
6
7
8
9
Lead Assignments
9
Application Information and Additional Details
Parameter Temperature Trends
Package Details
10-13
13-16
17
18
19
20
Tape and Reel Details
Part Marking Information
Ordering Information
2
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AUIRS211(7,8)S
Description
The AUIRS2117S/AUIRS2118S are high voltage, high speed power MOSFET and IGBT drivers. Proprietary
HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. The logic input is
compatible with standard CMOS outputs. The output drivers feature a high pulse current buffer stage. The
floating channel can be used to drive an N-channel power MOSFET or IGBT in the high- side or low-side
configuration which operates up to 600 V.
Qualification Information†
Automotive
(per AEC-Q100)
Comments: This family of ICs has passed an Automotive
qualification. IR’s Industrial and Consumer qualification
Qualification Level
level is granted by extension of the higher Automotive
level.
MSL3†† 260°C
(per IPC/JEDEC J-STD-020)
Moisture Sensitivity Level
ESD
SOIC8N
Class M2 (Pass +/-200V)
(per AEC-Q100-003)
Class H1B (Pass +/-1000V)
Machine Model
Human Body Model
Charged Device Model
(
)
per AEC-Q100-002
Class C4 (Pass +/-1000V)
(per AEC-Q100-011)
Class II, Level A
(per AEC-Q100-004)
Yes
IC Latch-Up Test
RoHS Compliant
†
Qualification standards can be found at International Rectifier’s web site http://www.irf.com/
†† Higher MSL ratings may be available for the specific package types listed here. Please contact your
International Rectifier sales representative for further information.
3
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AUIRS211(7,8)S
Absolute Maximum Ratings
Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage
parameters are absolute voltages referenced to COM lead. Stresses beyond those listed under "
Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only; and
functional operation of the device at these or any other condition beyond those indicated in the “Recommended
Operating Conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may
affect device reliability. The thermal resistance and power dissipation ratings are measured under board
mounted and still air conditions. Ambient temperature (TA) is 25°C, unless otherwise specified.
Symbol
Definition
Min.
Max.
Units
VB
VS
High-side floating absolute voltage
High-side floating supply offset voltage
High-side floating output voltage
Logic supply voltage
-0.3
VB - 25
VS - 0.3
-0.3
625
VB + 0.3
VB + 0.3
25
V
VHO
VCC
VIN
Logic input voltage
-0.3
VCC + 0.3
50
dVS/dt
Allowable offset supply voltage transient (Fig. 2)
—
V/ns
W
PD
Package power dissipation @ TA ≤ 25°C
—
—
0.625
200
RthJA
Thermal resistance, junction to ambient
°C/W
°C
Junction temperature
TJ
TS
TL
—
-55
—
150
150
300
Storage temperature
Lead temperature (soldering, 10 seconds)
Recommended Operating Conditions
The input/output logic timing diagram is shown in Fig. 1. For proper operation the device should be used within
the recommended conditions. The VS offset rating is tested with all supplies biased at 15 V differential.
Symbol
VB
Definition
High-side floating supply absolute voltage
High-side floating supply offset voltage
High-side floating output voltage
Logic supply voltage
Min
VS +10
†
Max
VS +20
600
VB
Units
VS
VHO
VCC
VIN
VS
V
10
20
Logic input voltage
0
VCC
TA
Ambient temperature
-40
125
°C
† Logic operational for VS of -5 V to +600 V. Logic state held for VS of -5 V to – VBS.
(Please refer to the Design Tip DT97-3 for more details).
4
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AUIRS211(7,8)S
Static Electrical Characteristics
Unless otherwise noted, these specifications apply for an operating junction temperature range of -40°C ≤ Tj ≤
125°C with bias conditions of VBIAS (VCC, VBS) = 15 V. The VIL, VIH and IIN parameters are referenced to COM. The
VO and IO parameters are referenced to COM and are applicable to the respective output leads: HO.
Symbol
VIH
Definition
Min Typ Max Units
Test Conditions
AUIRS2117
AUIRS2118
AUIRS2117
AUIRS2118
Logic “1” input voltage
9.5
—
—
—
VIL
Logic “0” input voltage
—
6.0
V
VOH
VOL
ILK
High level output voltage, VBIAS - VO
—
—
—
—
—
0.05 0.2
0.02 0.2
IO = 2 mA
†
Low level output voltage, VO
Offset supply leakage current
Quiescent VBS supply current
Quiescent VCC supply current
—
50
VB = VS = 600 V
VIN = 0 V or VCC
IQBS
IQCC
IIN+
50 240
70 340
µA
AUIRS2117
AUIRS2118
AUIRS2117
AUIRS2118
VIN = VCC
VIN = 0 V
VIN = VCC
Logic “1” input bias current
Logic “0” input bias current
—
—
20
40
IIN-
—
5.0
VBSUV+
VBSUV-
VCCUV+
VBS supply undervoltage positive going threshold 7.6 8.6 9.6
VBS supply undervoltage negative going threshold 7.2 8.2 9.2
VCC supply undervoltage positive going threshold 7.6 8.6 9.6
V
VCCUV-
VCC supply undervoltage negative going threshold 7.2 8.2 9.2
VO = 0 V,
VIN = Logic “1”
PW ≤ 10 µs
VO = 15 V,
VIN = Logic “0”
PW ≤ 10 µs
IO+
Output high short circuit pulsed current
Output low short circuit pulsed current
200 290
420 600
—
—
mA
IO-
Dynamic Electrical Characteristics
Unless otherwise noted, these specifications apply for an operating junction temperature range of -40°C ≤ Tj ≤
125°C with bias conditions of VBIAS (VCC, VBS) = 15 V, CL = 1000 pF. The dynamic electrical characteristics are
measured using the test circuit shown in Fig. 3.
Symbol
Definition
Min
—
Typ Max Units
Test Conditions
VS = 0 V
ton
toff
t r
Turn-on propagation delay
Turn-off propagation delay
Turn-on rise time
140
140
75
225
225
130
65
VS = 600 V
—
ns
—
tf
Turn-off fall time
—
25
Note: Please refer to figures in Parameter Temperature Trends section
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AUIRS211(7,8)S
Functional Block Diagram: (AUIRS2117)
AUIRS2117
VB
VCC
UV
DETECT
R
Q
HV
LEVEL
SHIFTER
R
S
PULSE
FILTER
HO
IN
PULSE
GENERATOR
VS
UV
DETECT
COM
Functional Block Diagram: (AUIRS2118)
AUIRS2118
6
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AUIRS211(7,8)S
Input/Output Pin Equivalent Circuit Diagrams: AUIRS2117S
VB
ESD
Diode
VCC
25V
HO
ESD
Diode
ESD
Diode
IN
VS
RESD
ESD
Diode
600V
RPD
VCC
COM
25V
COM
Input/Output Pin Equivalent Circuit Diagrams: AUIRS2118S
VB
ESD
Diode
VCC
25V
HO
ESD
Diode
ESD
Diode
RPU
IN
VS
RESD
ESD
600V
Diode
VCC
COM
25V
COM
7
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AUIRS211(7,8)S
Lead Definitions
Symbol
Description
PIN
1
VCC
IN
IN
Low-side and logic fixed supply
Logic input for gate driver output (HO), in phase with HO (AUIRS2117)
Logic input for gate driver output (HO), out of phase with HO (AUIRS2118)
2
COM
NC
NC
VS
Logic ground
3
4
5
6
7
8
No Connection
No Connection
High-side floating supply return
High-side gate drive output
High-side floating supply
HO
VB
Lead Assignments
VCC
IN
VCC
IN
1
VB
HO
VS
1
VB
HO
VS
8
8
2
3
4
7
6
5
2
3
4
7
6
5
COM
COM
8 Lead SOIC
8 Lead SOIC
AUIRS2117S
AUIRS2118S
Part Number
8
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AUIRS211(7,8)S
Application Information and Additional Details
HV = 10 V to 600 V
+
VCC = 15 V
IN
10 k F6
8
200
µH
100 µF
0.1
µF
0.1
µF
(AUIRS2118)
10 µF
10 k
F6
1
6
7
2
HO
10 k F6
dV
s > 50 V/ns
dt
AUIRS2117
AUIRS2118
3
OUTPUT
MONITOR
IN
(AUIRS2117)
AUIRF820
HO
Figure 2: Floating Supply Voltage Transient
Test Circuit
Figure 1: Input/Output Timing Diagram
IN
(AUIRS2118)
VCC = 15 V
50%
50%
50%
50%
VB
15 V
VS
(O V to 600 V)
10 µF
0.1
µF
10
µF
0.1
µF
10 µF
1
8
6
CL
2
7
IN
(AUIRS2117)
HO
IN
toff
tr
tf
ton
AUIRS2117
AUIRS2118
3
90%
90%
10%
10%
HO
Figure 4: Switching Time Waveform
Definition
Figure 3: Switching Time Test Circuit
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AUIRS211(7,8)S
Tolerant to Negative VS Transients
A common problem in today’s high-power switching converters is the transient response of the switch node’s
voltage as the power switches transition on and off quickly while carrying a large current. A typical half bridge
circuit is shown in Figure 5; here we define the power switches and diodes of the inverter.
If the high-side switch (e.g., Q1 in Figures 6 and 7) switches off, while the current is flowing to a load, a current
commutation occurs from high-side switch (Q1) to the diode (D2) in parallel with the low-side switch of the
inverter. At the same instance, the voltage node VS swings from the positive DC bus voltage to the negative
DC bus voltage.
Figure 5: Half Bridge Circuit
Also when the current flows from the load back to the inverter (see Figures 8 and 9), and Q2 switches on, the
current commutation occurs from D1 to Q2. At the same instance, the voltage node VS swings from the positive
DC bus voltage to the negative DC bus voltage.
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AUIRS211(7,8)S
However, in a real inverter circuit, the VS voltage swing does not stop at the level of the negative DC bus,
rather it swings below the level of the negative DC bus. This undershoot voltage is called “negative VS
transient”.
The circuit shown in Figure 10 depicts a half bridge circuit with parasitic elements shown; Figures 11 and 12
show a simplified illustration of the commutation of the current between Q1 and D2. The parasitic inductances
in the power circuit from the die bonding to the PCB tracks are lumped together in LD and LS for each switch.
When the high-side switch is on, VS is below the DC+ voltage by the voltage drops associated with the power
switch and the parasitic elements of the circuit. When the high-side power switch turns off, the load current can
momentarily flow in the low-side freewheeling diode due to the inductive load connected to VS (the load is not
shown in these figures). This current flows from the DC- bus (which is connected to the COM pin of the HVIC)
to the load and a negative voltage between VS and the DC- Bus is induced (i.e., the COM pin of the HVIC is at
a higher potential than the VS pin).
In a typical power circuit, dV/dt is typically designed to be in the range of 1-5 V/ns. The negative VS transient
voltage can exceed this range during some events such as short circuit and over-current shutdown, when di/dt
is greater than in normal operation.
International Rectifier’s HVICs have been designed for the robustness required in many of today’s demanding
applications. An indication of the AUIRS2117(8)s’ robustness can be seen in Figure 13, where there is
represented the IRS2117(8)S Safe Operating Area at VBS=15V based on repetitive negative VS spikes. A
negative VS transient voltage falling in the grey area (outside SOA) may lead to IC permanent damage;
viceversa unwanted functional anomalies or permanent damage to the IC do not appear if negative Vs
transients fall inside SOA.
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AUIRS211(7,8)S
Figure 13: Negative VS transient SOA for AUIRS2117(8)S @ VBS=15V
Even though the AUIRS2117(8)S has shown the ability to handle these large negative VS transient conditions, it
is highly recommended that the circuit designer always limit the negative VS transients as much as possible by
careful PCB layout and component use.
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AUIRS211(7,8)S
Parameter Temperature Trends
Figures 14-28 provide information on the experimental performance of the AUIRS2117(8)S HVIC. The line
plotted in each figure is generated from actual lab data. A large number of individual samples were tested at
three temperatures (-40 ºC, 25 ºC, and 125 ºC) in order to generate the experimental curve.
The line consists of three data points (one data point at each of the tested temperatures) that have been
connected together to illustrate the understood trend. The individual data points on the Typ. curve were
determined by calculating the averaged experimental value of the parameter (for a given temperature).
220
220
190
190
160
160
Max.
Max.
130Typ.
130Typ.
Min.
Min.
100
100
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Figure 15. Turn-Off Time vs. Temperature
Figure 14. Turn-On Time vs. Temperature
50
100
40
30
20
10
80
60
40
20
Max.
Typ.
Max.
Typ.
Min.
Min.
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Figure 16. Turn-On Rise Time vs. Temperature
Figure 17. Turn-Off Fall Time vs. Temperature
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0.10
0.08
0.06
0.04
0.02
0.25
0.20
0.15
0.10
0.05
0.00
Max.
Typ.
Max.
Typ.
Min.
Min.
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Figure 19. Low Level Output Voltage vs. Temperature
Figure 18. High Level Output Voltage vs. Temperature
50
100
85
35
Max.
20
70
Max.
5
55
Typ.
Typ.
Min.
Min.
-10
40
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Figure 20. Offset Supply Leakage Current vs.
Temperature
Figure 21. VBS Supply Current vs. Temperature
20
18
16
14
250
200
150
Max.
Max.
100
12
Typ.
Typ.
Min.
10
50
Min.
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Figure 23. Logic “1” Input Current vs. Temperature
Figure 22. VCC Supply Current vs. Temperature
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-4.00
-6.00
9.0
8.8
8.6
8.4
8.2
8.0
Max.
Typ
Max.
Min.
-8.00
Typ.
Min.
-10.00
-12.00
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Figure 24. Logic “0” (2118 “1”) Input Current vs.
Temperature
Figure 25. VCC Undervoltage Threshold (+) vs.
Temperature
9.0
8.8
8.5
Max
8.3
Max.
8.6
8.1
Typ.
Typ.
8.4
7.9
8.2
7.7
Min.
Min.
8.0
7.5
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (oC)
Temperature (oC)
Figure 26. VCC Undervoltage Threshold (-) vs.
Temperature
Figure 27. VBS Undervoltage Threshold (+) vs.
Temperature
8.5
Max.
8.3
8.1
Typ.
7.9
7.7
Min.
7.5
-50
-25
0
25
50
75
100
125
Temperature (oC)
Figure 28. VBS Undervoltage Threshold (-) vs.
Temperature
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AUIRS211(7,8)S
Package Details: SOIC8
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AUIRS211(7,8)S
Tape and Reel Details: SOIC8
LOADED TAPE FEED DIRECTION
A
B
H
D
F
C
NOTE : CONTROLLING
DIMENSION IN MM
E
G
CARRIER TAPE DIMENSION FOR 8SOICN
Metric Imperial
Code
A
B
C
D
E
F
G
H
Min
7.90
3.90
11.70
5.45
6.30
5.10
1.50
1.50
Max
8.10
4.10
12.30
5.55
6.50
5.30
n/a
Min
Max
0.318
0.161
0.484
0.218
0.255
0.208
n/a
0.311
0.153
0.46
0.214
0.248
0.200
0.059
0.059
1.60
0.062
F
D
B
C
A
E
G
H
REEL DIMENSIONS FOR 8SOICN
Metric
Imperial
Code
A
B
C
D
E
F
G
H
Min
329.60
20.95
12.80
1.95
98.00
n/a
14.50
12.40
Max
330.25
21.45
13.20
2.45
102.00
18.40
17.10
14.40
Min
12.976
0.824
0.503
0.767
3.858
n/a
Max
13.001
0.844
0.519
0.096
4.015
0.724
0.673
0.566
0.570
0.488
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AUIRS211(7,8)S
Part Marking Information
Part number
Date code
AS2117
AYWW ?
IR logo
Pin 1
Identifier
? XXXX
Lot Code
(Prod mode –
4 digit SPN code)
?
MARKING CODE
P
Lead Free Released
Non-Lead Free Released
Assembly site code
Per SCOP 200-002
Part number
Date code
AS2118
AYWW ?
IR logo
Pin 1
Identifier
? XXXX
Lot Code
(Prod mode –
4 digit SPN code)
?
MARKING CODE
P
Lead Free Released
Assembly site code
Per SCOP 200-002
Non-Lead Free Released
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AUIRS211(7,8)S
Ordering Information
Base Part Number
Standard Pack
Package Type
Complete Part Number
Form
Quantity
Tube/Bulk
95
AUIRS2117S
AUIRS2117STR
AIRS2118S
SOIC8
AUIRS2117S
AUIRS2118S
Tape and Reel
Tube/Bulk
2500
95
SOIC8
AUIRS2118STR
Tape and Reel
2500
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AUIRS211(7,8)S
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(IR) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to
its products and services at any time and to discontinue any product or services without notice. Part numbers
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conditions of sale supplied at the time of order acknowledgment.
IR warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with IR’s standard warranty. Testing and other quality control techniques are used to the extent IR
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July 15, 2014
AUIRS211(7,8)S
Revision History
Date
Comment
MM/DD/YY
Original document
Converted the datasheet to the new format.
6/17/08
9/26/08
02/10/09
Reviewed and added missing graphs, inserted input/output Pin Equivalent Diagrams
Typ application section and other minor changes
Reviewed electrical spec, updated test temperature, qual info, package info I/O equivalent
diagram page.
08/03/09
08/11/09
08/12/09
8/14/09
9/23/09
9/23/09
Reviewed electrical spec, updated test temperature and plots, add –VS note.
Updated figure numbers and page number table
Changed Ton/off typ to 150ns; Matched Toff delay to be same as Ton delay
Added ESD passing voltage; still need LU test result.
Added latch up test classification
Updated Voh and Vol graphs; changed Ton/off typ. 150 to 140, max. 200 to 225; Vol 0.1 to
0.2; Tf 35 to 25; IN- 5 to 1
10/16/09
10/27/09
11/5/09
Updated typ application section, Max Vs oper cond changed from 200V to 600V.
Removed parameter vs. voltage graphs.
Added Important Notice disclaimer, updated typ ton/off to 140nS & Max. to 225 nS, removed
SOIC8 from PD description, updated VOL max to 0.2A, tf typical to 25nS.
Corrected typical applications on front page from “BLCD” to “BLDC”; updated disclaimer
under Abs. Max. Rating.
12/8/09
2/2/2010
Vin low limit corrected from 0.3 to -0.3V in Abs.Max.Ratings;
Removed note II from AEC-Q100 (Page 3);
07/15/2014
Updated World Headquarters address (Page 20)
21 www.irf.com
© 2014 International Rectifier
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July 15, 2014
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