AN985BX [INFINEON]
LAN Controller, 1 Channel(s), 12.5MBps, CMOS, PQFP128, GREEN, PLASTIC, LQFP-128;
| 型号： | AN985BX |
| 厂家： | 
Infineon |
| 描述： | LAN Controller, 1 Channel(s), 12.5MBps, CMOS, PQFP128, GREEN, PLASTIC, LQFP-128 时钟 局域网 数据传输 PC 外围集成电路 |
| 文件： | 总112页 (文件大小：4450K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet, Rev. 1.51, Nov. 2005
AN985B/BX
CardBus-to-Ethernet LAN Controller
Communications
N e v e r s t o p t h i n k i n g .
Edition 2005-11-30
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2005.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
CardBus-to-Ethernet LAN Controller
Revision History: 2005-11-30, Rev. 1.51
Previous Version:
Page/Date Subjects (major changes since last revision)
2005-09-13 Rev. 1.51: when changed to the new Infineon format
2005-11-30 Minor change. Included Green package information
Trademarks
ABM®, ACE®, AOP®, ARCOFI®, ASM®, ASP®, DigiTape®, DuSLIC®, EPIC®, ELIC®, FALC®, GEMINAX®, IDEC®,
INCA®, IOM®, IPAT®-2, ISAC®, ITAC®, IWE®, IWORX®, MUSAC®, MuSLIC®, OCTAT®, OptiPort®, POTSWIRE®,
QUAT®, QuadFALC®, SCOUT®, SICAT®, SICOFI®, SIDEC®, SLICOFI®, SMINT®, SOCRATES®, VINETIC®,
10BaseV®, 10BaseVX® are registered trademarks of Infineon Technologies AG. 10BaseS™, EasyPort™,
VDSLite™ are trademarks of Infineon Technologies AG. Microsoft® is a registered trademark of Microsoft
Corporation, Linux® of Linus Torvalds, Visio® of Visio Corporation, and FrameMaker® of Adobe Systems
Incorporated.
Template: template_A4_3.0.fm / 3 / 2005-01-17
AN985B/BX
Table of Contents
Table of Contents
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1
2
3
4
5
5.1
Pin Assignment Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Pin Type and Buffer Type Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7
Functional Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Network Packet Buffer Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Descriptor Structure Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
The Point of Descriptor Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Transmit Scheme and Transmit Early Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Transmit Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Transmit Pre-fetch Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Transmit Early interrupt Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Receive Scheme and Receive Early Interrupt Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Network Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
MAC Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Transceiver Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
100BASE-TX Transmit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
100BASE-TX Receiving Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
10BASE-T Transmission Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
10BASE-T Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Loop-back Operation of Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Full Duplex and Half Duplex Operation of Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Auto-Negotiation Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Power Down Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Flow Control in Full Duplex Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
LED Display Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Reset Whole Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Reset Transceiver Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Wake on LAN Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
The Magic Packet Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
The Wake on LAN Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
ACPI Power Management Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Power States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.1
7.1.1
7.1.2
7.2
7.2.1
7.2.2
7.2.3
7.3
7.4
7.4.1
7.4.2
7.4.2.1
7.4.2.2
7.4.2.3
7.4.2.4
7.4.2.5
7.4.2.6
7.4.2.7
7.4.2.8
7.4.3
7.5
7.6
7.6.1
7.6.2
7.7
7.7.1
7.7.2
7.8
7.8.1
8
Registers and Descriptors Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
AN985B/BX Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
AN985B/BX Configuration Registers Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
PCI /CARDBUS Control/Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
PCI/CARDBUS Control/Status Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
8.1
8.1.1
8.2
8.2.1
Data Sheet
4
Rev. 1.51, 2005-11-30
AN985B/BX
Table of Contents
8.3
PHY Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
PHY Transceiver Registers Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Descriptors and Buffer Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Receive Descriptor Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Transmit Descriptor Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
8.3.1
8.4
8.4.1
8.4.2
9
Electrical Specifications and Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
9.1
9.2
9.3
9.4
10
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
11
Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
MII Management Access Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Debugging Purpose Registers: Offset FCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
EEPROM DATA TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
11.1
11.2
11.3
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Data Sheet
5
Rev. 1.51, 2005-11-30
AN985B/BX
List of Figures
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
System Diagram of the AN985B/BX 8
Block Diagram of the AN985B/BX 10
Pin Assignment (top view) 11
Ring Structure of Frame Buffer 18
Chain Structure of Frame Buffer 19
Transmit Pointers for Descriptor Management 20
Receive Pointers for Descriptor Management 21
Transmit Flow 22
Transmit Data Flow of Pre-fetch Data 23
Figure 10 Transmit Normal Interrupt and Early Interrupt Comparison 23
Figure 11 Receive Data Flow (without early interrupt and with early interrupt) 24
Figure 12 Detailed Receive Early Interrupt Flow 24
Figure 13 MAC Control Frame Format 29
Figure 14 PAUSE Operation Receive State Diagram 30
Figure 15 NIC, PHY, and I/O interconnection 91
Figure 16 Timing 92
Figure 17 PCI Clock Waveform 103
Figure 18 PCI Timings 104
Figure 19 Flash Write Timings 105
Figure 20 Flash Read Timings 106
Figure 21 Serial EEPROM Timing 107
Figure 22 Package Outline for the AN985B/BX 108
Data Sheet
6
Rev. 1.51, 2005-11-30
AN985B/BX
List of Tables
List of Tables
Table 1
Abbreviations for Pin Type 12
Table 2
Abbreviations for Buffer Type 12
Pin Definitions and Functions 13
Format 25
Table 3
Table 4
Table 5
Power State 32
Registers Address Space 34
Registers Overview 34
Registers Access ConditionsRegisters Access Conditions 34
Registers Access Types 34
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Table 20
Table 21
Table 22
Table 23
Table 24
Table 25
Table 26
Table 27
Table 28
Table 29
Table 30
Table 31
Registers Clock Domains 35
Registers Address Space 47
Registers Overview 47
Registers Access Types 48
Registers Address Space 82
Registers Overview 82
Registers Access Types 82
Registers Overview 93
Registers Access Types 93
Receive Descriptor Table 94
Transmit Descriptor Table 98
Min-Max Ratings 101
General DC Specifications 101
PCI Interface DC Specifications 101
Flash/EEPROM Interface DC Specifications 101
PCI Signaling AC Specifications for 3.3 V 102
PCI Clock Specifications 102
PCI Timings 103
Flash Interface Timings 104
EEPROM Interface Timings (AC/AD) 106
Dimensions for 128 -pin LQFP Package (AN985B/BX) 108
EEPROM DATA TABLE 110
Data Sheet
7
Rev. 1.51, 2005-11-30
AN985B/BX
General Description
1
General Description
The AN985B/BX is a high performance CARDBUS Fast Ethernet controller with a integrated physical layer
interface for 10BASE-T and 100BASE-TX applications. The AN983B/BX is the environmentally friendly “green”
package version.
The AN985B/BX was designed with 0.25um CMOS technology to provide glueless 32-bit bus master interface for
CARDBUS, boot ROM interface and CSMA/CD protocol for Fast Ethernet, as well as the physical media interface
for 100BASE-TX of IEEE802.3u and 10BASE-T of IEEE802.3. The auto-negotiation function is also supported for
speed and duplex detections.
The AN985B/BX provides both half-duplex and full-duplex operations, as well as support for full-duplex flow
control.
It provides long FIFO buffers for transmission and reception, and an early interrupt mechanism to enhance
performance.
The AN985B/BX also supports ACPI and CARDBUS compliant power management functions and Magic Packet
wake-up event.
2
System Block Diagram
Figure 1
System Diagram of the AN985B/BX
3
Features
Industry standard
•
•
•
•
•
IEEE802.3u 100BASE-TX and IEEE802.3 10BASE-T compliant
Supports for IEEE802.3x flow control
IEEE802.3u Auto-Negotiation support for 10BASE-T and 100BASE-TX
CARDBUS Interface
ACPI and PCI power management Ver.1.1 compliant
Data Sheet
8
Rev. 1.51, 2005-11-30
AN985B/BX
Features
•
Supports PC98 wake on LAN
FIFO
•
•
•
•
Provides two independent long FIFOs with 2k bytes each for transmission and reception
Pre-fetch up to two transmit packets to minimize inter frame gap (IFG) to 0.96 µs
Retransmit collided packet without reload from host memory within 64 bytes
Automatically retransmit FIFO under-run packet with maximum drain threshold until 3 times retry failure and
that will not influence the registers and transmit threshold of next packet
CARDBUS I/F
•
•
•
•
•
•
Provides 32-bit PCI bus master data transfer
Supports CARDBUS clock with frequency from 0 Hz to 33 MHz
Supports network operation with CARDBUS system clock from 20 MHz to 33 MHz
Performance meter, CARDBUS bus master latency timer, for tuning the threshold to enhance performance
Burst transmit packet interrupt and transmit/receive early interrupt to reduce host CPU utilization
Memory-read, memory-read-line, memory-read-multiple, memory-write, memory-write-and-invalidate
command while being bus master
•
Supports big or little endian byte ordering
EEPROM/Boot ROM I/F
•
•
•
•
•
Write-able Flash ROM and EPROM as boot ROM with size up to 128 KB
CARDBUS to access boot ROM by byte, word, or double word
Re-write Flash boot ROM through I/O port by programming register
Serial interface for read/write 93C46/66 EEPROM
Automatically loads device ID, vendor ID, subsystem ID, subsystem vendor ID, Maximum-Latency, and
Minimum-Grand from the 64 byte contents of 93C46/66 after PCI reset de-asserted in PCI environment
CIS data is recalled from 93C66 to AN985B/BX PC internal SRAM to speed up CIS access in CARDBUS
environment
•
MAC/Physical
•
•
•
•
•
•
•
•
•
Integrates the whole Physical layer functions of 100BASE-TX and 10BASE-T
Full -duplex operation on both 100 Mbit/s and 10 Mbit/s modes
Auto-negotiation (NWAY) function of full/half duplex operation for both 10 and 100 Mbit/s
Transmits wave-shaper, receive filters, and adaptive equalizer
MLT-3 transceivers with DC restoration for Base-line wander compensation
MAC and Transceiver (TXCVR) loop-back modes for diagnostic
Built in Stream Cipher Scrambler/ De-scrambler and 4B/5B encoder/decoder
External transmitting transformer with turn ratio 1:1
External receiving transformer with turn ratio 1:1
LED Display
•
3 LEDs display scheme provided:
– 100 Mbit/s (on) or Speed 10 (off)
– Link (keeps on when link ok) or Activity (will be blinking with 10 Hz when receiving or transmitting but not
collision)
– FD (keeps on when in Full duplex mode) or Collision (will be blinking with 20 Hz when colliding)
4 LEDs displayed scheme provided:
•
– 100 Mbit/s and Link (keep on when link and 100 Mbit/s)
– 10 Mbit/s and Link (keep on when link and 10 Mbit/s)
– Activity (will be blinking with 10 Hz when receiving or transmitting but not collision)
– FD (keeps on when in Full duplex mode) or Collision (will be blinking with 20 Hz when colliding)
Miscellaneous
128-pin QFP package for CARDBUS interface.
•
Data Sheet
9
Rev. 1.51, 2005-11-30
AN985B/BX
Block Diagram
4
Block Diagram
Figure 2
Block Diagram of the AN985B/BX
Data Sheet
10
Rev. 1.51, 2005-11-30
AN985B/BX
Pin Assignment Diagram
5
Pin Assignment Diagram
Figure 3
Pin Assignment (top view)
Data Sheet
11
Rev. 1.51, 2005-11-30
AN985B/BX
Pin Assignment Diagram
5.1
Pin Type and Buffer Type Abbreviations
Standardized abbreviations:
Table 1
Abbreviations for Pin Type
Abbreviations
Description
I
Standard input-only pin. Digital levels.
O
Output. Digital levels.
I/O
AI
I/O is a bidirectional input/output signal.
Input. Analog levels.
AO
AI/O
PWR
GND
MCL
MCH
NU
NC
Output. Analog levels.
Input or Output. Analog levels.
Power
Ground
Must be connected to Low (JEDEC Standard)
Must be connected to High (JEDEC Standard)
Not Usable (JEDEC Standard)
Not Connected (JEDEC Standard)
Table 2
Abbreviations for Buffer Type
Abbreviations
Description
Z
High impedance
Pull up, 10 kΩ
Pull down, 10 kΩ
Pull down, 20 kΩ
PU1
PD1
PD2
TS
Tristate capability: The corresponding pin has 3 operational states: Low, high and high-
impedance.
OD
Open Drain. The corresponding pin has 2 operational states, active low and tristate, and
allows multiple devices to share as a wire-OR. An external pull-up is required to sustain the
inactive state until another agent drives it, and must be provided by the central resource.
OC
PP
Open Collector
Push-Pull. The corresponding pin has 2 operational states: Active-low and active-high
(identical to output with no type attribute).
OD/PP
Open-Drain or Push-Pull. The corresponding pin can be configured either as an output with
the OD attribute or as an output with the PP attribute.
ST
TTL
Schmitt-Trigger characteristics
TTL characteristics
Data Sheet
12
Rev. 1.51, 2005-11-30
AN985B/BX
Pin Description
6
Pin Description
Table 3
Pin Definitions and Functions
Pin or Ball Name
No.
Pin
Type
Buffer
Type
Function
PCI Interface
24
INTA#
RST#
O/D
I
CARDBUS Interrupt Request
AN985B/BX asserts this signal when one of the interrupt
events occurs.
25
CARDBUS Signal to Initialize the AN985B/BX
The active reset signal should be sustained for at least
100µs to guarantee that the AN985B/BX has completed the
initializing activity. During the reset period, all the output
pins of AN985B/BX will be set to tri-state and all the O/D
pins are floated.
27
29
CLK
I
This CARDBUS Clock Inputs to AN985B/BX for
CARDBUS Relative Circuits as the Synchronized
Timing Base with CARDBUS
The Bus signals are recognized on the rising edge of
CARDBUS-CLK. In order to let the network operate
properly, the frequency range of the CARDBUS-CLK is
limited to between 20 MHz and 33 MHz when the network
is operating.
CARDBUS Bus Granted
This signal indicates that the bus request of AN985B/BX
has been accepted.
CARDBUS Bus Request
Bus master device wants to get bus access right
GNT#
REQ#
I
30
31
O
PME#/CSTSCH I/O
G
Power Management Event
The Power Management Event signal is an open drain,
active low signal for CARDBUS(PME#). When WOL-bit 18
of CSR is set into “1”, this means that the AN985B/BX is set
into Wake On LAN mode. In this mode, when the
AN985B/BX receives a Magic Packet frame from network
then the AN985B/BX will active this signal too. In the Wake
On LAN mode, when LWS-bit (bit 17) of CSR18 is set to “1”
this means the LAN-WAKE signal is a HP-style signal,
otherwise it is an IBM-style signal.
Data Sheet
13
Rev. 1.51, 2005-11-30
AN985B/BX
Pin Description
Table 3
Pin Definitions and Functions (cont’d)
Pin or Ball Name
No.
Pin
Buffer
Type
Function
Multiplexed Address Data Pin of CARDBUS Bus
Type
33
34
35
36
38
39
40
41
46
47
49
50
51
53
54
56
70
72
73
75
76
78
79
81
84
85
86
88
89
90
93
94
43
57
69
83
44
AD-31
AD-30
AD-29
AD-28
AD-27
AD-26
AD-25
AD-24
AD-23
AD-22
AD-21
AD-20
AD-19
AD-18
AD-17
AD-16
AD-15
AD-14
AD-13
AD-12
AD-11
AD-10
AD-9
I/O
AD-8
AD-7
AD-6
AD-5
AD-4
AD-3
AD-2
AD-1
AD-0
C-BEB3
C-BEB2
C-BEB1
C-BEB0
IDSEL
I/O
Bus Command and Byte Enable
I
Initialization Device Select
This signal is asserted when the host issues the
configuration cycles to the AN985B/BX.
59
FRAME#
I/O
Begin and Duration of Bus Access
Driven by master device
Data Sheet
14
Rev. 1.51, 2005-11-30
AN985B/BX
Pin Description
Table 3
Pin Definitions and Functions (cont’d)
Pin or Ball Name
No.
Pin
Type
Buffer
Type
Function
60
61
63
IRDY#
TRDY#
DEVSEL#
I/O
I/O
I/O
Master Device is Ready to Data Transaction
Slave Device is Ready to Data Transaction
Device Select
Device select, target is driving to indicate the address is
decoded
64
65
STOP#
PERR#
I/O
I/O
Stop the Current Transaction
Target device requests the master device to stop the
current transaction
Data Parity Error
Data parity error is detected, driven by the agent receiving
data
66
68
SERR#
PAR
O/D
I/O
Address Parity Error
Parity
Parity, even parity (AD [31:0] + C/BE [3:0]); master drives
par for address and write data phas; target drives par for
read data phase
92
Clk-run
I/O,
O/D
Clock Run for CARDBUS System
In the normal operation situation, Host should assert this
signal to indicate to AN985B/BX about the normal situation.
On the other hand, when Host deasserts this signal the
clock is going down to a non-operating frequency. When
AN985B/BX recognizes the deasserted status of clk-run,
then it will assert clk-run to request Host to maintain the
normal clock operation. When the clk-run function is
disabled then the AN985B/BX will set clk-run in tri-state.
BOOTROM/EEPROM Interface
98
99
BrA0
BrA1
BrA2
BrA3
BrA4
BrA5
BrA6
BrA7
I/O
ROM Data Bus
Provides up to 128kB EPROM or Flash-ROM application
space.
100
101
106
108
109
110
112
113
126
127
128
1
BrA8
BrA9
BrA10
BrA11
BrA12
BrA13
BrA14
BrA15
BrA16
2
3
105
Data Sheet
15
Rev. 1.51, 2005-11-30
AN985B/BX
Pin Description
Table 3
Pin Definitions and Functions (cont’d)
Pin or Ball Name
No.
Pin
Type
Buffer
Type
Function
116
117
118
119
120
121
122
123
124
125
114
115
BrD0
BrD1
BrD2
BrD3
O
BootROM Data Bus Bit (0~7)
Inputs/Output data for AN985B/BX
EDO: Data Output of serial EEPROM
EDI: Data Input of serial EEPROM
ECK: Clock input of serial EEPROM
BrD4
The AN985B/BX outputs clock signal to EEPROM.
BrD5/EDO
BrD6/EDI
BrD7/ECK
EECS
BrCS#
BrOE#
BrWE#
O/I
O/O
O/O
O
O
O
Chip Select of Serial EEPROM
BootROM Chip Select
BootROM Read Enable for Flash ROM Application
BootROM Write Enable for Flash ROM Application
O
Physical Interface
18
17
6
XTLP
XTLN
RXIN
RXIP
I
I
Crystal Inputs
To be connected to a 25 MHz crystal.
Differentials Receive Inputs
The differentials receive inputs of 100BASE-TX or
10BASE-T, these pins are directly inputted from Magnetic.
7
20
21
TXOP
TXON
O
I
Differential Transmit Outputs
The differential Transmit outputs of 100BASE-TX or
10BASE-T, these pins are directly outputted to Magnetic.
15
RIBB
Reference Bias Resistor
To be tied to an external 10.0K (1%) resistor which should
be connected to the analog ground at the other end.
9
TST0
TST1
TST2
TST3
NC
I
Test Pin
10
11
5
12
13
O
Not Connected
NC
LED Display and Miscellaneous
102
Led-Act
O
4 LED Mode: LED Display for Activity Status
This pin will be driven on with 10 Hz blinking frequency
when either effective receiving or transmitting is detected.
(Led-lnk/act)
Led-10Lnk
O
O
(3 LED Mode): LED Display for Link and Activity Status
Link and Activity
103
4 LED Mode: LED Display for 10 Mbit/s Speed
This pin will be driven on continually when the 10 Mbit/s
network operating speed is detected.
(Led-fd/col)
O
(3 LED Mode): LED Display for Full Duplex or Collision
Status
full duplex/collision
Data Sheet
16
Rev. 1.51, 2005-11-30
AN985B/BX
Pin Description
Table 3
Pin Definitions and Functions (cont’d)
Pin or Ball Name
No.
Pin
Type
Buffer
Type
Function
104
Led-100Lnk
O
O
O
4 LED Mode: LED Display for 100 Mbit/s Speed
This pin will be driven on continually when the 100 Mbit/s
network operating speed is detected.
(Led-speed)
Led-Fd/Col
(3 LED Mode): LED Display for 100 Mbit/s or 10 Mbit/s
speed
speed 100(on)/10(off)
105
4 LED Mode: LED Display for Full Duplex or Collision
Status
This pin will be driven on continually when a full duplex
configuration is detected. This pin will be driven on with
20 Hz blinking frequency when a collision status is detected
in the half duplex configuration.
bra(16)
Vaux
O
I
(3 LED Mode):bra 16
When this pin is asserted, it indicates an auxiliary
power source is supported.
95
ACPI purpose, for detecting the auxiliary power source.
This pin should be or-wired connected to:
1) 3.3 V when 3.3 Vaux support, or
2) 5 V when 5 Vaux support from 3-way switch.
96
97
Vcc-detect
PMEP
I
When this pin is asserted, it indicates PCI power
source is supported.
ACPI purpose, for detecting the main power is remained or
not. This pin should be connected to PCI bus power source
+5 V.
O
High pulse/low pulse 50ms
Digital Power Pins
26, 32, 42,
45, 52, 62,
71, 80, 82,
91, 107
V
ss-pci, Vss-IR
,
Vss-3
23, 28, 37,
48, 55, 58,
67, 74, 77,
87, 111
V
V
dd-pci, Vdd-IR
,
dd-3, Connect to
3.3 V
Analog Power Pins
4,16,22
V
AAR, VAAREF,
V
AAT, 3.3 V
8,14,19
GNDR,
GNDREF,
GNDT
Data Sheet
17
Rev. 1.51, 2005-11-30
AN985B/BX
Functional Descriptions
7
Functional Descriptions
7.1
Network Packet Buffer Management
7.1.1
Descriptor Structure Types
For networking operations, the AN985B/BX transmits the data packet from transmitting buffers in host memory to
AN985B/BX’s transmitting FIFO and receives the data packet from AN985B/BX’s receiving FIFO to receive buffers
in host memory. The descriptors that the AN985B/BX supports to build in host memory are used as the pointers
of these transmitting and receiving buffers.
There are two structure types for the descriptor, Ring and Chain, supported by the AN985B/BX and are shown
as below. The type selections are controlled by bit 24 of RDES1 and the bit 24 of TDES1.
The transmitting and receiving buffers are physically built in host memory. Any buffer can contain either a whole
packet or just part of a packet. But it can’t contain more than one packet.
•
Ring structure
There are two buffers per descriptor in the ring structure. Support receives early interrupt.
Figure 4
Chain structure
There is only one buffer per descriptor in the chain structure.
Ring Structure of Frame Buffer
•
Data Sheet
18
Rev. 1.51, 2005-11-30
AN985B/BX
Functional Descriptions
Figure 5
Chain Structure of Frame Buffer
7.1.2
The Point of Descriptor Management
OWN bit = 1, ready for network side access
OWN bit = 0, ready for host side access
•
Transmit Descriptor Pointers
Data Sheet
19
Rev. 1.51, 2005-11-30
AN985B/BX
Functional Descriptions
Figure 6
Transmit Pointers for Descriptor Management
•
Receive Descriptor Pointers
Data Sheet
20
Rev. 1.51, 2005-11-30
AN985B/BX
Functional Descriptions
Figure 7
Receive Pointers for Descriptor Management
Data Sheet
21
Rev. 1.51, 2005-11-30
AN985B/BX
Functional Descriptions
7.2
Transmit Scheme and Transmit Early Interrupt
Transmit Flow
7.2.1
The flow of packet transmit is shown below.
Figure 8
Transmit Flow
7.2.2
Transmit Pre-fetch Data Flow
•
•
•
Transmit FIFO size = 2K-byte
Two packets in the FIFO at the same time
Meet the transmit min. back-to-back
Data Sheet
22
Rev. 1.51, 2005-11-30
AN985B/BX
Functional Descriptions
Figure 9
Transmit Data Flow of Pre-fetch Data
7.2.3
Transmit Early interrupt Scheme
Figure 10 Transmit Normal Interrupt and Early Interrupt Comparison
7.3
Receive Scheme and Receive Early Interrupt Scheme
The following figure shows the difference of timing without early interrupt and with early interrupt.
Data Sheet
23
Rev. 1.51, 2005-11-30
AN985B/BX
Functional Descriptions
Figure 11 Receive Data Flow (without early interrupt and with early interrupt)
Figure 12 Detailed Receive Early Interrupt Flow
7.4
Network Operation
7.4.1
MAC Operation
The MAC (Media Access Control) portion of AN985B/BX, incorporates the essential protocol requirements for
operating as an IEEE802.3 and Ethernet compliant node.
Data Sheet
24
Rev. 1.51, 2005-11-30
AN985B/BX
Functional Descriptions
Table 4
Field
Format
Description
Preamble
A 7-byte field of (10101010b)
A 1-byte field of (10101011b)
A 6-byte field
Start Frame Delimiter
Destination Address
Source Address
Length/Type
A 6-byte field
A 2-byte field indicated the frame is in IEEE802.3
format or Ethernet format.IEEE802.3 format: 0000H ~
05DCH for Length field Ethernet format: 05DD ~ FFFFH
for Type field
Data
CRC
461) ~ 1500 bytes of data information
A 32-bit cyclic redundant code for error detection
1) If padding is disabled (TDES1 bit23), the data field may be shorter than 46 bytes.
Transmit Data Encapsulation
The differences between the encapsulation and a MAC frame while operating in the 100BASE-TX mode are listed
as follow:
1. The first byte of the preamble is replaced by the JK code according to the IEE802.3u, clause 24.
2. After the CRC field of the MAC frame, the AN985B/BX inserts the TR code according to the IEE802.3u, clause
24.
Receive Data Decapsulation
When operating in 100BASE-TX mode the AN985B/BX detects a JK code for a preamble as well as a TR code
for the packet end. If a JK code is not detected, the AN985B/BX will abort this frame receiving and wait for a new
JK code detection. If a TR code is not detected, the AN985B/BX will report a CRC error.
Deferring
The Inter-Frame Gap (IFG) time is divided into two parts:
1. IFG1 time (64-bit time): If a carrier is detected on the medium during this time, the AN985B/BX will reset the
IFG1 time counter and restart to monitor the channel for an idle again.
2. IFG2 time (32-bit time): After counting the IFG2 time the AN985B/BX will access the channel even though a
carrier has been sensed on the network.
Collision Handling
The scheduling of re-transmissions is determined by a controlled randomization process called “truncated binary
exponential back-off”. At the end of enforcing a collision (jamming), the AN985B/BX delays before attempting to
re-transmit the packet. The delay is an integer multiple of slot time. The number of slot times to delay before the
nth re-transmission attempt is chosen as a uniform distributed integer r in the range:
0 ≤ r < 2k, where k = min (n, 10)
Data Sheet
25
Rev. 1.51, 2005-11-30
AN985B/BX
Functional Descriptions
7.4.2
Transceiver Operation
The transceiver portion of the AN985B/BX, integrates the IEEE802.3u compliant functions of PCS (physical coding
sub-layer), PMA (physical medium attachment) sub-layer, PMD (physical medium dependent) sub-layer for
100BASE-TX, the IEEE802.3 compliant functions of Manchester encoding/decoding and a transceiver for
10BASE-T. All the functions and operation schemes are described in the following sections:
7.4.2.1
100BASE-TX Transmit Operation
Regarding the 100BASE-TX transmission, the transceiver provides transmission functions PCS, PMA, and PMD
for encoding of MII data nibbles to five-bit code-groups (4B/5B), scrambling, serialization of scrambled code-
groups, converting the serial NRZ code into NRZI code, converting the NRZI code into MLT3 code, and then
driving the MLT3 code into the category 5 Unshielded Twisted Pair cable through an isolation transformer with the
turns ratio of 1:1.
Data Code-Groups Encoder
In normal MII mode application, the transceiver receives nibble type 4B data via the TxD0~3 inputs of the MII.
These inputs are sampled by the transceiver on the rising edge of Tx-clk and passed to the 4B/5B encoder to
generate the 5B code-group used by 100BASE-TX.
Idle Code-Groups
In order to establish and maintain the clock synchronization, the transceiver needs to keep transmitting signals to
medium. The transceiver will generate Idle code-groups for transmission when there is no real data MAC wants
to send.
Start-of-Stream Delimiter-SSD (/J/K/)
In a transmission stream, the first 16 nibbles are MAC preamble. In order to let a partner delineate the boundary
of a data transmission sequence and to authenticate carrier events, the transceiver will replace the first 2 nibbles
of the MAC preamble with /J/K/ code-groups.
End-of-Stream Delimiter-ESD (/T/R/)
In order to indicate the termination of the normal data transmissions, the transceiver will insert 2 nibbles of /T/R/
code-group after the last nibble of FCS.
Scrambling
All the encoded data (including the idle, SSD, and ESD code-groups) is passed to data scrambler to reduce the
EMI and spread the power spectrum using a 10-bit scrambler seed loaded at the beginning.
Data Conversion of Parallel to Serial, NRZ to NRZI, NRZI to MLT3
After being scrambled, the transmission data with 5B type in 25 MHz will be converted to a serial bit stream in 125
MHz by the parallel to serial function. After serialization, the transmission serial bit stream will be further converted
from NRZ to NRZI format. After NRZI is converted, the NRZI bit stream is passed through MLT3 encoder to
generate the TP-PMD specified MLT3 code. With this MLT3 code, it lowers the frequency and reduces the energy
of the transmission signal in the UTP cable and also makes the system easy to meet the FCC specification of EMI.
Wave-Shaper and Media Signal Driver
In order to reduce the energy of the harmonic frequency of transmission signals, the transceiver provides the
wave-shaper prior to the line driver to smoothen but keep symmetric the rising/falling edge of transmission signals.
The wave-shaped signals including the 100BASE-TX and 10BASE-T both are passed to the same media signal
driver. This design can simplify the external magnetic connection with a single one.
Data Sheet
26
Rev. 1.51, 2005-11-30
AN985B/BX
Functional Descriptions
7.4.2.2
100BASE-TX Receiving Operation
Regarding the 100BASE-TX receiving operation, the transceiver provides the receiving functions of PMD, PMA,
and PCS for receiving incoming data signals through category 5 UTP cable and an isolation transformer with turn’s
ratio of 1:1. It includes the adaptive equalizer, baseline wander, data conversions of MLT3 to NRZI, NRZI to NRZ,
and serial to parallel, the PLL for clock and data recovery, the de-scrambler, and the decoder of 5B/4B.
Adaptive Equalizer and Baseline Wander
The high-speed signals over the unshielded (or shielded) twisted Pair cable will induce the amplitude attenuation
and phase shifting. Furthermore, these effects are dependent on the signal frequency, cable type, cable length
and the connectors of the cabling. So a reliable adaptive equalizer and baseline wander to compensate all the
amplitude attenuation and phase shifting are necessary. In the transceiver, it provides the robust circuits to
perform these functions.
MLT3 to NRZI Decoder and PLL for Data Recovery
After receiving the proper MLT3 signals, the transceiver converts the MLT3 to NRZI code for further processing.
After adaptive equalizer, baseline wander, and MLT3 to NRZI decoder, the compensated signals with NRZI type
in 125 MHz are passed to the Phase Lock Loop circuits to extract out the original data and the synchronous clock.
Data Conversions of NRZI to NRZ and Serial to Parallel
After data recovery, the signals will be passed to the NRZI to NRZ converter to generate the 125 MHz serial bit
stream. This serial bit stream will be packed to parallel 5B type for further processing.
De-scrambling and Decoding of 5B/4B
The parallel 5B type data is passed to the de-scrambler and 5B/4B decoder to return their original MII nibble type
data.
Carrier Sensing
Carrier Sense (CRS) signal is asserted when the transceiver detects any 2 non-contiguous zeros within any 10bit
boundary of the receiving bit stream. CRS is de-asserted when ESD code-group or Idle code-group is detected.
In half duplex mode, CRS is asserted during packet transmission or reception. But in full duplex mode, CRS is
asserted only during packet reception.
7.4.2.3
10BASE-T Transmission Operation
It includes the parallel to serial converter, Manchester Encoder, Link test function, Jabber function, the transmit
wave-shaper, and line driver described in the section of “Wave-Shaper and Media Signal Driver” of “100BASE-T
Transmission Operation”. It also provides Collision detection and SQE test for half duplex application.
7.4.2.4
10BASE-T Receive Operation
It includes the carrier sense function, receiving filter, PLL for clock and data recovering, Manchester decoder, and
serial to parallel converter.
7.4.2.5
Loop-back Operation of Transceiver
The transceiver provides internal loop-back (also called transceiver loop-back) operation for both the 100BASE-
TX and 10BASE-T operations. Setting bit 14 of PHY register 0 to 1 can enable the loop-back operation. In this
loop-back operation, PHY will not transmit packets (but PHY will still send MLT3 for Idle).
In the 100BASE-TX internal loop-back operation, the data comes from the transmit output of NRZ to NRZI
converter then loops-back to the receiving path into the input of NRZI to NRZ converter.
Data Sheet
27
Rev. 1.51, 2005-11-30
AN985B/BX
Functional Descriptions
In the 10BASE-T loop-back operation, the data is through transmitting path and loop-back from the output of the
Manchester encoder into the input of Phase Lock Loop circuit of receiving path.
7.4.2.6
Full Duplex and Half Duplex Operation of Transceiver
The transceiver can operate for either full duplex or half duplex network application. In full duplex, both
transmission and reception can be operated simultaneously. Under full duplex mode, collision (COL) signal is
ignored and carrier sense (CRS) signal is asserted only when the transceiver is receiving.
In half duplex mode, either transmission or reception can be operated at one time. Under half duplex mode,
collision signal is asserted when transmitted and received signals collided and carrier sense asserted during
transmission and reception.
7.4.2.7
Auto-Negotiation Operation
The Auto-Negotiation function is designed to provide the means to exchange information between the transceiver
and the network partner to automatically configure both to take maximum advantage of their abilities, and both are
setup accordingly. The Auto-Negotiation function can be controlled through bit 12 of PHY register 0.
The Auto-Negotiation exchanges information with the network partner using the Fast Link Pulses (FLPs) - a burst
of link pulses. There are 16 bits of signaling information contained in the burst pulses to advertise all remote
partners’ capabilities, which are determined by PHY, register 4. According to this information they find out their
highest common capability by following the priority sequence as below:
1. 100BASE-TX full duplex
2. 100BASE-TX half duplex
3. 10BASE-T full duplex
4. 10BASE-T half duplex
During power-up or reset, if Auto-Negotiation is found enabled, FLPs will be transmitted and the Auto-Negotiation
function will process. Otherwise, the Auto-Negotiation will not occur until the bit 12 of PHY register 0 is set to 1.
When the Auto-Negotiation is disabled, the Network Speed and Duplex Mode are selected by programming PHY
register 0.
7.4.2.8
Power Down Operation
To reduce the power consumption the transceiver is designed with power down feature, which can save the power
consumption significantly. Since the power supply of the 100BASE-TX and 10BASE-T circuits are separated, the
transceiver can turn off the circuit of either the 100BASE-TX or 10BASE-T when the other is operating.
7.4.3
Flow Control in Full Duplex Application
The PAUSE function operation is used to inhibit transmission of data frames for a specified period of time. The
AN985B/BX supports full duplex protocol of IEEE802.3x. To support the PAUSE function, the AN985B/BX
implements the MAC Control Sub-layer functions to decode the MAC Control frames received from MAC control
clients and execute the relative requests accordingly. When the Full Duplex mode and PAUSE functions are
selected after Auto-Negotiation is completed, the AN985B/BX enables the PAUSE function for flow control of full
duplex applications. In this section we will describe how the AN985B/BX implements the PAUSE function.
Data Sheet
28
Rev. 1.51, 2005-11-30
AN985B/BX
Functional Descriptions
MAC Control Frame and PAUSE Frame
Figure 13 MAC Control Frame Format
The MAC Control frame is distinguished from other MAC frames only by their Length/Type field identifier. The MAC
Control Opcode defined in MAC Control Frame format for PAUSE function is 0001H. Also, the PAUSE time is
specified in the MAC Control Parameters field with 2 Octets, unsigned integer, in the units of Slot-Times. The
range of possible PAUSE time is 0 to 65535 Slot-Times.
So, a valid PAUSE frame issued by a MAC control client (could be a switch or a bridge) which will contain:
1. The destination address set equal to the globally assigned 48 bit mulitcast address 01-80-C2-00-00-01, or
equal to the unicast address which the MAC control client wishes to inhibit its transmission of data frames
2. Filled MAC Control Opcode field with 0001H
3. 2 Octets of PAUSE time specified in the MAC Control parameter field to indicate the length of time for which
the destination is wished to inhibit data frame transmission
Receive Operation for PAUSE Function
Upon reception of a valid MAC Control frame, the AN985B/BX will start a timer for the length of time specified by
the MAC Control Parameters field. When the timer value reaches zero then the AN985B/BX ends PAUSE state.
However, a PAUSE frame should not affect the transmission of a frame that has been submitted to the MAC
(started Transmit out of the MAC and can’t be interrupted). On the other hand, the AN985B/BX shall not begin to
transmit a frame more than one Slot-Times after receiving a valid PAUSE frame with a non-zero PAUSE time. If
the AN985B/BX receives a PAUSE frame with a zero PAUSE time value, the AN985B/BX ends the PAUSE state
immediately.
Data Sheet
29
Rev. 1.51, 2005-11-30
AN985B/BX
Functional Descriptions
Figure 14 PAUSE Operation Receive State Diagram
Data Sheet
30
Rev. 1.51, 2005-11-30
AN985B/BX
Functional Descriptions
7.5
LED Display Operation
The AN985B/BX provides two LED schemes one is three-LED which provides display pins for Link test
status/Activity status, Speed mode, and Full duplex/Collision status. These pins can directly drive the LED device;
the other is four-LED schemes which provide link100, link10, act, fd/col. The detail descriptions about the
operation are described in the Pin Description section.
7.6
Reset Operation
7.6.1
Reset Whole Chip
There are two ways to reset the AN985B/BX. First, hardware reset, the AN985B/BX can be reset via RST# pin.
For ensuring proper reset operation, at least 100us active Reset input signal is required. Second, software reset,
when bit 0 of CSR0 register is set to 1, the AN985B/BX will reset entire circuits and registers to default values then
clear the bit 0 of CSR0 to 0.
7.6.2
Reset Transceiver Only
When bit 15 of XR0 register is set to 1, the transceiver will reset entire circuits and register contents to default value
then clear the bit 15 of XR0 to 0.
7.7
Wake on LAN Function
The AN985B/BX can assert a signal to wake up the system when it receives a Magic Packet from the network.
The Wake on LAN operation is described as follows:
7.7.1
The Magic Packet Format
•
•
Valid destination address that can pass the address filter of the AN985B/BX
The payload of frame must include at least 6 contiguous ‘FF’ followed immediately by 16 repetitions of IEEE
address
•
•
The frame can contain multiple ‘six FF + sixteen IEEE address’ patterns
CRC OK
7.7.2
The Wake on LAN Operation
The Wake on LAN enable function is controlled by bit 18 of CSR18; it is loaded from the EEPROM after reset or
programmed by a driver to enable Wake on LAN function. If the bit 18 of CSR18 is set and the AN985B/BX
receives a Magic Packet, it will assert the PME# signal (drive to low) to indicated is receiving a wake up frame as
well as to set the PME status bit (the bit 15 of CSR20).
7.8
ACPI Power Management Function
The AN985B/BX has a built-in capability for Power Management (PM), which controlled by the host system
The AN985B/BX will provide:
•
•
•
•
•
Compatibility with Device Class Power Management Reference Specification, Rev1.09
Compatibility with ACPI specification, Rev 1.0
Compatibility with CARDBUS Bus Power Management Interface Specification, Rev 1.1
Compatibility with AMD Magic Packet™ Technology.
Compatibility with CARDBUS CLKRUN scheme.
Data Sheet
31
Rev. 1.51, 2005-11-30
AN985B/BX
Functional Descriptions
7.8.1
Power States
DO (Fully On)
In this state the AN985B/BX operates at full functionality and consumes its normal power. While in the D0 state,
if the CARDBUS clock is lower than 16 MHz, the AN985B/BX may not receive or transmit frames properly.
D1
In this state the AN985B/BX doesn’t response to any accesses, except if configuration space and full function
contexts are in place. The only network operation the AN985B/BX can initiate is a wake-up event.
D2
In this state the AN985B/BX only responds to access configuration space and full function context in place. The
AN985B/BX can’t transmit or receive, even the wake-up frame.
D3cold (Power Removed)
In this state all function context is lost. When power is restored, the function will return to D0.
D3hot (Software Visible D3)
When the AN985B/BX is brought back to D0 from D3hot the software must perform a full initialization.
The AN985B/BX in the D3hot state responds to configuration cycles as long as power and clocks are supplied. This
requires the device to perform an internal reset and return to a power-up reset condition without the RST# pin
asserted.
Table 5
Power State
Device
State
CARDBU Function Context
S-Bus
State
Clock
Power
Supported
Actions to
Function
Supported
Actions from
Function
D0
D1
B0
Full function context in
place
Full speed
Full power
Any CARDBUS Any
transaction
CARDBUS
transaction or
interrupt
B0, B1
Configuration
Stopped to
Full speed
–
CARDBUS
configuration
access
Only wake-up
events
maintained. No Tx and
Rx except wake-up
events
D2
B0, B1,
B2
Configuration
maintained. No Tx and
Rx
Configuration lost, full
initialization required
upon return to D0
All configurations lost.
Power-on defaults in
place on return to D0
Stopped to
Full speed
–
CARDBUS
–
–
–
configuration
access (B0, B1)
D3hot
D3cold
B0, B1,
B2
Stopped to
Full speed
–
CARDBUS
configuration
access (B0, B1)
B3
No clock
No power
Power-on reset
Data Sheet
32
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
8
Registers and Descriptors Description
There are three kinds of registers designed for AN985B/BX. They are AN985B/BX configuration registers,
CARDBUS control/status registers, and Transceiver control/status registers.
The AN985B/BX configuration registers are used to initialize and configure the AN985B/BX for identifying and
querying the AN985B/BX.
The CARDBUS control/status registers are used to communicate between host and AN985B/BX. Host can
initialize, control, and read the status of the AN985B/BX through the mapped I/O or memory address space.
Regarding the registers of transceiver portion of AN985B/BX, there are 11 basic registers with 16bits supporting
for AN985B/BX. It includes 7 basic registers which are defined according to the clause 22 “Reconciliation Sub-
layer and Media Independent Interface” and clause 28 “Physical Layer link signaling for 10 Mbit/s and 100 Mbit/s
Auto-Negotiation on twisted pair” of IEEE802.3u standard. The AN985B/BX also provides receiving and
transmitting descriptors for packet buffering and management. These descriptors are described in the following
section
Data Sheet
33
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
8.1
AN985B/BX Configuration Registers
Table 6
Registers Address Space
Module
Configuration
Base Address
0000 0000H
End Address
0000 00C4H
Note
Xxxxx
Table 7
Registers Overview
Register Short Name
LID_CR0
Register Long Name
Loaded Identification Number of Device and
Vendor
Offset Address Page Number
00H
36
CSD_CR1
CC_CR2
LT_CR3
Configuration Command and Status
Class Code and Revision Number
Latency Timer
I/O Base Address
Memory Base Address
Card Information Structure
Subsystem ID and Vendor ID
Boot ROM Base Address
Capabilities Pointer
Configuration Interrupt
Driver Space for Special Purpose
Signature
04H
08H
0CH
10H
14H
28H
2CH
30H
34H
3CH
40H
80H
C0H
C4H
36
38
38
39
40
40
41
41
41
42
43
43
44
46
IOBA_CR4
MBA_CR5
CIS_CR10
SID_CR11
BRBA_CR12
CP_CR13
CI_CR15
DS_CR16
SIG_CR32
PMR0_CR48
PMR1_CR49
Power Management Register 0
Power Management Register 1
The register is addressed wordwise.
Table 8
Registers Access ConditionsRegisters Access Conditions
Access Condition Short Name
Dependency
= B.
Standard abbreviations:
Table 9
Mode
Registers Access Types
Symbol Description Hardware (HW)
Description Software (SW)
read/write
rw
Register is used as input for the HW
Register is read and writable by SW
read
r
Register is written by HW (register
Value written by software is ignored by
between input and output -> one cycle hardware; that is, software may write any
delay)
value to this field without affecting hardware
behavior (= Target for development.)
write
w
Register is writable by SW
read/write
hardware
affected
rwh
Register can be modified by HW
Register can be modified by HW, but the
priority SW versus HW has to be specified
Data Sheet
34
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
Table 9
Mode
Registers Access Types (cont’d)
Symbol Description Hardware (HW)
rwv
Description Software (SW)
Read only
ro
Register is set by HW (register between SW can only read this register
input and output -> one cycle delay)
Read virtual
rv
Physically, there is no new register, the SW can only read this register
input of the signal is connected directly
to the address multiplexer.
Latch high,
self clearing
Latch low,
self clearing
lhsc
llsc
Latch high signal at high level, clear on SW can read the register
read
Latch high signal at low-level, clear on SW can read the register
read
Latch high,
lhmk
llmk
ihsc
ilsc
Latch high signal at high level, register SW can read the register, with write mask
mask clearing
cleared with written mask
the register can be cleared (1 clears)
Latch low,
mask clearing
Interrupt high,
self clearing
Interrupt low,
self clearing
Latch high signal at low-level, register SW can read the register, with write mask
cleared on read
Differentiate the input signal (low-
>high) register cleared on read
the register can be cleared (1 clears)
SW can read the register
Differentiate the input signal (high-
>low) register cleared on read
SW can read the register
Interrupt high,
mask clearing
Interrupt low,
mask clearing
ihmk
ilmk
Differentiate the input signal (high-
SW can read the register, with write mask
>low) register cleared with written mask the register can be cleared
Differentiate the input signal (low-
>high) register cleared with written
mask
SW can read the register, with write mask
the register can be cleared
Interrupt enable ien
register
latch_on_reset lor
Enables the interrupt source for
interrupt generation
rw register, value is latched after first
clock cycle after reset
SW can read and write this register
Register is read and writable by SW
Read/write
self clearing
rwsc
Register is used as input for the hw, the Writing to the register generates a strobe
register will be cleared due to a HW
mechanism.
signal for the HW (1 pdi clock cycle)
Register is read and writable by SW.
Table 10
Registers Clock Domains
Clock Short Name
Description
8.1.1
AN985B/BX Configuration Registers Descriptions
Offset
00h
04h
b31------------------------------------------------b16 b15------------------------------------------------------------b0
Device ID*
Status
Base Class Code Subclass
Vendor ID*
Command
-----------
08h
Revision# Step#
Data Sheet
35
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
Offset
0ch
b31------------------------------------------------b16 b15------------------------------------------------------------b0
------
------
Latency timer Cache line size
10h
Base I/O address
14h
Base memory address
18h~24h Reserved
28h
2ch
30h
34h
38h
3ch
40h
80h
c0h
c4h
ROM-im*
Subsystem ID*
Boot ROM base address
Reserved
Reserved
Max_Lat*
Reserved
Signature of AN985B/BX
PMC
Reserved
Address space offset*
Add-indi*
Subsystem vendor ID*
Min_Gnt*
Interrupt pin
Interrupt line
Driver Space Reserved
Next_Item_Ptr Cap_ID
PMCSR
Note:Automatically recalled from EEPROM when CARDBUS reset is deserted.
1. CIS(28H) is a read-only register.
2. DS(40H), bit 15-8, is read/write able register.
3. SIG(80H) is hard wired register, read only.
Loaded Identification Number of Device and Vendor
LID_CR0
Offset
00H
Reset Value
From EEPROMH
Loaded Identification Number of Device and
Vendor
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/9,'
UR
UR
Field
Bits
Type
Description
LDID
31:16
ro
Loaded Device ID
The device ID number loaded from serial EEPROM.
LVID
15:0
ro
Loaded Vendor ID
The vendor ID number loaded from serial EEPROM.
Reset Value loaded from EEPROM
Configuration Command and Status
Data Sheet
36
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
CSD_CR1
Configuration Command and Status
Offset
04H
Reset Value
0290 0000H
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ꢆ
ꢇ
ꢈ
ꢉ
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UZ UR UZ
UZ UZ UZ
Field
SPE
Bits
31
Type
rw
Description
Status of Parity Error
1B
, means that AN985B/BX detected a parity error. This bit will be set
in this condition even if the parity error response (bit 6 of CR1) is
disabled.
SES
SMA
30
29
rw
rw
Status of System Error
1B
, means that AN985B/BX asserted the system error pin
Status of Master Abort
1B
, means that AN985B/BX received a master abort and terminated
a master transaction
Status of Target Abort
1B , means that AN985B/BX received a target abort and terminated a
master transaction
STA
28
rw
Res
SDST
27
26:25
ro
ro
Reserved
Status of Device Select Timing
The timing of the assertion of device select.
01B , means a medium assertion of DEVSEL#
SDPR
24
rw
Status of Data Parity Report
1: when three conditions are met:
AN985B/BX asserted parity error - PERR# or it detected parity error
asserted by other device.
AN985B/BX is operating as a bus master.
5AN985B/BX’s parity error response bit (bit 6 of CR1) is enabled.
SFBB
23
ro
Status of Fast Back-to-Back
Always 1, since AN985B/BX has the ability to accept fast back-to-back
transactions.
Res
NC
22:21
20
ro
ro
Reserved
New Capabilities
This bit indicates that whether the AN985B/BX provides a list of extended
capabilities, such as CARDBUS power management.
0B
1B
, the AN985B/BX doesn’t provide New Capabilities
, the AN985B/BX provides the CARDBUS management function
Res
CSE
19:9
8
ro
rw
Reserved
Command of System Error Response
1B
, enable system error response. AN985B/BX will assert SERR#
when it find a parity error on the address phase.
Res
7
ro
Reserved
Data Sheet
37
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
Field
Bits
Type
Description
CPE
6
rw
Command of Parity Error Response
0B
, disable parity error response. AN985B/BX will ignore any
detected parity error and keep on its operating. Default value is 0.
, enable parity error response. AN985B/BX will assert system error
(bit 13 of CSR5) when a parity error is detected.
1B
Res
CMO
5:3
2
ro
rw
Reserved
Command of Master Operation Ability
0B
1B
, disable the bus master ability
, enable the CARDBUS bus master ability. Default value is 1 for
normal operation.
CMSA
CIOSA
1
0
rw
rw
Command of Memory Space Access
0B
1B
, disable the memory space access ability
, enable the memory space access ability
Command of I/O Space Access
0B
1B
, disable the I/O space access ability
, enable the I/O space access ability
Class Code and Revision Number
CC_CR2
Offset
08H
Reset Value
0200 ????H
Class Code and Revision Number
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ꢅ ꢆ ꢇ ꢈ ꢉ ꢀ ꢃ ꢁ ꢂ
%&&
6&
5HV
UR
51
UR
61
UR
UR
UR
Field
Bits
Type
Description
BCC
31:24
ro
Base Class Code
It means AN985B/BX is network controller.
SC
23:16
ro
Subclass Code
It means AN985B/BX is a Fast Ethernet Controller.
Res
RN
15:8
7:4
ro
ro
Reserved
Revision Number
Identifies the revision number of AN985B/BX.
SN
3:0
ro
Step Number
Identifies the AN985B/BX steps within the current revision.
Latency Timer
LT_CR3
Latency Timer
Offset
0CH
Reset Value
0000 0000H
Data Sheet
38
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
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ꢅ ꢆ ꢇ ꢈ ꢉ ꢀ ꢃ ꢁ ꢂ
5HV
UR
/7
&/6
UZ
UZ
Field
Res
LT
Bits
31:16
15:8
Type
ro
rw
Description
Reserved
Latency Timer
This value specifies the latency timer of the AN985B/BX in units of
CARDBUS bus clock. Once the AN985B/BX asserts FRAME#, the
latency timer starts to count. If the latency timer expires and the
AN985B/BX still asserted FRAME#, then the AN985B/BX will terminate
the data transaction as soon as its GNT# is removed.
CLS
7:0
rw
Cache Line Size
This value specifies the system cache line size in units of 32-bit double
words (DW). The AN985B/BX supports 8, 16, and 32 DW of cache line
size. This value is used by the AN985B/BX driver to program the cache
alignment bits (bit 14 and 15 of CSR0). The cache alignment bits are used
for cache oriented CARDBUS commands; say memory-read-line,
memory-read-multiple, and memory-write-and-invalidate.
I/O Base Address
IOBA_CR4
I/O Base Address
Offset
10H
Reset Value
0000 0001H
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ꢆ
ꢇ
ꢈ
ꢉ
5HV
UR
ꢀ
ꢃ
ꢁ
ꢂ
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6,
,2%$
UZ
UR
Field
Bits
Type
Description
IOBA
31:8
rw
I/O Base Address
This value indicate the base address of CARDBUS control and status
register (CSR0~28).
Res
IOSI
7:1
0
ro
ro
Reserved
I/O Space Indicator
1B
, means that the configuration registers map into the I/O space
Data Sheet
39
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
Memory Base Address
MBA_CR5
Memory Base Address
Offset
14H
Reset Value
0000 0000H
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ꢅ
ꢆ
ꢇ
ꢈ
5HV
UR
ꢉ
ꢀ
ꢃ
ꢁ
ꢂ
,2
6,
0%$
UZ
UR
Field
Bits
Type
Description
MBA
31:10
rw
Memory Base Address
This value indicates the base address of CARDBUS control and status
register (CSR0~28).
Res
IOSI
9:1
0
ro
ro
Reserved
Memory Space Indicator
1B
, means that the configuration registers map into the I/O space
Card Information Structure
This register is used to point one of the possible address spaces where the CIS begins. This register is designed
for CARDBUS environment. It’s data is auto-loaded from the serial EEPROM after power on or hardware reset.
CIS_CR10
Card Information Structure
Offset
28H
Reset Value
From EEPROMH
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ꢅ ꢆ ꢇ ꢈ ꢉ ꢀ ꢃ ꢁ ꢂ
520
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$,
UR
UR
UR
Field
ROM
Bits
31:30
Type
ro
Description
ROM Image
This ROM image value is applied when the CIS is stored in a boot ROM.
This value is loaded from serial EEPROM.
ASO
AI
29:4
3:0
ro
ro
Address Space Offset
This value indicates the offset within the address space. The address
space is specified by address space indicator(bit 2~0 of CR10).
Address Space Indicator
This value indicates the location where the CIS address space begins.
111B , means that the CIS begins in the boot ROM space.
othersB, makes all the bits of CIS reset to 0
Data Sheet
40
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
Subsystem ID and Vendor ID
SID_CR11
Subsystem ID and Vendor ID
Offset
2CH
Reset Value
From EEPROMH
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ꢅ ꢆ ꢇ ꢈ ꢉ ꢀ ꢃ ꢁ ꢂ
6,'
69,'
UR
UR
Field
Bits
Type
Description
SID
31:16
ro
Subsystem ID
This value is loaded from EEPROM after power on or hardware reset.
SVID
15:0
ro
Subsystem Vendor ID
This value is loaded from EEPROM after power on or hardware reset.
Boot ROM Base Address
This register should be initialized before accessing the boot ROM space. (Write ffffffffH return fffe0001H)
BRBA_CR12
Boot ROM Base Address
Offset
30H
Reset Value
XXXX 0000H
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ꢈ
ꢉ
ꢀ
ꢃ
ꢁ
ꢂ
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(
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5HV
UR
UZ
UZ
Field
Bits
Type
Description
BRBA
31:17
rw
Boot ROM Base Address
This value indicates the address mapping of boot ROM field. Besides, it
also defines the boot ROM size. The value of bit 17~10 is set to 0 for
AN985B/BX to support up to 256 KB of boot ROM.
Res
BRE
16:1
0
ro
rw
Reserved
Boot ROM Enable
The AN985B/BX really enables its boot ROM access only if both the
memory space access bit (bit 1 of CR1) and this bit are set to 1.
1B
, enable Boot ROM (Combines with bit 1 of CR1)
Capabilities Pointer
CP_CR13
Capabilities Pointer
Offset
34H
Reset Value
0000 00C0H
Data Sheet
41
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢉ ꢀ ꢃ ꢁ ꢂ
5HV
UR
&3
UR
Field
Res
CP
Bits
31:8
7:0
Type
ro
ro
Description
Reserved
Capabilities Pointer
Configuration Interrupt
CI_CR15
Configuration Interrupt
Offset
3CH
Reset Value
XXXX 01XXH
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ꢅ
ꢆ
ꢇ
ꢈ
ꢉ ꢀ ꢃ ꢁ ꢂ
0/
0*
,3
,/
UZ
UR
UR
UR
Field
Bits
Type
Description
ML
31:24
ro
Max. Lat Register
This value indicates “how often” the AN985B/BX needs to access to the
CARDBUS bus in the units of 250 ns. This value is loaded from serial
EEPROM after power on or hardware reset.
Note:Automatically recalled from EEPROM.
MG
23:16
ro
Min. Gnt Register
This value indicates how long the AN985B/BX needs to retain the
CARDBUS bus ownership whenever it initiates a transaction, in the units
of 250 ns. This value is loaded from serial EEPROM after power on or
hardware reset.
Note:Automatically recalled from EEPROM.
IP
IL
15:8
7:0
ro
Interrupt Pin
This value indicates which of the four interrupt request pins that
AN985B/BX is connected.Always 01H: means the AN985B/BX connects
to INTA#
rw
Interrupt Line
This value indicates which of the system interrupt request lines the INTA#
of AN985B/BX is routed to. The BIOS will fill this field when it initializes
and configures the system. The AN985B/BX driver can use this value to
determine priority and vector information.
Data Sheet
42
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
Driver Space for Special Purpose
DS_CR16
Driver Space for Special Purpose
Offset
40H
Reset Value
0000 XX00H
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ ꢆ ꢇ ꢈ ꢉ ꢀ ꢃ ꢁ ꢂ
5HV
UR
'6
5HV
UR
UZ
Field
Res
DS
Bits
31:16
15:8
Type
ro
rw
Description
Reserved
Driver Space for special purpose
Since this area won’t be cleared in the software reset. The AN985B/BX
driver can use this rw area for special purpose.
Res
7:0
ro
Reserved
Signature of AN985B/BX
Hard wired register, read only
SIG_CR32
Signature
Offset
80H
Reset Value
0985 1317H
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ ꢆ ꢇ ꢈ ꢉ ꢀ ꢃ ꢁ ꢂ
','
9,'
UR
UR
Field
Bits
Type
Description
DID
31:16
ro
Device ID
The device ID number of AN985B/BX.
VID
15:0
ro
Vendor ID
The vendor ID number of ADM Technology Corp.
Data Sheet
43
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
Power Management Register 0
PMR0_CR48
Power Management Register 0
Offset
C0H
Reset Value
FE82 0001H
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ ꢆ ꢇ ꢈ ꢉ ꢀ ꢃ ꢁ ꢂ
'ꢀ 'ꢁ
'6 5H 30
30(6
$8;&
9(5
1,3
&$3,'
6
6
,
V (&
UR
UR UR
UR
UR UR UR
UR
UR
UR
Field
PMES
Bits
31:27
Type
ro
Description
PME Support
The AN985B/BX will assert PME#/CSTSCHG signal while in the D0, D1,
D2, D3 power state. The AN985B/BX supports Wake-up from the above
states.
D2S
26
ro
ro
ro
D2 Support
The AN985B/BX supports D2 Power Management State.
D1S
25
D1 Support
The AN985B/BX supports D1 Power Management State.
AUXC
24:22
Aux Current
These three bits report the maximum 3.3 Vaux current requirements for
AN985B/BX. If bit 31 of PMR0 is ‘1’, the default value is 0101B, means
AN985B/BX need 100 mA to support remote wake-up in D3cold power
state.
DSI
21
ro
Device Specific Initialization
The Device Specific Initialization bit indicates whether special
initialization of this function is required before the generic class device
driver is able to use it.
0B
, indicates that the function does not require a device specific
initialization sequence following transition to the D0 un-initialized
state
Res
PMEC
20
19
ro
ro
Reserved
PME Clock
When “1” indicates that the AN985B/BX relies on the presence of the
CARDBUS clock for PME#/CSTSCHG operation. While “0” indicates the
no CARDBUS clock is required for the AN985B/BX to generate
PME#/CSTSCHG.
VER
NIP
18:16
15:8
ro
ro
Version
The value of 010B indicates that the AN985B/BX complies with Revision
1.0a of the CARDBUS Power Management Interface Specification.
Next Item Pointer
This value is always 0H, indicates that there is no additional items in the
Capabilities List.
Data Sheet
44
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
Field
Bits
Type
Description
CAPID
7:0
ro
Capability Identifier
This value is always 01H, indicates the link list item as being CARDBUS
Power Management Registers.
Data Sheet
45
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
Power Management Register 1
PMR1_CR49
Power Management Register 1
Offset
C4H
Reset Value
0000 0000H
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ
ꢆ ꢇ ꢈ ꢉ ꢀ ꢃ ꢁ ꢂ
30 '6&$
30
((
5HV
UR
'6(/
5HV
UR
3:56
(6
/
UZꢊ UR
UZ
UZ
UZ
Field
Res
PMES
Bits
31:16
15
Type
ro
rw*
Description
Reserved
PME Status
This bit is set when the AN985B/BX would normally assert the
PME#/CSTSCHG signal for wake-up event, this bit is independent of the
state of the PME-En bit. Writing a “1” to this bit will clear it and cause the
AN985B/BX to stop asserting a PME#/CSTSCHG (if enabled). Writing a
“0” has no effect.
Note:rw*: Read and Write Clear
DSCAL
DSEL
14:13
12:9
8
ro
Data Scale
Indicates the scaling factor to be used when interpreting the value of the
Data register.
rw
rw
Data Select
This four-bit field is used to select which data is to be reported through the
Data register and Data_Scale field.
PMEE
PME En
“1” enables the AN985B/BX to assert PME#/CSTSCHG. When “0”
disables the PME#/CSTSCHG assertion.
Magic packet default enable:
Csr18 <18> and csr18 <19> are set ->csr13 <9> is set, then #pme
asserts without impact of PME_En.
Res
PWRS
7:2
1:0
ro
rw
Reserved
Power State
This two-bit field is used both to determine the current power state of the
AN985B/BX and to set the AN985B/BX into a new power state. The
definition of this field is given below.
Note:This field is auto cleared to D0 when power resumed.
00B D0,
01B D1,
10B D2,
11B D3hot,
Data Sheet
46
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
8.2
PCI /CARDBUS Control/Status Registers
Table 11
Registers Address Space
Module
Base Address
End Address
Note
PCI/CARDBUS
0000 0000H
0000 010CH
Table 12
Registers Overview
Register Short Name
PAR_CSR0
TDR_CSR1
RDR_CSR2
RDB_CSR3
TDB_CSR4
SR_CSR5
NAR_CSR6
IER_CSR7
LPC_CSR8
SPR_CSR9
TMR_CSR11
WCSR_CSR13
WTMR_CSR15
ACSR5_CSR16
ACSR7_CSR17
CR_CSR18
CARDBUSC_CSR19
PMCSR_CSR20
WTDP_CSR21
WRDP_CSR22
TXBR_CSR23
FROM_CSR24
PAR0_CSR25
PAR1_CSR26
MAR0_CSR27
MAR1_CSR28
UAR0_CSR_29
UAR1_CSR_30
OMR
Register Long Name
Offset Address Page Number
CARDBUS Access Register
Transmit Demand Register
Receive Demand Register
Receive Descriptor Base Address
Transmit Descriptor Base Address
Status Register
Network Access Register
Interrupt Enable Register
Lost Packet Counter
Serial Port Register
General-Purpose Timer
Wake-up Control/Status Register
Watchdog Timer
Assistant CSR5 (Status Register 2)
Assistant CSR7 (Interrupt Enable Register 2)
Command Register
CARDBUS Bus Performance Counter
Power Management Command and Status
Current Working Transmit Descriptor Pointer
Current Working Receive Descriptor Pointer
Transmit Burst Count/Time-out
Flash ROM (also the boot ROM) Port
Physical Address Register 0
Physical Address Register 1
Multicast Address Register 0
Multicast Address Register 1
Unicast Address Register 0
Unicast Address Register 1
Operation Mode Register
00H
08H
10H
18H
20H
28H
30H
38H
40H
48H
58H
68H
78H
80H
84H
88H
8CH
90H
94H
98H
9CH
A0H
A4H
A8H
ACH
B0H
B4H
B8H
FCH
100H
104H
108H
10CH
49
50
52
52
53
53
57
58
61
61
62
62
65
66
67
67
70
70
72
72
73
73
74
74
75
76
77
77
77
78
79
80
80
FER
FEMR
FPSR
FFER
Function Event Register
Function Event Mask Register
Function Present State Register
Function Force Event Register
Data Sheet
47
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
The register is addressed wordwise.
Standard abbreviations:
Table 13
Mode
Registers Access Types
Symbol Description Hardware (HW)
Description Software (SW)
read/write
rw
Register is used as input for the HW
Register is read and writable by SW
read
r
Register is written by HW (register
Value written by software is ignored by
between input and output -> one cycle hardware; that is, software may write any
delay)
value to this field without affecting hardware
behavior (= Target for development.)
write
w
Register is writable by SW
read/write
hardware
affected
rwh
Register can be modified by HW
Register can be modified by HW, but the
priority SW versus HW has to be specified
rwv
ro
Read only
Register is set by HW (register between SW can only read this register
input and output -> one cycle delay)
Read virtual
rv
Physically, there is no new register, the SW can only read this register
input of the signal is connected directly
to the address multiplexer.
Latch high,
self clearing
Latch low,
self clearing
lhsc
llsc
Latch high signal at high level, clear on SW can read the register
read
Latch high signal at low-level, clear on SW can read the register
read
Latch high,
lhmk
llmk
ihsc
ilsc
Latch high signal at high level, register SW can read the register, with write mask
mask clearing
cleared with written mask
the register can be cleared (1 clears)
Latch low,
mask clearing
Interrupt high,
self clearing
Interrupt low,
self clearing
Latch high signal at low-level, register SW can read the register, with write mask
cleared on read
Differentiate the input signal (low-
>high) register cleared on read
the register can be cleared (1 clears)
SW can read the register
Differentiate the input signal (high-
>low) register cleared on read
SW can read the register
Interrupt high,
mask clearing
Interrupt low,
mask clearing
ihmk
ilmk
Differentiate the input signal (high-
SW can read the register, with write mask
>low) register cleared with written mask the register can be cleared
Differentiate the input signal (low-
>high) register cleared with written
mask
SW can read the register, with write mask
the register can be cleared
Interrupt enable ien
register
latch_on_reset lor
Enables the interrupt source for
interrupt generation
rw register, value is latched after first
clock cycle after reset
SW can read and write this register
Register is read and writable by SW
Read/write
self clearing
rwsc
Register is used as input for the hw, the Writing to the register generates a strobe
register will be cleared due to a HW
mechanism.
signal for the HW (1 pdi clock cycle)
Register is read and writable by SW.
Data Sheet
48
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
8.2.1
PCI/CARDBUS Control/Status Registers Description
CARDBUS Access Register
PAR_CSR0
CARDBUS Access Register
Offset
00H
Reset Value
0000 1000H
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢉ
ꢀ ꢃ ꢁ ꢂ
0:055H05
,( /( V 0(
5H
V
%/
(
%$6:
5 5
5HV
UR
5HV 7$3
&$/
3%/
'6/
UZꢊ
UZꢊUZꢊ UR UZꢊ UR
UZꢊ UR UZꢊ
UZꢊ
UZꢊ
UZꢊUZꢊ
Field
Res
MWIE
Bits
31:25
24
Type
ro
rw*
Description
Reserved
Memory Write and Invalidate Enable
Note:rw*: Before writing the trasmitting and receiving operations should
be stopped.
0B
, disable AN985B/BX to generate memory write invalidate
command and use memory write commands instead
, enable AN985B/BX to generate memory write invalidate
command. AN985B/BX will generate this command while writing
full cache lines
1B
MRLE
23
rw*
Memory Read Line Enable
Note:rw*: Before writing the trasmitting and receiving operations should
be stopped.
1B
, enable AN985B/BX to generate memory read line command while
read access instruction reach the cache line boundary. If the read
access instruction doesn’t reach the cache line boundary then
AN985B/BX uses the memory read command instead.
Res
MRME
22
21
ro
rw*
Reserved
Memory Read Multiple Enable
Note:rw*: Before writing the trasmitting and receiving operations should
be stopped.
1B
, enable AN985B/BX to generate memory read multiple commands
while reading full cache line. If the memory is not cache aligned the
AN985B/BX uses memory read command instead.
Res
20:19
ro
Reserved
Data Sheet
49
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
Field
Bits
Type
Description
TAP
18:17
rw*
Transmit Auto-polling in Transmit Suspended State
Note:rw*: Before writing the trasmitting and receiving operations should
be stopped.
00B , disable auto-polling (default)
01B , polling own-bit every 200 μ s
10B , polling own-bit every 800 μ s
11B , polling own-bit every 1600 μ s
Res
CAL
16
15:14
ro
rw*
Reserved
Cache Alignment, Address Boundary for Data Burst, Set after Reset
Note:rw*: Before writing the trasmitting and receiving operations should
be stopped.
00B , reserved (default)
01B , 8 DW boundary alignment
10B , 16 DW boundary alignment
11B , 32 DW boundary alignment
PBL
BLE
13:8
7
rw*
rw*
Programmable Burst Length
This value defines the maximum number of DW to be transferred in one
DMA transaction. Value: 0 (unlimited), 1, 2, 4, 8, 16 (default), 32
Note:rw*: Before writing the trasmitting and receiving operations should
be stopped.
Big or Little Endian Selection
Note:rw*: Before writing the trasmitting and receiving operations should
be stopped.
0B
1B
, little endian (e.g. INTEL)
, big endian (only for data buffer)
DSL
BAR
6:2
1
rw*
rw*
Descriptor Skip Length
Defines the gap between two descriptions in the units of DW.
Note:rw*: Before writing the trasmitting and receiving operations should
be stopped.
Bus Arbitration
Note:rw*: Before writing the trasmitting and receiving operations should
be stopped.
0B
1B
, receive higher priority
, transmit higher priority
SWR
0
rw*
Software Reset
Note:rw*: Before writing the trasmitting and receiving operations should
be stopped.
1B
, reset all internal hardware except configuration registers. This
signal will be cleared by AN985B/BX itself after it completed the
reset process.
Transmit Demand Register
Data Sheet
50
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
TDR_CSR1
Transmit Demand Register
Offset
08H
Reset Value
FFFF FFFFH
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ ꢆ ꢇ ꢈ ꢉ ꢀ ꢃ ꢁ ꢂ
73'0
UZꢊ
Field
Bits
Type
Description
TPDM
31:0
rw*
Transmit Poll Demand
When written any value in suspended state, trigger read-tx-descriptor
process and check the own-bit, if own-bit = 1, then start transmit process.
Note:rw*: Before writing the trasmitting process should be in the
suspended state.
Data Sheet
51
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
Receive Demand Register
RDR_CSR2
Receive Demand Register
Offset
10H
Reset Value
FFFF FFFFH
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ ꢆ ꢇ ꢈ ꢉ ꢀ ꢃ ꢁ ꢂ
53'0
UZꢊ
Field
Bits
Type
Description
RPDM
31:0
rw*
Receive Poll Demand
When written any value in suspended state, trigger the read-rx-descriptor
process and check own-bit, if own- bit = 1, then start move data to buffer
from FIFO.
Note:rw*: Before writing the receiving process should be in the
suspended state.
Receive Descriptor Base Address
RDB_CSR3
Receive Descriptor Base Address
Offset
18H
Reset Value
xxxx xxxxH
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ ꢆ ꢇ ꢈ ꢉ ꢀ ꢃ ꢁ ꢂ
6$5
5%1'
UZꢊ
UR
Field
Bits
Type
Description
SAR
31:2
rw*
Start Address of Receive Descriptor
Note:rw*: Before writing the receiving process should be stopped.
RBND
1:0
ro
Must be 00, DW Boundary
Data Sheet
52
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
Transmit Descriptor Base Address
TDB_CSR4
Transmit Descriptor Base Address
Offset
20H
Reset Value
xxxx xxxxH
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ ꢆ ꢇ ꢈ ꢉ ꢀ ꢃ ꢁ ꢂ
6$7
7%1'
UZꢊ
UR
Field
Bits
Type
Description
SAT
31:2
rw*
Start Address of Transmit Descriptor
Note:rw*: Before writing the trasmitting process should be stopped.
TBND
1:0
ro
Must be 00, DW Boundary
Status Register
SR_CSR5
Status Register
Offset
28H
Reset Value
0000 0000H
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ ꢆ ꢇ ꢈ ꢉ ꢀ ꢃ ꢁ ꢂ
1, $, 5H )% 5H *3 5H5:535'5& 78 5H 7- 7' 73 7&
66 66 V V 77 V 6 8 8 6
5HV
UR
%(7
76
56
(
7
,
)
V
7
,
UR
UR
UR
URꢊOKURꢊOKURURꢊOKURURꢊOKURURꢊOKURꢊOKURꢊOKURꢊOKURꢊOKURURꢊOKURꢊOKURꢊOKURꢊOK
Field
Res
Bits
31:26
Type
ro
Description
Reserved
BET
25:23
ro
Bus Error Type
This field is valid only when bit 13 of CSR5 (fatal bus error) is set. There
is no interrupt generated by this field.
000B , parity error
001B , master abort
010B , target abort
011B , reserved
1xxB , reserved
Data Sheet
53
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
Field
Bits
Type
Description
TS
22:20
ro
Transmit State
Report the current transmission state only, no interrupt will be generated.
000B , stop
001B , read descriptor
010B , transmitting
011B , FIFO fill read the data from memory and put into FIFO
100B , reserved
101B , reserved
110B , suspended, unavailable transmit descriptor or FIFO overflow
111B , write descriptor
RS
19:17
ro
Receive State
Report current receive state only, no interrupt will be generated.
000B , stop
001B , read descriptor
010B , check this packet and pre-fetch next descriptor
011B , wait for receiving data
100B , suspended
101B , write descriptor
110B , flush the current FIFO
111B , FIFO drain. move data from receiving FIFO into memory
NISS
AISS
16
15
ro/lh
ro/lh
Normal Interrupt Status Summary
It’s set if any of below bits of CSR5 asserted. (Combines with bit 16 of
ACSR5)
bit0, transmit completed interrupt
bit2, transmit descriptor unavailable
bit6, receive descriptor interrupt
Note: LH = High Latching and cleared by writing 1
Abnormal Interrupt Status Summary
It’s set if any of below bits of CSR5 asserted. (Combines with bit 15 of
ACSR5)
bit1, transmit process stopped
bit3, transmit jabber timer time-out
bit5, transmit under-flow
bit7, receive descriptor unavailable
bit8, receive processor stopped
bit9, receive watchdog time-out
bit11, general purpose timer time-out
bit13, fatal bus error
Note:LH = High Latching and cleared by writing 1
Reserved
Fatal Bus Error
Res
FBE
14
13
ro
ro/lh
Note:LH = High Latching and cleared by writing 1
1B
, while any of parity error master abort, or target abort is occurred
(see bits 25~23 of CSR5). AN985B/BX will disable all bus access.
The way to recover parity error is by setting software reset.
Res
12
ro
Reserved
Data Sheet
54
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
Field
Bits
Type
Description
GPTT
11
ro/lh
General Purpose Timer Time-out
Base on CSR11 timer register.
Note:LH = High Latching and cleared by writing 1
Res
RWT
10
9
ro
ro/lh
Reserved
Receive Watchdog Time-out
Based on CSR15 watchdog timer register.
Note:LH = High Latching and cleared by writing 1
RPS
RDU
8
7
ro/lh
ro/lh
Receive Process Stopped
Receive state = stop
Note:LH = High Latching and cleared by writing 1
Receive Descriptor Unavailable
Note:LH = High Latching and cleared by writing 1
1B
, while the next receive descriptor can’t be applied by AN985B/BX.
The receive process is suspended in this situation. To restart the
receive process the ownership bit of next receive descriptor should
be set to AN985B/BX and a receive poll demand command should
be issued (or a new recognized frame is received, if the receive poll
demand is not issued).
RCI
6
5
ro/lh
ro/lh
Receive Completed Interrupt
Note:LH = High Latching and cleared by writing 1
1B
, while a frame reception is completed
TUF
Transmit Under-Flow
Note:LH = High Latching and cleared by writing 1
1B
, while the transmit FIFO had an under-flow condition happened
during transmitting. The transmit process will enter the suspended
state and report the under-flow error on bit1 of TDES0
Res
TJT
4
3
ro
ro/lh
Reserved
Transmit Jabber Timer Time-out
Note:LH = High Latching and cleared by writing 1
1B
, while the transmit jabber timer expired. The transmit processor
will enter the stop state and the transmit jabber time-out flag of bit
14 of TDES0 will be asserted
TDU
2
1
ro/lh
ro/lh
Transmit Descriptor Unavailable
Note:LH = High Latching and cleared by writing 1
1B
, while the next transmit descriptor can’t be applied by AN985B/BX.
The transmission process is suspended in this situation. To restart
the transmission process the ownership bit of next transmit
descriptor should be set to AN985B/BX and if the transmit
automatic polling is not enabled then a transmit poll demand
command should be issued.
TPS
Transmit Process Stopped
Note:LH = High Latching and cleared by writing 1
1B
, while transmit state = stop
Data Sheet
55
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
Field
Bits
Type
Description
TCI
0
ro/lh
Transmit Completed Interrupt
Note:LH = High Latching and cleared by writing 1
1B
, means a frame transmission is completed while bit 31 of TDES1
is asserted in the first transmit descriptor of the frame
Data Sheet
56
Rev. 1.51, 2005-11-30
UZꢊ UR UZꢊ
UZꢊ UZUZꢊꢊ UZꢊꢊ
UR UZꢊꢊU
ZꢊꢊUꢊZꢊꢊ URUZꢊꢊUZꢊꢊꢊUZ UR
AN985B/BX
Registers and Descriptors Description
Network Access Register
NAR_CSR6
Network Access Register
Offset
30H
Reset Value
0008 0040H
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢉ
ꢀ
ꢃ
ꢁ
ꢂ
5H 64
6% 5H
5H
V
5HV
UR
6)
5HV
UR
75 67 )& 20 5HV 0035
3% 38 65
V
(
& V
Field
Res
SF
Bits
31:22
21
Type
ro
rw*
Description
Reserved
Store and Forward for Transmit
Note:w* = only write when the transmit processor stopped.
0B
1B
, disable
, enable ignore the transmit threshold setting
Res
SQE
20
19
ro
rw*
Reserved
SQE Disable
Note:w* = only write when the transmit processor stopped.
0B
, enable SQE function for 10BASE-T operation. The AN985B/BX
provides SQE test function for 10BASE-T half duplex operation
, disable SQE function
1B
Res
TR
18:16
15:14
ro
rw*
Reserved
Transmit Threshold Control
Note:w* = only write when the transmit processor stopped.
00B , 128-byte (100 Mbit/s) 72-byte (10 Mbit/s)
01B , 256-byte (100 Mbit/s) 96-byte (10 Mbit/s)
10B , 512-byte (100 Mbit/s) 128-byte (10 Mbit/s)
00B , 1024-byte (100 Mbit/s) 160 -byte (10 Mbit/s)
ST
FC
13
12
rw
Stop Transmit
0B
1B
, stop (default)
, start
rw**
Force Collision Mode
Note:w** = only write when the transmit and receive processor both
stopped.
0B
1B
, disable
, generate collision when transmit (for test in loop-back mode)
Data Sheet
57
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
Field
Bits
Type
Description
OM
11:10
rw**
Operating Mode
Note:w** = only write when the transmit and receive processor both
stopped.
00B , normal
01B , MAC loop-back
10B , reserved
11B , reserved
Res
MM
9:8
7
ro
rw***
Reserved
Multicast Mode
Note:w*** = only write when the receive processor stopped.
1B
, receive all multicast packets
PR
6
5
rw***
rw**
Promiscuous Mode
Note:w*** = only write when the receive processor stopped.
0B
1B
, receive only the right destination address packets
, receive any good packet
SBC
Stop Back-off Counter
Note:w** = only write when the transmit and receive processor both
stopped.
0B
1B
, back-off counter is not effected by carrier
, back-off counter stop when carrier is active and resume when
carrier drop.
Res
PB
4
3
ro
rw***
Reserved
Pass Bad Packet
Note:w*** = only write when the receive processor stopped.
0B
1B
, filters all bad packets
, receives any packets if pass address filter, including runt packets,
CRC error, truncated packets... For receiving all bad packets, the
bit 6 of CSR6 should be set to 1.
PU
SR
2
1
rw***
rw
Pass Unicast Mode
Note:w*** = only write when the receive processor stopped.
1B
, back-off counter stop when carrier is active and resume when
carrier drop.
Start/Stop Receive
0B , receive processor will enter stop state after the current reception
frame completed. This value is effective only when the receive
processor is in the running or suspending state. Notice: In “Stop
Receive” state the PAUSE packet and Remote Wake Up packet
won’t be affected and can be received if the corresponding function
is enabled.
1B
, receive processor will enter running state
Res
0
ro
Reserved
Interrupt Enable Register
Data Sheet
58
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
IER_CSR7
Interrupt Enable Register
Offset
38H
Reset Value
0000 0000H
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ ꢆ ꢇ ꢈ ꢉ ꢀ ꢃ ꢁ ꢂ
1, $, 5H )% 5H *3 5H5:56585& 78 5H 7- 7' 73 7&
V (ꢀ V 7ꢀ V 7ꢀ ,( ,( ,( ,( V 7ꢀ 8ꢀ 6ꢀ ,(
5HV
UR
(
(
UZ UZ UR UZ UR UZ UR UZ UZ UZ UZ UZ UR UZ UZ UZ UZ
Field
Res
NIE
Bits
31:17
16
Type
ro
rw
Description
Reserved
Normal Interrupt Enable
1B , enable all the normal interrupt bits (see bit16 of CSR5)
Abnormal Interrupt Enable
1B , enable all the abnormal interrupt bits (see bit15 of CSR5)
AIE
15
rw
Res
FBEIE
14
13
ro
rw
Reserved
Fatal Bus Error Interrupt Enable
1B
, combine this bit and bit 15 of CSR7 to enable fatal bus error
interrupt
Res
GPTIE
12
11
ro
rw
Reserved
General Purpose Timer Interrupt Enable
1B
, combine this bit and bit 15 of CSR7 to enable general-purpose
timer expired interrupt
Res
RWTIE
10
9
ro
rw
Reserved
Receive Watchdog Time-out Interrupt Enable
1B
, combine this bit and bit 15 of CSR7 to enable receive watchdog
time-out interrupt
RSIE
RUIE
RCIE
TUIE
8
7
6
5
rw
rw
rw
rw
Receive Stopped Interrupt Enable
1B
, combine this bit and bit 15 of CSR7 to enable receive stopped
interrupt
Receive Descriptor Unavailable Interrupt Enable
1B
, combine this bit and bit 15 of CSR7 to enable receive descriptor
unavailable interrupt
Receive Completed Interrupt Enable
1B
, combine this bit and bit 16 of CSR7 to enable receive completed
interrupt
Transmit Under-flow Interrupt Enable
1B
, combine this bit and bit 15 of CSR7 to enable transmit under-flow
interrupt
Res
TJTTIE
4
3
ro
rw
Reserved
Transmit Jabber Timer Time-out Interrupt Enable
1B
, combine this bit and bit 15 of CSR7 to enable transmit jabber timer
time-out interrupt
TDUIE
2
rw
Transmit Descriptor Unavailable Interrupt Enable
1B
, combine this bit and bit 16 of CSR7 to enable transmit descriptor
unavailable interrupt
Data Sheet
59
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
Field
TPSIE
Bits
1
Type
rw
Description
Transmit Processor Stopped Interrupt Enable
1B
, combine this bit and bit 15 of CSR7 to enable transmit processor
stopped interrupt
TCIE
0
rw
Transmit Completed Interrupt Enable
1B
, combine this bit and bit 16 of CSR7 to enable transmit completed
interrupt.
Data Sheet
60
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
Lost Packet Counter
LPC_CSR8
Lost Packet Counter
Offset
40H
Reset Value
0000 0000H
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ ꢆ ꢇ ꢈ ꢉ ꢀ ꢃ ꢁ ꢂ
/3
5HV
/3&
&2
UR
URꢊOK
URꢊOK
Field
Res
LPCO
Bits
31:17
16
Type
ro
ro/lh
Description
Reserved
Lost Packet Counter Overflow
Note:LH = High Latching and cleared by writing 1
1B , while lost packet counter overflowed. Cleared after read
Lost Packet Counter
Increment the counter while packet discarded since there was no host
receives descriptors available. Cleared after read.
LPC
15:0
ro/lh
Note:LH = High Latching and cleared by writing 1
Serial Port Register
SPR_CSR9
Serial Port Register
Offset
48H
Reset Value
0004 000EH
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ
ꢆ
5HV
UR
ꢇ ꢈ ꢉ ꢀ ꢃ ꢁ ꢂ
0'000'0'5H 656:5H 65
6' 6' 6& 6&
, /. 6
5HV
,
& 2 &
V
& &
V
6
2
UR
UZ UZ UZ UZ UR UZ UZ UR UZ
UR UZ UZ UZ
Field
Res
Bits
31:20
Type
ro
Description
Reserved
MDI
19
rw
MII Management Data Input
Specified read data from the external PHY
MMC
MDO
18
17
rw
rw
MII Management Control
0B
1B
, Write operation to the external PHY
, Read operation from the external PHY
MII Management Data Output
Specified Write Data to the external PHY
Data Sheet
61
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
Field
Bits
Type
Description
MDC
16
rw
MII Management Clock
1B
, MII Management Clock is a output reference clock to the external
PHY
Res
15
14
13
12
11
10:4
3
ro
rw
rw
ro
rw
ro
ro
Reserved
SRC
SWC
Res
SRS
Res
Serial EEPROM Read Control
Serial EEPROM Write Control
Reserved
Serial EEPROM Select
Reserved
SDO
Serial EEPROM Data Out
This bit serially shifts data from the EEPROM to the AN985B/BX.
SDI
2
1
0
rw
rw
rw
Serial EEPROM Data In
This bit serially shifts data from the AN985B/BX to the EEPROM.
SCLK
SCS
Serial EEPROM Clock
High/Low this bit to provide the clock signal for EEPROM.
Serial EEPROM Chip Select
1B
, selects the serial EEPROM chip
General-Purpose Timer
TMR_CSR11
General-Purpose Timer
Offset
58H
Reset Value
0000 0000H
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ ꢆ ꢇ ꢈ ꢉ ꢀ ꢃ ꢁ ꢂ
&2
5HV
*79
0
UR
UZ
UZ
Field
Res
COM
Bits
31:17
16
Type
ro
rw
Description
Reserved
Continuous Operation Mode
1B , sets the general-purpose timer in continuous operating mode
GTV
15:0
rw
General-Purpose Timer Value
Sets the counter value. This is a countdown counter with the cycle time
of 204 μ s.
Wake-up Control/Status Register
WCSR_CSR13
Wake-up Control/Status Register
Offset
68H
Reset Value
0000 00??H
Data Sheet
62
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
5HV
UR
ꢉ ꢀ ꢃ ꢁ ꢂ
5H &5:3:3:3:3:3
V &7 ꢀ( ꢁ( ꢂ( ꢃ( ꢄ(
/L /L
Qꢅ Qꢅ
:)03 /6
5( 5( &(
:)03 /6
5 5 &
5HV
UR
5HV
UR
UR UZ UZ UZ UZ UZ UZ
UZ UZ
UZ UZ UZ
UZꢁUFZꢁUFZꢁF
Field
Res
Bits
31
Type
ro
Description
Reserved
CRCT
30
rw
CRC-16 Type
0B
1B
, Initial contents = 0000h
, Initial contents = FFFFh
WP1E
WP2E
WP3E
WP4E
WP5E
Res
29
28
27
26
25
24:18
17
rw
rw
rw
rw
rw
ro
Wake-up Pattern n Matched Enable
n = 1 to 5
Reserved
Link Off Detect Enable
LinkOFF
rw
The AN985B/BX will set the LSC bit of CSR13 after it has detected that
link status is from ON to OFF.
LinkON
16
rw
Link On Detect Enable
The AN985B/BX will set the LSC bit of CSR13 after it has detected that
link status is from OFF to ON.
Res
WFRE
15:11
10
ro
rw
Reserved
Wake-up Frame Received Enable
The AN985B/BX will include the “Wake-up Frame Received” event into
wake-up events. If this bit is set, AN985B/BX will assert PMES bit of
PMR1 after AN985B/BX has received a matched wake-up frame.
MPRE
LSCE
9
8
rw
rw
Magic Packet Received Enable
The AN985B/BX will include the “Magic Packet Received” event into
wake-up events. If this bit is set, AN985B/BX will assert PMES bit of
PMR1 after AN985B/BX has received a Magic packet.
Link Status Changed Enable
The AN985B/BX will include the “Link Status Changed” event into wake-
up events. If this bit is set, AN985B/BX will assert PMES bit of PMR1 after
AN985B/BX has detected a link status changed event.
Res
WFR
7:3
2
ro
rw1c
Reserved
Wake-up Frame Received
Note:rw1c: Read only and Write one cleared.
1B
, Indicates AN985B/BX has received a wake-up frame. It is cleared
by write 1 or upon power-up reset. It is not affected by a hardware
or software reset
Data Sheet
63
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
Field
Bits
Type
Description
MPR
1
rw1c
Magic Packet Received
Note:rw1c: Read only and Write one cleared.
1B
, Indicates AN985B/BX has received a magic packet. It is cleared
by write 1 or upon power-up reset. It is not affected by a hardware
or software reset
LSC
0
rw1c
Link Status Changed
Note:rw1c: Read only and Write one cleared.
1B
, Indicates AN985B/BX has detected a link status change event. It
is cleared by write 1 or upon power-up reset. It is not affected by a
hardware or software reset
CSR14, WPDR – Wake-up Pattern Data Register
All six wake-up patterns filtering information are programmed through WPDR register. The filtering information is
as follows:
Offset
0000h
0004h
0008h
000ch
0010h
0014h
0018h
001ch
0020h
0024h
0028h
002ch
0030h
0034h
0038h
003ch
0040h
0044h
0048h
004ch
0050h
0054h
0058h
005ch
0060h
31-24
23-16
15-8
7-0
Wake-up pattern 1 mask bits 31:0
Wake-up pattern 1 mask bits 63:32
Wake-up pattern 1 mask bits 95:64
Wake-up pattern 1 mask bits 127:96
CRC16 of pattern 1
Wake-up pattern 2 mask bits 31:0
Wake-up pattern 2 mask bits 63:32
Wake-up pattern 2 mask bits 95:64
Wake-up pattern 2 mask bits 127:96
CRC16 of pattern 2
Wake-up pattern 3 mask bits 31:0
Wake-up pattern 3 mask bits 63:32
Wake-up pattern 3 mask bits 95:64
Wake-up pattern 3 mask bits 127:96
CRC16 of pattern 3
Wake-up pattern 4 mask bits 31:0
Wake-up pattern 4 mask bits 63:32
Wake-up pattern 4 mask bits 95:64
Wake-up pattern 4 mask bits 127:96
CRC16 of pattern 4
Reserved
Reserved
Reserved
Reserved
Reserved
Wake-up pattern 1 offset
Wake-up pattern 2 offset
Wake-up pattern 3 offset
Wake-up pattern 4 offset
Wake-up pattern 5 mask bits 31:0
Wake-up pattern 5 mask bits 63:32
Wake-up pattern 5 mask bits 95:64
Wake-up pattern 5 mask bits 127:96
CRC16 of pattern 5
Wake-up pattern 5 offset
Rev. 1.51, 2005-11-30
1. CRC-16 polynomial: still pending
Data Sheet
64
UHRꢊHꢇUHKRꢊ
HꢇU@HKRꢊ
Hꢇ@HKꢁ>ꢁꢇ@K>ꢂ@
UZ UZ UR UZ UZ UZ
AN985B/BX
Registers and Descriptors Description
2. Offset value is from 0-255 (8-bit width).
3. To load the whole wake-up frame-filtering information, consecutive 25 long words write operation to CSR14
should be done.
Watchdog Timer
WTMR_CSR15
Watchdog Timer
Offset
78H
Reset Value
0000 0000H
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢉ
ꢀ
ꢃ
ꢁ
ꢂ
&% 5[ 5[
5:5:5H -&
5 ' V /.
-%
'
&6
5HV
UR
1-
6
6 5H
Field
Bits
Type
Description
CS
31
ro/ee16 Clock Save Mode
h[3]
0B
1B
, clock stuck at 0 when clock save mode enable
, clock stuck at 1 when clock save mode enable
CBS
RxS
30
29
28
ro/ee16 CARDBUS Save Mode
h[2] 1B , CARDBUS clock save mode enable
ro/ee16 Rx Save Mode
h[1] 1B , RX save mode enable
RxRe
ro/ee16 Rx Clock Reverse Mode
h[0]
ro
1B
, reverse (for NS HomePHY mode)
Res
RWR
27:6
5
Reserved
rw
Receive Watchdog Release
The time of release watchdog timer from last carrier deserted.
0B
1B
, 24 bit-time
, 48 bit-time
RWD
4
rw
Receive Watchdog Disable
0B
, If the receiving packet’s length is longer than 2560 bytes the
watchdog timer will be expired
1B
, disable the receive watchdog
Res
JCLK
3
2
ro
rw
Reserved
Jabber Clock
0B
1B
, cut off transmission after 2.6 ms (100 Mbit/s) or 26 ms (10 Mbit/s)
, cut off transmission after 2560 byte-time
NJ
1
0
rw
rw
Non-Jabber
0B
, if jabber expired re-enable transmit function after 42 ms
(100 Mbit/s) or 420 ms (10 Mbit/s)
, immediately re-enable the transmit function after jabber expired
1B
JBD
Jabber Disable
1B , disable transmit jabber function
Data Sheet
65
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
Assistant CSR5 (Status Register 2)
ACSR5_CSR16
Assistant CSR5 (Status Register 2)
Offset
80H
Reset Value
0000 0000H
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ ꢆ ꢇ ꢈ ꢉ ꢀ ꢃ ꢁ ꢂ
7( 5( /& 7' 5H 3)
,6 ,6 6 ,6 V
$1$$
,ꢀ ,ꢀ
5HV
UR
&65ꢁ
5
URꢊOKURꢊOKURꢊOKURꢊOKURURꢊOK
URꢊOKURꢊOK
UR
Field
TEIS
Bits
31
Type
ro/lh
Description
Transmit Early Interrupt Status
Transmit early interrupt status is set to 1 when Transmit early interrupt
function is enabled (set bit 31 of CSR17 = 1) and the transmitted packet
is moved completed from descriptors to TX-FIFO buffer. This bit is
cleared by written with 1.
Note:LH = High Latching and cleared by writing 1
REIS
30
ro/lh
Receive Early Interrupt Status
Receive early interrupt status is set to 1 when Receive early interrupt
function is enabled (set bit 30 of CSR17 = 1) and the received packet is
fill up its first receive descriptor. This bit is cleared by written with 1.
Note:LH = High Latching and cleared by writing 1
Status of Link Status Change
Note:LH = High Latching and cleared by writing 1
Transmit Deferred Interrupt Status
Note:LH = High Latching and cleared by writing 1
Reserved
LCS
29
28
ro/lh
ro/lh
TDIS
Res
PFR
27
26
ro
ro/lh
PAUSE Frame Received Interrupt Status
Note:LH = High Latching and cleared by writing 1
1B
, indicates a PAUSE frame received when the PAUSE function is
enabled
Res
ANISS
25:17
16
ro
ro/lh
Reserved
Added Normal Interrupt Status Summary
Note:LH = High Latching and cleared by writing 1
1B
, any of the added normal interrupts happened
AAISS
CSR5
15
ro/lh
ro
Added Abnormal Interrupt Status Summary
Note:LH = High Latching and cleared by writing 1
1B
, any of added abnormal interrupt happened
14:0
This bits are the same as CSR5
You can access those status bits through either CSR5 or CSR16
Data Sheet
66
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
Assistant CSR7 (Interrupt Enable Register 2)
ACSR7_CSR17
Assistant CSR7 (Interrupt Enable Register 2)
Offset
84H
Reset Value
0000 0000H
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ ꢆ ꢇ ꢈ ꢉ ꢀ ꢃ ꢁ ꢂ
7( 5( /& 7' 5H 3)
,( ,( ,( ,( V 5ꢀ
$1$$
,ꢀ ,(
5HV
UR
&65ꢁ
UZ UZ UZ UZ UR UZ
UZ UZ
UR
Field
TEIE
REIE
LCIE
TDIE
Res
Bits
31
30
29
28
Type
Description
rw
rw
rw
rw
ro
Transmit Early Interrupt Enable
Receive Early Interrupt Enable
Link Status Change Interrupt Enable
Transmit Deferred Interrupt Enable
Reserved
27
PFRIE
Res
ANISE
26
25:17
16
rw
ro
rw
PAUSE Frame Received Interrupt Enable
Reserved
Added Normal Interrupt Summary Enable
1B
, adds the interrupts of bit 30 and 31 of ACSR7 to the normal
interrupt summary (bit 16 of CSR5)
AAIE
15
rw
ro
Added Abnormal Interrupt Summary Enable
1B
, adds the interrupt of bit 26, 28 and 29 of ACSR7 to the abnormal
interrupt summary
CSR7
14:0
This bits are the same as CSR7
You can access those status bits through either CSR7 or CSR16
Command Register
Bit 31 to Bit 16
Automatically recall from EEPROM
CR_CSR18
Command Register
Offset
88H
Reset Value
A04C 0004H
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ ꢆ ꢇ ꢈ ꢉ ꢀ ꢃ ꢁ ꢂ
'ꢀ
&6
30303&
ꢂB
ꢀ/
&5
'
$3/:
0 6
3/ 'ꢀ5:3$ 57
6 $ 3 8ꢁ (
6, $7
$8;&/
36
5)6
30
5HV
UR
'57
(ꢁ (ꢁ
,
17 85
UZ
UR
UZ UZ UZ UZ UZ UZ UZ UR UZ UZ
UZ UZ UZ UZ UZ UZ UZ UZ
Field
Bits
Type
Description
D3CS
31
rw
D3cold Support, Mapped to CR48<31>
Data Sheet
67
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
Field
Bits
Type
Description
AUXCL
30:28
ro
Aux Current
Should be 0.
PMEPS
PMEPE
PCI
27
26
25
24
rw
rw
rw
rw
PMEP Select
0B
1B
, positive pulse
, negative pulse
PMEP Pin Enable
0B
1B
, disable(for old board)
, enable
PCI Pad
0B
1B
, apply CARDBUS Pad in CARDBUS Mode. No effect in PCI Mode
, apply PCI Pad in CARDBUS Mode(for twinhead notebook)
PS
PMES Sticky
0B
, pmez auto de-asserted: pmez will be disasserted by power up
after wakeup event trigger.
1B
, pmez sticky: Vcc_detect has no impact to pmez disasserts
4_3L
RFS
23
rw
rw
4_3LED
0B
1B
, 3 LED scheme
, 4 LED scheme
22:21
Receive FIFO Size Control
00B , reserved
01B , reserved
10B , 2K
11B , 1K
CRD
PM
20
19
rw
ro
Clock Run (clk-run pin) Disable
1B
, disables the function of clock run supports to CARDBUS
Power Management
Enables the AN985B/BX whether to activate the Power Management
abilities. When this bit is set into “0” the AN985B/BX will set the Cap_Ptr
register to zero, indicating no CARDBUS compliant power management
capabilities.The value of this bit will be mapped to NC-bit 20 of CR1.In
CARDBUS Power Management mode, the Wake-up events include
“Wake-up Frame Received”, “Magic Packet Received” and “Link Status
Changed” depends on the CSR13 settings.
APM
18
rw
APM Mode
This bit is effective when PM (csr18 [19]) = 1.
LWS
Res
PLS
17
16:9
8
rw
ro
rw
Should be 0
Reserved
PMEP Pulse Length Select
0B
1B
, long pulse 50ms
, short pulse 100us for test purpose
D3A
7
6
rw
rw
D3_cold APM Mode Enable
PMEZ can be asserted without the impact of PME_EN
RWP
Reset Wake-up Pattern Data Register Pointer
0B
1B
, Normal
, Reset
Data Sheet
68
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
Field
Bits
Type
Description
PAUSE
5
rw
PAUSE Function Control
To disable or enable the PAUSE function for flow control. The default
value of PAUSE is decided by the result of Auto-Negotiation. Driver can
force to enable or disable it after the Auto-Negotiation completed.
0B
1B
, PAUSE function is disabled
, PAUSE function is enabled
RTE
DRT
4
rw
rw
Receive Threshold Enable
0B
, disable the receive FIFO threshold selection in bit 3~2 of this
register, the receive threshold is set to 64-byte.
, the receive FIFO threshold is enabled
1B
3:2
Drain Receive Threshold
00B , 32 bytes (8 DW)
01B , 64 bytes (16 DW)
10B , store-and -forward
11B , reserved
SINT
ATUR
1
0
rw
rw
Software Interrupt
Automatically Transmit-Underrun Recovery
1B
, enable automatically transmit-underrun recovery
Data Sheet
69
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
CARDBUS Bus Performance Counter
CARDBUSC_CSR19
CARDBUS Bus Performance Counter
Offset
8CH
Reset Value
0000 0000H
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ ꢆ ꢇ ꢈ ꢉ ꢀ ꢃ ꢁ ꢂ
&/.&17
5HV
UR
':&17
URꢊ
URꢊ
Field
CLKCNT
Bits
31:16
Type
ro*
Description
Clock Count
The number of CARDBUS clock from read request asserted to access
completed. This CARDBUS clock number is accumulated all the read
command cycles from last CSR19 read to current CSR19 read.
Note:ro*: Read only and cleared by reading
Reserved
Double Word Count
Res
DWCNT
15:8
7:0
ro
ro*
The number of double word accessed by the last bus master. This double
word number is accumulated all the bus master data transactions from
last CSR19 read to current CSR19 read.
Note:ro*: Read only and cleared by reading
ro = Read only and cleared by reading
Power Management Command and Status
(The same register value mapping to CR49-PMR1)
PMCSR_CSR20
Power Management Command and Status
Offset
90H
Reset Value
0000 0000H
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ
ꢆ ꢇ ꢈ ꢉ ꢀ ꢃ ꢁ ꢂ
30 '6&$
30
(ꢀ
5HV
UR
'6(/
5HV
UR
3:56
(6
/
UR UR
UR
UR
UR
Field
Res
Bits
31:16
Type
ro
Description
Reserved
Data Sheet
70
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
Field
PMES
Bits
15
Type
ro
Description
PME_Status
This bit is set when the AN985B/BX would normally assert the PME#
signal for wake-up event, this bit is independent of the state of the PME-
En bit. Writing a “1” to this bit will clear it and cause the AN985B/BX to
stop asserting a PME# (if enabled). Writing a “0” has no effect. Since the
AN985B/BX doesn’t supports PME# from D3cold, this bit is defaulted to
“0”.
DSCAL
DSEL
14:13
12:9
8
ro
ro
ro
Data_Scale
Indicates the scaling factor to be used when interpreting the value of the
Data register. This field is required for any function that implements the
Data register. Otherwise, it’s optional.The AN985B/BX doesn’t support
Data register and Data_Scale.
Data_Select
This four bit field is used to select which data is to be reported through the
Data register and Data_Scale field. This field is required for any function
that implements the Data register. The AN985B/BX doesn’t support
Data_Select.
PME_En
PME_En
“1” enables the AN985B/BX to assert PME#. When “0” disables the
PME# assertion.This bit defaults to “0” if the function does not support
PME# generation from D3cold.
Res
PWRS
7:2
1:0
ro
ro
Reserved
PowerState
This two bit field is used both to determine the current power state of the
AN985B/BX and to set the AN985B/BX into a new power state. The
definition of this field is given below.
00B - D0
01B - D1
10B - D2
11B - D3hot
If software attempts to write an unsupported, optional state to this field,
the write operation must complete normally on the bus, however the data
is discarded a no state change occurs.
Data Sheet
71
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
Current Working Transmit Descriptor Pointer
WTDP_CSR21
Current Working Transmit Descriptor Pointer
Offset
94H
Reset Value
xxxx xxxxH
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ ꢆ ꢇ ꢈ ꢉ ꢀ ꢃ ꢁ ꢂ
:7'3
UR
Field
Bits
Type
Description
WTDP
31:0
ro
Working Transmit Descriptor Pointer
The current working transmit descriptor pointer for driver’s double-
checking or other special purpose.
Current Working Receive Descriptor Pointer
WRDP_CSR22
Current Working Receive Descriptor Pointer
Offset
98H
Reset Value
xxxx xxxxH
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ ꢆ ꢇ ꢈ ꢉ ꢀ ꢃ ꢁ ꢂ
:5'3
UR
Field
Bits
Type
Description
WRDP
31:0
ro
Working Receive Descriptor Pointer
The current working receive descriptor pointer for driver’s double-
checking or other special purpose.
Data Sheet
72
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
Transmit Burst Count/Time-out
TXBR_CSR23
Transmit Burst Count/Time-out
Offset
9CH
Reset Value
0000 0000H
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ ꢆ ꢇ ꢈ ꢉ ꢀ ꢃ ꢁ ꢂ
5HV
UR
7%&17
5HV
772
UZ
UZ
Field
Res
Bits
31:21
Type
ro
Description
Reserved
TBCNT
20:16
rw
Transmit Burst Count
After this number of consecutive successful transmit, transmit completed
interrupt will be generated. Continuously do this function if no reset.
TTO
11:0
rw
Transmit Time-Out = (deferred time + back-off time)
When the TDIE (bit28 of ACSR7) is set, the timer is decreased in unit of
2.56 μ s (100M) or 25.6 μ s (10M). If the timer expires before another
packet transmit begin, then the TDIE interrupt will be generated.
Flash ROM (also the boot ROM) Port
FROM_CSR24
Flash ROM (also the boot ROM) Port
Offset
A0H
Reset Value
8000 0000H
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ ꢆ ꢇ ꢈ ꢉ ꢀ ꢃ ꢁ ꢂ
%2
1
5(:(
1 1
5HV
UR
$''5
'$7$
UZ
UZ UZ
UZ
UZ
Field
BON
Bits
31
Type
rw
Description
Bra16_on
This bit is no effective when 3_LED scheme applied.
Driver needs to program this bit when 4_LED applied especially when
boot rom read.
0B
1B
, bra[16]=fd/col LED path
, no effect to bar[16]
Res
REN
30:28
27
ro
rw
Reserved
Read Enable
Clear if read data is ready in DATA, bit7-0 of FROM.
WEN
26
rw
Write Enable
Cleared if write completed.
Data Sheet
73
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
Field
ADDR
DATA
Bits
25:8
7:0
Type
rw
rw
Description
Flash ROM Address
Read/Write Data of Flash ROM
Physical Address Register 0
Automatically recall from EEPROM
PAR0_CSR25
Physical Address Register 0
Offset
A4H
Reset Value
xxxx xxxxH
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢉ ꢀ ꢃ ꢁ ꢂ
3$%ꢀ
3$%ꢁ
3$%ꢂ
3$%ꢃ
UZ
UZ
UZ
UZ
Field
PAB3
PAB2
PAB1
PAB0
Bits
Type
rw
rw
rw
rw
Description
Physical Address Byte n
n = 0 to 3
31:24
23:16
15:8
7:0
Physical Address Register 1
Automatically recall from EEPROM
PAR1_CSR26
Physical Address Register 1
Offset
A8H
Reset Value
xxxx xxxxH
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢉ ꢀ ꢃ ꢁ ꢂ
5HV
UR
5HV
UR
3$%ꢀ
3$%ꢁ
UZ
UZ
Field
Res
Res
PAB5
PAB4
Bits
31:24
23:16
15:8
7:0
Type
ro
ro
rw
rw
Description
Reserved
Reserved
Physical Address Byte 5
Physical Address Byte 4
For example, physical address = 00-00-e8-11-22-33
PAR0 = 11 e8 00 00
PAR1 = xx xx 33 22
PAR0 and PAR1 are readable, but can be written only if the receive state is in stopped (CSR5 bit19-17 = 000).
Data Sheet 74 Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
Multicast Address Register 0
MAR0_CSR27
Multicast Address Register 0
Offset
ACH
Reset Value
0000 0000H
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ ꢆ ꢇ ꢈ ꢉ ꢀ ꢃ ꢁ ꢂ
0$%ꢀ
0$%ꢁ
0$%ꢂ
0$%ꢃ
UZ
UZ
UZ
UZ
Field
Bits
Type
rw
rw
rw
rw
Description
Multicast Address Byte n
n = 0 to 3
MAB3
MAB2
MAB1
MAB0
31:24
23:16
15:8
7:0
Data Sheet
75
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
Multicast Address Register 1
MAR1_CSR28
Multicast Address Register 1
Offset
B0H
Reset Value
0000 0000H
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ ꢆ ꢇ ꢈ ꢉ ꢀ ꢃ ꢁ ꢂ
0$%ꢀ
0$%ꢁ
0$%ꢂ
0$%ꢃ
UZ
UZ
UZ
UZ
Field
Bits
Type
rw
rw
rw
rw
Description
MAB7
MAB6
MAB5
MAB4
31:24
23:16
15:8
7:0
Multicast Address Byte 7 (hash table 63:56)
Multicast Address Byte 6 (hash table 55:48)
Multicast Address Byte 5 (hash table 47:40)
Multicast Address Byte 4 (hash table 39:32)
MAR0 and MAR1 are readable, but can be written only if the receive state is in stopped (CSR5 bit19-17 = 000)
Data Sheet
76
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
Unicast Address Register 0
UAR0_CSR_29
Unicast Address Register 0
Offset
B4H
Reset Value
0000 0000H
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢉ ꢀ ꢃ ꢁ ꢂ
8$%ꢀ
8$%ꢁ
8$%ꢂ
8$%ꢃ
UZ
UZ
UZ
UZ
Field
UAB3
UAB2
UAB1
UAB0
Bits
Type
rw
rw
rw
rw
Description
31:24
23:16
15:8
7:0
Unicast Address Byte 3 (hash table 31:24)
Unicast Address Byte 2 (hash table 23:16)
Unicast Address Byte 1 (hash table 15:8)
Unicast Address Byte 0 (hash table 7:0)
Unicast Address Register 1
UAR1_CSR_30
Unicast Address Register 1
Offset
B8H
Reset Value
0000 0000H
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢉ ꢀ ꢃ ꢁ ꢂ
8$%ꢀ
8$%ꢁ
8$%ꢂ
8$%ꢃ
UZ
UZ
UZ
UZ
Field
UAB7
UAB6
UAB5
UAB4
Bits
Type
rw
rw
rw
rw
Description
31:24
23:16
15:8
7:0
Unicast Address Byte 7 (hash table 63:56)
Unicast Address Byte 6 (hash table 55:48)
Unicast Address Byte 5 (hash table 47:40)
Unicast Address Byte 4 (hash table 39:32)
Unicast64 Algorithm
The algorithm is the same with multicast64.
Operation Mode Register
OMR
Offset
FCH
Reset Value
0000 0007H
Operation Mode Register
Data Sheet
77
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ ꢆ ꢇ ꢈ ꢉ ꢀ ꢃ ꢁ ꢂ
63
(ꢀ
/, 5H
1. V
(ꢁ
6/
)'
(7
5HV
UR
&0RGH
UR UR UR UR UZ UZ
UZ
Field
Bits
Type
Description
SPEED
31
ro
Network Speed Status
0B
1B
, 10M
, 100M
FD
30
29
ro
ro
Full/Half Duplex Status
0B
1B
, Half duplex
, Full duplex
LINK
Network Link Status
0B
1B
, Link off
, Link OK
Res
ET
28
27
ro
rw
Reserved
ET
0B
1B
, 9346
, 9366
E2SL
26
rw
E2prom_Soft_Load
Write 1 to reload e2prom
Res
CMode
25:3
2:0
ro
rw
Reserved
Chip Mode
These three bits are used to configure AN985B/BX’s chip mode:
111B , normal mode
110B , monitor mode
100B , HOME PNA mode
001B , phy only mode
101B , HP94000tester mode(vaux, vcc_detect will be internal forced to
1B, and muxed with poweron_reset input and ssram_rdy)
Function Event Register
FER
Offset
100H
Reset Value
0000 0000H
Function Event Register
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢉ
ꢀ ꢃ ꢁ ꢂ
,Q
*:
8(
5HV
UR
5HV
UR
5HV
UR
(Y
UOKꢊZꢁF
UZꢁF
Field
Res
Bits
31:16
Type
ro
Description
Bits[31:16] are reserved in the CARDBUS Specification
Data Sheet
78
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
Field
Bits
Type
Description
InEv
15
rlh/w1c Interrupt Event
This bit is used for as the interrupt bit. It is set when the Ethernet interrupt
source is set,regardless of the mask value. It is cleared when the OS
writes 1B to the field and the interrupt source has been serviced. Writing
0B to the field has no effect.
Res
GWUE
14:5
4
ro
rw1c
Bits[14:5] are reserved in the CARDBUS Specification
General Wake-up Event
This bit is used for general wake-up. It is set when the Ethernet wake-up
source is set, regardless of the mask value. Writing 1B to the field clears
this bit and the PME status bit in the PMCSR. Writing 0B to the field has
no effect. Note that writing 1B to the PME status bit in the PMCSR has the
same effect.
Note:rw1c: Read only and Write one cleared.
Res
3:0
ro
Bits[3:0] are reserved in the CARDBUS Specification
Function Event Mask Register
FEMR
Offset
104H
Reset Value
0000 8000H
Function Event Mask Register
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢉ
ꢀ ꢃ ꢁ ꢂ
,Q :8
*:
8(
5HV
UR
5HV
UR
5HV
UR
(Y 0
UZ UZ
UR
Field
Res
InEv
Bits
31:16
15
Type
ro
rw
Description
Bits[31:16] are reserved in the CARDBUS Specification
Interrupt Event
This bit is the interrupt mask. When the bit equals 0B, it masks the
Ethernet function CSTSCHG signal bit has no effect on the Function
Event Register. This bit is dependent on bit 4 of this register.
WUM
14
rw
Wake-Up Mask
When the bit equals 0B, it masks the Ethernet function INTA# line bus has
no effect on the Function Event Register. The interrupt mask
Res
GWUE
13:5
4
ro
ro
Bits[14:5] are reserved in the CARDBUS Specification
General Wake-up Event
This bit is the general wake-up mask. When the bit equals 0B, it masks
Ethernet function wake-up events towards the CSTSCHG signal. It has
no effect on the Function Event register. The AN985B/BX can assert the
CSTSCHG signal in the following configuration of masked bits:wake-up
bit AND general wake-up bit, or PME Enable bit in the PMCSR register
only.
Res
3:0
ro
Bits[3:0] are reserved in the CARDBUS Specification
Data Sheet
79
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
Function Present State Register
FPSR
Offset
108H
Reset Value
0000 0000H
Function Present State Register
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢉ
ꢀ ꢃ ꢁ ꢂ
,Q
*:
8(
5HV
UR
5HV
UR
5HV
UR
(Y
UR
UR
Field
Res
InEv
Bits
31:16
15
Type
ro
ro
Description
Bits[31:16] are reserved in the CARDBUS Specification
Interrupt Event
This bit is used for interrupts. It reflects the current state of the Ethernet
source of the interrupt regardless of the mask value. It is set when the
Ethernet function hasa pending interrupt and cleared when the software
driver acknowledges all active interrups through the SCB Command
Word.
Res
GWUE
14:5
4
ro
ro
Bits[14:5] are reserved in the CARDBUS Specification
General Wake-up Event
This bit is used for general wake-up. It reflects the current state of the
Ethernet source of CSTSCHG. It is a logical OR reseult of the gated three
most significant bits in the PMDR: Link Status change bit is gated by the
Link Status Change Wake Enable bit in the Configuration command. The
Magic Packet bit is gated by the Magic Packet Wake-up disable bit in the
Configuration command. The Interesting Packet bit is gated by the
programmable filter command.
Res
3:0
ro
Bits[3:0] are reserved in the CARDBUS Specification
Function Force Event Register
FFER
Offset
10CH
Reset Value
0000 0000H
Function Force Event Register
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢉ
ꢀ ꢃ ꢁ ꢂ
,Q
*:
8)
5HV
UR
5HV
UR
5HV
UR
)ꢀ
Z
Z
Field
Res
Bits
31:16
Type
ro
Description
Bits[31:16] are reserved in the CARDBUS Specification
Data Sheet
80
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
Field
Bits
Type
Description
InFor
15
w
Interrupt Force
This bit is used for interrupts. Writing 1B in the field will set the interrupt
bit in the Function Event register. If the INTA# pin is not masked, then it
will also be actived. Writing 0B to the field has no effect.
Res
GWUF
14:5
4
ro
w
Bits[14:5] are reserved in the CARDBUS Specification
General Wake-up Force
This bit is used for general wake-up. Writing 1B in the field will set the
CSTSCHG bit in the Function Event register. If the CSTSCHG pin is not
masked, then it will also be actived. Writing 0B to the field has no effect
Res
3:0
ro
Bits[3:0] are reserved in the CARDBUS Specification
Data Sheet
81
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
8.3
PHY Registers
Table 14
Module
PHY
Registers Address Space
Base Address
End Address
0000 0006H
Note
0000 0000H
Table 15
Registers Overview
Register Short Name
Register Long Name
Register 0(MII Control)
Register 1(Status)
Register 2
Register 3
Register 4
Offset Address Page Number
R0
R1
R2
R3
R4
R5
R6
0H
1H
2H
3H
4H
5H
6H
83
85
87
87
88
89
90
Register 5
Register 6
The register is addressed wordwise.
Standard abbreviations:
Table 16
Mode
Registers Access Types
Symbol Description Hardware (HW)
Description Software (SW)
read/write
rw
Register is used as input for the HW
Register is read and writable by SW
read
r
Register is written by HW (register
Value written by software is ignored by
between input and output -> one cycle hardware; that is, software may write any
delay)
value to this field without affecting hardware
behavior (= Target for development.)
write
w
Register is writable by SW
read/write
hardware
affected
rwh
Register can be modified by HW
Register can be modified by HW, but the
priority SW versus HW has to be specified
rwv
ro
Read only
Register is set by HW (register between SW can only read this register
input and output -> one cycle delay)
Read virtual
rv
Physically, there is no new register, the SW can only read this register
input of the signal is connected directly
to the address multiplexer.
Latch high,
self clearing
Latch low,
self clearing
lhsc
llsc
Latch high signal at high level, clear on SW can read the register
read
Latch high signal at low-level, clear on SW can read the register
read
Latch high,
mask clearing
lhmk
Latch high signal at high level, register SW can read the register, with write mask
cleared with written mask
the register can be cleared (1 clears)
Data Sheet
82
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
Table 16
Mode
Registers Access Types (cont’d)
Symbol Description Hardware (HW)
Description Software (SW)
Latch low,
llmk
ihsc
ilsc
Latch high signal at low-level, register SW can read the register, with write mask
mask clearing
cleared on read
the register can be cleared (1 clears)
SW can read the register
Interrupt high,
self clearing
Interrupt low,
self clearing
Differentiate the input signal (low-
>high) register cleared on read
Differentiate the input signal (high-
>low) register cleared on read
SW can read the register
Interrupt high,
mask clearing
Interrupt low,
mask clearing
ihmk
ilmk
Differentiate the input signal (high-
SW can read the register, with write mask
>low) register cleared with written mask the register can be cleared
Differentiate the input signal (low-
>high) register cleared with written
mask
SW can read the register, with write mask
the register can be cleared
Interrupt enable ien
register
latch_on_reset lor
Enables the interrupt source for
interrupt generation
rw register, value is latched after first
clock cycle after reset
SW can read and write this register
Register is read and writable by SW
Read/write
self clearing
rwsc
Register is used as input for the hw, the Writing to the register generates a strobe
register will be cleared due to a HW
mechanism.
signal for the HW (1 pdi clock cycle)
Register is read and writable by SW.
8.3.1
PHY Transceiver Registers Descriptions
Register 0
MII Control
R0
Offset
0H
Reset Value
Register 0(MII Control)
1000H
ꢀꢁ
ꢀꢂ
/223
UZ
ꢀꢃ
ꢀꢄ
ꢀꢀ
ꢀꢅ
,6
UZ
ꢆ
ꢇ
ꢈ
ꢉ
ꢁ
ꢂ
ꢃ
5HV
UR
ꢄ
ꢀ
ꢅ
5(6(
7
63((
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5$1 '0
UZVF UZ
&7
UR
UZVF
UZ
UZ
UZ
Field
RESET
Bits
15
Type
rwsc
Description
Reset
0B
1B
, normal operation
, PHY Reset
LOOP
14
rw
Loopback
0B
1B
, disable loopback
, enable loopback
Data Sheet
83
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
Field
Bits
Type
Description
SPEED
13
rw
Speed Selection
0B
1B
, 10 Mbit/s
, 100 Mbit/s
ANE
PD
IS
12
11
10
rw
rw
rw
Autonegotiation Enable
0B
1B
, disable autoneg
, enable autoneg
Power Down
0B
1B
, normal operation
, Power Down
Isolate
0B
1B
, normal operation
, isolate PHY from MII
RAN
DM
9
8
rwsc
rw
Restart Autonegotiation
1B , Restart Autoneg
Duplex Mode
0B
1B
, half duplex
, full duplex
CT
7
ro
ro
Collision Test
Not implemented
Res
6:0
Reserved
SC: Self Clearing
Reset: Reset this port only. This will cause the following:
1. Restart the autonegotiation process.
2. Reset the registers to their default values. Note that this does not affect registers 20, 22, 30 or 31. These
registers are not reset by this bit to allow test configurations to be written and then not affected by resetting the
port.
Note:No reset is performed to analogue sections of the port. There is also no physical reset to any internal clock
synthesizers or the local clock recovery oscillator which will continue to run throughout the reset period.
However since the port is restarted and autoneg re-run the process of locking the frequency of the local
oscillator (slave) to the reference oscillator (master) will be repeated as it is at the start of any link initialization
process.
Loopback: Loop back of transmit data to receive via a path as close to the wire as possible. When set inhibits
actual transmission on the wire.
Speed selection: Forces speed of Phy only when autonegotiation is disabled. The default state of this bit will be
determined by a power-up configuration pin in this case. Otherwise it defaults to 1.
Auto-neg enable Defaults to pin programmed value. When cleared allows forcing of speed and duplex settings.
When set (after being cleared) causes re-start of autoneg process. Pin programming at power-up allows it to come
up disabled and for software to write the desired capability before allowing the first negotiation to commence.
Restart Negotiation: only has effect when autonegotiating. Restarts state machine.
Power down: Has no effect in this device. Test mode power down modes may be implemented in other specific
modules.
Isolate: Puts RMII receive signals into high impedance state and ignores transmit signals.
Duplex mode: When bit12 is cleared (i.e. autoneg disabled), this bit forces full duplex (bit = 1) or half duplex
(bit = 0).
Data Sheet
84
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
Collision test: Always 0 because collision signal is not implemented.
Register 1
Status
R1
Offset
1H
Reset Value
7849H
Register 1(Status)
ꢀꢁ
ꢀꢂ
ꢀꢃ
ꢀꢄ
ꢀꢀ
ꢀꢅ
ꢆ
ꢇ
ꢈ
ꢉ
ꢁ
ꢂ
ꢃ
ꢄ
ꢀ
ꢅ
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ꢀꢁꢁ% ꢀꢁꢁ%
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UR
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UR
UR
UR
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Field
Bits
Type
Description
100BT4
15
ro
100 BASE T4
Not supported
100BFD
100BHD
10FD
14
13
12
11
ro
ro
ro
ro
100 BASE-X Full Duplex
0B
1B
, PHY is not 100BASE-X full duplex capable
, PHY is 100BASE-X full duplex capable
100BASE-X Half Duplex
0B
1B
, PHY is not 100BASE-X half duplex capable
, PHY is 100BASE-X half duplex capable
10 Mbit/s Full Duplex
0B
1B
, PHY is not 10 Mbit/s/s Full duplex capable
, PHY is 10 Mbit/s/s Full duplex capable
10HD
10 Mbit/s Half Duplex
0B
1B
, PHY is not 10 Mbit/s/s Half duplex capable
, PHY is 10 Mbit/s/s Half duplex capable
100BT2FD
100BT2HD
10
9
ro
ro
100BASE-T2 Full Duplex
Not supported
100BASE-T2 Half Duplex
Not supported
Res
MFPS
8:7
6
ro
ro
Reserved
MF Preamble Suppression
0B
, PHY cannot accept management frames with preamble
suppression
, PHY can accept management frames with preamble suppression
1B
AC
RF
5
4
ro
Autoneg Complete
0B
1B
, autoneg incomplete
, autoneg completed
ro, lh
Remote Fault
Note:lh: Latch High
0B
1B
, no remote fault detected
, remote fault detected
Data Sheet
85
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
Field
Bits
Type
Description
AA
3
ro
Autoneg Ability
0B
1B
, PHY cannot auto-negotiate
, PHY can auto-negotiate
LS
JD
EC
2
1
0
ro, ll
ro, lh
ro
Link Status
Note:lh: Latch Low
0B
1B
, link is down
, link is up
Jabber Detect
Only used in 10Base-T mode. Reads as 0 in 100Base-TX mode.
Note:lh: Latch High
1B
, jabber condition detected
Extended Capability
0B
1B
, basic register set capabilities only
, extended register capabilities
Register 2 and 3
Each PHY has an unique identifier, which is assigned to the device.
The identifier contains a total of 32 bits, which consists of the following: 22 bits of a 24bit organizationally unique
identifier (OUI) for the manufacturer; a 6-bit manufacturer’s model number; a 4-bit manufacturer’s revision number.
For an explanation of how the OUI maps to the register, please refer to IEEE 802-1990 clause 5.1.
There is physically only one of each of these registers for all six network(MDI) ports. When reading this register
the port number is ignored.
Data Sheet
86
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
Register 2
R2
Register 2
Offset
2H
Reset Value
001DH
ꢀꢁ
ꢀꢂ
ꢀꢃ
ꢀꢄ
ꢀꢀ
ꢀꢅ
ꢆ
ꢇ
ꢈ
ꢉ
ꢁ
ꢂ
ꢃ
ꢄ
ꢀ
ꢅ
3+<B,'
UR
Field
Bits
Type
Description
PHY_ID
15:0
ro
PHY_ID[31-16]
3Com OUI (bits 3-18)
Register 3
R3
Register 3
Offset
3H
Reset Value
2411H
ꢀꢁ
ꢀꢂ
ꢀꢃ
ꢀꢄ
ꢀꢀ
ꢀꢅ
ꢆ
ꢇ
ꢈ
ꢉ
ꢁ
ꢂ
ꢃ
ꢄ
ꢀ
ꢅ
3+<B,'ꢀ
3+<B,'ꢁ
3+<B,'ꢂ
UR
UR
UR
Field
Bits
Type
Description
PHY_ID0
15:10
ro
PHY_ID[15-10]
3Com OUI (bits 19-24)
PHY_ID1
PHY_ID2
9:4
3:0
ro
ro
PHY_ID[9-4]
Manufacturer’s Model Number (bits 5-0)
PHY_ID[3-0]
Revision Number (bits 3-0); Register 3, bit 0 is LS bit of PHY Identifier
This uses the OUI of Infineon-ADMtek, device type of 1 and rev 0
Data Sheet
87
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
Register 4
R4
Register 4
Offset
4H
Reset Value
0001H
ꢀꢁ
13
UZ
ꢀꢂ
ꢀꢃ
5)
UZ
ꢀꢄ
ꢀꢀ
ꢀꢅ
ꢆ
ꢇ
ꢈ
ꢉ
ꢁ
ꢂ
ꢃ
ꢄ
ꢀ
ꢅ
3$86
(
ꢀꢂꢂ% ꢀꢂꢂ% ꢀꢂ%) ꢀꢂ%+
5HV
UR
1,ꢀ
1,ꢁ
UR
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UR
UZ
UZ
UZ
UZ
UZ
Field
NP
Bits
15
Type
rw
Description
Next Page
0B
1B
, Device not set to use Next Page
, Device set to use Next Page
Res
RF
14
13
ro
rw
Reserved
Remote Fault
0B
1B
, no fault detected
, Local remote fault sent to link partner
NI1
12:11
ro
rw
ro
rw
Not Implemented
Technology ability bits A7-A6
PAUSE
NI2
10
9
Pause
Technology ability bit A5
Not Implemented
Technology ability bit A4
100BASE-TX Full Duplex
Technology ability bit A3
100BFD
8
0B
1B
, Unit is not capable of Full Duplex
, Unit is capable of Full Duplex
100BHD
10BFD
10BHD
SF
7
rw
rw
rw
ro
100BASE-TX Half Duplex
Technology ability bit A2
0B
1B
, Unit is not capable of Half Duplex 100BASE-TX
, Unit is capable of Half Duplex
6
10BASE-T Full Duplex
Technology ability bit A1
0B
1B
, Unit is not capable of Full Duplex 10BASE-T
, Unit is capable of Full Duplex 10BASE-T
5
10BASE-T Half Duplex
Technology ability bit A0
0B
1B
, Unit is not capable of Half Duplex 10BASE-T
, Unit is capable of Half Duplex 10BASE-T
4:0
Selector Field
Identifies type of message being sent. Currently only one value is
defined.
Data Sheet
88
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
Register 5
The register is used to view the advertised capabilities of the link partner once autonegotiation is complete. The
contents of this register should not be relied upon unless register 1 bit 5 is set (autoneg complete). After
negotiation this register should contain a copy of the link partner’s register 4. All bits are therefore defined in the
same way as for register 4.
All bits are read only.
This register is used for Base Page code word only.
Base Page Register Format
R5
Register 5
Offset
5H
Reset Value
0000 0000H
ꢀꢁ
ꢀꢂ
ꢀꢃ
ꢀꢄ
ꢀꢀ
ꢀꢅ
ꢆ
ꢇ
ꢈ
ꢉ
ꢁ
ꢂ
ꢃ
ꢄ
ꢀ
ꢅ
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UR
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Field
NP
Bits
15
Type
ro
Description
Next Page
0B
1B
, Base Page is requested
, Link Partner is requesting Next Page function
ACK
RF
14
ro
ro
ro
ro
Acknowledge
Link Partner acknowledgement bit
13
Remote Fault
Link Partner is indicating a fault
Technology Ability
Link Partner technology ability field.
Selector Field
Link Partner selector field
TA
12:5
4:0
SF
Data Sheet
89
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
Register 6
R6
Register 6
Offset
6H
Reset Value
0004H
ꢀꢁ
ꢀꢂ
ꢀꢃ
ꢀꢄ
ꢀꢀ
ꢀꢅ
5HV
UR
ꢆ
ꢇ
ꢈ
ꢉ
ꢁ
ꢂ
ꢃ
ꢄ
ꢀ
ꢅ
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Field
Res
PDF
Bits
15:5
4
Type
ro
ro, lh
Description
Reserved
Parallel Detection Fault
Note:lh: Latch Hight
0B
1B
, No fault detected
, Local Device Parallel Detection Fault
LPNP
NP
3
2
1
ro
Link Partner Next Page Able
0B
1B
, Link Partner is not Next Page Able
, Link Partner is Next Page Able
ro
Next Page Able
0B
1B
, Local device is not Next Page Able
, Local device is Next Page Able
PR
ro, lh
Page Received
Note:lh: Latch Hight
0B
1B
, A New Page has not been received
, A New Page has been received
LPAA
0
ro
Link Partner Autonegotiation Able
0B
1B
, Link Partner is not Autonegotiation able
, Link Partner is Autonegotiation able
Data Sheet
90
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
LH: Latch High
Figure 15 NIC, PHY, and I/O interconnection
Data Sheet
91
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
Figure 16 Timing
Data Sheet
92
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
8.4
Descriptors and Buffer Management
Table 17
Registers Overview
Register Short Name
RDES0
Register Long Name
RDES0
Offset Address Page Number
00H
94
RDES1
RDES1
04H
97
RDES2
RDES2
08H
97
RDES3
TDES0
RDES3
TDES0
0ChH
00H
97
98
TDES1
TDES1
04H
99
TDES2
TDES3
TDES2
TDES3
08H
0ChH
100
100
The register is addressed wordwise.
Standard abbreviations:
Table 18
Mode
Registers Access Types
Symbol Description Hardware (HW)
Description Software (SW)
read/write
rw
Register is used as input for the HW
Register is read and writable by SW
read
r
Register is written by HW (register
Value written by software is ignored by
between input and output -> one cycle hardware; that is, software may write any
delay)
value to this field without affecting hardware
behavior (= Target for development.)
write
w
Register is writable by SW
read/write
hardware
affected
rwh
Register can be modified by HW
Register can be modified by HW, but the
priority SW versus HW has to be specified
rwv
ro
Read only
Register is set by HW (register between SW can only read this register
input and output -> one cycle delay)
Read virtual
rv
Physically, there is no new register, the SW can only read this register
input of the signal is connected directly
to the address multiplexer.
Latch high,
self clearing
Latch low,
self clearing
lhsc
llsc
Latch high signal at high level, clear on SW can read the register
read
Latch high signal at low-level, clear on SW can read the register
read
Latch high,
lhmk
llmk
Latch high signal at high level, register SW can read the register, with write mask
mask clearing
cleared with written mask
the register can be cleared (1 clears)
Latch low,
mask clearing
Latch high signal at low-level, register SW can read the register, with write mask
cleared on read the register can be cleared (1 clears)
Data Sheet
93
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
Table 18
Mode
Registers Access Types (cont’d)
Symbol Description Hardware (HW)
Description Software (SW)
Interrupt high,
self clearing
ihsc
Differentiate the input signal (low-
>high) register cleared on read
SW can read the register
Interrupt low,
self clearing
ilsc
Differentiate the input signal (high-
>low) register cleared on read
SW can read the register
Interrupt high,
mask clearing
Interrupt low,
mask clearing
ihmk
ilmk
Differentiate the input signal (high-
SW can read the register, with write mask
>low) register cleared with written mask the register can be cleared
Differentiate the input signal (low-
>high) register cleared with written
mask
SW can read the register, with write mask
the register can be cleared
Interrupt enable ien
register
latch_on_reset lor
Enables the interrupt source for
interrupt generation
rw register, value is latched after first
clock cycle after reset
SW can read and write this register
Register is read and writable by SW
Read/write
self clearing
rwsc
Register is used as input for the hw, the Writing to the register generates a strobe
register will be cleared due to a HW
mechanism.
signal for the HW (1 pdi clock cycle)
Register is read and writable by SW.
8.4.1
Receive Descriptor Descriptions
The AN985B/BX provides receive and transmit descriptors for packet buffering and management.
Descriptors and receive buffers addresses must be longword alignment
Table 19
Receive Descriptor Table
31 ----------------------------------------------------------------------------------------------------------------------------- 0
RDES0
RDES1
RDES2
RDES3
Own
Status
---
Control
Buffer2 byte-count
Buffer1 byte-count
Buffer1 address (DW boundary)
Buffer2 address (DW boundary)
RDES0
RDES0
RDES0
Offset
00H
Reset Value
xxxx xxxxH
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢉ
ꢀ
ꢃ ꢁ ꢂ
2:
5H
V
)/
(6 '( '7 5) 0) )6 /6 7/ &6 )75:
'%&( 2)
1
UZ
UZ
UZ UZ UZ UZ UZ UZ UZ UZ UZ UZ UZ UR UZ UZ UZ
Data Sheet
94
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
Field
OWN
Bits
31
Type
rw
Description
Own Bit
0B
1B
, Host does not move the receiving data out yet
, indicate the new receiving data can be put into this descriptor
FL
30:16
15
rw
rw
Frame Length, Including CRC
This field is valid only in last descriptor
ES
Error Summary, OR of the Following Bit
This field is valid only in last descriptor.
0: overflow
1: CRC error
6: late collision
7: frame too long
11: runt packet
14: descriptor error
DE
DT
14
rw
rw
Descriptor Error
This bit is valid only in last descriptor
1B
, the current receiving packet is not able to put into the current valid
descriptor. This packet is truncated
13:12
Data Type
These bits are valid only in last descriptor
00B , normal
01B , MAC loop-back
10B , Transceiver loop-back
11B , remote loop-back
RF
MF
11
10
rw
rw
Runt Frame (packet length < 64 bytes)
This bit is valid only in last descriptor.
Multicast Frame
This bit is valid only in last descriptor.
FS
LS
TL
9
8
7
rw
rw
rw
First Descriptor
Last Descriptor
Too Long Packet (packet length > 1518 bytes)
This bit is valid only in last descriptor.
CS
FT
6
5
rw
rw
Late Collision
Set when collision is active after 64 bytes. This bit is valid only in last
descriptor.
Frame Type
This bit is valid only in last descriptor.
0B
1B
, 802.3 type
, Ethernet type
RW
4
rw
Receive Watchdog (refer to CSR15, bit 4)
This bit is valid only in last descriptor.
Res
DB
3
2
ro
rw
Reserved
Dribble Bit
This bit is valid only in last descriptor.
ECPacket length is not integer multiple of 8-bit.
CE
1
rw
CRC Error
This bit is valid only in last descriptor.
Data Sheet
95
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
Field
OF
Bits
0
Type
rw
Description
Overflow
This bit is valid only in last descriptor.
Data Sheet
96
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
RDES1
RDES1
RDES1
Offset
04H
Reset Value
xxxx xxxxH
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ ꢆ ꢇ ꢈ ꢉ ꢀ ꢃ ꢁ ꢂ
5(5&
5HV
UR
5HV
5%6ꢀ
5%6ꢁ
5 +
UZ UZ UR
UZ
UZ
Field
Res
RER
Bits
31:26
25
Type
ro
rw
Description
Reserved
Receive End of Ring
Indicates this descriptor is last, return to base address of descriptor.
RCH
24
rw
Second Address Chain
Use for chain structure. Indicates the buffer2 address is the next
descriptor address.Ring mode takes precedence over chained mode
Res
RBS2
23:22
21:11
ro
rw
Reserved
Buffer 2 Size
DW boundary
RBS1
10:0
rw
Buffer 1 Size
DW boundary
RDES2
RDES2
RDES2
Offset
08H
Reset Value
xxxx xxxxH
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ ꢆ ꢇ ꢈ ꢉ ꢀ ꢃ ꢁ ꢂ
5%$ꢀ
UZ
Field
Bits
Type
Description
RBA1
31:0
rw
Receive Buffer Address 1
This buffer address should be double word aligned.
RDES3
Data Sheet
97
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
RDES3
RDES3
Offset
0ChH
Reset Value
xxxx xxxxH
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ ꢆ ꢇ ꢈ ꢉ ꢀ ꢃ ꢁ ꢂ
5%$ꢀ
UZ
Field
Bits
Type
Description
RBA2
31:0
rw
Receive Buffer Address 2
This buffer address should be double word aligned.
8.4.2
Transmit Descriptor Descriptions
The AN985B/BX provides receive and transmit descriptors for packet buffering and management.
Descriptor addresses must be longword alignment
Table 20
Transmit Descriptor Table
31 ----------------------------------------------------------------------------------------------------------------------------- 0
TDES0
TDES1
TDES2
TDES3
Own
Control
Buffer1 address
Buffer2 address
Status
Buffer2 byte-count
Buffer1 byte-count
TDES0
TDES0
TDES0
Offset
00H
Reset Value
xxxx xxxxH
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢉ
ꢀ
ꢃ
ꢁ ꢂ
2:
5H
V
5HV
UR
85
5HV
UR
(6 72 5HV /21& /& (& +)
&&
UZ
8) '(
1
UZ
UZ
UZ UZ UR UZ UZ UZ UZ UZ
UR UZ UZ
Field
OWN
Bits
31
Type
rw
Description
Own Bit
0B
1B
, No transmit data in this descriptor for transmission
, Indicate this descriptor is ready to transmit
Res
UR
Res
30:24
23:22
21:16
ro
rw
ro
Reserved
Under-run Count
Reserved
Data Sheet
98
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
Field
Bits
Type
Description
ES
15
rw
Error Summary, OR of the Following Bit
1: under-run error
8: excessive collision
9: late collision
10: no carrier
11: loss carrier
14: jabber time-out
TO
Res
LO
NC
LC
EC
HF
CC
Res
UF
DE
14
13:12
11
10
9
8
7
6:3
2
1
rw
ro
Transmit Jabber Time-out
Reserved
Loss Carrier
rw
rw
rw
rw
rw
rw
ro
No Carrier
Late Collision
Excessive Collision
Heartbeat Fail
Collision Count
Reserved
rw
rw
Under-run Error
Deferred
0
TDES1
TDES1
TDES1
Offset
04H
Reset Value
xxxx xxxxH
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ
ꢆ
ꢇ
ꢈ
ꢉ ꢀ ꢃ ꢁ ꢂ
7( 7& '3 5H
,& /6 )6 5HV $&
7%6ꢀ
7%6ꢁ
UZ
5 + '
V
UZ UZ UZ UR UZ UZ UZ UZ UR
UZ
Field
IC
LS
FS
Res
AC
Bits
31
30
29
28:27
26
Type
rw
rw
rw
ro
rw
rw
rw
Description
Interrupt Completed
Last Descriptor
First Descriptor
Reserved
Disable add CRC Function
End of Ring
TER
TCH
25
24
2nd Address Chain
Indicate the buffer2 address is the next descriptor address
DPD
Res
23
22
rw
ro
Disable Padding Function
Reserved
TBS2
TBS1
21:11
10:0
rw
rw
Buffer 2 Size
Buffer 1 Size
Data Sheet
99
Rev. 1.51, 2005-11-30
AN985B/BX
Registers and Descriptors Description
TDES2
TDES2
TDES2
Offset
08H
Reset Value
xxxx xxxxH
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ ꢆ ꢇ ꢈ ꢉ ꢀ ꢃ ꢁ ꢂ
%$ꢀ
UZ
Field
Bits
Type
Description
BA1
31:0
rw
Buffer Address 1
Without any limitation on the transmission buffer address.
TDES3
TDES3
TDES3
Offset
0ChH
Reset Value
xxxx xxxxH
ꢀꢁ ꢀꢂ ꢃꢄ ꢃꢅ ꢃꢆ ꢃꢇ ꢃꢈ ꢃꢉ ꢃꢀ ꢃꢃ ꢃꢁ ꢃꢂ ꢁꢄ ꢁꢅ ꢁꢆ ꢁꢇ ꢁꢈ ꢁꢉ ꢁꢀ ꢁꢃ ꢁꢁ ꢁꢂ ꢄ
ꢅ ꢆ ꢇ ꢈ ꢉ ꢀ ꢃ ꢁ ꢂ
%$ꢀ
UZ
Field
Bits
Type
Description
BA2
31:0
rw
Buffer Address 2
Without any limitation on the transmission buffer address.
Data Sheet
100
Rev. 1.51, 2005-11-30
AN985B/BX
Electrical Specifications and Timings
9
Electrical Specifications and Timings
9.1
Absolute Maximum Ratings
Table 21
Min-Max Ratings
Parameter
Symbol
Values
Typ.
–
–
–
Unit
Note / Test Condition
Min.
-0.5
-0.5
-0.5
- 65
0
Max.
3.6
V
V
150
70
2000
Supply Voltage
Input Voltage
Output Voltage
Storage Temperature
Ambient Temperature
ESD Protection
VCC
VCC
VCC
°C
V
–
CC + 0.5 V
CC + 0.5 V
°C
°C
V
°C
9.2
DC Specifications
Table 22
Parameter
General DC Specifications
Symbol
Values
Unit
Note / Test Condition
Min.
3.0
–
Typ.
–
–
Max.
3.6
1
Supply Voltage
Power Supply
VCC
ICC
V
A
–
–
Table 23
Parameter
PCI Interface DC Specifications
Symbol
Values
Unit
Note / Test Condition
Min.
Typ.
Max.
Input LOW Voltage
Input HIGH Voltage
Input Leakage Current
Output LOW Voltage
Output HIGH Voltage
Input Pin Capacitance
CLK Pin Capacitance
Vilp
Vihp
Iilp
Volp
Vohp
Cinp
Cclkp
-0.5
0.475 VCC
-10
–
0.9 VCC
5
10
–
–
–
–
–
–
–
0.325 VCC
V
–
–
V
CC + 0.5 V
10
0.1 VCC
–
17
22
µA
V
V
pF
pF
0 < Vin < VCC
I
I
out = 700 µA
out = -150 µA
–
–
Table 24
Parameter
Flash/EEPROM Interface DC Specifications
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Input LOW Voltage
Input HIGH Voltage
Input Leakage Current
Output LOW Voltage
Vilf
Vihf
Iif
0
–
–
–
–
0.3 VCC
V
V
µA
V
–
–
–
–
0.7 VCC
?
–
V
CC + 1
?
0.2
Volf
Data Sheet
101
Rev. 1.51, 2005-11-30
AN985B/BX
Electrical Specifications and Timings
Table 24
Flash/EEPROM Interface DC Specifications (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
Max.
Output HIGH Voltage
Input Pin Capacitance
Vohf
Cinf
V
?
CC - 0.2
–
–
–
?
V
pF
–
–
9.3
AC Specifications
Table 25
PCI Signaling AC Specifications for 3.3 V
Parameter
Symbol
Min.
Values
Typ.
Unit
Note / Test Condition
Max.
Switching Current High
Switching Current Low
Slew Rate
Unloaded Output Rise Time
Unloaded Output Fall Time
I
oh (AC)
–
–
0.25
1
1
4
6
–
–
–
–
–
1
4
4
mA
mA
V/ns
V/ns
V/ns
–
–
–
Iol (AC)
–
Tr
Tf
0.2 VCC ~ 0.6 VCC
0.6 VCC ~ 0.2 VCC
9.4
Timing Specifications
Table 26
Parameter
PCI Clock Specifications
Symbol
Values
Unit
Note / Test Condition
Min.
30
12
12
1
Typ.
Max.
Clock Cycle Time
Clock High Time
Clock Low Time
Clock Slew Rate
Tcyc
Thigh
Tlow
–
–
–
–
–
–
–
–
4
ns
ns
ns
V/ns
–
–
–
–
Data Sheet
102
Rev. 1.51, 2005-11-30
AN985B/BX
Electrical Specifications and Timings
0.6vcc
Thigh
0.4Vcc
Tlow
0.2Vcc
Tcyc
Figure 17 PCI Clock Waveform
Table 27
PCI Timings
Parameter
Symbol
Values
Typ.
–
–
–
–
–
Unit
Note / Test Condition
Min.
Max.
11
12
–
28
–
Access time – bused signals
Access time – point to point
Float to Active Delay
Active to Float Delay
Input Set up Time to Clock –
bused signals
Tval
2
2
2
–
7
ns
ns
ns
ns
ns
–
–
–
–
–
T
val (ptp)
Ton
Toff
Tsu
Input Set up Time to Clock –
point to point
T
su (ptp)
10, 12
–
–
ns
–
Input Hold Time from Clock
Reset Active Time after Power Trst
Stable
Th
0
1
–
–
–
–
ns
ms
–
–
Reset Active Time after CLK
Stable
Reset Active to Output Float
delay
Trst-clk
100
–
–
–
–
µs
–
–
Trst-off
40
ns
Data Sheet
103
Rev. 1.51, 2005-11-30
AN985B/BX
Electrical Specifications and Timings
CLK
1.5Vcc
Vth=2.4Vcc
Vtl=0.4Vcc
Tval (max=11ns)
OUTPUT Delay
Tri-state OUTPUT
Ton
Toff
Tsu
Th
INPUT
1.5V
1.5V
Figure 18 PCI Timings
Table 28
Parameter
Flash Interface Timings
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
90
–
–
–
0
0
–
–
Max.
–
90
90
45
–
Read cycle time
Trc
–
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
–
–
–
–
–
–
–
–
–
Chip enable access time
Address access time
Output enable access time
CE low to active output
OE low to active output
CE high to active output
OE high to active output
Tce
Taa
Toe
Tclz
Tolz
Tchz
Tohz
Toh
–
45
45
–
Output hold from address
change
0
Write cycle time
Twc
Tas
Tah
Tcs
Tch
Toes
Toeh
–
0
50
0
0
–
–
–
–
–
–
–
10
–
–
–
–
ms
ns
ns
ns
ns
ns
ns
–
–
–
–
–
–
–
Address setup time
Address hold time
WE and CE setup time
WE and CE hold time
OE high setup time
OE high hold time
10
10
–
–
Data Sheet
104
Rev. 1.51, 2005-11-30
AN985B/BX
Electrical Specifications and Timings
Table 28
Flash Interface Timings (cont’d)
Parameter
Symbol
Values
Typ.
Unit
Note / Test Condition
Min.
70
70
150
50
10
Max.
–
–
–
–
–
200
–
CE pulse width
WE pulse width
WE high width
Data setup time
Data hold time
Byte load cycle time
Byte load cycle time out
Tcp
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
µs
µs
–
–
–
–
–
–
–
Twp
Twph
Tds
Tdh
Tblc
Tblco
0.22
300
ADDRESS
Tas
Tah
Tfasc
Tcs
CS#
Twp
Twph
WE#
Tds
Tdh
DATA
Figure 19 Flash Write Timings
Data Sheet
105
Rev. 1.51, 2005-11-30
AN985B/BX
Electrical Specifications and Timings
ADDRESS
Trc
CS#
OE#
Tce
Toe
Toh
DATA
Figure 20 Flash Read Timings
Table 29
EEPROM Interface Timings (AC/AD)
Parameter
Symbol
Min.
Values
Typ.
Unit
Note / Test Condition
Max.
Serial Clock Frequency
Tscf
–
–
0.4M/
0.1M
Hz
2.7 V < VCC < 5.5 V
Delay from CS High to SK High Tecss
Delay from SK Low to CS Low Tecsh
160/640
1120/
4480
–
–
–
–
ns
ns
2.7 V < VCC < 5.5 V
2.7 V < VCC < 5.5 V
Setup Time of DI to SK
Hold Time of DI after SK
Tedts
Tedth
160/640
2320/
9280
–
–
–
–
ns
ns
2.7 V < VCC < 5.5 V
2.7 V < VCC < 5.5 V
CS Low Time
Tecsl
7400/
29600
–
–
ns
2.7 V < VCC < 5.5 V
Data Sheet
106
Rev. 1.51, 2005-11-30
AN985B/BX
Electrical Specifications and Timings
CS
Tecss
Tecsh
Tecsl
CLK
Tedts
Tedth
DI
Figure 21 Serial EEPROM Timing
Data Sheet
107
Rev. 1.51, 2005-11-30
AN985B/BX
Package Outlines
10
Package Outlines
Figure 22 Package Outline for the AN985B/BX
Table 30
Dimensions for 128 -pin LQFP Package (AN985B/BX)
Symbol Description
Minimum Maximum
- 1.6 mm
A
Overall Height
A1
b
c
Stand Off
Lead Width
Lead Thickness
0.05 mm 0.15 mm
0.17 mm 0.27 mm
0.13 mm 0.23 mm
D
D1
E
Terminal Dimension 1 21.9.0 mm 22.1 mm
Package Body 1 19.9 mm 20.1 mm
Terminal Dimension 2 15.9 mm 16.1 mm
E1
e1
L1
T
Package Body 2
Lead Pitch
Foot Length
Lead Angle
Coplanarity
13.9 mm 14.1 mm
0.50 mm
0.45 mm 0.75 mm
-
0°
7°
Y
0.076 mm
Data Sheet
108
Rev. 1.51, 2005-11-30
AN985B/BX
Appendix
11
Appendix
11.1
MII Management Access Procedure
Read Management Data From Phyter
1. Write CSR9[18]=1 to let Mdio become input mode.
2. Write CSR9[16] according to the IEEE802.3u spec to generate the MII management clock.
3. Read CSR9[19] with reference the MII management clock.
Write Management Data From Phyter
1. Write CSR9[18]=1 to let Mdio become output mode.
2. Write CSR9[16] according to the IEEE802.3u spec to generate the MII management clock.
3. Write CSR9[19] with reference the MII management clock.
11.2
Debugging Purpose Registers: Offset FCH
MAC(HOME/PNA), MODE/SET FCH[2:0]=100B
MDC:bra11
TXEN:bra10
TXD[3:0]:bra[9:6]
TXER:bra5
MDIO:bra3
RXDV:brd4
CRS:bra2
RXD[2:0]:brd[3:0]
COL:bra1
RXER:bra0
RXCLK:brwe_
RXCLK:broe_
PHY MINITOR MODE/SET FCH[2:0]=110B
bra[16:0]=rxd[3:0], crs, col, rx_clk, rx_dv, rx_er, rx_clk,txd[3:0], tx_er, tx_en, mdi
brd[7:6]=mdo, mdc
PHY ONLY MODE/SET FCH[2:0]=001B
bra[16:9]=rxd[3:0], csr, col,rx_er, rx_dv
brd[7:0]=mdc, mdio, tx_er, tx_en, txd[3:0]
broez=rx_clk
brwez=tx_clk
11.3
EEPROM DATA TABLE
Data Sheet
109
Rev. 1.51, 2005-11-30
AN985B/BX
Appendix
Table 31
Offset
08H
EEPROM DATA TABLE
b15------------------------------------------------b8 b7------------------------------------------------------------b0
PHY ADDR 00
PHY ADDR 01
PHY ADDR 10
0AH
0CH
16H
[b15~b4]=csr_MISC_control(offset f8H[15:4])
[b3~b0]=CSR15[31:28]
20H
22H
Device ID
Vendor ID
24H
Subsystem ID
26H
Subsystem Vendor ID
28H
MaxLat
MinGnt
2AH
2CH
LAN CISL
LAN CISH
2EH
CSR18_REG
30H~3FH
40H
PWRDATA1HB(LAN D0)
PWRDATA1LB(LAN D321)
42H~51H
52H
54H~7FH
80H~13FH
140H~1FFH
CARDBUS CIS word count(<128)
CARDBUS CIS DATA(192 Words)
Data Sheet
110
Rev. 1.51, 2005-11-30
AN985B/BX
References
References
[1]
[2]
[3]
[4]
[5]
[6]
Data Sheet
111
Rev. 1.51, 2005-11-30
w w w . i n f i n e o n . c o m
Published by Infineon Technologies AG
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