AFL2814DY [INFINEON]
DC-DC Regulated Power Supply Module, 2 Output, 100W, Hybrid;
| 型号： | AFL2814DY |
| 厂家： | 
Infineon |
| 描述： | DC-DC Regulated Power Supply Module, 2 Output, 100W, Hybrid |
| 文件： | 总12页 (文件大小：212K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AFL2800D Series
Dual Output, Hybrid - High Reliability
DC/DC Converters
DESCRIPTION
FEATURES
TheAFLSeriesofDC/DCconvertersfeaturehighpowerdensity
with no derating over the full military temperature range. This
series is offered as part of a complete family of converters
providing single and dual output voltages and operating from
nominal+28or+270voltinputswithoutputpowerrangingfrom
80to120watts. Forapplicationsrequiringhigheroutputpower,
individual converters can be operated in parallel. The internal
current sharing circuits assure accurate current distribution
amongtheparalleledconverters.ThisseriesincorporatesLambda
Advanced Analog’s proprietary magnetic pulse feedback
technologyprovidingoptimumdynamiclineandloadregulation
response. This feedback system samples the output voltage at
thepulsewidthmodulatorfixedclockfrequency,nominally550
KHz.Multipleconverterscanbesynchronizedtoasystemclock
inthe500KHzto700KHzrangeortothesynchronizationoutput
ofoneconverter. Undervoltagelockout,primaryandsecondary
referencedinhibit,soft-startandloadfaultprotectionareprovided
on all models.
n 16To40VoltInputRange
n ±5,±12,and±15VoltOutputsAvailable
3
n High Power Density - up to 70 W / in
n UpTo100WattOutputPower
n ParallelOperationwithPowerSharing
n LowProfile(0.380")SeamWeldedPackage
n CeramicFeedthruCopperCorePins
n High Efficiency - to 85%
n FullMilitaryTemperatureRange
n ContinuousShortCircuitandOverloadProtection
n OutputVoltageTrim
n PrimaryandSecondaryReferencedInhibitFunctions
n Line Rejection> 40dB -DC to50Khz
n ExternalSynchronizationPort
These converters are hermetically packaged in two enclosure
variations, utilizing copper core pins to minimize resistive DC
losses. Three lead styles are available, each fabricated with
Lambda Advanced Analog’s rugged ceramic lead-to-package
seal assuring long term hermeticity in the most harsh
environments.
n FaultTolerantDesign
n SingleOutputVersionsAvailable
n StandardMicrocircuitDrawingsAvailable
Manufactured in a facility fully qualified to MIL-PRF-38534,
theseconvertersareavailableinfourscreeninggradestosatisfy
a wide range of requirements. The CH grade is fully compliant
totherequirementsofMIL-H-38534forclassH. TheHBgrade
is processed and screened to the class H requirement, but may
notnecessarilymeetalloftheotherMIL-PRF-38534requirements,
e.g.,elementevaluationandPeriodicInspections(PI)notrequired.
Both grades are tested to meet the complete group “A” test
specification over the full military temperature range without
outputpowerderation. Twogradeswithmorelimitedscreening
are also available for use in less demanding applications.
Variations in electrical, mechanical and screening can be
accommodated. ContactLambdaAdvancedAnalogwithspecific
requirements.
SPECIFICATIONS
AFL28XXD
ABSOLUTE MAXIMUM RATINGS
Input Voltage
-0.5V to 50V
300°C for 10 seconds
Soldering Temperature
Case Temperature
Operating
Storage
-55°C to +125°C
-65°C to +135°C
Static Characteristics -55°C ≤ T
≤ +125°C, 160 ≤ V ≤ 400 unless otherwise specified.
CASE
IN
Group A
Subgroup
Parameter
Test Conditions
Min
Nom
28
Max
Unit
V
INPUT VOLTAGE
Note 6
16
40
OUTPUT VOLTAGE
Vin = 28 Volts, 100% Load
AFL2805D
1
1
1
1
1
1
Positive Output
Negative Output
Positive Output
Negative Output
Positive Output
Negative Output
4.95
-5.05
11.88
-12.12
14.85
-15.15
5
-5
12
-12
15
-15
5.05
-4.95
12.12
-11.88
15.15
-14.85
V
V
V
V
V
V
AFL2812D
AFL2815D
AFL2805D
AFL2812D
AFL2815D
2,3
2,3
2,3
2,3
2,3
2,3
Positive Output
Negative Output
Positive Output
Negative Output
Positive Output
Negative Output
4.90
-5.10
11.76
-12.24
14.70
-15.30
5.10
-4.90
12.24
-11.76
15.30
-14.70
V
V
V
V
V
V
OUTPUT CURRENT
OUTPUT POWER
Vin = 16, 28, 40 Volts-Note 6, 11
AFL2805D
AFL2812D
AFL2815D
Either Output
Either Output
Either Output
12.8
6.4
5.3
A
A
A
Total of Both Outputs. Note 6, 11
AFL2805D
AFL2812D
AFL2815D
80
96
100
W
W
W
MAXIMUM CAPACITIVE LOAD
Each Output Note 1
10,000
-0.015
ufd
OUTPUT VOLTAGE
Vin = 28 Volts, 100% Load-Note 1,6
+0.015
%/°C
TEMPERATURE COEFFICIENT
OUTPUT VOLTAGE REGULATION
Note 10
Line
Load
1,2,3
1,2,3
No Load, 50% Load, 100% Load
Vin = 16, 28, 40 Volts
-0.5
-1.0
+0.5
+1.0
%
%
Vin = 16, 28, 40 Volts. Note 12
Cross
AFL2805D
1,2,3
1,2,3,
1,2,3
Positive Output
Negative Output
Positive Output
Negative Output
Positive Output
Negative Output
-1.0
-8.0
-1.0
-5.0
-1.0
-5.0
+1.0
+8.0
+1.0
+5.0
+1.0
+5.0
%
%
%
%
%
%
AFL2812D
AFL2815D
OUTPUT RIPPLE VOLTAGE
Vin = 16, 28, 40 Volts, 100% Load,
BW = 10MHz
AFL2805D
AFL2812D
AFL2815D
1,2,3
1,2,3
1,2,3
60
80
80
mVpp
mVpp
mVpp
2
Static Characteristics (continued)
Group A
Subgroup
Parameter
Test Conditions
Vin = 28 Volts
Iout = 0
Min
Nom
Max
Unit
INPUT CURRENT
No Load
1
2,3
1,2,3
1,2,3
1,2,3
1,2,3
80
100
5
5
50
30
mA
mA
mA
mA
mA
mA
Inhibit 1
Inhibit 2
AFL2805D
Pin 4 Shorted to Pin 2
Pin 12 Shorted to Pin 8
AFL2812D, 15D
INPUT RIPPLE CURRENT
Vin = 28 Volts, 100% Load
BW = 10MHz
AFL2805D
AFL2812D
AFL2815D
1,2,3
1,2,3
1,2,3
60
60
60
mApp
mApp
mApp
CURRENT LIMIT POINT
Vout - 90% Vnom, Current split equally
on positive and negative outputs. Note 5
1
2
3
115
105
125
125
115
140
%
%
%
Expressed as a Percentage
of Full Rated Load
LOAD FAULT POWER DISSIPATION
Overload or Short Circuit
1,2,3
Vin = 28 Volts
33
W
EFFICIENCY
Vin = 28 Volts, 100% Load
AFL2805D
AFL2812D
AFL2815D
1,2,3
1,2,3
1,2,3
78
80
81
81
84
85
%
%
%
ENABLE INPUTS (Inhibit Function)
Converter Off
Sink Current
1,2,3
1,2,3
Logical Low, Pin 4 or Pin 12
Note 1
Logical High, Pin 4 and Pin 12-Note 9
Note 1
-0.5
2.0
0.8
100
50
V
uA
V
Converter On
Sink Current
100
uA
SWITCHING FREQUENCY
1,2,3
500
550
600
KHz
SYNCHRONIZATION INPUT
Frequency Range
1,2,3
1,2,3
1,2,3
500
2.0
-0.5
700
10
0.8
100
80
KHz
V
V
nSec
%
Pulse Amplitude, Hi
Pulse Amplitude, Lo
Pulse Rise Time
Note 1
Note 1
Pulse Duty Cycle
20
ISOLATION
1
Input to Output or Any Pin to Case
(except Pin 3). Test @ 500VDC
100
M
Ω
DEVICE WEIGHT
MTBF
Slight Variations with Case Style
85
gms
MIL-HDBK-217, AIF @ Tc = 70°C
300
KHrs
3
Dynamic Characteristics -55°C≤ T
≤
+125°C, V = 28 Volts unless otherwise specified.
IN
CASE
Group A
Subgroups
Parameter
Test Conditions
Min
Nom
Max
Unit
LOAD TRANSIENT RESPONSE
AFL2805D
Note 2, 8
Positive Output Amplitude
Recovery
4,5,6
4,5,6
Load Step 50% <=> 100%
-450
-450
450
200
mV
uSec
Amplitude
Recovery
4,5,6
4,5,6
Load Step 10% <=> 50%
10% => 50%
50% => 10%
450
200
400
mV
uSec
uSec
AFL2805D
Negative Output Amplitude
Recovery
4,5,6
4,5,6
Load Step 50% <=> 100%
-450
-450
450
200
mV
uSec
Amplitude
Recovery
4,5,6
4,5,6
Load Step 10% <=> 50%
10% => 50%
50% => 10%
450
200
400
mV
uSec
uSec
AFL2812D
Positive Output Amplitude
Recovery
4,5,6
4,5,6
Load Step 50% <=> 100%
-750
-750
750
200
mV
uSec
Amplitude
Recovery
4,5,6
4,5,6
Load Step 10% <=> 50%
10% => 50%
50% => 10%
750
200
400
mV
uSec
uSec
AFL2812D
Negative Output Amplitude
Recovery
4,5,6
4,5,6
Load Step 50% <=> 100%
-750
-750
750
200
mV
uSec
Amplitude
Recovery
4,5,6
4,5,6
Load Step 10% <=> 50%
10% => 50%
50% => 10%
750
200
400
mV
uSec
uSec
AFL2815D
Positive Output Amplitude
Recovery
4,5,6
4,5,6
Load Step 50% <=> 100%
-750
-750
750
200
mV
uSec
Amplitude
Recovery
4,5,6
4,5,6
Load Step 10% <=> 50%
10% => 50%
50% => 10%
750
200
400
mV
uSec
uSec
AFL2815D
Negative Output Amplitude
Recovery
4,5,6
4,5,6
Load Step 50% <=> 100%
-750
-750
750
200
mV
uSec
Amplitude
Recovery
4,5,6
4,5,6
Load Step 10% <=> 50%
10% => 50%
50% => 10%
750
200
400
mV
uSec
uSec
LINE TRANSIENT RESPONSE
Note 1,2,3
Amplitude
Recovery
Vin Step = 16 <=> 40 Volts
-500
500
500
mV
uSec
TURN-ON CHARACTERISTICS
Note 4
Overshoot
Delay
4,5,6
4,5,6
Enable 1,2 on. (Pins 4, 12 high or open)
250
10
mV
mSec
0
4
LOAD FAULT RECOVERY
LINE REJECTION
Same as Turn On Characteristics.
MIL-STD-461D, CS101, 30Hz to 50KHz
Note 1
40
50
dB
Notes to Specifications:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Parameters not 100% tested but are guaranteed to the limits specified in the table.
Recovery time is measured from the initiation of the transient to where V
Line transient transition time ≥ 100 µSec.
has returned to within ±1% of V
at 50% load.
OUT
OUT
Turn-on delay is measured with an input voltage rise time of between 100 and 500 volts per millisecond.
Current limit point is that condition of excess load causing output voltage to drop to 90% of nominal.
Parameterverifiedaspartofanothertest.
All electrical tests are performed with the remote sense leads connected to the output leads at the load.
Load transient transition time ≥ 10 µSec.
Enableinputsinternallypulledhigh. Nominalopencircuitvoltage≈4.0VDC.
10. Loadcurrentsplitequallybetween+V and-V
.
out out
11. Output load must be distributed so that a minimum of 20% of the total output power is being provided by one of the outputs.
12. Cross regulation measured with load on tested output at 20% while changing the load on other output from 20% to 80%.
AFL2800D Case Outlines
Case X
Case W
Pin Variation of Case Y
0.050
3.000
2.760
ø 0.128
0.050
0.250
1.000
0.250
1.000
Ref
1.260 1.500
0.200 Typ
Non-cum
Pin
ø 0.040
Pin
ø 0.040
0.220
0.220
2.500
2.800
0.525
2.975 max
0.238 max
0.42
0.380
Max
0.380
Max
Case Y
Case Z
Pin Variation of Case Y
0.050
1.150
0.300
ø
0.140
0.25 typ
0.050
0.250
0.250
1.000
Ref
1.000
Ref
1.500 1.750 2.00
0.200 Typ
Non-cum
Pin
0.040
Pin
ø
ø
0.040
0.220
0.220
0.36
1.750
2.500
0.375
2.800
2.975 max
0.525
0.238 max
0.380
Max
0.380
Max
Tolerances, unless otherwise specified: .XX =
.XXX =
±
±
0.010
0.005
AFL2800D Pin Designation
PPiinn NNoo..
Pin No.
DDeessiiggnnaattiioonn
Designation
1
2
Positive Input
Input Return
Case
3
4
Enable 1
5
Sync Output
Sync Input
6
7
Positive Output
Output Return
Negative Output
Output Voltage Trim
Share
8
9
10
11
12
Enable 2
Available Screening Levels and Process Variations for AFL2800D Series.
MIL-STD-883
Method
No
Suffix
ES
Suffix
HB
Suffix
CH
Suffix
Requirement
Temperature Range
Element Evaluation
Internal Visual
-20 to +85°C
*
-55°C to +125°C -55°C to +125°C -55°C to +125°C
MIL-PRF-38534
2017
1010
2001
1015
Yes
Cond B
500g
Yes
Cond C
Yes
Cond C
Temperature Cycle
Constant Acceleration
Burn-in
Cond A
Cond A
96hrs @ 125°C
96hrs @ 125°C
25°C
160hrs @ 125°C
160hrs @ 125°C
Final Electrical (Group A) MIL-PRF-38534
25°C
-55, +25, +125°C -55, +25, +125°C
Seal, Fine & Gross
External Visual
1014
2009
*
*
Cond A, C
Yes
Cond A, C
Yes
Cond A, C
Yes
*
Per Commercial Standards
Part Numbering
AFL 28 05 D X / CH
Model
Screening
–
,
ES
Input Voltage
Case Style
W, X, Y, Z
HB, CH
28 = 28V
270 = 270V
Output Voltage
05 = 5V, 12 = 12V,
15 = 15V
Outputs
S = Single
D = Dual
6
AFL2800D Circuit Description
Figure I. AFL Dual Output Block Diagram
Input
Filter
Output
Filter
1
4
+ Output
DC Input
Enable 1
7
Current
Sense
Primary
Bias Supply
Output Return
-Output
8
9
Output
Filter
Sync Output
5
Share
Amplifier
Control
Share
11
Error
Amp
& Ref
Sync Input
Case
6
3
2
12 Enable 2
Trim
10
Input Return
Circuit Operation and Application Information
Althoughincorporatingseveralsophisticatedanduseful
ancillary features, basic operation of the AFL2800D
series can be initiated by simply applying an input
voltage to pins 1 and 2 and connecting the appropriate
loads between pins 7, 8, and 9. Of course, operation of
any converter with high power density should not be
attempted before secure attachment to an appropriate
heat dissipator. (See Thermal Considerations, page 9)
The AFL series of converters employ a forward switched
mode converter topology. (refer to Figure I.) Operation of
the device is initiated when a DC voltage whose magnitude
is within the specified input limits is applied between pins 1
and 2. If pins 4 and 12 are enabled (at a logical 1 or open)
the primary bias supply will begin generating a regulated
housekeeping voltage bringing the circuitry on the primary
side of the converter to life. Two power MOSFETs used to
chop the DC input voltage into a high frequency square
wave, apply this chopped voltage to the power transformer.
As this switching is initiated, a voltage is impressed on a
second winding of the power transformer which is then
rectified and applied to the primary bias supply. When this
occurs, the input voltage is excluded from the bias voltage
generator and the primary bias voltage becomes internally
generated.
Inhibiting Converter Output
As an alternative to application and removal of the DC
voltage to the input, the user can control the converter
output by providing TTL compatible, positive logic
signals to either of two enable pins (pin 4 or 12). The
distinction between these two signal ports is that enable
1 (pin 4) is referenced to the input return (pin 2) while
enable 2 (pin 12) is referenced to the output return (pin
8). Thus, the user has access to an inhibit function on
either side of the isolation barrier.
The switched voltage impressed on the secondary output
transformer windings is rectified and filtered to provide the
positive and negative converter output voltages. An error
amplifieronthesecondarysidecomparesthepositiveoutput
voltage to a precision reference and generates an error signal
proportional to the difference. This error signal is magneti-
cally coupled through the feedback transformer into the
control section of the converter varying the pulse width of
thesquarewavesignaldrivingtheMOSFETs,narrowingthe
pulse width if the output voltage is too high and widening it
if it is too low. These pulse width variations provide the
necessary corrections to maintain the magnitude of output
voltage within its’ specified limits.
Figure II. Enable Input Equivalent Circucuit
+5.6V
100K
1N4148
Pin 4 or
Pin 12
Disable
290K
2N3904
150K
Pin 2 or
Pin 8
Because the primary and secondary sides are coupled by
magnetic elements, full isolation from input to output is
achieved.
7
designated as the master oscillator provides a conve-
nient frequency source for this mode of operation.
When external synchronization is not indicated, the
sync in pin should be left unconnected thereby permit-
ting the converter to operate at its’ own internally set
frequency.
The sync output signal is a continuous pulse train set at
550 ±50 KHz, with a duty cycle of 15 ±5%. This signal is
referenced to the input return and has been tailored to be
compatiblewiththeAFLsyncinputport. Transitiontimes
are less than 100 ns and the low level output impedance is
less than 50 ohms. This signal is active when the DC input
voltage is within the specified operating range and the
converter is not inhibited. The sync output has adequate
drive reserve to synchronize at least five additional con-
verters. A typical connection is illustrated in Figure III.
Each port is internally pulled “high” so that when not used,
an open connection on both enable pins permits normal
converter operation. When their use is desired, a logical
“low”oneitherportwillshuttheconverterdown. Internally,
these ports differ slightly in their operation. In use, a low on
Enable 1 completely shuts down all circuits in the converter,
whilealowonEnable2shutsdownthesecondarysidewhile
alteringthecontrollerdutycycletonearzero.Externally,the
use of either port is transparent to the user save for minor
differences in idle current. (See specification table).
Synchronization of Multiple Converters
When operating multiple converters, system requirements
often dictate operation of the converters at a common
frequency. To accommodate this requirement, the AFL
series converters provide both a synchronization input and
synchronization output.
Parallel Operation — Current and Stress Sharing
Figure III. illustrates the preferred connection scheme for
operation of a set of AFL converters with outputs operat-
ing in parallel. Use of this connection permits equal
The sync input port permits synchronization of an AFL
converter to any compatible external frequency source
operating between 500 and 700 KHz. This input signal
FigureIII.PreferredConnectionforParallelOperation
1
12
Power
Input
Enable 2
Vin
Rtn
Share
Trim
Case
Enable
AFL
1
-
Output
Return
Output
Sync Out
Sync In
+
7
6
1
Optional
Synchronization
Connection
Share Bus
12
Enable
2
Vin
Rtn
Share
Trim
Case
AFL
Enable
1
-
Output
Return
Output
to Negative Load
to Positive Load
Sync Out
Sync In
+
7
6
1
12
Enable
2
Vin
Rtn
Share
Trim
Case
AFL
Enable
1
-
Output
Return
Output
Sync Out
Sync In
+
6
7
(Other Converters)
current sharing among the members of a set whose load
current exceeds the capacity of an individual AFL. An
importantfeatureoftheAFLseriesoperatingintheparallel
mode is that in addition to sharing the current, the stress
induced by temperature will also be shared. Thus if one
should be referenced to the input return and have a
10% to 90% duty cycle. Compatibility requires
transition times less than 100 ns, maximum low level of
+0.8 volts and a minimum high level of +2.0 volts. The
sync output of another converter which has been
8
provide similar effectiveness, these alternatives are
often less convenient and are frequently messy to
use.
A conservative aid to estimating the total heat sink
surface area (AHEAT SINK) required to set the
maximum case temperature rise (∆T) above ambi-
enttemperatureisgivenbythefollowingexpression:
member of a paralleled set is operating at a higher case
temperature, the current it provides to the load will be
reduced as compensation for the temperature induced
stress on that device.
When operating in the shared mode, it is important that
symmetry of connection be maintained as an assurance of
optimum load sharing performance. Thus, converter
outputs should be connected to the load with equal lengths
of wire of the same gauge and should be connected to a
common physical point, preferably at the load along with
the converter return leads. All converters in a paralleled set
must have their share pins connected together. This
arrangement is diagrammatically illustrated in Figure III.
showing the output and return pins connected at a star point
which is located close as possible to the load.
−1.43
∆T
A
HEAT SINK
≈
− 3.0
80P0.85
where ∆T = case temperature rise above ambient,
1
Pout
−1
P = device dissipation in watts =
Eff
As an example, assume that it is desired to operate
an AFL2815D while maintaining the case tempera-
ture at TC ≤ +85°C in an area where the ambient
temperature is held to a constant +25°C; then
∆T = 85 - 25 = 60°C.
As a consequence of the topology utilized in the current
sharing circuit, the share pin may be utilized in other
functions. For applications requiring only a single con-
verter, the voltage appearing on the share pin may be used
as a “total current monitor”. The share pin open circuit
voltageisnominally+1.00vatnoloadandincreaseslinearly
with increasing total output current to +2.20v at full load.
Note that the current we refer to here is the total device
output current, that is, the sum of the positive and negative
output currents.
From the Specification Table, the worst case full
load efficiency for this device is 83% @ 100W; thus
the power dissipation at full load is given by
1
P = 100•
−1 = 100• 0.205 = 20.5W
(
)
Thermal Considerations
.83
Because of the incorporation of many innovative techno-
logical concepts, the AFL series of converters is capable of
providing very high output power from a package of very
small volume. These magnitudes of power density can only
be obtained by combining high circuit efficiency with
effective methods of heat removal from the die junctions.
This requirement has been effectively addressed inside the
device; but when operating at maximum loads, a significant
amount of heat will be generated and this heat must be
conducted away from the case. To maintain the case
temperature at or below the specified maximum of 125°C,
this heat must be transferred by conduction to an appropri-
ateheatdissipaterheldinintimatecontactwiththeconverter
base-plate.
and the required heat sink area is
−1.43
60
A
HEAT SINK
=
− 3.0 = 56.3 in2
80• 20.50.85
Thus, a total heat sink surface area (including fins,
if any)of56in2 inthisexample,wouldlimitcaserise
to60°Caboveambient. Aflataluminumplate,0.25"
2
thick and of approximate dimension 4" by 7" (28 in
per side) would suffice for this application in a still
airenvironment. Notethattomeetthecriteriainthis
example, both sides of the plate require unrestricted
exposure to the +25°C ambient air.
Since the effectiveness of this heat transfer is dependent on
theintimacyofthebaseplate-heatsinkinterface,itisstrongly
recommended that a high thermal conductivity heat trans-
ferring medium is inserted between the baseplate and
heatsink. The material most frequently utilized at the
factory during all testing and burn-in processes is sold
under the trade name of Sil-PadR 4001 . This particular
product is an insulator but electrically conductive versions
are also available. Use of these materials assures maximum
surface contact with the heat dissipater thereby compensat-
ing for any minor surface variations. While other available
types of heat conductive materials and thermal compounds
Input Filter
The AFL 2800D series converters incorporate a
singlestageLCinputfilterwhoseelementsdominate
the input load impedance characteristic during the
turn-on sequence. The input circuit is as shown in
Figure IV.
1
Sil-Pad is a registered Trade Mark of Bergquist, Minneapolis, MN
9
Figure IV. Input Filter Circuit
Note that the nominal magnitude of output voltage resides in
the middle of the table and the corresponding resistor value
is set to α. To set the magnitude above nominal, the adjust
resistor is connected to output return. To set the magnitude
below nominal, the adjust resistor is connected to the
positive output. (Refer to Figure V.)
900nH
130nH
Pin 1
Pin 2
6
µfd
11.2 µfd
Figure V. Connection for Vout Adjustment
12
Enable
2
Undervoltage Lockout
Share
Trim
R ADJ
Aminimumvoltageisrequiredattheinputoftheconverter
toinitiateoperation. Thisvoltageissetto14.0± 5volts. To
preclude the possibility of noise or other variations at the
input falsely initiating and halting converter operation, a
hysteresis of approximately 10 volts is incorporated in this
circuit. Thus if the input voltage droops to 13.0 ± 5 volts,
the converter will shut down and remain inoperative until
the input voltage returns to »140 volts.
-
+
AFL28xxD
-
Vout
To
Loads
Return
+
Vout
7
Connect Radj to + to increase, - to decrease.
Output Voltage Adjust
For output voltage settings that are within the limits, but
between those presented in Table I, it is suggested that the
resistor values be determined empirically by selection or by
use of a variable resistor. The value thus determined can
then be replaced with a good quality fixed resistor for
permanentinstallation.
By use of the trim pin (10), the magnitude of output
voltages can be adjusted over a limited range in either a
positive or negative direction. Connecting a resistor
between the trim pin and either the output return or the
positive output will raise or lower the magnitude of output
voltage. Thespanofoutputvoltagemagnitudeisrestricted
to the limits shown in Table I.
When use of the trim feature is elected, the user should be
aware that the temperature performance of the converter
output voltage will be affected by the temperature perfor-
mance of the resistor selected as the adjustment element and
therefore, the user is advised to employ resistors with an
very small temperature coefficient of resistance.
Table I. Output Voltage Trim Values and Limits
AFL2805D
Vout Radj
5.5
AFL2812D
Vout Radj
AFL2815D
Vout Radj
General Application Information
0
12.5
12.4
12.3
12.2
12.1
12.0
11.7
0
15.5
15.4
15.3
15.2
15.1
15.0
14.6
14.0
13.5
13.0
12.917
0
The AFL2800 series of converters are capable of providing
large transient currents to user loads on demand. Because
thenominalinputvoltagerangeinthisseriesisrelativelylow,
the resulting input current demands will be correspondingly
large. It is important therefore, that the line impedance be
kept very low to prevent steady state and transient input
currents from degrading the supply voltage between the
voltage source and the converter input. In applications
requiring high currents and large transients, it is recom-
mended that the input leads are of adequate size to minimize
resistive losses. It is also recommended that a good quality
capacitor of approximately 100µfd be connected directly
across the input terminals to assure an adequately low
dynamic impedance at the input. Table I relates nominal
resistance values for selected wire sizes.
5.4
5.3
12.5K
33.3K
75K
200K
∞
47.5K
127K
285K
760K
∞
62.5K
167K
375K
1.0M
∞
5.2
5.1
5.0
4.9
190K
65K
23K
2.5K
0
975K
288K
72.9K
29.9K
0
1.2M
325K
117K
12.5K
0
4.8
11.3
4.7
10.8
10.6
10.417
4.6
4.583
10
Table I. Nominal Resistance Of Cu Wire
reduced to 25% or 31% of that with 20 gauge wire.
Another potential problem resulting from parasitically
induced voltage drop on the input lines is with regard to
the operation of the enable 1 port. The minimum and
maximum operating levels required to operate this port
are specified with respect to the input common return
line at the converter. If a logic signal is generated with
respect to a ‘common’ that is distant from the con-
verter, the effects of the voltage drop over the return line
must be considered when establishing the worst case
TTL switching levels. These drops will effectively
impart a shift to the logic levels. In Figure VI, it can be
seen that referred to system ground, the voltage on the
input return pin is given by
Wire Size, AWG
Resistance per ft
24 Ga
22 Ga
20 Ga
18 Ga
16 Ga
14 Ga
12 Ga
25.7 mΩ
16.2 mΩ
10.1 mΩ
6.4 mΩ
4.0 mΩ
2.5 mΩ
1.6 mΩ
As an example of the effects of parasitic resistance,
consider an AFL2815D operating at full power of 100
W. From the specification sheet, this device has a
minimum efficiency of 83% which represents an input
power of more than 120 W. If we consider the case
where line voltage is at its’ minimum of 16 volts, the
steady state input current necessary for this example
will be slightly greater than 7.5 amperes. If this device
were connected to a voltage source with 10 feet of 20
gauge wire, the round trip (input and return) would
result in 0.2Ω of resistance and 1.5 volts of drop from
the source to the converter. To assure 16 volts at the
input, a source closer to 18 volts would be required. In
applicationsusingtheparallelingoption,thisdropwillbe
multiplied by the number of paralleled devices. By
choosing 14 or 16 gauge wire in this example, the
parasitic resistance and resulting voltage drop will be
eRtn = IRtn • RP
Therefore, the logic signal level generated in the system
must be capable of a TTL logic high plus sufficient
additional amplitude to overcome eRtn. When the con-
verter is inhibited, IRtn diminishes to near zero and eRtn
will then be at system ground.
Incorporation of a 100 µfd capacitor at the input
terminals is recommended as compensation for the
dynamic effects of the parasitic resistance of the
input cable reacting with the complex impedance of
the converter input, and to provide an energy reser-
voir for transient input current requirements.
Figure VI. Effects of Parasitic Resistance in Input Lead
R p
Iin
Vin
100
µfd
e s o u r c e
Rtn
e Rt n
IRt n
R p
Case
Enable 1
Sync Out
Sync In
System Ground
11
AFL2800D to Standard Microcircuit Equivalence Table
AFL2805D
AFL2812D
AFL2815D
5962-95795*
5962-95796*
5962-94724*
Ø
At time of specification publication, DSCC approval of these
devices was pending. Consult factory for current status.
The information in this data sheet has been carefully checked and is believed to be accurate; however no
responsibility is assumed for possible errors. These specifications are subject to change without notice.
Ó
9849
Lambda Advanced Analog
2270 Martin Avenue
Santa Clara CA 95050-2781
(408) 988-4930 FAX (408) 988-2702
MIL-PRF-38534 Certified
ISO9001 Registered
l
LAMBDA ADVANCED ANALOG INC.
12
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