6ED2742S01Q [INFINEON]
MOTIX™ 6ED2742S01Q是一款160V 绝缘体上硅 (SOI) 栅极驱动器，专为三相BLDC电机驱动应用而设计。这款驱动器集成自举二极管，可为三个外高压侧自举电容充电，具有涓流充电电路，支持100%占空比。主要保护功能包括，欠压锁定、可配置阈值的过流保护、故障通信和自动故障清除。其输出驱动器具有高脉冲电流缓冲级，同时可最大限度地规避桥臂直通风险。在电流检测放大时，可选择是否加入VSS和COM的直流分量。本驱动器十分便捷易用、具有可扩展性和鲁棒性，且性价比十足，适用电压范围也很广泛，是电动工具、机器人和轻型电动车（LEV）应用的一站式解决方案。;
| 型号： | 6ED2742S01Q |
| 厂家： | 
Infineon |
| 描述： | MOTIX™ 6ED2742S01Q是一款160V 绝缘体上硅 (SOI) 栅极驱动器，专为三相BLDC电机驱动应用而设计。这款驱动器集成自举二极管，可为三个外高压侧自举电容充电，具有涓流充电电路，支持100%占空比。主要保护功能包括，欠压锁定、可配置阈值的过流保护、故障通信和自动故障清除。其输出驱动器具有高脉冲电流缓冲级，同时可最大限度地规避桥臂直通风险。在电流检测放大时，可选择是否加入VSS和COM的直流分量。本驱动器十分便捷易用、具有可扩展性和鲁棒性，且性价比十足，适用电压范围也很广泛，是电动工具、机器人和轻型电动车（LEV）应用的一站式解决方案。 通信 电机 栅极驱动 高压 脉冲 二极管 驱动器 |
| 文件： | 总36页 (文件大小：2071K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
6ED2742S01Q
160 V pre-regulated three phase SOI gate driver with integrated charge pump,
current sense amplifier, over-current protection, and bootstrap diodes
Features
Product summary
Bootstrap voltage (VB node) of +160 V
Floating channel designed for bootstrap operation
Integrated power management unit (PMU) with;
VB_OFFSET = 160 V max
IO+_pk / IO-_ pk (typ) = + 1 A / - 2 A
Deadtime (typ) = 100 ns
tON / tOFF (typ) = 100 ns/ 100 ns
Delay matching = 20 ns max
o
o
Linear pre-regulator to enable wide input VIN range
Integrated charge pump for stable VCC
Integrated current sense amplifier (CSA) with selectable gain
Integrated over-current protection with selectable VREF threshold
100% duty cycle operation with trickle charge pump per high side
Integrated low RON, ultra-fast bootstrap diodes
Independent under voltage lockout for both high and low side
Integrated shoot-through protection with built-in dead time
Multi-function RFE pin (Enable, Fault, and automatic Fault clear)
Integrated short pulse / noise rejection input filter
Schmitt trigger inputs with hysteresis
Package
3.3 V, 5 V input logic compatible, outputs in phase with inputs
Available in small footprint QFN32 lead, 5x5 mm package
2kV HBM ESD, RoHS compliant
Applications
32-Lead QFN
5x5mm
General purpose three phase gate driver for N-Channel MOSFETs
Servo Drives in Robotics and Factory Automation
General Purpose Low Voltage Drives or inverters
e-Scooters, e-Bikes, and other e-Vehicles that do not require Automotive Qualification (LSEV)
Battery operated Small Home Appliances (SHA)
Commercial and Agricultural Drones
Professional and Consumer Service Robotics
Logistics Vehicles (eForklifts, Autonomous warehouse robotics)
Battery operated hand-held power tools
Gardening or Outdoor Power Equipment (OPE) Tools
Product validation
Qualified for industrial applications according to the relevant tests of JEDEC78/20/22
Ordering information
Standard pack
Base part number Package type
Orderable part number
6ED2742S01QXUMA1
Form
Quantity
6ED2742S01Q
5 x 5mm QFN32 Tape and Reel
2,500
Final Datasheet
www.infineon.com/SOI
Please read the Important Notice and Warnings at the end of this document
Page 1 of 36
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6ED2742S01Q
160 V pre-regulated three phase SOI gate driver with integrated charge pump,
current sense amplifier, over-current protection, and bootstrap diodes
1
Description
The 6ED2742S01Q is a 160 V SOI based gate driver designed for three phase BLDC motor drive
applications. Integrated bootstrap diodes are used to supply the three external high sides charging
bootstrap capacitors and supports 100% duty cycle operation by a trickle charge pump. Protection features
include under voltage lockout, over current protection with configurable threshold, fault communication and
automatic fault clear. The output drivers feature a high-pulse current buffer stage designed for minimum
driver cross-conduction. A current sense operational amplifier (CSA) with selectable gain is integrated
between the VSS and COM.
V BATT +
10 uF
BJT DR
VCC
VIN
VB 1,2,3
HO 1,2,3
10 nF
CP1
1 uF
CP2
VREG
10 uF
10 nF
HIN 1,2,3
1 uF
LIN 1,2,3
RFE
VS 1,2,3
LO 1,2,3
ITRIP
ITRIP CONF
CSO GAIN
CSO
STR
VSS
COM
V BATT -
*Bootstrap diode is monolithically integrated.
* For optimal operation use the minimum capacitance values on supply pins as shown here
This diagram shows electrical connections only. Please refer to our application notes and design tips
for proper circuit board layout.
Figure 1
Typical application block diagram
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6ED2742S01Q
160 V pre-regulated three phase SOI gate driver with integrated charge pump,
current sense amplifier, over-current protection, and bootstrap diodes
2
Table of contents
2
Table of contents......................................................................................................3
Absolute maximum ratings................................................................................................... 4
Recommended operating conditions.................................................................................. 5
Static electrical characteristics............................................................................................. 5
Dynamic electrical characteristics....................................................................................... 8
2.1
2.2
2.3
2.4
3
Block diagram ..........................................................................................................9
4
4.1
4.2
Pin configuration and functionality.........................................................................10
Pin configuration.................................................................................................................. 10
Pin functionality.................................................................................................................... 11
5
Application information and additional details........................................................12
MOSFET gate drive............................................................................................................. 12
Switching relationships ....................................................................................................... 12
Timing diagrams .................................................................................................................. 13
Deadtime and matched propagation delays.................................................................... 14
Input logic compatibility....................................................................................................... 15
Undervoltage lockout .......................................................................................................... 15
Shoot-through protection.................................................................................................... 16
Enable, Fault reporting and programmable fault clear timer......................................... 16
Over-current protection....................................................................................................... 17
Current sense operational amplifier.................................................................................. 19
Gain settings for the over current protection (ITRIP_Conf) and current sense
operational amplifier (CSO)................................................................................................ 20
Advanced input filter............................................................................................................ 21
Short-Pulse / Noise rejection filters................................................................................... 22
Power Management Unit (PMU) ....................................................................................... 22
Internal linear pre-regulator........................................................................................... 23
Internal charge pump..................................................................................................... 23
Config #1 - Charge pump only: VBATT connected directly to VREG....................... 24
Config #2 - Pre-regulator / charge pump: VBATT connected to VIN........................ 25
Config #3: VBATT connected to VIN and external BJT .............................................. 26
Config #4: Direct External VCC drive......................................................................... 27
Bootstrap diode.................................................................................................................... 27
Internal trickle charge pumps – 100% duty cycle operation.......................................... 28
Calculating the bootstrap capacitance CBS ...................................................................... 28
PCB layout tips..................................................................................................................... 30
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10
5.11
5.12
5.13
5.14
5.14.1
5.14.2
5.14.3
5.14.4
5.14.5
5.14.6
5.15
5.16
5.17
5.18
6
7
Related products....................................................................................................32
Packaging information ...........................................................................................33
8
8.1
Additional documentation and resources ...............................................................34
Infineon online forum resources........................................................................................ 34
9
Revision history .....................................................................................................35
Final Datasheet
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6ED2742S01Q
160 V pre-regulated three phase SOI gate driver with integrated charge pump,
current sense amplifier, over-current protection, and bootstrap diodes
Electrical parameters
2.1
Absolute maximum ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may
occur. All voltage parameters are absolute voltages referenced to VSS unless otherwise stated
in the table. The thermal resistance and power dissipation ratings are measured under board
mounted and still air conditions.
Table 1
Absolute maximum ratings
Symbol
Definition
High-side floating well supply voltage (Note 1)
Input battery supply voltage
High-side floating well supply return voltage
Bootstrap supply range
Floating gate drive output voltage
Charge pump input voltage
Low side supply voltage
Min.
-0.3
5
Max.
160
140
140
20
VB + 0.3
20
20
Vcc + 0.3
5
Units
VB
VIN
VS
VBS
VHO
VREG
VCC
VLO
-0.3
-0.3
VS – 0.3
-0.3
-0.3
–0.3
-0.3
-0.3
-0.3
-0.3
Low-side output voltage
VLOGIC IN Logic input voltage (HIN, LIN)
BJTDR Output signal for base drive of external NPN BJT
20
5
5
V
RFE
ITRIP
ITRIP
CONF
CSO
Enable, Fault and automatic fault clear pin
Over current protection input pin
Over current protection threshold configuration
pin
-0.3
5
Current sense op amp output
-0.3
-0.3
-0.3
-0.3
-0.3
-5.0
3.6
5
5
20
20
+5.0
CSO GAIN Current sense op amp gain configuration pin
STR
CP1
CP2
COM
Strobe signal for op amp offset compensation
Charge pump capacitor pin1
Charge pump capacitor pin2
Low side power ground return
Allowable VS offset supply transient relative to
COM
dVS/dt
—
50
V / ns
W
Package power
dissipation @ TA
+25ºC
Thermal resistance,
junction to ambient
Junction temperature
Storage temperature
PD
5 x 5mm QFN-32
5 x 5mm QFN-32
3
RthJA
41
ºC/W
ºC
TJ
TS
TL
—
-50
—
150
150
260
Lead temperature (soldering, 10 seconds)
Note 1:
In case VCC > VB there is an additional power dissipation in the internal bootstrap diode
between pins VCC and VB.
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6ED2742S01Q
160 V pre-regulated three phase SOI gate driver with integrated charge pump,
current sense amplifier, over-current protection, and bootstrap diodes
2.2
Recommended operating conditions
For proper operation, the device should be used within the recommended conditions. All
voltage parameters are absolute voltages referenced to COM unless otherwise stated below
Table 2
Recommended operating conditions
Symbol
VIN
Definition
Input battery supply voltage
Bootstrap voltage
Min
6
Max
140
140
18
Units
VB
VS + 6
6
VBS
High-side floating well supply voltage
High-side floating well supply offset
voltage
VS
0
122
VHO
Floating gate drive output voltage
VS
5
VB
18
V
VREG Charge pump input voltage
Low-side supply voltage (internal PM
block)
VCC
11
13
VCC
VLO
Low-side supply voltage (external supply)
Low-side output voltage
9
0
VSS
-40
18
VCC
5
VLOGIC IN Logic input voltage(HIN, LIN, RFE, STR)
TA Ambient temperature
125
ºC
Note 2: Logic operational for VS of -8V to +120V. Logic state held for VS of -8V to -VBS.
2.3
Static electrical characteristics
(VCC – COM) = (VB – VS) = 12 V, VSS = COM and TA = 25 °C unless otherwise specified. The VIL,
VIH and IIN parameters are referenced to Vss / COM and are applicable to the respective input
leads: HIN and LIN. The VO and IO parameters are referenced to VS / COM and are applicable to
the respective output leads HO or LO. The VCCUV parameters are referenced to COM. The VBSUV
parameters are referenced to VS.
Table 3
Static electrical characteristic
Test
Symbol
Definition
Min.
Typ.
Max.
Units
Conditions
VCC supply undervoltage
positive going threshold
VCCUVLO
6.6
7.5
8.4
+
VCC supply undervoltage
negative going threshold
VCCUVLO
6
6.8
0.7
5
7.6
1.3
5.4
4.9
-
supply undervoltage
VCC
V
VCCUVLOHY
0.2
4.6
4.1
hysteresis
VBS supply undervoltage
positive going threshold
VBSUVLO
+
VBS supply undervoltage
negative going threshold
VBSUVLO
4.5
-
VBS supply undervoltage
hysteresis
V
VBSUVLOHY
0.2
0.5
1.3
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6ED2742S01Q
160 V pre-regulated three phase SOI gate driver with integrated charge pump,
current sense amplifier, over-current protection, and bootstrap diodes
Test
Symbol
Definition
Min.
Typ.
Max.
Units
Conditions
High-side floating well offset
supply leakage
ILK
IQCC
IQBS
—
—
3
VB = VS =
140 V
250
15
350
25
450
40
uA
Quiescent supply current
VBS quiescent supply current
HO = Off
All input
combinations
High level output voltage
LO 1,2,3
HO 1,2,3
—
—
140
70
200
120
VOH
V
IO = 20 mA
Low level output voltage
LO 1,2,3
VOL
HO 1,2,3
—
—
1000
2000
1.7
—
—
Iopk+
Peak output current turn-on1
PW ≤ 10 µs
PW ≤ 10 µs
mA
V
Iopk-
Peak output current turn-off1
Logic “1” input voltage
Logic “0” input voltage
VIH
1.4
0.8
10
2.0
1.4
30
1.1
VIL
Input bias current (Output =
High)
20
ILOGIC IN+
ILOGIC IN-
RBSD
VIN = 4 V
VIN = 0 V
µA
Ω
Input bias current (Output =
Low)
—
0.15
38
0.5
55
20
Bootstrap diode resistance
ITRIP Conf >
3 V
950
475
225
1000
500
250
1050
525
275
1.5V < ITRIP
Conf < 2V
0.5V < ITRIP
Conf < 1V
VITRIP
Over current threshold
voltage
mV
ITRIP Conf <
0.25V
110
130
150
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6ED2742S01Q
160 V pre-regulated three phase SOI gate driver with integrated charge pump,
current sense amplifier, over-current protection, and bootstrap diodes
Test
Symbol
Definition
Min.
Typ.
Max.
Units
Conditions
CSO gain >
3 V
36
18
9
40
20
41
21
1.5V < CSO
gain< 2V
GCSO
Current sense amplifier gain
V/V
0.5V < CSO
gain < 1V
10
11
CSO gain <
0.25V
4
5
6
VOFF_OUT_40
VOFF_OUT_20
VOFF_OUT_10
VOFF_OUT_5
Current sense amplifier
output offset @ gain = 40
15
80
110
130
-10
150
150
150
150
285
220
190
170
+10
Current sense amplifier
output offset @ gain = 20
mV
COM = Vss
Current sense amplifier
output offset @ gain = 10
Current sense amplifier
output offset @ gain = 5
1
VOFF_T
Current sense amplifier
output offset drift vs.
Temperature
COM = Vss, -
40 °C < Tj <
150 °C
%
6.5
1.4
0.8
—
—
1.7
1.1
—
—
2.0
1.4
1
V/us
SR
Slew rate
VRFE+
VRFE-
IRFE+
IRFE-
RFE positive going threshold
RFE negative going threshold
V
Input bias current
Logic “1”
uA
Input bias current
Logic “0”
-1
—
—
1 Not subjected to production test, verified by characterization.
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6ED2742S01Q
160 V pre-regulated three phase SOI gate driver with integrated charge pump,
current sense amplifier, over-current protection, and bootstrap diodes
2.4
Dynamic electrical characteristics
VCC = VBS= 12 V, VSS = COM, TA = 25 oC and CL = 1000 pF unless otherwise specified.
Table 4
Symbol
tON
Dynamic electrical characteristics
Test
Definition
Min.
Typ.
Max.
Units
Conditions
Cload = 1nF,
IN 50% rise to
OUT 10% rise
Cload = 1nF,
IN 50% fall to
OUT 90% fall
Cload = 1nF,
OUT 10% to
OUT 90%
50
190
Turn-on propagation delay
100
tOFF
Turn-off propagation delay
Turn-on rise time
100
20
50
5
190
40
tR
Cload = 1nF,
OUT 90% to
OUT 10%
Cload = 1nF,
OUT 90% to
OUT 10%
tF
Turn-off fall time
10
—
40
20
5
Delay matching time (HS & LS
turn-on/off)
ns
MT
DT
—
70
Deadtime: LO Turn-off to HO
Turn-on & HO Turn-off to LO turn-
on
100
160
Enable low to output shutdown
propagation delay
ITRIP to output shutdown
propagation delay
tEN
60
100
100
160
400
tITRIP
150
tBL
tfil
ITRIP blanking time
Input noise filter time
ITRIP to FAULT propagation
delay
—
—
150
30
—
—
tFLT
150
—
200
—
350
2
VIN = 12V,
VREG = 1uF,
VCC = 1uF,
Ccp = 10nF,
Tfltclr < 10us,
when Vcc is
above 8.5V
R =2 MΩ,
Twakep-up Sleep wake-up time
ms
FAULT clear time
(R = 2 MΩ, C = 1 nF)
tFLTCLR
—
1.5
—
C = 1 nF on
RFE
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6ED2742S01Q
160 V pre-regulated three phase SOI gate driver with integrated charge pump,
current sense amplifier, over-current protection, and bootstrap diodes
3
Block diagram
Trickle Charge
Pump
VB3
HO3
S
Latch
&
UVLO
Detect
VSS/COM
Level
Shifter
HV Level
Shifter
Driver
Input
Noise
Filter
HIN3
LIN3
HIN2
LIN2
R
VS3
VB2
Input
Noise
Filter
Trickle Charge
Pump
S
Latch
&
UVLO
Detect
VSS/COM
Level
Shifter
Input
Noise
Filter
HV Level
Shifter
HO2
Driver
Deadtime &
Shoot-Through
Prevention
R
VS2
VB1
Input
Noise
Filter
Trickle Charge
Pump
S
Input
Noise
Filter
Latch
&
UVLO
Detect
VSS/COM
Level
Shifter
HV Level
Shifter
HIN1
LIN1
VSS
HO1
VS1
Driver
R
Input
Noise
Filter
UVLO
Detect
VCC
LO3
ITRIP
Noise
Filter
VSS/COM
Level
Shifter
ITRIP
Delay
Driver
ITRIP CONF
VSS/COM
Level
Shifter
Delay
LO2
Driver
Noise
Filter
RFE
VSS/COM
Level
Shifter
Delay
LO1
Driver
Sense
COM
VCC
COM
RShunt
CSA
Offset
Power Management Block
Linear Charge
Regulator Pump
Sense
VSS
Figure 2
Functional block diagram
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6ED2742S01Q
160 V pre-regulated three phase SOI gate driver with integrated charge pump,
current sense amplifier, over-current protection, and bootstrap diodes
4
Pin configuration and functionality
Pin configuration
4.1
25
32
31
30
29 28 27 26
24
23
1
2
3
4
5
6
7
8
HIN3
LIN1
BJT DR
VREG
CP1
22 LIN2
21
CP2
LIN3
6ED2742S01M
32 pin 5x5mm QFN
20
VCC
LO3
19
VSS
HO3
18
ITRIP
COM
VS3
17 VB3
9
10 11 12
13 14
15 16
Figure 3
6ED2742S01Q pin assignments (top view)
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6ED2742S01Q
160 V pre-regulated three phase SOI gate driver with integrated charge pump,
current sense amplifier, over-current protection, and bootstrap diodes
4.2
Pin functionality
Table 5
Pin descriptions
Pin No. Type
Symbol
Description
26,25,24
Input
Logic input for high side gate driver output (HOx), in
phase
HIN1,2,3
LIN1,2,3
VB1,2,3
23,22,21
9, 13, 17
Input
Output
Output
Logic input for low side gate driver output (LOx), in phase
High side floating supplies
11, 15,
19
HO1,2,3
VS1,2,3
High side gate drive outputs
10, 14,
18
Input
High side floating supply returns
VCC
LO1,2,3
COM
5
Input
Output
Ground
Input
Low side and logic fixed supply
Low side gate drive outputs
12,16,20
8
32
6
Low side power ground return
VIN
Input voltage (Battery voltage)
VSS
Ground
Output
Input
Logic ground
BJT DR
ITRIP CONF
ITRIP
1
Output signal for base drive of external NPN BJT
Over current protection threshold configuration pin
Over current protection input pin
Charge pump input voltage
27
7
Input
VREG
CP1
2
Output
Input
3
Charge pump capacitor pin1
CP2
4
Input
Charge pump capacitor pin2
CSO
30
29
28
31
Output
Input
Current sense op amp output
STR
Strobe signal for op amp offset compensation
Current sense op amp gain configuration pin
CSO GAIN
Input
Input /
Output
Enable, Fault and automatic fault clear pin
RFE
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6ED2742S01Q
160 V pre-regulated three phase SOI gate driver with integrated charge pump,
current sense amplifier, over-current protection, and bootstrap diodes
5
Application information and additional details
MOSFET gate drive
5.1
The 6ED2742S01Q HVIC is designed to drive MOSFET power devices in battery operated
applications. Figures 4 and 5 illustrate several parameters associated with the gate drive
functionality of the HVIC. The output current of the HVIC, used to drive the gate of the power
switch, is defined as IO. The voltage that drives the gate of the external power switch is defined
as VHO for the high-side power switch and VLO for the low-side power switch; this parameter is
sometimes generically called VOUT and in this case does not differentiate between the high-side
or low-side output voltage.
VB
(or VCC
VB
(or VCC
)
)
IO+
HO
(or LO)
HO
(or LO)
+
IO-
VHO (or VLO)
-
VS
or COM
S
V
(
)
(or COM)
Figure 4
HVIC Sourcing current
Figure 5
HVIC Sinking current
5.2
Switching relationships
The relationships between the input and output signals of the 6ED2742S01Q are illustrated
below in Figure 6. We can see the definitions of several timing parameters (i.e. tON, tOFF, tR, and
tF) associated with this device.
Figure 6
Switching timing diagram
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6ED2742S01Q
160 V pre-regulated three phase SOI gate driver with integrated charge pump,
current sense amplifier, over-current protection, and bootstrap diodes
5.3
Timing diagrams
The following two figures illustrate the timing relationships of some of the functionality of the
6ED2742S01Q, in particular over-current protection feature with fault reporting and automatic
fault clear.
Interval A of Figures 7 and 8 shows that the signal between Vss and COM has gone from a low
to a high state crossing the threshold set up by ITRIP CONF pin; as a result, all of the gate drive
outputs have been disabled (i.e., see that HO has returned to the low state; LO is also held low),
and a fault condition is reported on the RFE pin, which goes 0V. Once the over-current event has
returned to the low state, the output will remain disabled and the fault condition reported until the
voltage on the RFE pin charges up to VRFE+ threshold (see interval C in Figure 4); the charging
characteristics are dictated by the RC network attached to the RFE pin.
During interval B and D of Figure 7 and 9, we can see that the RFE pin has been pulled low (as
is the case when the driver IC has received a command from the control IC to shutdown); these
results in the outputs (HO and LO) being held in the low state until the RFE pin is pulled high.over
D
A
B
C
HIN
LIN
V(ITRIP)
RFE
HO
LO
Figure 7
Input/output timing diagram
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6ED2742S01Q
160 V pre-regulated three phase SOI gate driver with integrated charge pump,
current sense amplifier, over-current protection, and bootstrap diodes
Figure 8
Detailed view of C interval
Figure 9
Detailed view of D interval
5.4
Deadtime and matched propagation delays
This 6ED2742S01Q features integrated deadtime protection circuitry. The deadtime feature
inserts a time period (a minimum deadtime) in which both the high- and low-side power switches
are held off; this is done to ensure that the power switch being turned off has fully turned off before
the second power switch is turned on. This minimum deadtime is automatically inserter whenever
the external deadtime is shorter than DT; external deadtimes larger than DT are not modified by
the gate driver. Figure 10 illustrates the deadtime period and the relationship between the output
gate signals.
The deadtime circuitry of 6ED2742S01Q is matched with respect to the high- and low-side
outputs. Figure 10 defines the two deadtime parameters (i.e., DTLO-HO and DTHO-LO); the
deadtime matching parameter (MDT) associated with the 6ED2742S01Q specifies the maximum
difference between DTLO-HO and DTHO-LO.
LIN
1
1.65V
1.65V
HIN
12V
3V
HO
LO
DT
DT
3V
12 V
Figure 10 Dead Time Definitions
Figure 11 Delay Matching Waveform
Definitions
The 6ED2742S01Q is designed with propagation delay matching circuitry. With this feature, the
IC’s response at the output to a signal at the input requires approximately the same time duration
(i.e., tON, tOFF) for both the low-side channels and the high-side channels; the maximum
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160 V pre-regulated three phase SOI gate driver with integrated charge pump,
current sense amplifier, over-current protection, and bootstrap diodes
difference is specified by the delay matching parameter (MT). The propagation turn-on delay (tON)
of the 6ED2742S01Qis matched to the propagation turn-on delay (tOFF).
5.5
Input logic compatibility
The input pins of are based on a TTL and CMOS compatible input-threshold logic that is
independent of the Vcc supply voltage. With typical high threshold (VIH) of 2.0 V and typical low
threshold (VIL) of 0.8 V, along with very little temperature variation as summarized in Figure 12,
the input pins are conveniently driven with logic level PWM control signals derived from 3.3 V and
5 V digital power-controller devices. Wider hysteresis (typically 0.8 V) offers enhanced noise
immunity compared to traditional TTL logic implementations, where the hysteresis is typically less
than 0.5 V. 6ED2742S01Q also features tight control of the input pin threshold voltage levels
which eases system design considerations and ensures stable operation across temperature. The
6ED2742S01Q features floating input protection wherein if any of the input pin is left floating, the
output of the corresponding stage is held in the low state. This is achieved using pull-down
resistors on all the input pins (HIN, LIN) as shown in the block diagram. The 6ED2742S01Q has
input pins that are capable of sustaining voltages higher than the bias voltage applied on the Vcc
pin of the device.
Figure 12 HIN & LIN input thresholds
5.6
Undervoltage lockout
This IC provides undervoltage lockout protection on both the VCC (logic and low-side circuitry)
power supply and the VBS (high-side circuitry) power supply. Figure 13 is used to illustrate this
concept; VCC (or VBS) is plotted over time and as the waveform crosses the UVLO threshold (VCC
UVLO+/- or VBSUVLO+/-) the undervoltage protection is enabled or disabled.
Upon power-up, should the VCC voltage fail to reach the VCCUV+ threshold, the IC won’t turn-on.
Additionally, if the VCC voltage decreases below the VCCUV- threshold during operation, the
undervoltage lockout circuitry will recognize a fault condition and shutdown the high and low-side
gate drive outputs.
Upon power-up, should the VBS voltage fail to reach the VBSUV+ threshold, the IC won’t turn-on.
Additionally, if the VBS voltage decreases below the VBSUVLO- threshold during operation, the
undervoltage lockout circuitry will recognize a fault condition, and shutdown the high-side gate
drive outputs of the IC.
The UVLO protection ensures that the IC drives the external power devices only when the gate
supply voltage is sufficient to fully enhance the power devices. Without this feature, the gates of
the external power switch could be driven with a low voltage, resulting in the power switch
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160 V pre-regulated three phase SOI gate driver with integrated charge pump,
current sense amplifier, over-current protection, and bootstrap diodes
conducting current while the channel impedance is high; this could result in very high conduction
losses within the power device and could lead to power device failure.
VCC REG
(or VBS)
VCC REGUV+
(or VBSUV +)
VCC REGUV-
(or VBSUV -)
Time
UVLO Protection
(Gate Drive Outputs Disabled)
Normal
Normal
Operation
Operation
Figure 13 UVLO protection
5.7
Shoot-through protection
The 6ED2742S01Q is equipped with shoot-through protection circuitry (also known as cross-
conduction prevention circuitry). Figure 14 shows how this protection circuitry prevents both the
high- and low-side switches from conducting at the same time.
Normal Operation
Abnormal Operation
HIN
LIN
HO
LO
Figure 14 Illustration of shoot-through protection circuitry
5.8
Enable, Fault reporting and programmable fault clear timer
The 6ED2742S01Q provides an enable functionality that allows it to shutdown or enable the HVIC
and also provides an integrated fault reporting output along with an adjustable fault clear timer.
There are two situations that would cause the IC to report a fault via the RFE pin. The first is an
undervoltage condition of VCC and the second is if the over-current feature has recognized a
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current sense amplifier, over-current protection, and bootstrap diodes
fault. Once the fault condition occurs, the RFE pin is internally pulled to VSS and the fault clear
timer is activated. The RFE output stays in the low state until the fault condition has been removed
and the fault clear timer expires; once the fault clear timer expires, the voltage on the RFE pin will
return to its external pull-up voltage.
The length of the fault clear time period (tFLTCLR) is determined by exponential charging
characteristics of the capacitor where the time constant is set by RRFE and CRFE. Figure 15 shows
that RRFE is connected between the external supply (VDD) and the RFE pin, while CRFE is placed
between the RFE and VSS pins.
VCC
HIN U
LIN U
HIN
LIN
HIN V
LIN V
HIN W
LIN W
VDD
uC
HO
VS
GK
RRFE
RFE
LO
CRFE
VSS
ITRIP
R
DC - BUS
Figure 15 Programming the fault clear timer
The design guidelines for this network are shown in Table 6
Table 6
Design guidelines
≤1 nF
CRFE
Ceramic
0.5 MΩ to 2 MΩ
>> RON, RCIN
RRFE
The length of the fault clear time period can be determined by using the formula below.
vC(t) = Vf*(1-e-t/RC
)
tFLTCLR = -(RRFE*CRFE) *ln (1-VRFE+/VDD ) + 100ns
The voltage on the RFE pin should not exceed the VDD of the uC power supply.
5.9
Over-current protection
The 6ED2742S01Q is equipped with an over-current feature in addition to the stand-alone Current
Sense Amplifier (CSA). This functionality can sense over-current events in the DC- bus. Once
the IC detects an over-current event, the outputs are shutdown, and RFE is pulled to VSS.
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160 V pre-regulated three phase SOI gate driver with integrated charge pump,
current sense amplifier, over-current protection, and bootstrap diodes
The level of current at which the over-current protection (OCP) is initiated is determined by the
shunt resistor connected between COM pin and VSS pin as shown in Figure 16, and by the
threshold configured by ITRIP CONF pin (VITRIP+). The circuit designer will need to determine the
maximum allowable level of current in the DC- bus and select R0 and VITRIP+
.
VITRIP+ = R0 x IDC-
DC BUS +
VIN
HIN
LIN
RFE
VB
HO
Q2
Q3
VS
VSS
LO
ITRIP
COM
C1
R1
DC BUS -
R0
IDC -
Figure 16 Programming the over-current protection
For example, a typical value for resistor R0 could be 10 mΩ.
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160 V pre-regulated three phase SOI gate driver with integrated charge pump,
current sense amplifier, over-current protection, and bootstrap diodes
5.10
Current sense operational amplifier
A current sense operational amplifier (CSA) with configurable gain is integrated in the gate driver
sensing the voltage between VSS and COM pins. The amplifier has a strobe input signal. When
strobe signal is LOW the operational amplifier output signal CSO is following the VSS-COM
voltage multiplied by a certain gain, when strobe signal is HIGH CSO signal is reporting the op
amp offset. CSO output has an offset added above VSS of 150 mV. This offset ensures the
measured current remains positive and does not go negative in any regular operating conditions.
Sense
COM
Zero level shift
&
RShunt
variable gain
Sense
VSS
STR
CSO
Figure 17 Current sense operational amplifier
VSS - COM
Real Zero Shift available on CSO for
150 mV
ADC calibration
CSO
STR = 0
STR = 1
STR
Figure 18 Current sense operational amplifier timing diagram
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160 V pre-regulated three phase SOI gate driver with integrated charge pump,
current sense amplifier, over-current protection, and bootstrap diodes
5.11
Gain settings for the over current protection (ITRIP_Conf) and current sense
operational amplifier (CSO)
The gain for the over current protection via ITRIP and current sense operation amplifier output
can be set using a simple potential divider network as shown in below figure 19.
V BATT +
BJT DR
VCC
VIN
VB 1,2,3
HO 1,2,3
CP1
CP2
VREG
HIN 1,2,3
LIN 1,2,3
RFE
3.3 V
VS 1,2,3
LO 1,2,3
ITRIP
ITRIP CONF
CSO GAIN
CSO
STR
VSS
COM
V BATT -
Figure 19 Setting over current protection (ITRIP) gain and current sense operational
amplifier gain via the resistor divider
The voltage of the potential divider network can be scaled down from an external 3.3 V. It should
be noted that when powering from external 3.3 V the supply sequencing should be such that the
6ED2742 is first powered up via VIN before applying the 3.3 V to the Gain / Config pins. Two use
cases are shown in figure 20. Figure “a” shows the option where the 3.3 V input is either ramped
up after or along with VIN / VCC. RFE gets asserted (IC gets enabled) after the UVLO of VCC is
crossed and VRFE+ threshold is crossed. Figure” b” shows use case when the 3.3 V input is already
available before VIN / VCC arrive. In this case, RFE gets asserted when the UVLO of VCC is
crossed. It is good to note that the RFE pin is held low under two conditions:
a. Under Voltage Lock Out (UVLO) of VCC / VRFE
b. ITRIP threshold as set by ITRIP Config is crossed
In case the 3.3 V arrives before VCC toggling(pulling down and the pulling up) the RFE will re-
read the values of ITRIP config and CSO Gain.
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160 V pre-regulated three phase SOI gate driver with integrated charge pump,
current sense amplifier, over-current protection, and bootstrap diodes
3.3 V
ITRIP Conf
8 V to 120 V
CSO Gain
3.3 V
3.3 V
VIN
0 V
0 V
8 V to 120 V
12 V
3.3 V
VIN
VCC
0 V
0 V
12 V
3.3 V
ITRIP Conf
CSO Gain
VCC
0 V
0 V
~10 us
3.3 V
3.3 V
RFE
0 V
0 V
RFE
ITRIP
ITRIP
Fig a 0 V
Fig b
Figure 20 Input voltage sequencing for setting up different gain and ITRIP config
The voltage limits for different gains are as shown in the electrical characterisitics table 3 in page
6 and 7. They are summarized as beow in Table 7 and 8
Table 7
ITRIP Config pin voltage settings for different overcurrent threshold
voltages
950 1000 1050
ITRIP Conf > 3 V
475
225
110
500
250
130
525
275
150
1.5V < ITRIP Conf < 2V
0.5V < ITRIP Conf < 1V
ITRIP Conf < 0.25V
Over current
threshold voltage
mV
VITRIP
Table 8
CSO gain pin voltage settings for different gain of CSO output
36
18
9
40
20
10
5
41
21
11
6
CSO gain > 3 V
1.5V < CSO gain< 2V
0.5V < CSO gain < 1V
CSO gain < 0.25V
Current sense
amplifier gain
GCSO
V/V
4
5.12
Advanced input filter
The advanced input filter allows an improvement in the input/output pulse symmetry of the HVIC
and helps to reject noise spikes and short pulses. This input filter has been applied to the HIN
and LIN inputs.
Figure 19 shows a typical input filter and the asymmetry of the input and output. The upper pair
of waveforms (Example 1) show an input signal with a duration much longer then tFIL,IN; the
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160 V pre-regulated three phase SOI gate driver with integrated charge pump,
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resulting output is approximately the difference between the input signal and tFIL,IN
.
The lower
pair of waveforms (Example 2) show an input signal with a duration slightly longer then tFIL,IN; the
resulting output is approximately the difference between the input signal and tFIL,IN
.
Figure 20 shows the advanced input filter and the symmetry between the input and output. The
upper pair of waveforms (Example 1) show an input signal with a duration much longer then tFIL,IN
;
the resulting output is approximately the same duration as the input signal. The lower pair of
waveforms (Example 2) show an input signal with a duration slightly longer then tFIL,IN; the resulting
output is approximately the same duration as the input signal.
Figure 21
Typical input filter
Figure 22
Advanced input filter
5.13
Short-Pulse / Noise rejection filters
This device’s input filter provides protection against short-pulses (e.g., noise) on the input lines.
If the duration of the input signal is less than tFIL,IN, the output will not change states. Example 1
of Figure 21 shows the input and output in the low state with positive noise spikes of durations
less than tFIL,IN; the output does not change states. Example 2 of Figure 21 shows the input and
output in the high state with negative noise spikes of durations less than tFIL,IN; the output does
not change states.
1
Figure 23 Noise rejecting input filters
5.14
Power Management Unit (PMU)
The integrated power management unit enables the gate driver to operate across a wide range
of input voltages without requiring and external VCC supply. For some applications requiring
higher VCC voltages above 12 V, such as 15 V, the driver can also be driven with an external
VCC voltage supply.
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Four possible configurations are as shown in Figure 22 to Figure 25. The four different
configurations support different values of ICP_AVG from the Power Management Unit (PMU)
depending on the input voltage range and whether an external BJT is used to enable higher power
and voltage operation.
5.14.1
Internal linear pre-regulator
A linear pre-regulated circuit with the charge pump supplies a voltage of approximately 12 V to
VCC via the VIN voltage. This regulated VCC voltage is used for the low-side gate drive supply
as well as for the high-side gate driver circuit supplied through the integrated bootstrap diodes
and external bootstrap capacitors.
5.14.2
Internal charge pump
Depending on the configuration and setup, the 6ED2742S01Q can provide a gate drive voltage
(VCC) of 12 V, even if the input supply voltage drops as low as 8 V. This gate drive voltage is
generated by an internal charge pump, which requires an external capacitor. The charge pump
requires external capacitors between CP1 and CP2 and from VREG to ground.
The charge pump flying capacitor between CP1 and CP2 should have a capacitance of 10nF.
The capacitor must be rated to withstand the maximum VIN power supply voltage. An X7R or
X5R ceramic capacitor is recommended. With a 10nF capacitor, internal charge pump can output
approximately 10 mA when VIN is 6 V.
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U
T
6ED2742S01Q
160 V pre-regulated three phase SOI gate driver with integrated charge pump,
current sense amplifier, over-current protection, and bootstrap diodes
5.14.3
Config #1 - Charge pump only: VBATT connected directly to VREG
Configuration #1 provides the smallest form factor and highest efficiency operating mode for input
voltages from 12 V to 18 V. This configuration would be typically used for 12 V nominal battery
voltage power tools.
Charge Pump Only Configuration
VIN
LINEAR Pre-REGULATOR
LRIN
LRO
U T
Current Flow Direction
CHARGE
ICP_AVG
VCC
VREG
PUMP
CPO
CPIN
D1
VBATT
VCC
CVREG
CVCC
3-PHASE GATE DRIVER
CP1
WHO_LO
UHO_LO
VHO_LO
CP2
CCP
Figure 24 Typical configuration for 8.4 V to 18 V applications
Table 9
Charge pump only operating conditions (typical)
VREG1 =
VBATT
VCC
(V)
ICP_AVG Max.
(mA @
25 °C)
15
(V)
18
12
8
12
12
12
11
10
15
10
10
10
7
6
Note 1: Maximum absolute VREG voltage =
20V (including transients)
Please note that for configuration #1, there is an optimal operating range that strongly depends
on the supplied input voltage to the VREG pin. Exceeding 20V input to the VREG pin may
permanently damage the device.
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5.14.4
Config #2 - Pre-regulator / charge pump: VBATT connected to VIN
Configuration #2 provides wider input voltage flexibility with the smallest form factor since an
external BJT is not used. Typical input voltage range operation up to 96 V is possible.
Current Flow Direction
VIN
BJT_DR
VREG
LINEAR Pre-REGULATOR
ICP_AVG
LRIN
LROU T
VBATT
VCC
CHARGE
PUMP
CPOU T
CPIN
D1
VCC
CVREG
CVCC
3-PHASE GATE DRIVER
1 uF
CP1
WHO_LO
UHO_LO
VHO_LO
CP2
CCP
Figure 25 Typical configuration for 12 V to 90 V applications
Table 10
Charge pump only operating conditions (typical)
VBATT
VIN
(V)
=
VCC
()
ICP_AVG
Max.
(mA @
25 °C)
BJT_DR
= VREG
(V)
11
14
90
72
60
48
36
24
12
9
15.5
12
15
10.5
7.5
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5.14.5
Config #3: VBATT connected to VIN and external BJT
Configuration #3 provides the widest input voltage range with the addition of an external NPN BJT
to share the power dissipation between the internal PMU blocks and BJT.
Current Flow Direction
BJT_DR
VIN
LINEAR Pre-REGULATOR
Q1
LRIN
LROU T
ICP_AVG
VCC
VREG
VBATT
CHARGE PUMP
CPOU T
CPIN
D1
VCC
CVREG
10 uF
CVCC
3-PHASE GATE DRIVER
CP1
WHO_LO
UHO_LO
VHO_LO
CP2
CCP
Figure 26 Typical configuration for VIN > 60 VDC applications. For stability reasons VREG
capacitor needs to be 10 uF in this configuration
Table 11
Pre-regulator, Charge pump, external BJT operating conditions (typ – 25°C)
VIN (V)
BJT_DR (V)
VREG (V)
VCC (V)
120
90
80
36
24
18
12
8
15.5
16.5
12
10
14.5
9.5
10.5
6.7
5.7
Typical input voltage range recommended is up to 120 V. ICP_AVG of 15 mA for VIN operating
range of 10 V - 120 V.
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5.14.6
Config #4: Direct External VCC drive
An external VCC power supply (< 18 V) can be connected to the VCC pin to power the gate
driver circuit directly with a voltage greater than 12 V (eg. 15V). This can be useful for
applications where the MOSFET is driven with a gate voltage greater than 12 V.
Current Flow Direction
VIN
BJT_DR
LINEAR REGULATOR
LRIN
LROU T
VREG
VCC
CHARGE PUMP
CPOU T
CPIN
D1
VCC
CVCC
3-PHASE GATE DRIVERS
External DC
< 20 V
CP1
WHO_LO
UHO_LO
VHO_LO
CP2
Figure 27 Typical configuration for direct gate drive using an external VCC power supply
5.15
Bootstrap diode
An ultra-fast bootstrap diode is monolithically integrated for establishing the high side supply. The
differential resistor of the diode helps to avoid extremely high inrush currents when initially
charging the bootstrap capacitor. The integrated diode with its low ohmic resistance helps save
cost and improve reliability by reducing external components as shown below figure 26.
VCC
VB
RBS
Diode
Figure 28 6ED2742S01Q with integrated components
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The low ohmic current limiting resistor (typically 38 Ω) provides essential advantages over other
competitor devices with high ohmic bootstrap structures. A low ohmic resistor such as in the
6ED2742S01Q allows faster recharging of the bootstrap capacitor during periods of small duty
cycles on the low side transistor. The bootstrap diode is usable for all kind power electronic
converters. The bootstrap diode is a real uni-directional PN-diode and is temperature robust. It
can be used at high temperatures with a low duty cycle of the low side transistor.
The bootstrap diode of the 6ED2742S01Q works with all control algorithms of modern power
electronics, such as trapezoidal or sinusoidal motor drives control.
5.16
Internal trickle charge pumps – 100% duty cycle operation
External bootstrap capacitors are charged to VCC via the integrated bootstrap diodes when the
lowside MOSFET (LS-FET) is turned on. This charge is then used to drive the high-side MOSFET
(HS-FET) gate when it is turned on.
To keep the bootstrap capacitors charged and allow for operation at 100% duty cycle, internal
trickle charge pumps for each high side well supply a small current to overcome leakages that
would discharge the bootstrap capacitors.
Bootstrap capacitor charging and its optimal value are explained in the subsequent sections.
5.17
Calculating the bootstrap capacitance CBS
Bootstrapping is a common method of pumping charges from a low potential to a higher one. With
this technique a supply voltage for the floating high side sections of the gate drive can be easily
established according to Figure 27. This method has the advantage of being simple and low cost
but may force some limitations on duty-cycle and on-time since they are limited by the requirement
to refresh the charge in the bootstrap capacitor. Proper capacitor choice can reduce drastically
these limitations.
Upto 140 V
VCC
VB
IBS
Q1
RBS
DBS
CBS
HO
VS
HIN
RGH
Controller
LIN
To Load
Q2
COM
LO
RGL
COM
Figure 29
Half bridge bootstrap circuit in 6ED2742S01Q
When the low side MOSFET turns on, it will force the potential of pin VS to GND. The existing
difference between the voltage of the bootstrap capacitor VCBS and VCC results in a charging
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current IBS into the capacitor CBS. The current IBS is a pulse current and therefore the ESR of the
capacitor CBS must be very small in order to avoid losses in the capacitor that result in lower
lifetime of the capacitor. This pin is on high potential again after low side is turned off and high
side is conducting current. But now the bootstrap diode DBS blocks a reverse current, so that the
charges on the capacitor cannot flow back to the capacitor CVCC. The bootstrap diode DBS also
takes over the blocking voltage between pin VB and VCC. The voltage of the bootstrap capacitor
can now supply the high side gate drive sections. It is a general design rule for the location of
bootstrap capacitors CBS, that they must be placed as close as possible to the IC. Otherwise,
parasitic resistors and inductances may lead to voltage spikes, which may trigger the
undervoltage lockout threshold of the individual high side driver section. However, all parts of the
6ED2742S01Q, which have the UVLO also contain a filter at each supply section in order to
actively avoid such undesired UVLO triggers.
The current limiting resistor RBS according to Figure 27 reduces the peak of the pulse current
during the low side MOSFET turn-on. The pulse current will occur at each turn-on of the low side
MOSFET, so that with increasing switching frequency, the capacitor CBS is charged more
frequently. Therefore, a smaller capacitor is suitable at higher switching frequencies. The
bootstrap capacitor is mainly discharged by two effects: the high side quiescent current and gate
charge of the high side MOSFET to be turned on.
The minimum size of the bootstrap capacitor is given by
푄ꢂꢃꢄꢃ
퐶ꢀꢁ
=
∆푉ꢀꢁ
VBS is the maximum allowable voltage drop at the bootstrap capacitor within a switching
period, typically 1 V. It is recommended to keep the voltage drop below the undervoltage lockout
(UVLO) of the high side and limit
VBS ≤ (VCC– VF– VGSmin– VDSon
)
VGSmin > VBSUV- , VGSmin is the minimum gate source voltage we want to maintain and VBSUV- is the
high-side supply undervoltage negative threshold.
VCC is the IC voltage supply, VF is bootstrapdiode forward voltage and VDSon is drain-source
voltage of low side MOSFET.
Please note, that the value QGTOT may vary to a maximum value based on different factors as
explained below and the capacitor shows voltage dependent derating behavior of its capacitance.
The influencing factors contributing VBS to decrease are:
- MOSFET turn on required Gate charge (QG)
- MOSFET gate-source leakage current (ILK_GS
)
- Floating section quiescent current (IQBS
)
- Floating section leakage current (ILK)
- Bootstrap diode leakage current (ILK_DIODE
- Charge required by the internal level shifters (푄ꢅꢁ): typical 1nC
- Bootstrap capacitor leakage current (ILK_CAP
- High side on time (THON
)
)
)
Considering the above,
푄ꢂꢃꢄꢃ = 푄ꢂ + 푄ꢅꢁ + ꢆ퐼ꢇꢀꢁ + 퐼ꢅꢈ + 퐼ꢅꢈ + 퐼ꢅꢈ
+ 퐼ꢅꢈ ꢒ ∗ 푇ꢓꢄꢔ
ꢏꢐꢑ
ꢉꢊ
ꢋꢌꢍꢋꢎ
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6ED2742S01Q
160 V pre-regulated three phase SOI gate driver with integrated charge pump,
current sense amplifier, over-current protection, and bootstrap diodes
ILK_CAP is only relevant when using an electrolytic capacitor and can be ignored if other types of
capacitors are used. It is strongly recommend using at least one low ESR ceramic capacitor
(paralleling electrolytic capacitor and low ESR ceramic capacitor may result in an efficient
solution).
The above CBS equation is valid for pulse by pulse considerations. It is easy to see, that higher
capacitance values are needed, when operating continuously at small duty cycles of low side.
The recommended bootstrap capacitance is therefore in the range up to 4.7 μF for most switching
frequencies. The performance of the integrated bootstrap diode supports the requirement for
small bootstrap capacitances.
5.18
PCB layout tips
Distance between high and low voltage components: It’s strongly recommended to place the
components tied to the floating voltage pins (VB and VS) near the respective high voltage portions
of the device. Please see the Case Outline information in this datasheet for the details.
Ground Plane: In order to minimize noise coupling, the ground plane should not be placed under
or near the high voltage floating side.
Gate Drive Loops: Current loops behave like antennas and are able to receive and transmit EM
noise (see Figure 29). In order to reduce the EM coupling and improve the power switch turn
on/off performance, the gate drive loops must be reduced as much as possible. Moreover, current
can be injected inside the gate drive loop via the MOSFET collector-to-gate parasitic capacitance.
The parasitic auto-inductance of the gate loop contributes to developing a voltage across the
gate-emitter, thus increasing the possibility of a self turn-on effect.
Figure 30
Optimal layout of 6ED2742 driving three phases of OptiMOS™ MOSFETs
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160 V pre-regulated three phase SOI gate driver with integrated charge pump,
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Supply Capacitor: It is recommended to place a bypass capacitor (CIN) between the VCC and
COM pins. A ceramic 1μF ceramic capacitor is suitable for most applications. This component
should be placed as close as possible to the pins in order to reduce parasitic elements.
Routing and Placement: Power stage PCB parasitic elements can contribute to large negative
voltage transients at the switch node; it is recommended to limit the phase voltage negative
transients. See figure 30 for optimal placement of components. Ceramic capacitors close to the
VCC, VIN, VREG, Charge pump and VB pins.
Figure 31
6ED2742S01Q and its surrounding components optimal placement
Figure 32
6ED2742S01Q 500 W demo board schematic
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160 V pre-regulated three phase SOI gate driver with integrated charge pump,
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Qualification information1
Table 12
Qualification information
Industrial2
Note: This family of ICs has passed JEDEC’s
Industrial qualification. Consumer qualification level
is granted by extension of the higher Industrial level.
Qualification level
MSL1, 260 °C
(per IPC/JEDEC J-STD-020)
Moisture sensitivity level
VQFN-32
Charged device model Class C3 (1.0 kV) (per JEDEC JS-002-2018)
ESD
Human body model
Class 2 (2 kV) (per JEDEC JS-001-2017)
Class II Level A (per JESD78E)
Yes
IC latch-up test
RoHS compliant
6
Related products
Table 13
Product
Description
Gate Driver ICs
6EDL04I06 /
6EDL04N06
600 V, 3 phase level shift thin-film SOI gate driver with integrated high speed, low
RDS(ON) bootstrap diodes with over-current protection (OCP), 240/420 mA source/sink
current drive, fault reporting, and Enable for MOSFET or MOSFET switches.
6EDL04N02PR 200 V, 3 phase level shift thin-film SOI gate driver with integrated high speed, low
RDS(ON) bootstrap diodes with over-current protection (OCP), 240/420 mA source/sink
current drive, fault reporting, and Enable for MOSFET or MOSFET switches.
iMOTION™ Controllers
IRMCK099
iMOTION™ Motor control IC for variable speed drives utilizing sensor-less Field
Oriented Control (FOC) for Permanent Magnet Synchronous Motors (PMSM).
High performance Motor Control IC for variable speed drives based on field oriented
control (FOC) of permanent magnet synchronous motors (PMSM).
IMC101T
1 Qualification standards can be found at Infineon’s web site www.infineon.com
2 Higher qualification ratings may be available should the user have such requirements. Please contact your Infineon sales
representative for further information.
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7
Packaging information
Figure 33 Target Packaging outline PG- VQFN-32-13 (6ED2742S01Q)
Figure 34 Target Package Dimensions PG-VQFN-32-13 (6ED2742S01Q)
Figure 35 Recommended Footprint PG-VQFN-32-13 (6ED2742S01Q)
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8
Additional documentation and resources
Several technical documents related to the use of HVICs are available at www.infineon.com; use
the Site Search function and the document number to quickly locate them.
Below is a short list of some of these documents.
Application Notes:
Understanding HVIC Datasheet Specifications
HV Floating MOS-Gate Driver ICs
Use Gate Charge to Design the Gate Drive Circuit for Power MOSFETs and MOSFETs
Bootstrap Network Analysis: Focusing on the Integrated Bootstrap Functionality
Design Tips:
Using Monolithic High Voltage Gate Drivers
Alleviating High Side Latch on Problem at Power Up
Keeping the Bootstrap Capacitor Charged in Buck Converters
Managing Transients in Control IC Driven Power Stages
Simple High Side Drive Provides Fast Switching and Continuous On-Time
8.1
Infineon online forum resources
The Gate Driver Forum is live at Infineon Forums (www.infineonforums.com). This online forum
is where the Infineon gate driver IC community comes to the assistance of our customers to
provide technical guidance – how to use gate drivers ICs, existing and new gate driver information,
application information, availability of demo boards, online training materials for over 500 gate
driver ICs. The Gate Driver Forum also serves as a repository of FAQs where the user can review
solutions to common or specific issues faced in similar applications.
Register online at the Gate Driver Forum and learn the nuances of efficiently driving a power
switch in any given power electronic application.
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9
Revision history
Date of release
Document
version
1.0
Description of changes
April 10, 2022
Final Datasheet
Final Datasheet
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相关型号：
6EDL04
200 V and 600 V three-phase gate driver with Over Current Protection (OCP), Enable (EN), Fault and Integrated Bootstrap Diode (BSD)
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