2EDN752X [INFINEON]
EiceDRIVERâ¢;
| 型号： | 2EDN752X |
| 厂家： | 
Infineon |
| 描述： | EiceDRIVER⢠驱动 |
| 文件： | 总31页 (文件大小：1180K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EiceDRIVER™
2EDN752x / 2EDN852x
Features
Fast, precise, strong and compatible
•
Highly efficient SMPS enabled by 5 ns fast slew rates and 17 ns propagation delay precision for fast MOSFET
and GaN switching
•
•
•
1 ns channel-to-channel propagation delay accuracy enables safe use of two channels in parallel
Two independent 5 A channels enable numerous deployment options
Industry standard packages and pinout ease system-design upgrades
The new Reference in Ruggedness
•
•
•
4.2 V and 8 V UVLO (Under Voltage Lock Out) options ensure instant MOSFET protection under abnormal
conditions
-10 V control and enable input robustness delivers crucial safety margin when driving pulse-transformers or
driving MOSFETs in through hole packaging
5 A reverse current robustness eliminates the need for output protection circuitry.
Typical Applications
•
•
•
•
•
•
•
•
Server SMPS
TeleCom SMPS
DC-to-DC Converter
Bricks
Power Tools
Industrial SMPS
Motor Control
Solar SMPS
Example Topologies
•
•
•
Single and interleaved PFC
LLC, ZVS with pulse transformer
Synchronous Rectification
Description
The 2EDN752x/2EDN852x is an advanced dual-channel driver. It is suited to drive logic and normal level MOSFETs
and supports OptiMOSTM, CoolMOSTM, Standard Level MOSFETs, Superjunction MOSFETs, as well as IGBTs and
GaN Power devices.
Data Sheet
www.infineon.com
Please read the Important Notice and Warnings at the end of this document
Rev. 2.5
2018-04-20
EiceDRIVER™
2EDN752x / 2EDN852x
Features
The control and enable inputs are LV-TTL compatible (CMOS 3.3 V) with an input voltage range from -5 V to +20 V.
-10 V input pin robustness protects the driver against latch-up or electrical overstress which can be induced by
parasitic ground inductances. This greatly enhances system stability.
4.2 V and 8 V UVLO (Under Voltage Lock Out) options ensure instant MOSFET and GaN protection under abnormal
conditions. Under such circumstances, this UVLO mechanism provides crucial independence from whether and
when other supervisors circuitries detect abnormal conditions.
Each of the two outputs is able to sink and source 5 A currents utilizing a true rail-to-rail stage. This ensures very
low on resistance of 0.7 Ω up to the positive and 0.55 Ω down to the negative rail respectively. Very tight channel
to channel delay matching, typ. 1 ns, permits parallel use of two channels, leading to a source and sink capability
of 10 A. Industry leading reverse current robustness eliminates the need for Schottky diodes at the outputs and
reduces the bill-of-material.
The pinout of the 2EDN family is compatible with the industry standard. Two different control input options,
direct and inverted, offer high flexibility. Three package variants, DSO 8-pin, TSSOP 8-pin, WSON 8-pin, allow
optimization of PCB board space usage and thermal characteristics.
VDD
Load1
M1
Load2
2EDN752x /
2EDN852x
ENA
ENB
OUTA
VDD
1
8
Rg1
2
7
INA
GND
INB
3
6
M2
Rg2
5
4
OUTB
CVDD
Data Sheet
2
Rev.2.5
2018-04-20
EiceDRIVER™
2EDN752x / 2EDN852x
Table of Contents
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1
1.1
1.2
Product Versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Logic Versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Package Versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
3
Pin Configuration and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Input Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Driver Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Undervoltage Lockout (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1
4.2
4.3
4.4
4.5
5
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1
5.2
5.3
5.4
6
7
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Typical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8
Outline Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
PG-DSO-8-60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
PG-TSSOP-8-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
PG-WSON-8-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8.1
8.2
8.3
9
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Data Sheet
3
Rev.2.5
2018-04-20
EiceDRIVER™
2EDN752x / 2EDN852x
Product Versions
1
Product Versions
The 2EDN752x / 2EDN852x are available in 2 different logic, 2 different undervoltage lockout and 3 package
versions.
Table 1
Product Versions
Package
Type.
UVLO
Control Input Part Number
IC Topside
Marking Code
PG-DSO-8-60
4.2V
direct
2EDN7524F
2EDN7523F
2EDN8524F
2EDN8523F
2N7524AF
EiceDRIV
XXHYYWW
inverted
direct
2N7523AF
EiceDRIV
XXHYYWW
8V
2N8524AF
EiceDRIV
XXHYYWW
inverted
2N8523AF
EiceDRIV
XXHYYWW
PG-TSSOP-8-1
4.2V
8V
direct
2EDN7524R
2EDN7523R
2EDN8524R
2EDN8523R
2N7524
AR_XXX
HYYWW
inverted
direct
2N7523
AR_XXX
HYYWW
2N8524
AR_XXX
HYYWW
inverted
2N8523
AR_XXX
HYYWW
PG-WSON-8-3
4.2V
direct
2EDN7524G
2EDN7523G
2N7524
AG_XXX
HYYWW
inverted
2N7523
AG_XXX
HYYWW
Data Sheet
4
Rev.2.5
2018-04-20
EiceDRIVER™
2EDN752x / 2EDN852x
Product Versions
1.1
Logic Versions
The 2 logic versions are indicated by the variable x in the product version 2EDNy52x:
•
•
x=3: inverting input logic
x=4: non-inverting / direct input logic
The logic relations between inputs, enable pins and outputs are given in Table 2 for the inverting and non-
inverting version 2EDNx523 and 2EDNx524. The state of the driving output is defined by the state of the respective
input, if the enable inputs ENA and ENB are high (or left open). A logic “low” at an enable input or an undervoltage
lockout event, due to low voltage at VDD, causes the respective output to be low too, regardless of the input signal.
Functional description is shown in Chapter 3 ( Block Diagram) and Chapter 4 (Input Configurations).
Table 2
Logic Table
Inputs
Output Inverting
Output Standard
ENA
x
ENB
x
INA
INB
x
UVLO1)
active
OUTA
OUTB
OUTA
OUTB
x
L
L
L
L
L
L
x
x
inactive
inactive
inactive
inactive
inactive
inactive
inactive
inactive
inactive
L
L
L
L
H
H
L
L
L
H
x
x
H
L
L
L
L
L
x
L
H
L
L
H
H
H
H
H
H
L
L
H
L
L
L
x
H
L
L
L
H
L
H
H
H
H
L
H
L
H
H
L
H
H
L
L
L
H
L
L
H
H
H
H
H
L
L
H
1) Inactive means that VDD is above UVLO threshold voltage and release logic to control output stage.
Active means that UVLO disable active the output stages.
1.2
Package Versions
The logic and UVLO versions are available in 3 different packages.
•
•
•
a standard PG-DSO-8-60 (designated by “F”)
a small PG-TSSOP-8-1 (designated by “R”)
a leadless PG-WSON-8-3 (designated by “G”)
Drawings can be viewed in Chapter 8 (Outline Dimensions).
Data Sheet
5
Rev.2.5
2018-04-20
EiceDRIVER™
2EDN752x / 2EDN852x
Pin Configuration and Description
2
Pin Configuration and Description
The pin configuration for all input versions of 2EDN7524F, 2EDN7523F, 2EDN8524F and 2EDN8523F in the PG-
DSO-8-60 package is shown in Figure 1. Drawings can be viewed in Chapter 8 (PG-DSO-8-60).
ENA
INA
ENB
OUTA
VDD
1
2
3
4
8
7
6
5
GND
INB
OUTB
Figure 1
Table 3
Pin Configuration PG-DSO-8-60, Top View
Pin Configuration 2EDN7524F, 2EDN7523F, 2EDN8524F and 2EDN8523F in the PG-DSO-8-60
Package
Pin Symbol Description
1
ENA
Enable input channel A
Logic input; if ENA is high or left open, OUTA is controlled by INA; ENA low causes OUTA low
2
INA
Input signal channel A
Logic input, controlling OUTA (inverting or non-inverting)
3
4
GND
INB
Ground
Input signal channel B
Logic input, controlling OUTB (inverting or non-inverting)
5
6
7
8
OUTB
VDD
Driver output channel B
Low-impedance output with source and sink capability
Positive supply voltage
Operating range 4.5 V/8.6V to 20 V
OUTA
ENB
Driver output channel A
Low-impedance output with source and sink capability
Enable input channel B
Logic Input; if ENB is high or left open, OUTB is controlled by INB; ENB low causes OUTB low
Data Sheet
6
Rev.2.5
2018-04-20
EiceDRIVER™
2EDN752x / 2EDN852x
Pin Configuration and Description
The pin configuration for all input versions of 2EDN7524R, 2EDN7523R, 2EDN8524R and 2EDN8523R in the PG-
TSSOP-8-1 package is shown in Figure 2. Drawings can be viewed in Chapter 8 (PG-TSSOP-8-1).
1
2
3
4
ENA
INA
ENB
OUTA
VDD
8
7
6
5
Exposed
Pad
GND
INB
OUTB
Figure 2
Table 4
Pin Configuration PG-TSSOP-8-1, Top View
Pin Configuration 2EDN7524R, 2EDN7523R, 2EDN8524R and 2EDN8523R in the PG-TSSOP-8-1
Package
Pin Symbol Description
1
ENA
Enable input channel A
Logic input; if ENA is high or left open, OUTA is controlled by INA; ENA low causes OUTA low
2
INA
Input signal channel A
Logic input, controlling OUTA (non-inverting)
3
4
GND
INB
Ground1)
Input signal channel B
Logic input, controlling OUTB (non-inverting)
5
6
7
8
OUTB
VDD
Driver output channel B
Low-impedance output with source and sink capability
Positive supply voltage
Operating range 4.5 V/8.6V to 20 V
OUTA
ENB
Driver output channel A
Low-impedance output with source and sink capability
Enable input channel B
Logic Input; if ENB is high or left open, OUTB is controlled by INB; ENB low causes OUTB low
1) Exposed Pad sink of PG-TSSOP-8-1 packages has to be connected to GND pin.
Data Sheet
7
Rev.2.5
2018-04-20
EiceDRIVER™
2EDN752x / 2EDN852x
Pin Configuration and Description
The pin configuration for direct input versions of 2EDN7524G and 2EDN7523G in the PG-WSON-8-3 package is
shown in Figure 3. Drawings can be viewed in Chapter 8 (PG-WSON-8-3).
ENA 1
8
7
6
5
ENB
INA
GND
INB
2
OUTA
VDD
Exposed
Pad
3
4
OUTB
Figure 3
Table 5
Pin Configuration PG-WSON-8-3, Top View
Pin Configuration 2EDN7524G and 2EDN7523G in the PG-WSON-8-3 Package
Pin Symbol Description
1
ENA
Enable input channel A
Logic input; if ENA is high or left open, OUTA is controlled by INA; ENA low causes OUTA low
2
INA
Input signal channel A
Logic input, controlling OUTA (non-inverting)
3
4
GND
INB
Ground1)
Input signal channel B
Logic input, controlling OUTB (non-inverting)
5
6
7
8
OUTB
VDD
Driver output channel B
Low-impedance output with source and sink capability
Positive supply voltage
Operating range 4.5 V/8.6V to 20 V
OUTA
ENB
Driver output channel A
Low-impedance output with source and sink capability
Enable input channel B
Logic Input; if ENB is high or left open, OUTB is controlled by INB; ENB low causes OUTB low
1)Exposed Pad of PG-WSON-8-3 packages has to be connected to GND pin.
Data Sheet
8
Rev.2.5
2018-04-20
EiceDRIVER™
2EDN752x / 2EDN852x
Block Diagram
3
Block Diagram
A simplified functional block diagram for the non-inverted / direct version is given in Figure 4. Please refer to the
functional description section for more details in Chapter 4.
VDD
VDD
VDD
ENA
6
1
UVLO
400k
Logic A
OUTA
7
INA
2
100k
GND
GND
VDD
VDD
400k
ENB
INB
8
4
3
Logic B
OUTB
5
100k
GND
GND
GND
Figure 4
Block Diagram, direct input, pull-up/pull-down resistor configuration
Data Sheet
9
Rev.2.5
2018-04-20
EiceDRIVER™
2EDN752x / 2EDN852x
Block Diagram
A simplified functional block diagram for the inverted version is given in Figure 5. Please refer to the functional
description section for more details in Chapter 4.
VDD
VDD
VDD
ENA
6
1
UVLO
400k
400k
VDD
Logic A
OUTA
7
INA
2
GND
VDD
VDD
VDD
400k
400k
ENB
INB
8
4
3
Logic B
OUTB
5
GND
GND
GND
Figure 5
Block Diagram, inverting input, pull-up/pull-down resistor configuration
Data Sheet
10
Rev.2.5
2018-04-20
EiceDRIVER™
2EDN752x / 2EDN852x
Functional Description
4
Functional Description
4.1
Introduction
The 2EDN752x / 2EDN852x is a fast dual-channel driver for low-side switches. Two true rail-to-rail output stages
with very low output impedance and high current capability are chosen to ensure highest flexibility and cover a
high variety of applications.
The focus on robustness at the input and output side additionally gives this device a safety margin in critical
abnormal situations. An extended negative voltage range protects input pins against ground shifts. No current
flows over the ESD structure in the IC during a negative input level. All outputs are robust against reverse current.
The interaction with the power MOSFET, even reverse reflected power will be handled by the strong internal
output stage.
All inputs are compatible with LV-TTL signal levels. The threshold voltages with a typical hysteresis of 1.1 V are
kept constant over the supply voltage range.
Since the 2EDN752x / 2EDN852x aims particularly at fast-switching applications, signal delays and rise/fall times
have been minimized. Special effort has been made towards minimizing delay differences between the 2
channels to very low values of typically 1 ns.
4.2
Supply Voltage
The maximum supply voltage is 20 V. This high voltage can be valuable in order to exploit the full current
capability of 2EDN752x / 2EDN852x when driving very large MOSFETs. The minimum operating supply voltage is
set by the undervoltage lockout function to a typical default value of 4.2 V or of 8 V. This lockout function protects
power MOSFETs from running into linear mode with subsequent high power dissipation.
4.3
Input Configurations
As described in Chapter 1, 2EDN752x / 2EDN852x is available in 2 different configurations with respect to the logic
configuration of the 4 input pins (input plus enable).
The enable inputs are internally pulled up to a logic high voltage, i.e. the driver is enabled with these pins left
open. The direct PWM inputs are internally pulled down to a logic low voltage. This prevents a switch-on event
during power up and a not driven input condition. Version with inverted PWM input have an internal pull up
resistor to prevent unwanted switch-on.
All inputs are compatible with LV-TTL levels and provide a hysteresis of 1.1 V typ. This hysteresis is independent
of the supply voltage.
All input pins have a negative extended voltage range. This prevents cross current over single wires during GND
shifts between signal source (controller) and driver input.
4.4
Driver Outputs
The two rail-to-rail output stages realized with complementary MOS transistors are able to provide a typical 5 A
of sourcing and sinking current. This driver output stage has a shoot through protection and current limiting
behavior. After a switching event, current limitation is raised up to achieve the typical current peak for an
excellent fast reaction time of the following power MOS transistor.
The output impedance is very low with a typical value below 0.7 Ω for the sourcing p-channel MOS and 0.5 Ω for
the sinking n-channel MOS transistor. The use of a p-channel sourcing transistor is crucial for achieving true rail-
to-rail behaviour and avoiding a source follower’s voltage drop.
Data Sheet
11
Rev.2.5
2018-04-20
EiceDRIVER™
2EDN752x / 2EDN852x
Functional Description
Gate Drive Outputs held active low in case of floating inputs ENx, INx or during startup or power down once UVLO
is not exceeded. Under any situation, startup, UVLO or shutdown, outputs are held under defined conditions.
4.5
Undervoltage Lockout (UVLO)
The Undervoltage Lockout function ensures that the output can be switched to its high level only if the supply
voltage exceeds the UVLO threshold voltage. Thus it can be guaranteed, that the switch transistor is not switched
on if the driving voltage is too low to completely switch it on, thereby avoiding excessive power dissipation.
The UVLO level is set to a typical value of 4.2 V / 8 V (with hysteresis). UVLO of 4.2 V is normally used for logic level
based MOSFETs. For higher level, like standard and high voltage superjunction MOSFETS, an UVLO voltage of
typical 8 V is available.
Data Sheet
12
Rev.2.5
2018-04-20
EiceDRIVER™
2EDN752x / 2EDN852x
Characteristics
5
Characteristics
The absolute maximum ratings are listed in Table 6. Stresses beyond these values may cause permanent damage
to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
5.1
Absolute Maximum Ratings
Table 6
Absolute Maximum Ratings
Symbol
Parameter
Values
Typ.
Unit Note or Test Condition
Min.
-0.3
-10
Max.
22
Positive supply voltage
VVDD
VIN
V
V
Voltage at pins INA, INB, ENA,
ENB
22
Voltage at pins OUTA, OUTB
VOUT
-0.3
-2
VVDD+0.3
VVDD+0.3
V
Note1)
Repetitive pulse <200ns2)
V
Reverse current peak at pins
OUTA, OUTB
ISNKREV
ISRCREV
-5
5
Apk
< 500ns
Junction temperature
Storage temperature
ESD capability
TJ
-40
-55
150
150
1.5
°C
°C
kV
TS
VESD
Charged Device Mode
(CDM) 3)
ESD capability
VESD
2.5
kV
Human Body Model
(HBM) 4)
1) Voltage spikes resulting from reverse current peaks are allowed.
2) Values are verified by characterization on bench.
3) According to JESD22-C101
4) According to JESD22-A114
5.2
Thermal Characteristics
Table 7
Thermal Characteristics
Symbol
Parameter
Values
Typ.
Unit Note or Test Condition
Min.
Max.
Thermal resistance junction- RthJA25
ambient 1)
125
K/W
K/W
K/W
K/W
K/W
PG-DSO-8-60, Tamb=25°C
PG-DSO-8-60, Tamb=25°C
PG-DSO-8-60, Tamb=25°C
PG-DSO-8-60, Tamb=25°C
PG-DSO-8-60, Tamb=25°C
Thermal resistance junction- RthJC25
case (top) 2)
66
Thermal resistance junction- RthJB25
board 3)
62
Characterization parameter
junction-top 4)
ΨthJC25
16
Characterization parameter
junction-board 5)
ΨthJB25
55
Data Sheet
13
Rev.2.5
2018-04-20
EiceDRIVER™
2EDN752x / 2EDN852x
Characteristics
Table 7
Thermal Characteristics (continued)
Symbol
Parameter
Values
Typ.
Unit Note or Test Condition
Min.
Max.
Thermal resistance junction- RthJA25
ambient 1)
64
56
55
9
K/W
K/W
K/W
K/W
K/W
PG-TSSOP-8-1,
amb=25°C
PG-TSSOP-8-1,
amb=25°C
PG-TSSOP-8-1,
amb=25°C
PG-TSSOP-8-1,
amb=25°C
PG-TSSOP-8-1,
amb=25°C
T
Thermal resistance junction- RthJP25
case (top) 2)
T
Thermal resistance junction- RthJB25
board 3)
T
Characterization parameter
junction-top 4)
ΨthJC25
T
Characterization parameter
junction-board 5)
ΨthJB25
13
T
Thermal resistance junction- RthJA25
ambient 1)
61
54
52
8
K/W
K/W
K/W
K/W
K/W
PG-WSON-8-3,
Tamb=25°C
Thermal resistance junction- RthJP25
case (top) 2)
PG-WSON-8-3,
T
amb=25°C
PG-WSON-8-3,
amb=25°C
PG-WSON-8-3,
amb=25°C
PG-WSON-8-3,
amb=25°C
Thermal resistance junction- RthJB25
board 3)
T
Characterization parameter
junction-top 4)
ΨthJC25
T
Characterization parameter
junction-board 5)
ΨthJB25
11
T
1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-
standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a.
2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No
specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to
control the PCB temperature, as described in JESD51-8.
4) The characterization parameter junction-top, estimates the junction temperature of a device in a real system and is
extracted from the simulation data for obtaining Rth, using a procedure described in JESD51-2a (sections 6 and 7).
5) The characterization parameter junction-board, estimates the junction temperature of a device in a real system and
is extracted from the simulation data for obtaining Rth, using a procedure described in JESD51-2a (sections 6 and 7).
5.3
Operating Range
Table 8
Operating Range
Parameter
Symbol
Values
Typ.
Unit Note or Test Condition
Min.
4.5
-5
Max.
20
Supply voltage
VVDD
VIN
TJ
V
Min. defined by UVLO
Logic input voltage
Junction temperature
20
V
1)
-40
150
°C
1) Continuous operation above 125 °C may reduce life time.
Data Sheet
14
Rev.2.5
2018-04-20
EiceDRIVER™
2EDN752x / 2EDN852x
Characteristics
5.4
Electrical Characteristics
Unless otherwise noted, min./max. values of characteristics are the lower and upper limits respectively. They are
valid within the full operating range. The supply voltage is VVDD= 12 V. Typical values are given at TJ=25°C.
Table 9
Power Supply
Parameter
Symbol
Values
Typ.
Unit Note or Test Condition
Min.
0.5
Max.
1.2
VDD quiescent current
VDD quiescent current
IVDDQU1
IVDDQU2
0.7
mA
mA
OUT = high, VVDD= 12 V
OUT = low, VVDD= 12 V
0.3
0.48
0.7
Table 10 Undervoltage Lockout for Logic Level MOSFET
Parameter Symbol Values
Typ.
Unit Note or Test Condition
Min.
Max.
Undervoltage Lockout (UVLO) UVLOON 3.9
turn on threshold
4.2
3.9
0.3
4.5
V
V
V
Undervoltage Lockout (UVLO) UVLOOFF 3.6
turn off threshold
4.2
UVLO threshold hysteresis
UVLOHYS
Table 11 Undervoltage Lockout for Standard and Superjunction MOSFET Version
Parameter
Symbol
Values
Typ.
Unit Note or Test Condition
Min.
Max.
Undervoltage Lockout (UVLO) UVLOON 7.4
turn on threshold
8.0
7.0
1.0
8.6
V
V
V
Undervoltage Lockout (UVLO) UVLOOFF 6.5
turn off threshold
7.5
—
UVLO threshold hysteresis
UVLOHYS
—
Table 12 Logic Inputs INA, INB, ENA, ENB
Parameter
Symbol
Values
Unit Note or Test Condition
Min.
Typ.
Max.
Input voltage threshold for
transition LH
VINH
VINL
1.98
2.1
2.2
V
V
Input voltage threshold for
transition HL
0.95
1.02
1.1
Input pull up resistor1)
Input pull down resistor2)
RINH
RINL
400
100
kΩ
kΩ
1) Inputs with initial high logic level
2) Inputs with initial low logic level
Data Sheet
15
Rev.2.5
2018-04-20
EiceDRIVER™
2EDN752x / 2EDN852x
Characteristics
Table 13 Static Output Caracteristics (see Figure 7)
Parameter
Symbol
Values
Typ.
Unit Note or Test Condition
Min.
Max.
High Level (Sourcing) Output RONSRC
Resistance
0.35
0.7
1.2
Ω
A
ISRC = 50mA
1)
High Level (Sourcing) Output ISRCPEAK
Current
5.0
Low Level (Sinking) Output
Resistance
RONSNK
0.28
0.55
-5.0
1.0
Ω
A
ISNK = 50mA
2)
Low Level (Sinking) Output
Current
ISNKPEAK
1) Active limited by design at approx. 6.5Apk, parameter is not subject to production test - verified by design /
characterization, max. power dissipation must be observed
2) Active limited by design at approx. -6.5Apk, parameter is not subject to production test - verified by design /
characterization, max. power dissipation must be observed
Table 14 Dynamic Characteristics (see Figure 6, Figure 7, Figure 8 and Figure 9)
Parameter
Symbol
Values
Typ.
Unit Note or Test Condition
Min.
Max.
Input/Enable to output
propagation delay
TPDlh
15
17
23
ns
ns
ns
CLOAD= 1.8 nF, VVDD= 12 V;
low to high transition at
Input/Enable
Input/Enable to output
propagation delay
TPDhl
15
19
23
2
CLOAD= 1.8 nF, VVDD= 12 V
high to low transition at
Input/Enable
Input/Enable to output
propagation delay mismatch
between the two channels on
the same IC
delta tPD
Rise Time
Fall Time
TRISE
TFAll
TPW
—
—
—
5.3
4.5
6
10 1)
10 1)
10 1)
ns
ns
ns
CLOAD= 1.8 nF, VVDD= 12 V
CLOAD= 1.8 nF, VVDD= 12 V
CLOAD= 1.8 nF, VVDD= 12 V
Minimum input pulse width
that changes output state
1) Parameter verified by design, not 100% tested in production.
Data Sheet
16
Rev.2.5
2018-04-20
EiceDRIVER™
2EDN752x / 2EDN852x
Timing Diagrams
6
Timing Diagrams
Figure 6 shows the definition of rise, fall and delay times for the inputs of the non-inverting / direct version (with
Enable pin high or open).
ENx (high)
VIN H
VINL
VIN H
VINL
INx
90%
10%
OUT
TRIS E
TFAL L
TPDON
TPDOF F
Figure 6
Propagation delay, rise and fall time, non-inverted
Figure 7 shows the definition of rise, fall and delay times for the inputs of the inverting version (with enable pins
high or open).
(high)
ENx
VINH
VIN L
INx
VINH
VINL
90%
10%
OUT
TRIS E
TFAL L
TPDON
TPDOF F
Figure 7
Propagation delay, rise and fall Time, inverted
Figure 8 illustrates the undervoltage lockout function.
UVLOON
UVLOOFF
VDD
OUT
Figure 8
UVLO behaviour, input ENx and INx drives OUTx normally high
Data Sheet
17
Rev.2.5
2018-04-20
EiceDRIVER™
2EDN752x / 2EDN852x
Timing Diagrams
Figure 9 illustrates the minimum input pulse width that changes output state.
ENx (high)
VIN H
VINL
VIN H
VIN L
INx
TPW
90%
OUTx
Figure 9
TPW, minimum input pulse width that changes output state
Data Sheet
18
Rev.2.5
2018-04-20
EiceDRIVER™
2EDN752x / 2EDN852x
Typical Characteristics
7
Typical Characteristics
UVLO ON/OFF
vs
TEMPERATURE
UVLO HYSTERESIS
vs
TEMPERATURE
4.5
4.3
4.1
3.9
3.7
0.4
0.35
0.3
on value
off value
0.25
0.2
Inx, ENx high
Indication Outx
Inx, ENx high
Indication Outx
-50
0
50
100
150
-50
0
50
100
150
T junction [°C]
T junction [°C]
Figure 10 Undervoltage lockout 2ED7x (4.2V)
UVLO ON/OFF
vs
TEMPERATURE
UVLO HYSTERESIS
vs
TEMPERATURE
1.05
1
8.8
on value
off value
8.4
8
0.95
0.9
7.6
7.2
6.8
6.4
Inx, ENx high
Indication Outx
Inx, ENx high
Indication Outx
0.85
-50
0
50
100
150
-50
0
50
T junction [°C]
100
150
T junction [°C]
Figure 11 Undervoltage lockout 2ED8x (8V)
Data Sheet
19
Rev.2.5
2018-04-20
EiceDRIVER™
2EDN752x / 2EDN852x
Typical Characteristics
INPUT THRESHOLD INx to OUTx
INx HYSTERESIS
vs
vs
TEMPERATURE
TEMPERATURE
1.2
1.1
1
typ ON threshold
typ OFF threshold
2.5
2
1.5
1
VDD=12V
VDD=12V
100 150
0.9
0.5
-50
0
50
100
150
-50
0
50
T junction [°C]
T junction [°C]
Figure 12 Input (INx) characteristic
INPUT THRESHOLD ENx to OUTx
ENx HYSTERESIS
vs
TEMPERATURE
vs
TEMPERATURE
1.2
1.1
1
typ ON threshold
typ OFF threshold
2.5
2
1.5
1
VDD=12V
VDD=12V
0.5
0.9
-50
0
50
100
150
-50
0
50
100
150
T junction [°C]
T junction [°C]
Figure 13 Input (ENx) characteristic
Data Sheet
20
Rev.2.5
2018-04-20
EiceDRIVER™
2EDN752x / 2EDN852x
Typical Characteristics
VINx to OUTx PROPAGATIONDELAY
VINx to OUTx PROPAGATIONDELAY
vs
vs
TEMPERATURE
TEMPERATURE
25
22.5
20
25
22.5
20
typ input rise-up
typ input rise-up
typ input fall-down
typ input fall-down
17.5
15
17.5
15
VDD=12V
Input 5V
VDD=12V
Input 3.3V
12.5
-50
0
50
100
150
-50
0
50
100
150
T junction [°C]
T junction [°C]
Figure 14 Propagation delay (INx) on different input logic levels (see Figure 6)
VINx to OUTx PROPAGATIONDELAY
VENx to OUTx PROPAGATIONDELAY
vs
vs
TEMPERATURE
TEMPERATURE
25
22.5
20
25
22.5
20
typ input rise-up
typ input rise-up
typ input fall-down
typ input fall-down
17.5
15
17.5
15
VDD=12V
Input 3.3V
VDD=12V
Enable 5V
-50
0
50
100
150
-50
0
50
100
150
T junction [°C]
T junction [°C]
Figure 15 Propagation delay (ENx) on different input logic levels (see Figure 6)
Data Sheet
21
Rev.2.5
2018-04-20
EiceDRIVER™
2EDN752x / 2EDN852x
Typical Characteristics
OUTx RISE/FALLTIME 10%- 90%
vs
TEMPERATURE
6.5
6
typ turn-on
typ turn-off
5.5
5
4.5
4
VDD=12V
OUTx with 1.8nF load
3.5
-50
0
50
100
150
T junction [°C]
Figure 16 Rise / fall times with load on output (see Figure 6)
Data Sheet
22
Rev.2.5
2018-04-20
EiceDRIVER™
2EDN752x / 2EDN852x
Typical Characteristics
CURRENT CONSUMPTION
CURRENT CONSUMPTION
vs
vs
OPERATING SUPPLYVDD
TEMPERATURE
0.80
0.70
0.60
0.50
0.40
0.30
OUTx High
OUTx Low
0.8
0.6
0.4
0.2
OUTx High
VDD=12V
Tj=25°C
ENx floating (VDD)
ENx NC
OUTx Low
0
10
VDD [V]
20
-50
0
50
100
150
T junction [°C]
CURRENT CONSUMPTION
vs
FREQUENCY
50
40
30
20
10
0
Tamb 25°C
Input 50%@3.3V
Device self-heating
Load 1.8nF serial
VDD 4,5V
VDD 12V
VDD 20V
0
250
500
Frequency [kHz]
750
1000
Figure 17 Power consumption related to temperature, supply voltage and frequency
Data Sheet
23
Rev.2.5
2018-04-20
EiceDRIVER™
2EDN752x / 2EDN852x
Typical Characteristics
REVERSECURRENT @OUTx
with OUTx HIGH
REVERSECURRENT @OUTx
with OUTx LOW
vs REVERSEVOLTAGE
vs REVERSEVOLTAGE
-1.5
-3.0
-4.5
-6.0
-7.5
7.5
6.0
4.5
3.0
1.5
0.0
Test Conditions:
Tj = 25°C,
1µs negative Pulse
fsw = 1kHz
VDD = 12V
TestConditions:
Tj = 25°C,
1µs positive Pulse
fsw = 1kHz
2.5 W
10 W
VDD = 12V
5 W
7.5 W
5 W
7.5 W
2.5 W
10 W
0.75
1.00
1.25
1.50
1.75
2.00
-2.25
-2.00
-1.75
-1.50
VOUT [V]
-1.25
-1.00
-0.75
VOUT [V] - VDD
Figure 18 Output OUTx with reverse current and resulting power dissipation
Data Sheet
24
Rev.2.5
2018-04-20
EiceDRIVER™
2EDN752x / 2EDN852x
Outline Dimensions
8
Outline Dimensions
Notes
1. For further information on package types, recommendation for board assembly, please go to:
http://www.infineon.com/cms/en/product/technology/packages/.
8.1
PG-DSO-8-60
Figure 19 PG-DSO-8-60 outline
Figure 20 PG-DSO-8-60 footprint
Data Sheet
25
Rev.2.5
2018-04-20
EiceDRIVER™
2EDN752x / 2EDN852x
Outline Dimensions
0.3
8
1.75
2.1
6.4
Figure 21 PG-DSO-8-60 packaging
8.2
PG-TSSOP-8-1
Figure 22 PG-TSSOP-8-1 outline
Data Sheet
26
Rev.2.5
2018-04-20
EiceDRIVER™
2EDN752x / 2EDN852x
Outline Dimensions
Figure 23 PG-TSSOP-8-1 footprint
Figure 24 PG-TSSOP-8-1 packaging
Data Sheet
27
Rev.2.5
2018-04-20
EiceDRIVER™
2EDN752x / 2EDN852x
Outline Dimensions
8.3
PG-WSON-8-3
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Figure 26 PG-WSON-8-3 footprint
Data Sheet
28
Rev.2.5
2018-04-20
EiceDRIVER™
2EDN752x / 2EDN852x
Outline Dimensions
ꢂ
ꢄ
3,1 ꢀ
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Figure 27 PG-WSON-8-3 packaging
Data Sheet
29
Rev.2.5
2018-04-20
EiceDRIVER™
2EDN752x / 2EDN852x
Revision History
9
Revision History
Page/ Item
Subjects (major changes since previous revision)
Responsible
Rev. 2.5, 2018-04-20
29
Update package diagram for PG-WSON
Vincent Zhang
Rev. 2.4, 2017-08-18
updated from version 2.3
correct typo (VOUT [V] - VDD),
add detail for test condition (VDD = 12V) Figure 18
Tobias Gerber
Tobias Gerber
24
13
add min. voltage reference for OUTA, OUTB in reverse current condition.
(Note 1) Table 6
Data Sheet
30
Rev.2.5
2018-04-20
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