2ED4820-EM [INFINEON]
48 V smart high-side MOSFET gate driver with SPI for automotive applications;
| 型号： | 2ED4820-EM |
| 厂家： | 
Infineon |
| 描述： | 48 V smart high-side MOSFET gate driver with SPI for automotive applications |
| 文件： | 总45页 (文件大小：1213K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EiceDRIVER™ APD 2ED4820-EM
48 V smart high-side MOSFET gate driver with SPI
Features
•
•
•
•
•
•
Extended supply voltage range: 20 - 70 V
Two independent high-side gate driver outputs
1 A pull down, 0.3 A pull up for fast switch off/on
Device control, configuration and diagnostic via SPI
Low supply current in sleep mode IBAT_Q < 5 µA
Supports back-to-back MOSFET topologies (common drain
and common source)
•
One bidirectional high or low-side analog current sense
interface with configurable gain
•
•
•
Configurable overcurrent/short circuit protection
Gate undervoltage lock-out
Safe state mode (both channels OFF) activated by direct
input pin
Package
Marking
PG-TSDSO-24
2ED4820-EM
•
Ground loss detection
Potential applications
•
•
•
48 V battery protection switch
48 V input protection switch for DCDC converters, motor control unit etc.
48 V relay and fuse replacement
CVBAT
Low
Ohmic
Path
CVCP
CCPHL
CPL
5V or
3.3V
VBAT VCP CPH
RG
VDD
GA
SA
CVDD
RGS
2ED4820-EM
MCU
RProt
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
CSN
SCLK
MOSI
MISO
Capacitor
Pre-Charge
Path
48V
Battery
cells
RG
INTERRUPT
ENABLE
SAFESTATEN
GB
SB
RGS
ADC
CSO
RFiltCSO
CFiltCSO
RPreCh
RFiltSh
CFiltSh
RFiltSh
ISN
ISP
Shunt
Freewheel.
diode
LOAD(s)
AGND
GND EP
CPGND
Figure 1
48 V battery main switch application diagram
Product validation
Qualified for automotive applications. Product validation according to AEC-Q100 grade 1.
Datasheet
www.infineon.com
Please read the sections "Important notice" and "Warnings" at the end of this document
Rev. 1.10
2022-12-20
EiceDRIVER™ APD 2ED4820-EM
48 V smart high-side MOSFET gate driver with SPI
Description
Description
2ED4820-EM is a gate driver designed for high current 48 V automotive applications, with powerful gate outputs
to drive many MOSFETs in parallel in order to minimize the conduction losses. It supports the back-to-back
configuration, both common source and common drain structures, thanks to its two gate outputs.
In common source configuration, one gate output can be used to pre-charge highly capacitive loads.
2ED4820-EM generates the supply for the gate outputs based on an integrated one-stage charge pump
with external pump and tank capacitors.
2ED4820-EM comes with an SPI interface, for easy configuration, diagnosis and control.
Several protection mechanisms are provided:
•
•
•
Supply under- and overvoltage detection with configurable restart timer
Charge pump undervoltage detection
Gate to source undervoltage detection with immediate lock-out to prevent linear mode conduction of the
MOSFETs
•
•
Configurable drain to source overvoltage detection, which can also be deactivated
Configurable overcurrent protection based on an analog current sense amplifier compatible for high-side
or low-side shunt topologies
•
Internal overtemperature warning and protection
An interrupt pin informs the MCU whenever one of these protections is triggered. Status registers can then be
read by the MCU to understand what was the trigger for the notification.
The output of the current sense amplifier can be monitored by the MCU to implement additional protections,
such as wire overtemperature.
In addition, 2ED4820-EM enables to implement an open load detection mechanism, checking the source
voltage of the MOSFETs with respect to ground in the OFF state.
Datasheet
2
Rev. 1.10
2022-12-20
EiceDRIVER™ APD 2ED4820-EM
48 V smart high-side MOSFET gate driver with SPI
Table of contents
Table of contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Potential applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Product validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
1
2
3
General product characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Functional range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1
3.2
3.3
4
4.1
4.2
4.2.1
4.2.2
4.2.3
4.2.4
4.3
General product description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Operation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Safe state mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Reset behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Electrical characteristics: supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Electrical characteristics: digital IOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Electrical characteristics: charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
4.4
4.5
4.6
5
High-side gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Channel activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Channel deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
MOSFET driver output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1
5.2
5.3
6
6.1
Protection and monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Monitorings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Source voltage monitoring in OFF state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Charge pump voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
SPI address monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Warnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Temperature warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
One time programmable (OTP) memory data corruption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Ground loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Failures detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Failure notification and clearing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.1.1
6.1.2
6.1.3
6.2
6.2.1
6.2.2
6.2.3
6.3
6.3.1
Datasheet
3
Rev. 1.10
2022-12-20
EiceDRIVER™ APD 2ED4820-EM
48 V smart high-side MOSFET gate driver with SPI
Table of contents
6.3.2
Non-latching failures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.3.2.1
6.3.2.2
6.3.3
VBAT overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
VBAT undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Latching failures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Blank time and filter time for failures detections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Blank time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Filter time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Drain-source overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Gate-source undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Channel cross-control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
VDD undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
VCP undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
SAFESTATEN activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Overtemperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Current sense amplifier and overcurrent comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Gain configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Current sense position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Current sense output load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Overcurrent detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Electrical characteristics: current sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
INTERRUPT pin control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Electrical characteristics: protection and monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.3.3.1
6.3.3.1.1
6.3.3.1.2
6.3.3.2
6.3.3.3
6.3.3.4
6.3.3.5
6.3.3.6
6.3.3.7
6.3.3.8
6.3.3.9
6.3.3.9.1
6.3.3.9.2
6.3.3.9.3
6.3.3.9.4
6.3.3.9.5
6.4
6.5
7
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Communication start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Communication end . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
SPI: electrical characteristics: timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Daisy Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
SPI Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.1
7.2
7.3
7.4
7.5
8
Register specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8.1
Control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
48 V battery protection switch with low-side current sense and capacitive pre-charge . . . . . . . . .40
Common drain with high-side current sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.1
9.2
9.3
10
Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Datasheet
4
Rev. 1.10
2022-12-20
EiceDRIVER™ APD 2ED4820-EM
48 V smart high-side MOSFET gate driver with SPI
1 Block diagram
1
Block diagram
undervoltage and
overvoltage detection
ENABLE
Charge pump
VDD
Internal
supply
Internal temperature
warning & shutdown
VBAT
VCP
Control logic
MOSI
MISO
SCLK
CSN
16-bit
SPI
VDS
overvoltage
Ich
GA
SA
VGS
undervoltage
OTP
Idisch
18V
VS
SAFESTATEN
INTERRUPT
monitoring
Diagnostics
&
protections
VBAT
VCP
MOSFET
activation
VDS
Ich
overvoltage
CSA gain
config
GB
SB
VGS
undervoltage
Idisch
18V
Overcurrent
config
VS
monitoring
DVOCTHnH
* R=2.5kW typ.
GDIFF x R*
R*
R*
ISN
ISP
≥1
ITrip
DVOCTHnL
VREF_BIDIR = VDD/2
CSO
EP AGND CPGND GND
Figure 2
Block diagram
Datasheet
5
Rev. 1.10
2022-12-20
EiceDRIVER™ APD 2ED4820-EM
48 V smart high-side MOSFET gate driver with SPI
2 Pin configuration
2
Pin configuration
SAFESTATEN
INTERRUPT
SCLK
1
24
23
22
21
20
19
18
17
16
15
14
13
VBAT
VCP
CPH
CPL
NC
2
3
CSN
4
MOSI
MISO
5
6
CPGND
GA
ENABLE
VDD
7
8
SA
CSO
9
NC
ISN
10
11
12
SB
ISP
GB
exposed pad
(bottom)
AGND
GND
Figure 3
Pin assignment
Table 1
Pin definitions and functions
Pin No. Function
Symbol
SAFESTATEN
INTERRUPT
SCLK
Comment
1
µController
µController
SPI
Watchdog connection for safe state mode
Interrupt signal output
2
3
SPI clock input with internal pull-down
Chip select not with internal pull-up
Master out slave in with internal pull-down
Master in slave out
4
SPI
CSN
5
SPI
MOSI
6
SPI
MISO
7
µController
Supply
ENABLE
VDD
Switch device ON/OFF with internal pull-down
Main supply
8
9
µController
V-Sensing
V-Sensing
Supply
CSO
Current sense amplifier output
Negative input for shunt voltage
Positive input for shunt voltage
Analog GND
10
11
12
13
14
15
16
17
18
19
20
21
22
ISN
ISP
AGND
GND
Supply
Common usage ground
Gate connection
GB
Gate connection to channel B
Source connection to channel B
Not connected
Source connection SB
NC
Source connection SA
Source connection to channel A
Gate connection to channel A
Charge pump GND
Gate connection
Supply
GA
CPGND
NC
Not connected
ChargePump
ChargePump
CPL
CPH
Negative terminal of CP capacitor
Positive terminal of CP capacitor
(table continues...)
Datasheet
6
Rev. 1.10
2022-12-20
EiceDRIVER™ APD 2ED4820-EM
48 V smart high-side MOSFET gate driver with SPI
2 Pin configuration
Table 1
(continued) Pin definitions and functions
Pin No. Function
Symbol
VCP
Comment
23
24
ChargePump
Supply
Charge pump output / connection buffer capacitor
VBAT
E.P.
48 V supply
Exposed pad (for cooling purpose only, do not use as electrical
GND)
Datasheet
7
Rev. 1.10
2022-12-20
EiceDRIVER™ APD 2ED4820-EM
48 V smart high-side MOSFET gate driver with SPI
3 General product characteristic
3
General product characteristic
3.1
Absolute maximum ratings
Unless otherwise specified: TJ = -40°C to +150°C; all voltages are referenced to GND.
Table 2
Absolute maximum ratings
Parameter
Symbol
Values
Typ.
Unit Note or condition
P-
Number
Min.
-0.3
Max.
105
1)
VBAT supply voltage
VBAT
–
V
PRQ-9
1)
Gate voltage with respect VGx_S
to Source
-0.3
–
18
V
PRQ-11
1)
Gate voltage with respect VGx_BAT
to VBAT
-80
–
18
V
PRQ-10
1)
Gate voltage
VGx
-80
-90
-90
–
–
–
VCP
105
2
V
PRQ-12
PRQ-199
PRQ-92
1)
Source voltage
VSx
V
1)
Source voltage with
respect to VBAT
VSx_VBAT
V
1)
VDD logic supply voltage
Current sense
VDD
-0.3
–
5.5
V
PRQ-98
1)
ISP and ISN voltage
VISP, VISN
-6
–
–
105
2
V
PRQ-13
1)
ISP and ISN voltage with
respect to VBAT
VISP_ISN_VBAT -105
V
PRQ-542
1)
ISP and ISN differential
VISP_ISN_DIFF -5
–
–
5
V
PRQ-204
PRQ-97
voltage
1)
CSO voltage
VCSO
-0.3
-0.3
VDD+0.3 V
VDD+0.3 V
Logic
1)
1)
Logic input voltages (SCLK, VSCLK, VCSN
CSN, MOSI, SAFESTATEN,
ENABLE)
,
–
–
PRQ-94
PRQ-96
VMOSI
VSAFESTATEN
VENABLE
,
,
Logic output voltages
(MISO, INTERRUPT)
VMISO
VINTERRUPT
,
-0.3
VDD+0.3 V
Charge pump
1)
1)
Charge pump voltage
(VCP)
VCP
-0.3
-0.3
-0.3
–
–
–
105
18
V
V
PRQ-337
PRQ-400
Charge pump voltage
(VCP) with respect to VBAT
VCP_VBAT
1)
1)
Charge pump voltage (CPL) VCPL
VBAT
V
V
PRQ-95
Charge pump voltage
(CPH)
VCPH
VBAT-0.3 –
VCP+0.3
PRQ-261
(table continues...)
Datasheet
8
Rev. 1.10
2022-12-20
EiceDRIVER™ APD 2ED4820-EM
48 V smart high-side MOSFET gate driver with SPI
3 General product characteristic
Table 2
(continued) Absolute maximum ratings
Parameter
Symbol
Values
Typ.
Unit Note or condition
P-
Number
Min.
Max.
0.3
1)
Charge pump ground and VCPGND, VAGND -0.3
analog ground voltage
–
V
PRQ-205
Temperature
1)
Junction temperature
Storage temperature
ESD susceptibility
TJ
-40
-55
–
–
150
150
°C
PRQ-17
PRQ-19
1)
TSTG
°C
ESD susceptibility at all
pins (HBM)
VESD_HBM1
-2
–
–
–
–
2
kV
kV
V
1) 2) HBM
1) 2) HBM
1) 3) CDM
1) 3) CDM
PRQ-20
ESD susceptibility of VBAT VESD_HBM2
pin versus GND (HBM)
-4
4
PRQ-100
PRQ-401
PRQ-414
ESD susceptibility at all
pins (CDM)
VESD_CDM
VESD_CDM
-500
-750
500
750
ESD susceptibility at
corner pins (CDM) (pins 1,
12, 13, 24)
V
1)
2)
3)
Not subject to production test, specified by design.
ESD susceptibility, human body model "HBM", according to AEC Q100-002
ESD susceptibility, charged device model "CDM", according to AEC Q100-011
3.2
Functional range
Unless otherwise specified: VBAT and VDD inside the normal operation range; TJ = -40°C to +150°C; all voltages
are referenced to GND; positive current flowing into pin.
Table 3
Functional range
Symbol
Parameter
Values
Typ.
Unit Note or condition
P-
Number
Min.
24
Max.
54
VBAT supply voltage range VBAT(NORM)
for normal operation
–
V
–
PRQ-101
PRQ-102
PRQ-397
VBAT extended supply
voltage range
VBAT(EXT)
20
–
–
70
10
V
Parameter
deviations possible
1)
VBAT supply transients
slew rate
dVBAT/dt
-10
V/µs
Logic supply voltage (VDD) VDD
3.0
-10
–
–
5.5
10
V
–
1)
PRQ-105
PRQ-398
VDD logic supply transients dVDD/dt
slew rate
V/µs
SPI logic input voltage
VSCLK, VCSN
VMOSI
,
0
–
VDD
V
–
PRQ-106
(table continues...)
Datasheet
9
Rev. 1.10
2022-12-20
EiceDRIVER™ APD 2ED4820-EM
48 V smart high-side MOSFET gate driver with SPI
3 General product characteristic
Table 3
(continued) Functional range
Parameter
Symbol
Min.
Values
Typ.
Unit Note or condition
P-
Number
Max.
70
1)
Source voltage transients dVSx/dt
slew rate
-70
–
V/µs
PRQ-399
PRQ-107
Logic input voltage
VSAFESTATEN
VENABLE
,
0
–
VDD
V
–
CSO output current
ISP, ISN input voltage
ICSO
-4
-2
–
–
0
mA
V
–
–
PRQ-355
PRQ-508
VISP, VISN
VBAT +
2
1)
1)
ISP, ISN common mode
slew rate
VSENSE_COMMO -70
N
–
–
–
70
V/µs
V/µs
°C
PRQ-491
PRQ-492
PRQ-18
ISP, ISN differential mode VSENSE_DIFFERE -5
slew rate
5
NTIAL
Junction temp
TJ
-40
150
–
1)
Not subject to production test, specified by design.
3.3
Thermal resistance
TJ = -40°C to +150°C.
Table 4
Thermal resistance
Symbol
Parameter
Values
Typ.
Unit Note or condition
P-
Number
Min.
Max.
1)
Junction to case, TA =
-40°C
RthJC_cold
–
4
–
K/W
PRQ-99
1)
Junction to case, TA = 85°C RthJC_hot
–
–
5
–
–
K/W
PRQ-71
PRQ-72
1) 2)
Junction to ambient, TA = RthJA_cold_2s2p
-40°C
38
31
K/W
1) 2)
Junction to ambient, TA = RthJA_hot_2s2p
85°C
–
–
K/W
PRQ-73
1)
2)
Not subject to production test, specified by design.
Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; the product (chip+package)
was simulated on a 76.2 × 114.3 × 1.5 mm board with 2 inner copper layers (2 × 70 µm Cu, 2 × 35 µm Cu). Where applicable a
thermal via array under the exposed pad contacted the first inner copper layer. The device is dissipating 1 W power.
Datasheet
10
Rev. 1.10
2022-12-20
EiceDRIVER™ APD 2ED4820-EM
48 V smart high-side MOSFET gate driver with SPI
4 General product description
4
General product description
4.1
Power supply
The device is externally supplied by two pins: VDD and VBAT.
The gate driver requires multiple power supplies:
•
•
•
VBAT supplies the charge pump and parts of the gate control block
VDD supplies SPI interface, internal logic, protection functions as well as the current sense interface
Internally generated charge pump voltage VCP supplies the gate control block, VDS and VGS detection
blocks and current sense amplifier
4.2
Operation mode
SLEEP
Channels OFF
ENABLE = 1
AND VDD ON
ENABLE = 0
OR VDD OFF
NORMAL
Channels’ state defined
by MOSONCH_(x)
ENABLE = 0
OR VDD OFF
Failure occurs
OR SAFESTATEN = 0
Failure flags cleared
AND SAFESTATEN = 1
SAFE STATE
Channels OFF
Figure 4
Operation modes overview
4.2.1
Normal mode
The device enters normal mode afer the SPI setup time tSET_SPI, if the microcontroller sets the pin ENABLE to
high.
In normal mode, the MOSFET gate driver is enabled and can be configured through the SPI interface, provided
that the voltages applied to VBAT and VDD are within the operating range.
4.2.2
Sleep mode
The device enters sleep mode if the microcontroller sets the ENABLE pin to low.
In sleep mode, most of the internal circuitry is deactivated: the current consumption of VBAT and VDD is
reduced respectively to IVBAT_Q and IVDD_Q
.
4.2.3
Safe state mode
The device will enter safe state if the pin SAFESTATEN is set to low.
In safe state the external MOSFETs of both channels are deactivated (e.g. switched off).
Datasheet
11
Rev. 1.10
2022-12-20
EiceDRIVER™ APD 2ED4820-EM
48 V smart high-side MOSFET gate driver with SPI
4 General product description
To bring the device from safe state back to normal mode, the pin SAFESTATEN has to be set to high and the
failure flag SAFESTATE must be cleared via SAFESTATE_CL or FAIL_RST_0 together with FAIL_RST_1.
If the microcontroller sets the ENABLE pin to low, the device enters the sleep mode.
4.2.4
Reset behavior
Afer the ENABLE pin is pulled high or afer an undervoltage event at VDD, the logic content is reset.
In both cases, the failure flag VDD_UV is set to high to indicate that a reset was performed.
4.3
Charge pump
The charge pump generates the positive supply for the gate control block, for the VGS and VDS comparators and
for the current sense amplifier.
VCP_PUMP thresholds define hysteresis control of the charge pump output voltage by activating/deactivating
charge pumping.
VCP_READY thresholds flag the microcontroller that the charge pump output voltage is high enough to activate a
channel.
VCP_UV thresholds flag a charge pump output under voltage failure. In this case, turning on and protecting a
channel cannot be ensured any more, so the channels are switched off.
VCP pulled down
VCP - VBAT
externally
VCP_PUMP_H
VCP_PUMP_L
VCP_READY_H
VCP_READY_L
VCP_UV_H
VCP_UV_L
t
VCP_PUMP
t
VCP_READY
t
VCP_UV
t
t < tVCP_UV_BLK
Figure 5
Charge pump operating
The charge pump is ready to operate according the VCP_PUMP signal when the following condition is fulfilled:
ENABLE = high AND TSD = low AND VBAT_OV = low AND VCP_UV = low.
At the first activation of the charge pump, the VCP_UV diagnostic will be blanked for the tVCP_UV_BLK duration in
order to operate a safe start.
Datasheet
12
Rev. 1.10
2022-12-20
EiceDRIVER™ APD 2ED4820-EM
48 V smart high-side MOSFET gate driver with SPI
4 General product description
Note that a triggering of VCP_UV will therefore switch off the charge pump in a latched way.
The VCP_PUMP signal is controlling the charge pump activity:
•
•
When the charge pump is enabled it is pumping as long as the VCP_PUMP signal is high
As soon as the VCP - VBAT voltage gets above the VCP_PUMP_H threshold, the VCP_PUMP signal is turned low
and the charge pump stops pumping
•
As soon as the VCP - VBAT voltage gets below the VCP_PUMP_L threshold, the VCP_PUMP signal is turned high
and the charge pump is pumping
The VCP_READY bit is set to 1 once the VCP - VBAT voltage gets higher than the VCP_READY_H threshold.
The VCP_READY bit is set to 0 once the VCP - VBAT voltage gets lower than the VCP_READY_L threshold.
The VCP_UV bit is set to 0 once the VCP - VBAT voltage gets higher than the VCP_UV_H threshold.
The VCP_UV bit is set to 1 once the VCP - VBAT voltage gets lower than the VCP_UV_L threshold.
VCP_UV is blanked for a duration of tVCP_UV_BLK afer charge pump gets enabled (e.g.: afer device enable or
afer clearing VCP_UV failure flag).
4.4
Electrical characteristics: supply
Unless otherwise specified: VBAT and VDD inside the normal operation range; TJ = -40°C to +150°C; CSO pin lef
open; all voltages are referenced to GND; positive current flowing into pin.
Table 5
Electrical characteristics: supply
Symbol Values
Typ.
Parameter
Unit Note or condition
P-
Number
Min.
Quiescent current consumption, ENABLE = LOW
Max.
VBAT supply quiescent
current
IBAT_Q
–
–
–
5
7
µA
µA
1) TA ≤ 85°C
PRQ-112
PRQ-114
1)
VDD logic supply quiescent IDD_Q
current
–
TA ≤ 85°C
Current consumption, ENABLE = HIGH
1)
VBAT supply current
IBAT_SUP
–
–
10
mA
MOSONCH_A = 1; PRQ-27
MOSONCH_B = 1;
RGS ≥ 1 MΩ;
CVCP = 2.2 µF
VDD logic supply current
VDD logic supply current
IDD_SUP
IDD_SUP
–
–
–
–
10
15
mA
mA
CSA_HSS = 0;
PRQ-118
PRQ-543
CSA_COUTSEL = 0
1) CSA_HSS = 1;
CSA_COUTSEL = 1
1)
Not subject to production test, specified by characterization.
4.5
Electrical characteristics: digital IOs
Unless otherwise specified: VBAT and VDD inside the normal operation range; TJ = -40°C to +150°C; all voltages
are referenced to GND; positive current flowing into pin; pull-up resistors connected to VDD, pull-down resistors
connected to GND.
Datasheet
13
Rev. 1.10
2022-12-20
EiceDRIVER™ APD 2ED4820-EM
48 V smart high-side MOSFET gate driver with SPI
4 General product description
Table 6
Electrical characteristics: digital IOs
Parameter
Symbol
Values
Typ.
Unit Note or condition
P-
Number
Min.
Max.
Logic input voltage
Logic high input voltage
Logic low input voltage
VIH
VIL
0.7*VDD
0
–
–
–
VDD
V
–
–
–
PRQ-30
PRQ-31
PRQ-32
0.7
–
V
Logic input threshold
hysteresis
VIHY
100
mV
Logic output voltage
Logic high output voltage VOH
VDD
0.4
-
VDD
0.2
-
VDD
V
V
IO = -1.6 mA
IO = 1.6 mA
PRQ-415
PRQ-416
level
Logic low output voltage
level
VOL
0
0.2
0.4
Pull-up / -down resistors
ENABLE pull-down resistor RPD_ENABLE
30
30
40
40
40
50
50
50
kΩ
kΩ
kΩ
–
–
–
PRQ-126
PRQ-410
PRQ-409
SCLK pull-down resistor
RPD_SCLK
SAFESTATEN pull-down
resistor
RPD_SAFESTATE 30
N
MOSI pull-down resistor
RPD_MOSI
30
40
40
50
50
kΩ
kΩ
–
–
PRQ-411
PRQ-479
INTERRUPT pull-down
resistor
RPD_INTERRUPT 30
CSN pull-up resistor
RPU_CSN
30
–
40
–
50
kΩ
–
–
PRQ-412
PRQ-413
SPI interface setup time
SPI interface setup time
tSET_SPI
150
µs
4.6
Electrical characteristics: charge pump
Unless otherwise specified: VBAT and VDD inside the normal operation range; TJ = -40°C to +150°C; all voltages
are referenced to GND; positive current flowing into pin.
Table 7
Electrical characteristics: charge pump
Parameter
Symbol
Values
Typ.
Unit Note or condition
P-
Number
Min.
140
Max.
172
Charge pump frequency
VCP_PUMP
fCP
156
kHz
–
PRQ-127
VCP_PUMP_H threshold
VCP_PUMP_L threshold
VCP_PUMP_H
VCP_PUMP_L
12.7
11.7
14
13
1
15
14
1.5
V
V
V
–
–
–
PRQ-343
PRQ-344
PRQ-402
VCP_PUMP hysteresis
VCP_PUMP_HY 0.5
(table continues...)
Datasheet
14
Rev. 1.10
2022-12-20
EiceDRIVER™ APD 2ED4820-EM
48 V smart high-side MOSFET gate driver with SPI
4 General product description
Table 7
(continued) Electrical characteristics: charge pump
Parameter
Symbol
Values
Typ.
Unit Note or condition
P-
Number
Min.
Max.
VCP_READY
VCP_READY_H threshold
VCP_READY_L threshold
VCP_READY hysteresis
VCP_UV
VCP_READY_H
VCP_READY_L
VCP_READY_HY 0.38
10
11
11.7
V
V
V
–
–
–
PRQ-345
PRQ-346
PRQ-403
9.5
10.5
0.5
11.2
0.62
VCP_UV_H threshold
VCP_UV_L threshold
VCP_UV hysteresis
VCP_UV Blanking time
VCP_UV_H
VCP_UV_L
VCP_UV_HY
tVCP_UV_BLK
5.7
5.2
0.25
2.4
6.5
6
7
V
–
–
–
–
PRQ-347
PRQ-348
PRQ-404
PRQ-494
6.5
0.75
4
V
0.5
3
V
ms
Charge pump output current
Charge pump output
ICPO
–
–
-10
mA
mA
CCPHL = 220 nF;
PRQ-349
PRQ-487
current capability at VCP
CPL pulsed current
|ICPL_PULSE
|
60
80
110
–
Datasheet
15
Rev. 1.10
2022-12-20
EiceDRIVER™ APD 2ED4820-EM
48 V smart high-side MOSFET gate driver with SPI
5 High-side gate driver
5
High-side gate driver
The high-side gate driver is capable to drive multiple external MOSFETs for high current capability. Two
independent channels are available, and they can be switched on and off by the SPI register commands. The
gate drivers are supplied by an internal one-stage charge pump with external capacitors.
CSN
ON
OFF
command
command
MOSONCH_x = 1
MOSONCH_x = 0
t
t
tDGDRV_ON
tDGDRV_OFF
VGSx
VCP_PUMP_H
VCP_PUMP_L
VGS_LOW
I(Gx)
ISINK
Actual current (example)
Maximum current capability
ICHARGE_LOW
ICHARGE
t
tMOS_BLKx
tSINK_MAX
Figure 6
Maximum gate driving capability
5.1
Channel activation
The selected channel is activated under the following condition:
ENABLE = high AND MOSONCH_(x) = high AND SAFESTATEN = high.
Table 8
MOSFET activation
MOSONCH_(x)[0]
MOSFET activation state
0
1
MOSFET channel not activated (default)
MOSFET channel activated
Datasheet
16
Rev. 1.10
2022-12-20
EiceDRIVER™ APD 2ED4820-EM
48 V smart high-side MOSFET gate driver with SPI
5 High-side gate driver
When a channel is activated through the SPI interface, its output gate current capability is set to ICHARGE for a
duration of maximum tMOS_BLKx (MOS blanking time). ICHARGE is active until VGS reaches VCP, so the actual time
depends on the MOSFETs gate capacitance.
Once the tMOS_BLKx time expires, the output gate current capability is reduced to maximum ICHARGE_LOW ; the
actual current delivered by the driver depends on external leakages, coming for example from an external
pull-down resistor added between gate and source of the MOSFETs.
5.2
Channel deactivation
The channel is deactivated by discharging the external MOSFET's gate if one of the following conditions are
met:
•
•
•
MOSONCH_(x) set from high to low
Pin ENABLE set from high to low
SAFESTATEN set from high to low
Note:
In case of a failure, MOSONCH_(x) is automatically set from high to low, which immediately triggers a
channel deactivation.
When a channel is deactivated either due to MOSONCH_(x) or pin SAFESTATEN set from high to low, the output
gate control pulls a high discharge current, set to ISINK for a duration of maximum tSINK_MAX. ISINK is active until
VGS is zero, so the actual time depends on the MOSFETs gate capacitance.
Once tSINK_MAX expires, the output gate control changes to a voltage clamping structure, which limits the gate
to source voltage (VGS) to maximum VGS_LOW. This clamping structure ensures that the MOSFETs' VGS is below
VGS(th) to keep them OFF.
When MOSONCH_(x) is low while ENABLE pin is high, there is a leakage current flowing out of the Sx pins:
ISx_OFF
.
When the channels are deactivated due to pin ENABLE set from high to low, the output gate control does not
pull the high discharge current (ISINK), it immediately changes to the voltage clamping structure with very low
leakage current on the Sx pins.
5.3
MOSFET driver output
Unless otherwise specified: VBAT and VDD inside the normal operation range; TJ = -40°C to +150°C; all voltages
are referenced to GND; positive current flowing into pin.
Table 9
MOSFET driver output
Symbol
Parameter
Values
Typ.
Unit Note or condition
P-
Number
Min.
Max.
-300
Gate charge current high
Gate charge current low
Gate discharge current
ICHARGE
–
–
mA
mA
A
VGx = VSx = 0 V
PRQ-133
PRQ-488
PRQ-134
PRQ-539
ICHARGE_LOW -5
-4
-2.5
1.3
12
–
ISINK
0.9
1.1
10
VGx - VSx = 13 V
1)
Gate discharge current
maximum active time
tSINK_MAX
8
µs
Source current in OFF
mode
ISx_OFF
–
40
–
–
µA
V
1) MOSONCH_(x) = 0; PRQ-544
ENABLE = HIGH
High level output voltage VGS
Gx vs. Sx
VCP_PUM
P_L
VCP_PUM
P_H
Current between Gx PRQ-135
and Sx = 1 mA
(table continues...)
Datasheet
17
Rev. 1.10
2022-12-20
EiceDRIVER™ APD 2ED4820-EM
48 V smart high-side MOSFET gate driver with SPI
5 High-side gate driver
Table 9
(continued) MOSFET driver output
Parameter
Symbol
Values
Typ.
Unit Note or condition
P-
Number
Min.
Max.
1.7
Low level output voltage
Gx vs. Sx
VGS_LOW
–
–
–
V
TJ < 25°C
PRQ-498
Current beween Gx
and Sx = 100 mA
0 V ≤ VBAT
≤ VBAT(EXT)_MAX
0 V ≤ VDD ≤ VDD_MAX
Low level output voltage
Gx vs. Sx
VGS_LOW
–
1.5
V
TJ ≥ 25°C
PRQ-524
Current between Gx
and Sx = 100 mA
0 V ≤ VBAT
≤ VBAT(EXT)_MAX
0 V ≤ VDD ≤ VDD_MAX
Gate driver dynamic parameter
Gate turn-on delay time
tDGDRV_ON
–
–
–
–
–
–
3
3
3
µs
µs
µs
Duration between
CSN goes from low
to high and gate
charge current is
activated
PRQ-137
PRQ-139
PRQ-527
Gate turn-off delay time
tDGDRV_OFF
Duration between
CSN goes from low
to high and gate
dicharge current is
activated
Delay time for gate turn-off tDGOFF_SFSTN
triggered by SAFESTATEN
Duration between
SAFESTATEN goes
from high to
low and gate
dicharge current is
activated
Gate to source clamped
voltage
VGS_TH
15.5
–
19.5
V
–
PRQ-476
Active zener clamping
Gate zener clamping with VCLAMP_G_VBAT 78
82
82
87
87
V
V
I_G = -2.5 mA
I_G = -2.5 mA
PRQ-489
PRQ-490
respect to VBAT
Gate zener clamping with VCLAMP_G_GND 78
respect to GND
1)
Not subject to production test, specified by design.
Datasheet
18
Rev. 1.10
2022-12-20
EiceDRIVER™ APD 2ED4820-EM
48 V smart high-side MOSFET gate driver with SPI
6 Protection and monitoring
6
Protection and monitoring
The device provides three sets of features to protect and monitor:
•
•
•
Monitorings, which give a status to the MCU
Warnings, which inform the MCU of critical events with limited impact
Failure detections, which trigger internal actions (channel deactivation mainly) and notify immediately the
MCU
6.1
Monitorings
6.1.1
Source voltage monitoring in OFF state
If the source voltage VSx of a deactivated channel rises above VS_TH, and ENABLE is high, then the appropriate
flag VSOURCE_(x) is set to 1.
This warning allows to implement an "open load detection in OFF state", since the voltage on the source pin Sx
would be pulled up by the leakage of the gate driver if there is no load connected.
6.1.2
Charge pump voltage monitoring
If the charge pump voltage VCP is above VCP_READY_H, then the VCP_READY flag is set to 1.
6.1.3
SPI address monitoring
If the MCU tries to read or write a register with an address which is not available, then the ADD_NOT_AVAIL flag
is set to 1.
6.2
Warnings
In order to inform the MCU about any warning on the driver, the warning flags will be used and updated by the
device, which notifies the MCU by setting the INTERRUPT pin to high.
The warnings are not latched and will be reset, if the condition no longer applies.
The warnings do not change the state of the output channels.
6.2.1
Temperature warning
The OT_WARNING is set to 1 if the overtemperature warning threshold TJW is reached and exceeded.
6.2.2
One time programmable (OTP) memory data corruption
The device embeds an OTP to store internal settings, used to trim internal blocks for full specification
compliance. These settings are written during manufacturing and this memory cannot be accessed by SPI.
The MEM_FAIL flag is set to 1 if OTP data is corrupted or if OTP readout failed. In this case all affected trimmings
are set to default values, therefore parameter deviations are possible. OTP is checked and read out right afer
the device is enabled.
Note:
OTP cannot be read in case of a not connected ground pin.
6.2.3
Ground loss
In case of a voltage difference between 2 ground pins (whether GND, AGND or CPGND) higher than VGND_LOSS
,
the corresponding LOG_(x) warning flags will be set to 1. This is typically the case for not connected ground
pins.
•
Disconnecting AGND will trigger LOG_A and LOG_CP flags
Datasheet
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EiceDRIVER™ APD 2ED4820-EM
48 V smart high-side MOSFET gate driver with SPI
6 Protection and monitoring
•
•
Disconnecting CPGND will trigger LOG_CP and LOG_D flags
Disconnecting DGND will trigger LOG_A and LOG_D flags
6.3
Failures detection
Failures detection is provided to implement protections for the external MOSFETs and eventually for the load.
There are two types of failures detected by the gate driver:
•
Latching failures, which require to be cleared before the gate driver can operate again. This category is split
into two sub-categories:
-
Latching failures for which clearing the flag will automatically turn the channel on again. They include:
-
-
-
Undervoltage on the charge pump
Undervoltage on gate-source voltage ( VGS = [VGx-VSx] )
Overvoltage on drain-source voltage ( VDS = [VBAT-VSx] ), when VDS(x)_SS_[0] = 0 to enable the
protection
-
Latching failures for which an SPI command has to follow the flag clearing in order to turn the channel
on again. They include :
-
-
-
-
Undervoltage on VDD
SAFESTATEN pin activation
Overtemperature shut down
Overcurrent
•
Non-latching failures, which do not need to be cleared: once the failure source is gone, the gate driver can
operate again afer a configurable delay. They include:
-
-
Overvoltage on VBAT
Undervoltage on VBAT
6.3.1
Failure notification and clearing
In case of failure detection, the FAILURE flag is set to high, the INTERRUPT pin is set to high and the
corresponding channel(s) is (are) deactivated automatically by setting register bit MOSONCH_(x) to 0 (except
for drain-source failure detection when it is disabled through the VDS(x)_SS register).
A latching failure can only be cleared when the failure is not present anymore, except for VCP_UV, VGSTH_(x)
and VDSTRIP_(x).
6.3.2
Non-latching failures
The non-latching failures do not need to be reset: the gate driver activates the MOSFET again, if the failure does
not exist anymore.
6.3.2.1
VBAT overvoltage
If VBAT exceeds VBAT_OV_OFF, the FAILURE bit and VBAT_OV flag are set to 1.
If the VBAT gets lower than VBAT_OV_ON, then the restart will be done afer tOV_RESTART
.
While the device is in auto-restart duration, none of the channels can be activated by the µC.
Table 10
VBAT overvoltage auto-restart time
VBAT overvoltage auto-restart time (typical): tOV_RESTART
VBATOVARST[1:0]
00
01
10
11
10 µs (default)
50 µs
200 µs
1 ms
Datasheet
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EiceDRIVER™ APD 2ED4820-EM
48 V smart high-side MOSFET gate driver with SPI
6 Protection and monitoring
VBAT
VBAT
VBAT_OV_OFF
VBAT_OV_ON
VBAT_UV_ON
VBAT_UV_OFF
t
t
t
CHANNELS
ACTIVATION
CHANNELS
ACTIVATION
t
tOV_RESTART
tUV_RESTART
Figure 7
VBAT overvoltage and undervoltage auto-restart time diagrams
6.3.2.2
VBAT undervoltage
If VBAT gets lower than VBAT_UV_OFF, the FAILURE bit and VBAT_UV flag are set to 1.
If the VBAT gets higher than VBAT_UV_ON, then the restart will be done afer tUV_RESTART
.
While the device is in auto-restart duration, none of the channels can be activated by the µC.
Table 11
VBAT undervoltage auto-restart time
VBATUVARST[1:0]
VBAT undervoltage auto-restart time tUV_RESTART (typical)
00
01
10
11
1 ms (default)
5 ms
20 ms
50 ms
6.3.3
Latching failures
Once a latching failure (except VDD_UV) has been detected, a reset can be operated either by toggling ENABLE,
VDD (Chapter 4.2.4), or by an SPI command.
6.3.3.1
Blank time and filter time for failures detections
Blank time
6.3.3.1.1
Both drain-source and gate-source failure detections are inherently triggered at the turn-on of a channel.
Turning on a MOSFET implies a transient phase where the gate-source voltage is rising and drain-source voltage
is decreasing before they reach their steady state.
Both failure detections have therefore to be temporary blanked at turn-on, which is the purpose of the
configurable blank time: tMOS_BLKx. Its value is configured for each channel independently, based on the
MOSFETs characteristics (total CGS mainly).
Note:
As described in Chapter 5.1, tMOS_BLKx also defines the maximum duration of the ICHARGE current.
Datasheet
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EiceDRIVER™ APD 2ED4820-EM
48 V smart high-side MOSFET gate driver with SPI
6 Protection and monitoring
MOSONCH_(x)
‘1'
‘0'
t
V
GSx = VGx - VSx
VCP_PUMP_H
VCP_PUMP_L
VGS_TH_RIS
Miller plateau
t
t
t
GS_TH_RIS < tMOS_BLKx
VGSTH_(x)
‘1'
‘0'
V
DSx = VBAT - VSx
VBAT
VDSTHx
t
t
DSTHx < tMOS_BLKx
VDSTRIP_(x)
‘1'
‘0'
Figure 8
Blank time at MOSFET turn-on
A configurable blank time for the drain-source and gate-source failure detections is applied at the turn-on of the
selected channel. During the blank time tMOS_BLKx, a drain-source or gate-source overvoltage failure is masked.
Table 12
MOSFET voltage blank time
MOSFET voltage blank time (typical) tMOS_BLKx
MOSBLK_(x)_[1:0]
00
01
10
11
10 µs (default)
20 µs
50 µs
100 µs
Datasheet
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Rev. 1.10
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EiceDRIVER™ APD 2ED4820-EM
48 V smart high-side MOSFET gate driver with SPI
6 Protection and monitoring
6.3.3.1.2
Filter time
Both drain-source and gate-source failure detections may be wrongly triggered due to noisy signals on the
monitored pins. A configurable filter time is therefore provided for each channel independently, which applies
for the two failure detections: tMOS_FLTx
.
Table 13
MOSFET voltage filter time
MOSFET voltage filter time (typical) tMOS_FLTx
MOSFLT_(x)_[1:0]
00
01
10
11
0.5 µs
1 µs (default)
2 µs
5 µs
6.3.3.2
Drain-source overvoltage
The drain to source voltage of activated channel(s) is continuously monitored in order to protect high-side
MOSFETs against a short circuit to ground during ON-state.
If a channel is activated and the VBAT (drain) to VSx (source) voltage VDS exceeds VDSTHx for longer than the
filter time tMOS_FLTx afer the blanking time tMOS_BLKx, the bit FAILURE and the VDSTRIP_(x) bit are set to 1 and
the register bit MOSONCH_(x) is set to 0 if the VDS(x)_SS bit is set to 0.
Otherwise (VDS(x)_SS bit is set to 1) only the bit FAILURE and the VDSTRIP_(x) bit are set to 1 and the register
bit MOSONCH_(x) is still set to 1.
Each channel has a dedicated threshold that can be selected by the register VDSTH_(x).
When VDS(x)_SS bit is set to 0 and the VDSTRIP_(x) failure flag is cleared, the selected channel immediately
turns on again. If the VDS of the channel is still above VDSTHx for longer than the filter time tMOS_FLTx afer the
blanking time tMOS_BLKx (e.g. the failure cause is still present), the channel is disabled again.
Table 14
Drain-source overvoltage threshold
VDSTH_(x)_[2:0]
Positive drain-source overvoltage
Negative drain-source overvoltage
threshold
threshold (typical) VDSTHx
000
001
010
011
100
101
110
111
100 mV
-100 mV
-150 mV
150 mV
200 mV (default)
250 mV
- 200 mV (default)
-250 mV
300 mV
-300 mV
400 mV
- 400 mV
500 mV
- 500 mV
600 mV
- 600 mV
Table 15
Drain-source channel de-activation condition
Drain-source channel condition
VDS(x)_SS_[0]
0
1
Channel is de-activated in case of drain-source overvoltage
Channel is not de-activated in case of drain-source overvoltage (default)
Datasheet
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EiceDRIVER™ APD 2ED4820-EM
48 V smart high-side MOSFET gate driver with SPI
6 Protection and monitoring
6.3.3.3
Gate-source undervoltage
The device reports a gate-source undervoltage failure if the following conditions are both met:
•
•
Afer expiration of the configured blank time tMOS_BLKx
If the gate-source voltage is less than the threshold VGS_TH(x) for the selected channel for a duration longer
than the configured filter time tMOS_FLTx
In case of gate-source undervoltage failure, the bit FAILURE and the bit VGSTH_(x) are set to 1.
When the VGSTH_(x) flag is cleared, the selected channel automatically turns on again. If the VGS of the channel
is still below VGS_TH_RIS for longer than the filter time tMOS_FLTx afer the blanking time tMOS_BLKx (e.g. the
failure cause is still present), the channel is disabled again.
6.3.3.4
Channel cross-control
While activating both channels, VGSTH_(x) and VDSTRIP_(x) failures related to one channel may or may not
affect the other channel. This cross-control between the 2 channels is programmable by SPI.
While the CHCRCTRL bit is set to 1, any of the following failures will deactivate the channels A (CHA) and B (CHB)
according this overview:
•
•
•
•
•
In case of VGSTH_(x) = 1 -> CHA = OFF and CHB = OFF
In case of VDSTRIP_A = 1, VDSA_SS = 0 and VDSB_SS = 0 -> CHA = OFF and CHB = OFF
In case of VDSTRIP_A = 1, VDSA_SS = 1 and VDSB_SS = 0 -> CHA = Keep previous state (ON) and CHB = OFF
In case of VDSTRIP_A = 1, VDSA_SS = 0 and VDSB_SS = 1 -> CHA = OFF and CHB = Keep previous state
In case of VDSTRIP_A = 1, VDSA_SS = 1 and VDSB_SS = 1 -> CHA = Keep previous state (ON) and CHB =
Keep previous state
•
•
•
•
In case of VDSTRIP_B = 1, VDSA_SS = 0 and VDSB_SS = 0 -> CHA = OFF and CHB = OFF
In case of VDSTRIP_B = 1, VDSA_SS = 1 and VDSB_SS = 0 -> CHA = Keep previous state and CHB = OFF
In case of VDSTRIP_B = 1, VDSA_SS = 0 and VDSB_SS = 1 -> CHA = OFF and CHB = Keep previous state (ON)
In case of VDSTRIP_B = 1, VDSA_SS = 1 and VDSB_SS = 1 -> CHA = Keep previous state and CHB = Keep
previous state (ON)
If the CHCRCTRL bit is set to 0, only the faulty channel will be treated.
Table 16
Channel cross-control
Channel cross-control status
CHCRCTRL[0]
0
1
Cross-control deactivated
Cross-control activated (default)
6.3.3.5
VDD undervoltage
If the VDD voltage falls below the VDD_UV_ON threshold, the device is reset. When VDD comes back above the
VDD_UV_ON threshold, VDD_UV bit is set to 1.
6.3.3.6
VCP undervoltage
The VCP_UV bit and the FAILURE bit are set to 1 as soon as the (VCP - VBAT) voltage gets lower than the VCP_UV_L
threshold. The charge pump is immediately disabled.
When the failure flag VCP_UV is cleared, the charge pump immediately restarts. If the (VCP - VBAT) voltage is
still below VCP_UV_H afer the startup blanking time tVCP_UV_BLK, (e.g. the failure cause is still present), the charge
pump is disabled again.
6.3.3.7
SAFESTATEN activation
Once the SAFESTATEN signal is set to low, the FAILURE bit is set to 1.
Datasheet
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EiceDRIVER™ APD 2ED4820-EM
48 V smart high-side MOSFET gate driver with SPI
6 Protection and monitoring
6.3.3.8
Overtemperature
If the internal temperature sensor reaches TJSD, the gate drivers are latched off, the charge pump and the
current sense amplifier are deactivated and the TSD and FAILURE flags are set to 1.
6.3.3.9
Current sense amplifier and overcurrent comparator
Current sense amplifier is used for monitoring the voltage drop across the shunt resistor as a sensor for the load
current. If overcurrent is detected, this will switch off both channels.
Current sense comparator and amplifier are active under the following condition:
ENABLE = high AND VCP_UV = low AND VBAT_UV = low AND VBAT_OV = low AND TSD = low AND VDD > VDD_UV_ON.
6.3.3.9.1
Gain configuration
The differential gain of the current sense amplifier is configurable by the configuration bits CSAG_(x).
Table 17
Configuration of the current sense amplifier gain
CSAG[2:0]
000
Current sense amplifier gain GDIFF (typical)
10 V/V
001
15 V/V
010
20 V/V
011
25 V/V
100
31.5 V/V
35 V/V (default)
40 V/V
101
110
111
47.7 V/V
6.3.3.9.2
Current sense position
In order to adjust the internal circuitry to the proper shunt position (high-side or low-side), the CSA_HSS needs
to be set.
While the CSA_HSS bit is set to 0, the internal circuitry is optimized for a current sense in low-side position.
If the CSA_HSS bit is set to 1, the internal circuitry is optimized for a current sense in high-side position.
Table 18
Current sense position adjustment
Current sense position
CSA_HSS[0]
0
1
Shunt is in low-side position (default)
Shunt is in high-side position
6.3.3.9.3
Current sense output load
In order to adjust to the amount of output charge connected to the CSO pin, some internal circuitry can be
activated.
While the CSA_COUTSEL bit is set to 1, the internal circuitry is optimized for an external load capacitance higher
than 100 pF.
If the CSA_COUTSEL bit is set to 0, the internal circuitry is optimized for an external load capacitance lower than
100 pF.
Datasheet
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Rev. 1.10
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48 V smart high-side MOSFET gate driver with SPI
6 Protection and monitoring
Table 19
Current sense output load adjustment
Current sense output charge
CSA_COUTSEL[0]
0
1
Output load < 100 pF (default)
Output load > 100 pF
6.3.3.9.4
Overcurrent detection
A comparator at CSO detects overcurrent conditions.
If the CSA output is out of the range between threshold voltages ΔVOCTHxL and ΔVOCTHxH configured in
OCTH, all channels are switched off and the bits FAILURE and ITRIP are set to 1 if at least one channel was in ON
state.
VDD
DVOCTH2H
+0.2*VDD
=
DVOCTH3H
+0.25*VDD
=
DVOCTH4H
+0.3*VDD
=
DVOCTH1H
+0.1*VDD
DVOCTH1L
=
VREF_BIDIR
0.5*VDD
=
=
DVOCTH2L
-0.2*VDD
=
DVOCTH3L
-0.25*VDD
=
DVOCTH4L =
-0.3*VDD
-0.1*VDD
OCTH_[1:0]
"00"
"01"
"10"
"11"
Figure 9
Overcurrent detection thresholds
6.3.3.9.5
Electrical characteristics: current sense
Unless otherwise specified: VBAT and VDD inside the normal operation range; TJ = -40°C to +150°C; all voltages
are referenced to GND; positive current flowing into pin.
Datasheet
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Rev. 1.10
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EiceDRIVER™ APD 2ED4820-EM
48 V smart high-side MOSFET gate driver with SPI
6 Protection and monitoring
Table 20
Electrical characteristics: current sense
Parameter
Symbol
Values
Typ.
Unit Note or condition
P-
Number
Min.
-1.4
Max.
1.4
Input offset voltage
VOFFSET
0
mV
–
PRQ-52
Integrated output noise
voltage at CSO pin
VCSO_NOISE
–
–
5
mVrm 1) ISP shorted to
s
PRQ-262
ISN; all gain settings;
output open (no
load at CSO)
PSRR - Power supply
rejection ratio VCP
PSRR
tSET
60
–
–
–
–
7
dB
µs
DC up to 1 kHz
PRQ-63
Settling time to 98%
Duration between
CSN goes from low
to high and signal
at CSO pin is settled
(98% of final value)
PRQ-222
Reference voltage for
bidirectional CSA
VREF_BIDIR
-2%
1.2
-5
VDD/2
1.5
–
+2%
1.8
5
V
–
PRQ-228
PRQ-505
PRQ-392
1)
Digital glitch filter time for tITRIP_FLT
ITRIP
µs
µA
ISP, ISN leakage current
while off
ISP_OFF
,
ENABLE = 0; VISP =
ISN_OFF
VISN; 0 V ≤ VISN,VISP ≤
VBAT
Common mode rejection ratio
CMRR - common mode
rejection ratio @ Gain = 10
V/V
CMRR10
75
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dB
dB
dB
dB
dB
dB
dB
DC up to 1 kHz
DC up to 1 kHz
DC up to 1 kHz
DC up to 1 kHz
DC up to 1 kHz
DC up to 1 kHz
DC up to 1 kHz
PRQ-64
CMRR - common mode
rejection ratio @ Gain = 15
V/V
CMRR15
CMRR20
CMRR25
CMRR31.5
CMRR35
CMRR40
77
PRQ-148
PRQ-149
PRQ-150
PRQ-210
PRQ-211
PRQ-212
CMRR - common mode
rejection ratio @ Gain = 20
V/V
81
CMRR - common mode
rejection ratio @ Gain = 25
V/V
83
CMRR - common mode
rejection ratio @ Gain =
31.5 V/V
83
CMRR - common mode
rejection ratio @ Gain = 35
V/V
85.5
86
CMRR - common mode
rejection ratio @ Gain = 40
V/V
(table continues...)
Datasheet
27
Rev. 1.10
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EiceDRIVER™ APD 2ED4820-EM
48 V smart high-side MOSFET gate driver with SPI
6 Protection and monitoring
Table 20
(continued) Electrical characteristics: current sense
Parameter
Symbol
Values
Typ.
Unit Note or condition
P-
Number
Min.
88.5
Max.
CMRR - common mode
rejection ratio @ Gain =
47.7 V/V
CMRR47.7
–
–
dB
DC up to 1 kHz
PRQ-213
Current sense amplifier differential gain
Current sense amplifier
GDIFF10
GDIFF15
GDIFF20
GDIFF25
GDIFF31.5
GDIFF37.7
GDIFF40
GDIFF47.7
9.8
10
10.2
15.3
20.4
25.5
32.13
35.7
40.8
48.65
V/V
V/V
V/V
V/V
V/V
V/V
V/V
V/V
Test condition: CSAG PRQ-53
= (000)
differential gain 10 V/V
Current sense amplifier
differential gain 15 V/V
14.7
19.6
24.5
30.87
34.3
39.2
46.75
15
Test condition: CSAG PRQ-77
= (001)
Current sense amplifier
differential gain 20 V/V
20
Test condition: CSAG PRQ-78
= (010)
Current sense amplifier
differential gain 25 V/V
25
Test condition: CSAG PRQ-79
= (011)
Current sense amplifier
differential gain 31.5 V/V
31.5
35
Test condition: CSAG PRQ-206
= (100)
Current sense amplifier
differential gain 35 V/V
Test condition: CSAG PRQ-207
= (101)
Current sense amplifier
differential gain 40 V/V
40
Test condition: CSAG PRQ-208
= (110)
Current sense amplifier
differential gain 47.7 V/V
47.7
Test condition: CSAG PRQ-209
= (111)
Current sense bandwidth
Low gain current sense
bandwidth
fBW_LOW
200
150
–
–
–
–
kHz Max output current PRQ-388
capability = 4 mA,
cload between 10
pF and 400 pF,
CSAG[2:0] from '000'
to '110'
High gain current sense
bandwidth
fBW_HIGH
kHz Max output current PRQ-389
capability = 4 mA,
cload between 10
pF and 400 pF,
CSAG[2:0]='111'
Overcurrent thresholds
Overcurrent threshold
1 high relative to
VREF_BIDIR
ΔVOCTH1H
ΔVOCTH1L
0.095* 0.105* 0.115*
VDD VDD VDD
V
V
OCTH = (00)
OCTH = (00)
PRQ-531
PRQ-532
Overcurrent threshold 1
low relative to VREF_BIDIR
-0.115* -0.105* -0.095*
VDD
VDD
VDD
(table continues...)
Datasheet
28
Rev. 1.10
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EiceDRIVER™ APD 2ED4820-EM
48 V smart high-side MOSFET gate driver with SPI
6 Protection and monitoring
Table 20
(continued) Electrical characteristics: current sense
Parameter
Symbol
Values
Typ.
Unit Note or condition
P-
Number
Min.
Max.
Overcurrent threshold
2 high relative to
VREF_BIDIR
ΔVOCTH2H
0.199* 0.210* 0.221*
VDD VDD VDD
V
OCTH = (01)
PRQ-533
Overcurrent threshold 2
low relative to VREF_BIDIR
ΔVOCTH2L
-0.214* -0.203* -0.192*
VDD VDD VDD
V
V
OCTH = (01)
OCTH = (10)
PRQ-534
PRQ-535
Overcurrent threshold
3 high relative to
VREF_BIDIR
ΔVOCTH3H
0.243* 0.254* 0.265*
VDD VDD VDD
Overcurrent threshold 3
low relative to VREF_BIDIR
ΔVOCTH3L
ΔVOCTH4H
ΔVOCTH4L
-0.265* -0.254* -0.243*
VDD VDD VDD
V
V
OCTH = (10)
OCTH = (11)
PRQ-536
PRQ-537
Overcurrent threshold
4 high relative to
VREF_BIDIR
0.293* 0.304* 0.315*
VDD VDD VDD
Overcurrent threshold 4
low relative to VREF_BIDIR
-0.315* -0.304* -0.293*
VDD VDD VDD
V
OCTH = (11)
PRQ-538
1)
Not subject to production test, specified by design.
6.4
INTERRUPT pin control
The INTERRUPT pin is set high and latched if one of the following occurs:
•
•
•
•
•
FAILURE bit is set to 1
OT_WARNING is set to 1
GEN_INTERRUPT flag is set to 1 (for testing the interrupt signal connection to controller)
GND_LOSS bit is set to 1
MEM_FAIL bit is set to 1
Once the INTERRUPT signal has been set high due to a failure or a warning flag, it can be cleared either by:
•
•
Reading the corresponding failure bit via SPI
Setting the INT_CLEAN bit to 1
If the INTERRUPT signal has been set high via the GEN_INTERRUPT bit, it can be cleared only by setting
GEN_INTERRUPT back to 0. INT_CLEAN will not remove that interrupt in this case.
6.5
Electrical characteristics: protection and monitoring
Unless otherwise specified: VBAT and VDD inside the normal operation range; TJ = -40°C to +150°C; all voltages
are referenced to GND; positive current flowing into pin.
Datasheet
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Rev. 1.10
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EiceDRIVER™ APD 2ED4820-EM
48 V smart high-side MOSFET gate driver with SPI
6 Protection and monitoring
Table 21
Electrical characteristics: protection and monitoring
Parameter
Symbol
Values
Typ.
Unit Note or condition
P-
Number
Min.
Max.
MOS voltage blank time
1)
MOS voltage blank time 1 tMOS_BLK1
MOS voltage blank time 2 tMOS_BLK2
MOS voltage blank time 3 tMOS_BLK3
MOS voltage blank time 4 tMOS_BLK4
MOS voltage monitoring filter time
8
10
12
µs
µs
µs
µs
Start: gate charge PRQ-152
current is activated
1)
16
40
80
20
24
Start: gate charge PRQ-153
current is activated
1)
50
60
Start: gate charge PRQ-154
current is activated
1)
100
120
Start: gate charge PRQ-155
current is activated
1)
MOS voltage filter time 1
MOS voltage filter time 2
MOS voltage filter time 3
MOS voltage filter time 4
tMOS_FLT1
tMOS_FLT2
tMOS_FLT3
tMOS_FLT4
0.4
0.8
1.6
4
0.5
1
0.6
1.2
2.4
6
µs
µs
µs
µs
PRQ-295
1)
PRQ-296
1)
2
PRQ-297
1)
5
PRQ-298
Drain to source monitoring threshold
Positive drain to source
monitoring threshold 1
VDSTH_1_POS 80
VDSTH_1_NEG -120
VDSTH_2_POS 120
VDSTH_2_NEG -180
VDSTH_3_POS 160
VDSTH_3_NEG -240
VDSTH_4_POS 200
VDSTH_4_NEG -300
VDSTH_5_POS 240
VDSTH_5_NEG -360
VDSTH_6_POS 320
100
-100
150
-150
200
-200
250
-250
300
-300
400
120
-80
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
–
–
–
–
–
–
–
–
–
–
–
PRQ-82
PRQ-417
PRQ-83
PRQ-418
PRQ-84
PRQ-419
PRQ-85
PRQ-420
PRQ-86
PRQ-421
PRQ-87
Negative drain to source
monitoring threshold 1
Positive drain to source
monitoring threshold 2
180
-120
240
-160
300
-200
360
-240
480
Negative drain to source
monitoring threshold 2
Positive drain to source
monitoring threshold 3
Negative drain to source
monitoring threshold 3
Positive drain to source
monitoring threshold 4
Negative drain to source
monitoring threshold 4
Positive drain to source
monitoring threshold 5
Negative drain to source
monitoring threshold 5
Positive drain to source
monitoring threshold 6
(table continues...)
Datasheet
30
Rev. 1.10
2022-12-20
EiceDRIVER™ APD 2ED4820-EM
48 V smart high-side MOSFET gate driver with SPI
6 Protection and monitoring
Table 21
(continued) Electrical characteristics: protection and monitoring
Parameter
Symbol
Values
Typ.
Unit Note or condition
P-
Number
Min.
Max.
-320
Negative drain to source
monitoring threshold 6
VDSTH_6_NEG -480
VDSTH_7_POS 400
VDSTH_7_NEG -600
VDSTH_8_POS 480
VDSTH_8_NEG -720
-400
mV
mV
mV
mV
mV
–
–
–
–
–
PRQ-422
PRQ-88
PRQ-423
PRQ-89
PRQ-424
Positive drain to source
monitoring threshold 7
500
600
Negative drain to source
monitoring threshold 7
-500
600
-400
720
Positive drain to source
monitoring threshold 8
Negative drain to source
monitoring threshold 8
-600
-480
Gate to source monitoring threshold
Gate to source
undervoltage threshold
rising
VGS_TH_RIS
VGS_TH_FAL
VGS_UV_HYS
5.8
7
8.5
7.4
900
V
–
–
–
PRQ-144
PRQ-495
PRQ-496
Gate to source
undervoltage threshold
falling
5.65
100
6.6
400
V
Gate to source
mV
undervoltage threshold
hysteresis
Source overvoltage threshold
VSx overvoltage threshold VS_TH
VBAT undervoltage
3.5
5
6.5
V
–
PRQ-145
VBAT_UV switch OFF
voltage
VBAT_UV_OFF
VBAT_UV_ON
VBAT_UV_HYS
17.5
18
18.5
19
19.5
20
V
V
V
–
–
–
PRQ-23
PRQ-24
PRQ-431
VBAT_UV switch ON
voltage
VBAT_UV hysteresis
0.3
0.5
0.7
VBAT overvoltage
VBAT_OV switch ON
voltage
VBAT_OV_ON
VBAT_OV_OFF
VBAT_OV_HYS
70
71
0.5
72
73
1
74
75
2
V
V
V
–
–
–
PRQ-119
PRQ-26
VBAT_OV switch OFF
voltage
VBAT_OV hysteresis
PRQ-432
VBAT undervoltage auto-restart duration
1)
Undervoltage auto-restart tUV_RESTART1 0.8
time 1
1
1.2
ms
PRQ-309
(table continues...)
Datasheet
31
Rev. 1.10
2022-12-20
EiceDRIVER™ APD 2ED4820-EM
48 V smart high-side MOSFET gate driver with SPI
6 Protection and monitoring
Table 21
(continued) Electrical characteristics: protection and monitoring
Parameter
Symbol
Values
Typ.
Unit Note or condition
P-
Number
Min.
Max.
1)
Undervoltage auto-restart tUV_RESTART2
4
5
6
ms
PRQ-310
PRQ-311
PRQ-312
time 2
1)
Undervoltage auto-restart tUV_RESTART3 16
time 3
20
50
24
60
ms
1)
Undervoltage auto-restart tUV_RESTART4 40
time 4
ms
VBAT overvoltage auto-restart duration
1)
Overvoltage auto-restart
time 1
tOV_RESTART1 10
tOV_RESTART2 40
tOV_RESTART3 160
tOV_RESTART4 0.8
13
50
200
1
16
µs
PRQ-299
PRQ-301
PRQ-302
PRQ-303
1)
Overvoltage auto-restart
time 2
60
µs
1)
Overvoltage auto-restart
time 3
240
1.2
µs
1)
Overvoltage auto-restart
time 4
ms
Temperature warning and shutdown
1)
Thermal warning junction TJW
110
155
–
130
175
10
150
195
–
°C
PRQ-48
PRQ-49
PRQ-405
PRQ-406
temperature
1)
Thermal shutdown
junction temperature
TJSD
°C
1)
Thermal warning
hysteresis
TJW_HYS
TJSD_HYS
K
1)
Thermal shutdown
hysteresis
–
10
–
K
VDD undervoltage
VDD_UV switch ON voltage VDD_UV_ON
–
–
2.8
0.5
V
V
–
–
PRQ-120
PRQ-507
Ground loss
Ground loss
|VGND_LOSS
|
0.18
0.3
1)
Not subject to production test, specified by design.
Datasheet
32
Rev. 1.10
2022-12-20
EiceDRIVER™ APD 2ED4820-EM
48 V smart high-side MOSFET gate driver with SPI
7 SPI
7
SPI
The device provides a SPI communication slave which uses the input lines SCLK, CSN and MOSI and the output
line MISO.
The SPI uses a 16-bit protocol which transfers the MSB first and provides a daisy chain capability with other
16-bit SPI devices.
Any 16-bit data transfer starts by a falling edge on CSN.
While CSN is low, the incoming data on MOSI is sampled on the falling edge of SCLK while the outgoing data on
MISO is shifed out on the rising edge of SCLK.
Each 16-bit data transfer is terminated by a rising edge on CSN.
The SPI includes a modulo 16 counter ensuring that data is taken only when a multiple of 16 bit has been
transferred.
In case a wrong number of bit is transferred, or a wrong number of clock cycles is propagated, the SPI interface
will generate a transmission error and it will not accept the data that has been just sent.
The system microcontroller selects the device by means of the CSN pin.
If CSN is high, the SPI ignores any signals at the SCLK and MOSI pins and forces the pin MISO into a high
impedance state.
tCSN(LEAD)
tSCLK(P)
tCSN(LAG)
tCSN(TD)
CSN
VIH,min
VIL, max
t
t
t
t
tSCLK(H) tSCLK(L)
SCLK
VIH,min
VIL, max
tSI(SU) tSI(H)
MOSI
VIH,min
VIL, max
tSO(DIS)
tSO(EN)
tSO(V)
MISO
VOH,min
VOL, max
Figure 10
SPI timings
7.1
Communication start
While CSN is low, data transfer can take place.
If CSN changes from high to low and SCLK is low for tCSN LEAD or longer:
•
•
•
The SPI transfers the information requested in the previous communications into the shif buffer
The pin MISO changes from high impedance state to low state within tSO(EN)
The modulo16 counter starts counting SCLK clocks
Note:
CSN has to be kept low during the transfer of the whole communication frame.
If SCLK changes from low to high while CSN is low:
The MISO signals the bit shifed out of the shif buffer (first clock the MSB) afer tSO(V)
If SCLK changes from high to low while CSN is low:
The data bits are shifed for one position to the MSB direction
•
•
Datasheet
33
Rev. 1.10
2022-12-20
EiceDRIVER™ APD 2ED4820-EM
48 V smart high-side MOSFET gate driver with SPI
7 SPI
•
•
The MOSI signal is read into the shif buffer (at the LSB position) within tSI(H)
The modulo 16 counter is increased by 1
The SPI MOSI input has to be valid tSI(SU) before the falling edge of SCLK.
The clock circles with write, read and shif function have to be repeated, until the whole frame is read into the
shif buffer (e.g. 16 repetitions for one SPI buffer).
7.2
Communication end
If CSN rises from low to high and the SCLK is low since tCSN(LAG), the value of the modulo 16 counter is checked.
If the modulo 16 counter signals a multiple (1,2,3...) of 16 SCLK clocks, the shif buffer data is executed as
command (e.g. writing into the addressed register) within tCSN(TD)
.
MISO signals switches to high impedance within tSO(DIS) afer CSN went high.
The SPI interface is ready to start a new transfer with a CSN to low transition if the time tCSN(TD) elapsed afer the
CSN went high.
7.3
SPI: electrical characteristics: timings
Unless otherwise specified: VBAT and VDD inside the normal operation range; TJ = -40°C to +150°C.
Table 22
SPI electrical characteristics: timings
Parameter
Symbol
Values
Typ.
Unit Note or condition
P-
Number
Min.
400
Max.
1)
Transfer delay time
Enable lead time
tCSN(TD)
tCSN(LEAD)
tCSN(LAG)
tSO(EN)
–
–
–
–
ns
PRQ-370
PRQ-371
PRQ-372
PRQ-373
PRQ-374
PRQ-375
PRQ-376
1)
200
200
–
–
ns
1)
Enable lag time
–
ns
1)
Output enable time
Output disable time
Serial clock high time
Serial clock low time
SPI frequency
100
100
–
150
150
–
ns
ns
ns
ns
Cload = 100 pF
Cload = 100 pF
1)
1)
1)
tSO(DIS)
tSCLK(H)
tSCLK(L)
–
90
90
–
–
1)
1)
1)
1)
1)
Serial clock frequency
Serial input setup time
Serial input hold time
Serial output valid time
SCLK duty cycle
fSCLK
0.5
20
20
–
–
5
MHz
ns
PRQ-377
PRQ-426
PRQ-427
PRQ-428
PRQ-478
tSI(SU)
tSI(H)
–
–
–
–
ns
tSO(V)
DCSCLK
100
50
150
53
ns
Cload = 100 pF
47
%
1)
Not subject to production test, specified by design.
Datasheet
34
Rev. 1.10
2022-12-20
EiceDRIVER™ APD 2ED4820-EM
48 V smart high-side MOSFET gate driver with SPI
7 SPI
7.4
Daisy Chain
Device 1
Device 2
SPI
Device 3
SPI
MOSI
MISO MOSI
MISO MOSI
MISO
SPI
MOSI
MCSN
MCLK
MISO
Figure 11
Daisy chain capability
The SPI of the device provides daisy chain capability for modulo 16 bit SPI devices. In this configuration several
devices are activated by the same CSN signal, called MCSN. The MOSI line of one device is connected with the
MISO line of another device (see Figure 11), in order to build a chain. The end of the chain is connected to the
input of the microcontroller, the output of the microcontroller to the beginning of the chain. The master device
provides the master clock MCLK which is connected to the SCLK line of each device in the chain.
The microcontroller must set the MCSN to low and start the communication with a multiple of 16 bit data, the
multiplier is the number of chained devices. The first data sent goes to the last devices (device 3 in Figure 11)
with the last bit transferred. Afer the communication is finished the MCSN must go to high again.
Note:
A wrong number of master serial clocks will generate a transmission error from all devices in the
chain.
7.5
SPI Protocol
SI
frame A
frame B
frame C
previous
response
response to
frame A
response to
frame B
SO
Figure 12
Command response sequence
The SPI protocol provides the answer to a command frame only with the next transmission triggered by the
microcontroller.
The relationship between MOSI and MISO content during SPI communication is shown in Figure 12.
MOSI line represents the frame sent from the microcontroller and MISO line is the answer provided by the gate
driver SPI. The “previous response” means that the frame sent back depends on the command frame sent from
the microcontroller before.
The responses of write commands are deterministic and are reporting the default diagnosis register.
The responses of a read command are the required register.
In case of transmission error the default response is the diagnosis register with the transmission error bit set to
1.
The SPI word is 16 bit wide and is structured according to the following tables.
Datasheet
35
Rev. 1.10
2022-12-20
EiceDRIVER™ APD 2ED4820-EM
48 V smart high-side MOSFET gate driver with SPI
8 Register specification
Word from microcontroller:
Read/Write
Address
Data
R/W
A6/nu A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Response from SPI interface :
Trans ERROR
TER
Address
Data
A6/nu A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
A6..A0 are used to address a register, D7..D0 are data.
Note: Bit A6 is reserved for future use (default value 0).
The microcontroller can access to the SPI registers using the 16 bit word as described below.
Write procedure :
•
•
•
Set MSB to 1 (read/write bit)
Addressing the register using A [6...0]
Preparing the data in Data [7 ... 0]
Read procedure:
•
•
•
Set MSB to 0 (read/write bit)
Addressing the register using A [6...0]
Data bits are don't care
Any communication of the microcontroller with the SPI interface is responded by the SPI interface.
In any case the response will report the transmission error bit TER as MSB representing the validity of the
previous communication.
Table 23
TER bit
TER bit
Communication status
1
0
Error in the previous communication
No error in the previous communication
Afer a reset as described in Chapter 4.2.4, the TER bit in the response to the first command is set high, to inform
the master that this is the first communication.
Beside the TER bit, the response to a microcontroller communication contains:
•
•
In case of a write command: the standard diagnosis (address 00000b).
In case of a read command: the data in the addressed register. In this case, the answer will contain both the
address of the register and the data there contained.
The answer is on the next frame, as explained in Figure 12.
The first response afer power on is by default the standard diagnosis register content. Within the information
the VDD_UV is set to 1 in order to inform about the power off situation before the communication.
8
Register specification
8.1
Control registers
Datasheet
36
Rev. 1.10
2022-12-20
EiceDRIVER™ APD 2ED4820-EM
48 V smart high-side MOSFET gate driver with SPI
8 Register specification
Datasheet
37
Rev. 1.10
2022-12-20
EiceDRIVER™ APD 2ED4820-EM
48 V smart high-side MOSFET gate driver with SPI
8 Register specification
Table 24
Bit descriptions
Bit Bit name
Register
Name
Description
STDIAG
7
6
5
4
3
2
FAILURE
Main failure indication, 1 when there is a failure
Charge pump is ready
VCP_READY
MEM_FAIL
OT_WARNING
TSD
Error in the memory, trimming not possible (flag cannot be cleaned)
Temperature warning
Chip in overtemperature (latched)
VDD_UV
VDD undervoltage propagated in the first command and indicates
an under voltage event
1
0
7
6
5
4
3
2
1
0
VBAT_UV
VBAT_OV
VCP_UV
VBAT undervoltage failure (not latched)
VBAT overvoltage failure (not latched)
Charge pump undervoltage
CHDIAG
ITRIP
Overcurrent failure (latched)
VGSTH_B
VDSTRIP_B
VSOURCE_B
VGSTH_A
VDSTRIP_A
VSOURCE_A
LOG_A
Gate-source undervoltage - channel B (latched)
Drain to source overvoltage - channel B (latched)
Source overvoltage - channel B
Gate-source undervoltage - channel A (latched)
Drain to source overvoltage - channel A (latched)
Source overvoltage - channel A
DIAG
4
3
2
1
Loss of ground connection on AGND
Loss of ground connection on GND
Loss of ground connection on CPGND
Address not available
LOG_D
LOG_CP
ADD_NOT_AVAIL
SAFESTATEN
CHCRCTRL
0
7
Reflection of the SAFESTATEN pin
Channel cross control activation
MOS_CHS_CT
RL
6
5
4
3
2
1
0
7
ITRIP_CL
Clear ITRIP flag
VGSTH_B_CL
VDSB_CL
Clear VGS flag channel B
Clear VDS flag channel B
Switch on channel B
MOSONCH_B
VGSTH_A_CL
VDSA_CL
Clear VGS flag channel A
Clear VDS flag channel A
Switch on channel A
MOSONCH_A
VCP_UC_CL
FAILURE
CLEAN
Clear charge pump undervoltage failure
5
4
SAFESTATE_CL
INT_CLEAN
TSD_CL
Clear Safestate failure
Clear interrupt
3
2
Clear overtemperature failure
Clear VDD undervoltage failure
VDD_UV_CL
(table continues...)
Datasheet
38
Rev. 1.10
2022-12-20
EiceDRIVER™ APD 2ED4820-EM
48 V smart high-side MOSFET gate driver with SPI
8 Register specification
Table 24
(continued) Bit descriptions
Bit Bit name Description
Register
Name
1
0
7
VBATUV_CL
VBATOV_CL
VDSB_SS
Clear VBAT overvoltage failure
Clear VBAT undervoltage failure
VDSTHA_B
VDS channel B safe state on when 1. VDS safe state off when 0.
Drain-source overvoltage threshold channel B
VDS channel A safe state on when 1. VDS safe state off when 0.
Drain-source overvoltage threshold channel A
MOS voltage blank time channel B
[6:4] VDSTH_B
VDSA_SS
[2:0] VDSTH_A
3
MOSFLTBLKA_ [7:6] MOSBLK_B
B
[5:4] MOSFLT_B
[3:2] MOSBLK_A
[1:0] MOSFLT_A
MOS voltage filter time channel B
MOS voltage blank time channel A
MOS voltage filter time channel A
CSAG_OCTH
6
CSA_COUTSEL
Configures the current sense amplifier output stage depending on
the output capacitor
5
CSA_HSS
Control signal to select the CSA configuration LSS or HSS (or
bidirectional)
[4:3] OCTH
[2:0] CSAG
Overcurrent detection thresholds
Current sense amplifier gain GDIFF
VBAT undervoltage auto-restart time
VBAT overvoltage auto-restart time
Reset Fails registers 1
VBATOVUVRST [3:2] VBATUVARST
[1:0] VBATOVARST
RESETS
5
FAIL_RST_1
SFT_RST_1
4
2
1
0
7
6
5
4
3
2
1
0
Sofꢀare Reset 1
GEN_INTERRUPT Generate interrupt signal
FAIL_RST_0
SFT_RST_0
SPARE_7
SPARE_6
SPARE_5
SPARE_4
SPARE_3
SPARE_2
SPARE_1
SPARE_0
Reset Fails registers 0
Sofꢀare Reset 0
SPARE_REG
Spare register bit 7
Spare register bit 6
Spare register bit 5
Spare register bit 4
Spare register bit 3
Spare register bit 2
Spare register bit 1
Spare register bit 0
Datasheet
39
Rev. 1.10
2022-12-20
EiceDRIVER™ APD 2ED4820-EM
48 V smart high-side MOSFET gate driver with SPI
9 Application information
9
Application information
9.1
48 V battery protection switch with low-side current sense and
capacitive pre-charge
CVBAT
Low
Ohmic
Path
CVCP
CCPHL
CPL
5V or
3.3V
VBAT VCP CPH
RG
VDD
GA
SA
CVDD
RGS
2ED4820-EM
MCU
RProt
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
CSN
SCLK
MOSI
MISO
Capacitor
Pre-Charge
Path
48V
Battery
cells
RG
INTERRUPT
ENABLE
SAFESTATEN
GB
SB
RGS
ADC
CSO
RFiltCSO
CFiltCSO
RPreCh
RFiltSh
CFiltSh
RFiltSh
ISN
ISP
Shunt
Freewheel.
diode
LOAD(s)
AGND
GND EP
CPGND
Figure 14
48 V battery protection switch application diagram
Datasheet
40
Rev. 1.10
2022-12-20
EiceDRIVER™ APD 2ED4820-EM
48 V smart high-side MOSFET gate driver with SPI
9 Application information
9.2
Common drain with high-side current sense
RFiltSh
CFiltSh
Shunt
CVCP
CCPHL
CPL
RFiltSh
ISP ISN VCP CPH
5V or
3.3V
VDD
CSO
SA
CVDD
RGS
RG
GA
ADC
VBAT
RFiltCSO
CFiltCSO
CVBAT
2ED4820-EM
RG
MCU
GB
SB
RProt
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
CSN
48V
SCLK
MOSI
MISO
Battery
cells
RGS
INTERRUPT
ENABLE
SAFESTATEN
Freewheel.
diode
LOAD(s)
AGND
GND EP
CPGND
Figure 15
Common drain with high-side current sense application diagram
9.3
Bill of material
Supply pins have to be decoupled with ceramic capacitors, positioned as follows:
•
•
•
CVBAT close to VBAT and AGND pins
CVDD close to VDD and GND pins
CVCP close to VCP and VBAT pins
Table 25
Bill of material
Reference
RProt
Value
1.0 kΩ
1.0 µF
Purpose
Protection of the microcontroller
CVDD
Supply decoupling; on layout, located close to the VDD & GND
pins
CVBAT
CVCP
4.7 µF + 220 nF
Supply decoupling; on layout, located close to the VBAT & AGND
pins
2.2 µF
Charge pump output capacitor - value depends on number of
MOSFETs to drive
CCPHL
RG
220 nF
10.0 Ω
150.0 kΩ
10.0 Ω
Charge pump capacitor
Gate protection resistor
RGS
Gate to source pull-down resistor
Power resistor limiting the capacitor pre-charge current
RPreCh
(table continues...)
Datasheet
41
Rev. 1.10
2022-12-20
EiceDRIVER™ APD 2ED4820-EM
48 V smart high-side MOSFET gate driver with SPI
9 Application information
Table 25
(continued) Bill of material
RFiltCSO
10.0 kΩ
10 nF
4.7 Ω
1 µF
Protection of the microcontroller and low pass filter on current
sense output
CFiltCSO
RFiltSh
CFiltSh
Low pass filter on current sense output - value depends on
bandwidth required
Filter to cancel the inductive part of the shunt - value depends on
Shunt
Filter to cancel the inductive part of the shunt - value depends on
Shunt
Datasheet
42
Rev. 1.10
2022-12-20
EiceDRIVER™ APD 2ED4820-EM
48 V smart high-side MOSFET gate driver with SPI
10 Package
10
Package
Figure 16
Package dimensions
To meet the world-wide customer requirements for environmentally friendly products and to be compliant with
government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e.
Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
Datasheet
43
Rev. 1.10
2022-12-20
EiceDRIVER™ APD 2ED4820-EM
48 V smart high-side MOSFET gate driver with SPI
Revision history
Revision history
Document
Date of
Description of changes
version
release
Rev.1.10
Rev.1.00
2022-12-20
2021-07-23
•
•
•
Updated Block diagram, Figure 2
Added PRQ-544 in Chapter 5.3
Improved CMRR performance Chapter 6.3.3.9.5 → PRQ-64, PRQ-148,
PRQ-149, PRQ-150, PRQ-210, PRQ-211, PRQ-212, PRQ-213
•
Datasheet creation
Datasheet
44
Rev. 1.10
2022-12-20
Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
Edition 2022-12-20
Published by
Infineon Technologies AG
81726 Munich, Germany
Important notice
Warnings
The information given in this document shall in no
event be regarded as a guarantee of conditions or
characteristics (“Beschaffenheitsgarantie”).
With respect to any examples, hints or any typical
values stated herein and/or any information regarding
the application of the product, Infineon Technologies
hereby disclaims any and all warranties and liabilities
of any kind, including without limitation warranties of
non-infringement of intellectual property rights of any
third party.
In addition, any information given in this document is
subject to customer’s compliance with its obligations
stated in this document and any applicable legal
requirements, norms and standards concerning
customer’s products and any use of the product of
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