2ED1322S12M [INFINEON]
EiceDRIVER™ 1200 V half-bridge gate driver IC with typical 2.3 A source, 4.6 A sink current and cross conduction prevention in DSO-16 (300mils) package for 1200 V SiC MOSFET and IGBT power devices. The 2ED1322S12M is based on our SOI-technology which has an excellent ruggedness and noise immunity against negative transient voltages on VS pin. Since the device has no parasitic thyristor structures, the design is very robust against parasitic latch up across the operating temperature and voltage range.;型号: | 2ED1322S12M |
厂家: | Infineon |
描述: | EiceDRIVER™ 1200 V half-bridge gate driver IC with typical 2.3 A source, 4.6 A sink current and cross conduction prevention in DSO-16 (300mils) package for 1200 V SiC MOSFET and IGBT power devices. The 2ED1322S12M is based on our SOI-technology which has an excellent ruggedness and noise immunity against negative transient voltages on VS pin. Since the device has no parasitic thyristor structures, the design is very robust against parasitic latch up across the operating temperature and voltage range. 驱动 双极性晶体管 |
文件: | 总31页 (文件大小:1033K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
2ED1322S12M/2ED1321S12M
1200 V half-bridge gate driver with integrated bootstrap diode and OCP
Features
Product summary
Unique Infineon Thin-Film-Silicon On Insulator (SOI)-technology
VS_OFFSET = 1200 V (maximum)
Io+ / Io- = 2.3 A / 4.6 A (peak)
VCC = 13 V to 20 V (typical)
Propagation delay = 500 ns typ.
Dead-time = 380 ns typ.
Floating channel designed for bootstrap operation
Maximum bootstrap voltage (VB node) of + 1225 V
Operating voltages (VS node) upto + 1200 V
Negative VS transient voltage immunity of 100 V
With repetive 700 ns pulses
2.3 A / 4.6 A peak output source / sink current capability
Integrated ultra-fast over-current protection (OCP)
± 5% high accuracy reference threshold
Less than 1 us over-current sens to output shutdown
Integrated ultra-fast, low resistance bootstrap diode
Integrated dead-time and shoot-through prevention logic(2ED1322S12M)
Enable, Fault, and programmable Fault clear RFE input
Logic operational up to –8 V on VS Pin
Independent per channel undervoltage lockout (UVLO)
25 V VCC supply voltage (maximum)
Separate Logic (VSS) and output ground (COM)
Greater than 5 mm clearance / creepage
Package
2 kV HBM ESD capability
PG-DSO-16-U02 (300 mil)
Typical applications
Industrial Drives
Embedded inverters for Motor Control in Pumps, Fans
Commercial and Lite Commercial Air Conditioning
Product validation
Qualified for industrial applications according to the relevant tests of JEDEC78/20/22
Ordering information
Standard pack
Sales Product Name Package type
Orderable part number
Form
Tape and Reel
Tape and Reel
Quantity
1,000
PG-DSO-16-U02
PG-DSO-16-U02
2ED1322S12M
2ED1321S12M
2ED1322S12MXUMA1
2ED1321S12MXUMA1
1,000
Datasheet
www.infineon.com/soi
Please read the Important Notice and Warnings at the end of this document
Page 1 of 31
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2ED1322S12M/2ED1321S12M
1200 V half bridge gate driver with integrated bootstrap diode and OCP
Description
The 2ED132x family contains devices, which control IGBT or SiC MOSFET power devices with a maximum blocking
voltage of +1200 V in half bridge configurations. Based on the used SOI-technology there is an excellent
ruggedness on transient voltages. No parasitic thyristor structures are present in the device. Hence, the design
is very robust against parasitic latch up across the operating temperature and voltage range.
The two independent driver outputs are controlled at the low-side using two different CMOS resp. LSTTL
compatible signals, down up to 3.3V logic. The device includes an under-voltage detection unit with hysteresis
characteristic.
The 2ED132x has symmetric undervoltage lockout levels, which support strongly the integrated ultrafast
bootstrap diode. Additionally, the offline gate clamping function provides an inherent protection of the
transistors for parasitic turn-on by floating gate conditions, when the IC is not supplied via VCC.
VCC
VBUS
VCC
VB
HO
Refer to lead assignments for
correct pin configuration. This
diagram shows electrical
connections only. Please refer to
our application notes and design
tips for proper circuit board
layout.
HIN
LIN
VS
To Load
RFE 2ED1322
ITRIP 2ED1321
VCC
LO
COM
VSS
*Bootstrap diode is monolithically integrated
Figure 1
Typical application block diagram
Summary of feature comparison of the 2ED132x family:
Table 1
Source /
sink drive
(peak - A)
Integrated
Integrated
Cross
conduction
prevention
Sales Product
Name
Key
Features
tON / tOFF
(typ)
Package Type
Bootstrap
Deadtime
Diode
OCP, AMC,
SCC, RFE
PG-DSO-20-U03 + 2.3 / - 2.3
2ED1324S12P
Yes
No
380 ns
None
Yes
Yes
500 ns
350 ns
OCP, AMC,
SCC, RFE
+ 2.3 / - 2.3
2ED1323S12P PG-DSO-20-U03
+ 2.3 / - 4.6
+ 2.3 / - 4.6
2ED1322S12M PG-DSO-16-U02
2ED1321S12M PG-DSO-16-U02
OCP, RFE
OCP, RFE
Yes
No
380 ns
None
Yes
Yes
500 ns
350 ns
Datasheet
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2ED1322S12M/2ED1321S12M
1200 V half bridge gate driver with integrated bootstrap diode and OCP
1
Table of contents
Features
Product summary ........................................................................................................................1
Typical applications.....................................................................................................................................................1
Product validation .......................................................................................................................................................1
Ordering information...................................................................................................................................................1
Description
2
1
2
Table of contents ................................................................................................................... 3
Block diagram........................................................................................................................ 4
3
3.1
3.2
Pin configuration and functionality.......................................................................................... 5
Pin configuration.....................................................................................................................................5
Pin functionality ......................................................................................................................................6
4
Electrical parameters ............................................................................................................. 7
Absolute maximum ratings.....................................................................................................................7
Recommended operating conditions.....................................................................................................8
Static electrical characteristics...............................................................................................................9
Dynamic electrical characteristics........................................................................................................10
4.1
4.2
4.3
4.4
5
5.1
5.2
5.3
5.4
5.5
5.6
5.7
Application information and additional details.........................................................................11
Gate drive...............................................................................................................................................11
Switching relationships.........................................................................................................................11
Timing diagram .....................................................................................................................................12
Deadtime ...............................................................................................................................................13
Matched propagation delays ................................................................................................................13
Input logic compatibility.......................................................................................................................14
Undervoltage lockout ...........................................................................................................................14
Shoot-through protection.....................................................................................................................15
Enable, Fault reporting and programmable fault clear timer .............................................................15
Over-current protection........................................................................................................................16
Truth table: Undervoltage lockout, OCP and Enable...........................................................................17
Daisy Chain Multiple Devices ................................................................................................................17
Bootstrap diode.....................................................................................................................................18
Calculating the bootstrap capacitance CBS ..........................................................................................19
Tolerant to negative transients on input pins......................................................................................21
Negative voltage transient tolerance of VS pin....................................................................................21
NTSOA – Negative Transient Safe Operating Area ...............................................................................22
PCB layout tips ......................................................................................................................................23
5.8
5.9
5.10
5.11
5.12
5.13
5.14
5.15
5.16
5.17
5.18
6
7
8
9
Qualification information.......................................................................................................25
Related products...................................................................................................................26
Package details.....................................................................................................................27
Part marking information ......................................................................................................28
10
10.1
Additional documentation and resources.................................................................................29
Infineon online forum resources ..........................................................................................................29
11
Revision history ....................................................................................................................30
Datasheet
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2ED1322S12M/2ED1321S12M
1200 V half bridge gate driver with integrated bootstrap diode and OCP
2
Block diagram
VB
HO
VS
S
Input
Noise
filter
Latch
&
UV Detect
HV Level
Shifter
HIN
Driver
Deadtime & Shoot-
Through Prevention
R
Input
Noise
filter
LIN
VSS
UV
Detect
VCC
ITRIP
RFE
ITRIP
Noise
filter
VSS/COM
Level
Shifter
Driver
Delay
LO
COM
Noise
filter
Figure 2
Block diagram of 2ED1322S12M
Datasheet
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2ED1322S12M/2ED1321S12M
1200 V half bridge gate driver with integrated bootstrap diode and OCP
3
Pin configuration and functionality
3.1
Pin configuration
1
2
3
4
5
6
7
8
HIN
LIN
DNC 16
NC 15
NC 14
RFE
VSS
ITRIP
COM
LO
VS
13
HO 12
VB 11
NC 10
DNC
VCC
9
16-Lead PG-DSO-16-U02 (300 mil)
2ED1322S12M/2ED1321S12M
Figure 3
Pin assignment (top view)
Datasheet
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2ED1322S12M/2ED1321S12M
1200 V half bridge gate driver with integrated bootstrap diode and OCP
3.2
Pin functionality
Table 2
Symbol
Description
HIN
LIN
Logic input for high side gate driver output (HO), in phase with HO
Logic input for low side gate driver output (LO), in phase with LO
Integrated fault reporting function like over-current protection (OCP), or low-side
undervoltage lockout and the fault clear timer. This pin has negative logic and an
open-drain output. The use of over-current protection requires the use of
external components
RFE
VSS
Logic ground
Analog input for over-current shutdown. When active, OCP shuts down outputs
and activates RFE low. When OCP becomes inactive, RFE stays active low for an
externally set time tFLTCLR, then automatically becomes inactive (open-drain high
impedance)
ITRIP
COM
LO
Low-side gate drive return
Low-side driver output
VCC
VS
Low-side and logic supply voltage
High voltage floating supply return
High-side driver output
HO
VB
High-side gate drive floating supply
Pin Not Connected
NC
DNC
Do Not Connect the pin to any electrical node
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2ED1322S12M/2ED1321S12M
1200 V half bridge gate driver with integrated bootstrap diode and OCP
4
Electrical parameters
4.1
Absolute maximum ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage
parameters are absolute voltages referenced to COM unless otherwise stated in the table. The thermal resistance
and power dissipation ratings are measured under board mounted and still air conditions. (Ta = 25oC).
Table 3
Absolute maximum ratings
Symbol
Definition
High-side floating well supply voltage Note 1
High-side floating well supply return voltage Note 1
High-side floating supply voltage (VB vs. VS)
(internally clamped)
Floating gate drive output voltage
Low side supply voltage (VCC vs. VSS) (internally
clamped)
Min.
-0.5
VB – 25
Max.
1225
VB + 0.5
Units
VB
VS
VBS
VHO
-1
VS – 0.5
-1
25
VB + 0.5
25
V
VCCGND
Low side supply voltage (VCC vs. VCOM) (internally
clamped)
VCC
-1
25
VLO
VIN
Low-side output voltage
Logic input voltage (HIN, LIN, RFE, ITRIP)
–0.5
VSS - 5
—
—
—
VCC + 0.5
VCC + 0.5
50
dVS/dt Allowable VS offset supply transient relative to COM
PD
RthJA
V/ns
W
Note 2
1.6
78
Package power dissipation @ TA +25ºC
Thermal resistance, junction to ambient Note 3
Characterization parameter junction to package
topNote 3
ºC/W
ºC
ΨJtop
4
TJ
TS
TL
Junction temperature
Storage temperature
Lead temperature (soldering, 10 seconds)
-40
-55
—
150
150
300
Note 1: In case VCC > VB there is an additional power dissipation in the internal bootstrap diode between pins VCC and VB in case of
activated bootstrap diode
Note 2: Consistent power dissipation of all outputs. All parameters inside operating range
Note 3: Obtained in a simulation on a JEDEC-standard and Ta = 50 °C, PD= 1W, PCB: JEDEC 2s2p (JESD 51-5)
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2ED1322S12M/2ED1321S12M
1200 V half bridge gate driver with integrated bootstrap diode and OCP
4.2
Recommended operating conditions
For proper operation, the device should be used within the recommended conditions. All voltage parameters
are absolute voltages referenced to COM unless otherwise stated in the table. The offset rating is tested with
supplies of (VCC – COM) = (VB – VS) = 15 V (Ta = 25oC).
Table 4
Recommended operating conditions
Symbol
Definition
Bootstrap voltage
High-side floating well supply voltage
Min
VS + 13
13
Max
VS + 20
20
Units
VB
VBS
VS
High-side floating well supply offset voltage Note 1
Transient High-side floating well supply offer
-8
1200
VSt
-100
1200
Note 2
voltage (<700ns)
V
VHO
VCC
VLO
VIN
VSS
tIN
Floating gate drive output voltage
Low-side supply voltage
Low-side output voltage
Logic input voltage (HIN, LIN, RFE, ITRIP)
Logic ground
Minimal pulse width for ON or OFF
Ambient temperature
VS
13
0
VSS
-5
0.3
-40
VB
20
VCC
VCC
5
—
125
µs
ºC
TA
Note 1: Logic operational for VS of -8 V to +1200 V
Note 2: In case VCC > VB there is an additional power dissipation in the internal bootstrap diode between pins VCC and VB. Insensitivity of
bridge output to negative transient voltage up to –100 V is not subject to production test – verified by design / characterization
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2ED1322S12M/2ED1321S12M
1200 V half bridge gate driver with integrated bootstrap diode and OCP
4.3
Static electrical characteristics
(VCC– COM) = (VB – VS) = 15 V, VSS = COM and TA = 25 °C unless otherwise specified. The VIL, VIH and IIN parameters are
referenced to COM and are applicable to the respective input leads: HIN and LIN. The VO and IO parameters are
referenced to VS / COM and are applicable to the respective output leads HO or LO. The VCCUV parameters are
referenced to COM. The VBSUV parameters are referenced to VS.
Table 5
Symbol
Static electrical characteristics
Definition
Min.
11.5
10.6
0.5
Typ.
12.2
11.3
0.9
Max. Units Test Conditions
VBSUV VBS supply undervoltage positive going threshold
12.9
12
+
VBSUV VBS supply undervoltage negative going threshold
-
V
VBSUVHY
VBS supply undervoltage hysteresis
—
VCCUV VCC supply undervoltage positive going threshold
11.5
10.6
0.5
12.2
11.3
0.9
12.9
12
—
+
VCCUV VCC supply undervoltage negative going threshold
-
VCCUVHY
VCC supply undervoltage hysteresis
VB = 1215 V
VS = 1200 V
ILK
IQBS
IQCC
High-side floating well offset supply leakage
—
0.5
20
uA
Quiescent VBS supply current
Quiescent VCC supply current
—
—
—
—
1.4
180
600
0.32
0.18
2.0
350
VIN = 0V or 3.3V
1000
VOH High level output voltage drop, Vcc- VLO , VB- VHO
VOL Low level output voltage drop, VO
Io+mean Mean output current from 4.5 V to 7.5 V
0.7
0.4
—
V
A
V
IO = 100 mA
CL = 56 nF
RL = 0 Ω
PW ≤ 10 µs
CL = 56 nF
RL = 0 Ω
1
Io+
Peak output current turn-on
—
2.8
—
2.3
4.0
4.6
—
—
—
Io-mean Mean output current from 7.5 V to 4.5 V
1
Io-
Peak output current turn-off
PW ≤ 10 µs
VIH
VIL
Logic “1” input voltage (HIN, LIN, EN)
Logic “0” input voltage (HIN, LIN, EN)
1.7
0.7
15
—
—
—
2.0
0.9
35
0
0
0
2.3
1.1
60
—
1
—
1
IIN+ Input bias current (Output = High)
IIN- Input bias current (Output = Low)
IRFE+ Logic “1” Input bias current (RFE)
IRFE- Logic “0” Input bias current (RFE)
IITRIP+ Logic “1” Input bias current (ITRIP)
IITRIP- Logic “0” Input bias current (ITRIP)
VIN = 3.3 V
VIN = 0 V
VRFE = 3.3 V
= 0 V
VRFE
VIN = 1 V
VIN = 0 V
µA
—
—
0
0
—
Bootstrap diode forward voltage between Vcc and
VFBSD
VB
—
1
1.2
V
IF=0.3 mA
Bootstrap diode forward current between Vcc and
IFBSD
VB
40
70
100
mA
VCC-VB = 4 V
VF1 = 4 V,
VF2 = 5 V
VRFE = 0.5 V
IOUT- = 200 mA
VCC/VBS open
RBSD Bootstrap diode resistance
18
—
—
30
35
42
70
Ω
Ron,FLT RFE low on resistance of the pull-down transistor
VACTSD Active shut-down voltage
2.1
2.4
V
Vth,OCP OCP comparator threshold
Vth,OCPH OCP comparator hysteresis
0.416
0.04
0.44
0.05
0.464
—
1 Not subjected to production test, verified by design/characterization
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2ED1322S12M/2ED1321S12M
1200 V half bridge gate driver with integrated bootstrap diode and OCP
4.4
Dynamic electrical characteristics
VCC = VBS= 15 V, TA = 25 oC and CL = 1000 pF unless otherwise specified.
Table 6 Dynamic electrical characteristics
Symbol Definition
Min.
400
250
400
250
—
Typ.
500
350
500
350
48
Max.
700
500
700
500
80
Units
Test Conditions
2ED1322
2ED1321
2ED1322
2ED1321
tON
Turn-on propagation delay
VIN = 0 V or 3.3 V
VS = 0 V or 1200 V
tOFF Turn-off propagation delay
tR
tF
Turn-on rise time
Turn-off fall time
VIN = 0 or 3.3 V
CL = 4.9 nF
VRFE = 0.5 V,
—
48
80
ns
TEN RFE Enable propagation delay
400
100
500
150
700
VLO/VHO = 20%
Input filter time at LIN/HIN for
tFILIN turn-on and -off
2ED1322
2ED1321
—
VIN = 0 & 3.3 V
25
35
—
tFILEN RFE Input filter time
tFLTCLR RFE Fault-clear time
tOCPfil ITRIP Filter time
100
150
220
VITRIP = 0.1 V,
VRFE = 2.1 V
VITRIP = 1 V
VITRIP = 1V
VOUT = 3V
120
0.3
0.4
160
0.5
—
0.7
0.9
tOCPOUT,LS OCP Sense to Low-side OUT LOW delay
tOCPOUT,HS OCP Sense to High-side OUT LOW delay
0.65
s
µ
VITRIP = 1V
VOUT = 3V
0.6
0.85
1.1
VITRIP = 1V
VRFE = 10%
tOCPFLT OCP Sense to RFE LOW delay
tUVLOFIL UVLO Noise filter
0.4
1.0
—
0.65
1.5
10
0.9
—
Delay matching time (HS & LS turn-
external dead time >
500 ns
MT
60
on/off)
DT Dead time (2ED1322 only)
260
—
380
10
540
80
VIN = 0 & 3.3 V
external dead time
0ns
ns
MDT Matching Dead time (2ED1322 only)
PM Output pulse width matching
—
20
80
PWIN > 1 µs
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2ED1322S12M/2ED1321S12M
1200 V half bridge gate driver with integrated bootstrap diode and OCP
5
Application information and additional details
5.1
Gate drive
The 2ED132xS12 HVIC is designed to drive IGBTs or SiC MOSFETs. Figure 4 and Figure 5 illustrate several
parameters associated with the gate drive functionality of the HVIC. The output current of the HVIC, used to drive
the gate of the power switch, is defined as IO. The voltage that drives the gate of the external power switch is
defined as VHO for the high-side power switch and VLO for the low-side power switch; this parameter is sometimes
generically called VOUT and in this case does not differentiate between the high-side or low-side output voltage.
VB
VB
(or VCC
)
(or VCC)
IO+
HO
HO
(or LO)
(or LO)
+
IO-
VHO (or VLO)
-
VS
VS
(or COM)
(or COM)
Figure 4
HVIC Sourcing current
Figure 5
HVIC Sinking current
5.2
Switching relationships
The relationships between the input and output signals of the 2ED132xS12 are illustrated below in Figure 6 and
Figure 7. From these figures, we can see the definitions of several timing parameters (i.e. tON, tOFF, tR, and tF)
associated with this device, and the input filter function that is used to reject noise.
tFILIN
tIN
HIN/LIN
50%
50%
tIN < tFILIN
HIN
LIN
HO/LO
HIN/LIN
HO/LO
tF
tON tR
tOFF
low
90%
90%
tIN
HO
LO
tIN > tFILIN
10%
10%
Figure 6
Switching timing diagram
Figure 7
Input filter
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2ED1322S12M/2ED1321S12M
1200 V half bridge gate driver with integrated bootstrap diode and OCP
5.3
Timing diagram
Here below Figure 8 and Figure 9 illustrate the timing relationships of some of the functionality of the
2ED1322S12M as an example; this functionality is described in further detail later in this document. During
interval A of Figure 8, the HVIC has received the command to turn-on both the high- and low-side switches at the
same time; as a result, the shoot-through protection of the HVIC has prevented this condition. HVIC is keeping on
output channel that is already on ignoring the 2nd input signal.
Interval B of Figure 8 and Figure 9 shows that the signal on the ITRIP input pin has gone from a low to a high state;
as a result, all of the gate drive outputs have been disabled (i.e., see that HO has returned to the low state; LO is
also held low), and a fault condition is reported on the RFE pin, which goes 0V. Once the ITRIP input has returned
to the low state, the output will remain disabled and the fault condition reported until the voltage on the RFE pin
charges up to VRFE+ threshold; the charging characteristics are dictated by the RC network attached to the RFE
pin. After fault clear time HVIC is waiting for a new input signal on LIN/HIN before activate the output stage
(LO/HO).
During interval C of Figure 8 and Figure 10, we can see that the RFE pin has been pulled low (as is the case when
the driver IC has received a command from the control IC to shutdown); these results in the outputs (HO and LO)
being held in the low state until the RFE pin is pulled high. After an enable event HVIC will wait for a new input
signal on LIN/HIN before activate the output stage (LO/HO).
Figure 8
ITRIP
Input/ put timing diagram
0.5V
tEN
RFE
0.1V
FAULT
2.1V
0.5V
tOCPFLT
tFLTCLR
Any
output
HO1
LO1
3V
3V
tOCPOUT
Figure 9
OCP timing (low-side)
Figure 10 Enable delay time
definition
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2ED1322S12M/2ED1321S12M
1200 V half bridge gate driver with integrated bootstrap diode and OCP
5.4
Deadtime
This 2ED1322S12M features integrated deadtime protection circuitry. The deadtime feature inserts a time period
(a minimum deadtime) in which both the high- and low-side power switches are held off; this is done to ensure
that the power switch being turned off has fully turned off before the second power switch is turned on. This
minimum deadtime is automatically inserted whenever the external deadtime is shorter than interal deadtime;
external deadtimes larger than internal deadtime are not modified by the gate driver. Figure 11 illustrates the
deadtime period and the relationship between the output gate signals.
The deadtime circuitry of 2ED1322S12M is matched with respect to the high- and low-side outputs. Figure 11
defines the two deadtime parameters (i.e., DTLO-HO and DTHO-LO); the deadtime matching parameter (MDT)
associated with the 2ED1322S12M specifies the maximum difference between DTLO-HO and DTHO-LO
.
HIN
50%
50%
LIN
LO
90%
10%
DTHO-LO
90%
DTLO-HO
HO
10%
MDT = I DTLO-HO – DTHO-LO
I
Figure 11 Deadtime matching waveform definition
5.5
Matched propagation delays
The 2ED132xS12 is designed with propagation delay matching circuitry. With this feature, the IC’s response at
the output to a signal at the input requires approximately the same time duration (i.e., tON, tOFF) for both the low-
side channels and the high-side channels; the maximum difference is specified by the delay matching parameter
(MT). The propagation turn-on delay (tON) of the 2ED132xS12 is matched to the propagation turn-on delay (tOFF).
50%
50%
HIN
LIN
LO
HO
10%
MT
HO
MT
90%
LO
Figure 12 Delay matching waveform definition
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2ED1322S12M/2ED1321S12M
1200 V half bridge gate driver with integrated bootstrap diode and OCP
5.6
Input logic compatibility
The input pins are based on a TTL and CMOS compatible input-threshold logic that is independent of the Vcc
supply voltage. With typical high threshold (VIH) of 2.0 V and typical low threshold (VIL) of 0.9 V, along with very
little temperature variation as summarized in Figure 13, the input pins are conveniently driven with logic level
PWM control signals derived from 3.3 V and 5 V digital power-controller devices. Wider hysteresis (typically 1.1 V)
offers enhanced noise immunity compared to traditional TTL logic implementations, where the hysteresis is
typically less than 0.5 V. 2ED132xS12 also features tight control of the input pin threshold voltage levels which
eases system design considerations and ensures stable operation across temperature. The 2ED132xS12 features
floating input protection wherein if any of the input pin is left floating, the output of the corresponding stage is
held in the low state. This is achieved using pull-down resistors on all the input pins (HIN, LIN) as shown in the
block diagram. The 2ED132xS12 has input pins that are capable of sustaining voltages higher than the bias
voltage applied on the Vcc pin of the device.
VIH
VIL
High
Low
Low
Figure 13 HIN & LIN input thresholds
5.7
Undervoltage lockout
This IC provides undervoltage lockout protection on both the VCC (logic and low-side circuitry) power supply and
the VBS (high-side circuitry) power supply. Figure 14 is used to illustrate this concept; VCC (or VBS) is plotted over
time and as the waveform crosses the UVLO threshold (VCCUV+/- or VBSUV+/-) the undervoltage protection is enabled
or disabled.
Upon power-up, should the VCC voltage fail to reach the VCCUV+ threshold, the IC won’t turn-on. Additionally, if the
VCC voltage decreases below the VCCUV- threshold during operation, the undervoltage lockout circuitry will
recognize a fault condition and shutdown the high and low-side gate drive outputs.
Upon power-up, should the VBS voltage fail to reach the VBSUV+ threshold, the IC won’t turn-on. Additionally, if the
VBS voltage decreases below the VBSUV- threshold during operation, the undervoltage lockout circuitry will
recognize a fault condition, and shutdown the high-side gate drive outputs of the IC.
The UVLO protection ensures that the IC drives the external power devices only when the gate supply voltage is
sufficient to fully enhance the power devices. Without this feature, the gates of the external power switch could
be driven with a low voltage, resulting in the power switch conducting current while the channel impedance is
high; this could result in very high conduction losses within the power device and could lead to power device
failure.
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2ED1322S12M/2ED1321S12M
1200 V half bridge gate driver with integrated bootstrap diode and OCP
VCC
(or VBS
)
VCCUV+
(or VBSUV+
)
VCCUV-
(or VBSUV-
)
Time
UVLO Protection
(Gate Drive Outputs Disabled)
Normal
Normal
Operation
Operation
Figure 14 UVLO protection
5.8
Shoot-through protection
The 2ED1322S12M is equipped with shoot-through protection circuitry (also known as cross-conduction
prevention circuitry). Figure 15 shows how this protection circuitry prevents both the high- and low-side switches
from conducting at the same time.
Note: 2ED1321S12M no shoot-through protection because it is a high-side and low-side gate driver, HO and LO
can turn on at the same time.
Figure 15 Illustration of shoot-through protection circuitry
5.9
Enable, Fault reporting and programmable fault clear timer
The 2ED132xS12 provides an enable functionality that allows it to shutdown or enable the HVIC and also provides
an integrated fault reporting output along with an adjustable fault clear timer. There are two situations that
would cause the IC to report a fault via the RFE pin. The first is an undervoltage condition of VCC and the second
is if the over-current feature has recognized a fault. Once the fault condition occurs, the RFE pin is internally
pulled to VSS and the fault clear timer is activated. The RFE output stays in the low state until the fault condition
has been removed and the fault clear timer expires; once the fault clear timer expires, the voltage on the RFE pin
will return to its external pull-up voltage.
The length of the fault clear time period (tFLTCLR) is determined by exponential charging characteristics of the
capacitor where the time constant is set by RRFE and CRFE. Figure 16 shows that RRFE is connected between the
external supply (VDD)1) and the RFE pin, while CRFE is placed between the RFE and VSS pins.
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2ED1322S12M/2ED1321S12M
1200 V half bridge gate driver with integrated bootstrap diode and OCP
VCC
HIN U
LIN U
HIN V
LIN V
HIN W
LIN W
VDD
HIN
LIN
uC
HO
VS
GK
RRFE
RFE
LO
CRFE
VSS
ITRIP
R
DC - BUS
Figure 16 Programming the fault clear timer
The design guidelines for this network are shown in Table 7
Table 7
Design guidelines
≤ 1 nF
CRFE
Ceramic capacitor
0.5 MΩ to 2 MΩ
>> RON,RCIN
RRFE
The length of the fault clear time period can be determined by using the formula below.
vC(t) = Vf*(1-e-t/RC
)
tFLTCLR = - (RRFE*CRFE) *ln (1-VRF+/VDD ) + 160us
The voltage on the RFE pin should not exceed the VDD of the uC power supply.
1) In case VDD is higher than 5V, the RRFE resistor needs to be at least 200 kΩ in order to limit the IC power
dissipation.
5.10
Over-current protection
The 2ED132xS12 is equipped with an over-current feature (ITRIP input pin). This functionality can sense over-
current events in the DC- bus or low side power switch. Once the HVIC detects an over-current event, the outputs
are shutdown, and RFE is pulled to VSS.
The level of current at which the over-current protection is initiated is determined by the resistor network (i.e.,
R0, R1, and R2) connected to ITRIP as shown in Figure 17, and the OCP threshold (Vth,OCP). The circuit designer will
need to determine the maximum allowable level of current in the DC- bus and select R0, R1, and R2 such that the
voltage at node VX reaches the over-current threshold (Vth,OCP) at that current level.
Vth,OCP = R0*IDC-*(R1/ (R1+R2))
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2ED1322S12M/2ED1321S12M
1200 V half bridge gate driver with integrated bootstrap diode and OCP
DC BUS +
VCC
VB
HIN
LIN
RFE
HO
ITRIP
VS
To load
LO
VSS
COM
R2
R1
Vx
R0
DC BUS -
IDC-
Figure 17 Programming the over-current protection
For example, a typical value for resistor R0 could be 50 mΩ. The voltage of the ITRIP pin should not be allowed to
exceed 5 V; if necessary, an external voltage clamp may be used.
5.11
Truth table: Undervoltage lockout, OCP and Enable
Table 8 provides the truth table for the 2ED132xS12. The first line shows that the UVLO for VCC has been tripped;
the RFE output has gone low and the gate drive outputs have been disabled. VCCUV is not latched in this case
and when VCC is greater than VCCUV, the FAULT output returns the driver is functional.
The second case shows that the UVLO for VBS has been tripped and that the high-side gate drive outputs have
been disabled. After VBS exceeds the VBSUV threshold, HO will stay low until the HVIC input receives a new rising
transition of HIN. The third case shows the normal operation of the HVIC. The fourth case illustrates that the OCP
trip threshold has been reached and that the gate drive outputs have been disabled. This condition is stored in
the external RC network waiting for fault clear time. The last case shows when the HVIC has received an external
disable command through the RFE input to shutdown; as a result, the gate drive outputs have been disabled.
Table 8
2ED132xS12 UVLO, OCP, FLT/EN/RCIN
VCC
<
VBS
—
ITRIP
—
RFE
0
LO
0
HO
0
UVLO VCC
UVLO VBS
VCCUV
<
15 V
15 V
15 V
15V
0 V
HIGH
LIN
0
VBSUV
Normal
operation
15 V
15 V
15V
0 V
HIGH
LIN
0
HIN
0
OCP fault
>Vth,OCP
0 V
0
0
Disable
command
0
0
5.12
Daisy Chain Multiple Devices
The 2ED132xS12 can be daisy chained together for applications which require more than one device, such as in
the three phase circuit shown below. In Figure 18, the three 2ED132xS12 RFE pins are connected together. The
ITRIP sensing is only used on the first HVIC; the other two ITRIP pins are disabled by tying them to VSS. The
programmable fault clear timing components, RRFE and CRFE, are populated only once for the RFE pin. When a fault
occurs, either from ITRIP or UVLO, or an external command, all three HVICs are disabled via the daisy chained RFE
pin being pulled low to VSS.
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2ED1322S12M/2ED1321S12M
1200 V half bridge gate driver with integrated bootstrap diode and OCP
DC + BUS
VCC
VCC
VCC
HIN U
LIN U
HIN V
LIN V
HIN W
LIN W
VDD
HIN
LIN
HIN
LIN
uC
HIN
LIN
HO
VS
HO
VS
HO
VS
V
W
To
GK
RRFE
Load
U
RFE
RFE
RFE
LO
LO
LO
CRFE
VSS
VSS
VSS
ITRIP
ITRIP
ITRIP
RSH
DC - BUS
Figure 18 Figure 13: Daisy Chain Circuit with Single Shunt
In Figure 19 three of the individual leg currents of the three phases can be measured. The RFE pins are connected
together with the components for the pin only populated for the first HVIC. Three of the ITRIP pins are used to
monitor the three of the individual leg current. A fault can occur by the ITRIP sensing network for either of the
three legs, shutting down all three 2ED132xS12 HVICs, which means all the three phases have over current
protection indidvidually.
DC + BUS
VCC
VCC
VCC
HIN U
LIN U
HIN V
LIN V
HIN W
LIN W
VDD
HIN
LIN
HIN
LIN
uC
HIN
LIN
HO
VS
HO
VS
HO
VS
V
W
To
GK
RRFE
Load
U
RFE
RFE
RFE
LO
LO
LO
CRFE
VSS
VSS
VSS
ITRIP
ITRIP
ITRIP
RSH
RSH
RSH
DC - BUS
Figure 19 Daisy Chain circuit with Leg Shunt
5.13
Bootstrap diode
An ultra-fast bootstrap diode is monolithically integrated for establishing the high side supply. The dynamic
resistor of the diode helps to avoid extremely high inrush currents when initially charging the bootstrap
capacitor. The integrated diode with its resistrance helps save cost and improve reliability by reducing external
components as shown below Figure 20.
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2ED1322S12M/2ED1321S12M
1200 V half bridge gate driver with integrated bootstrap diode and OCP
Figure 20 2ED132xS12 with integrated components
The low ohmic current limiting resistor provides essential advantages over other competitor devices with high
ohmic bootstrap structures. A low ohmic resistor such as in the 2ED132xS12 allows faster recharging of the
bootstrap capacitor during periods of small duty cycles on the low side transistor. The bootstrap diode is usable
for all kind power electronic converters. The bootstrap diode is a real pn-diode and is temperature robust. It can
be used at high temperatures with a low duty cycle of the low side transistor.
The bootstrap diode of the 2ED132xS12 works with all control algorithms of modern power electronics, such as
trapezoidal or sinusoidal motor drives control.
5.14
Calculating the bootstrap capacitance CBS
Bootstrapping is a common method of pumping charges from a low potential to a higher one. With this technique
a supply voltage for the floating high side sections of the gate drive can be easily established according toFigure
21. This method has the advantage of being simple and low cost but may force some limitations on duty-cycle
and on-time since they are limited by the requirement to refresh the charge in the bootstrap capacitor. Proper
capacitor choice can reduce drastically these limitations.
IBS
VBus
RBS DBS
VB
VCC
CBS
T1
HO
VS
Gate
Drive
IC
D1
CVCC
T2
LO
D2
GND
Figure 21 Half bridge bootstrap circuit in 2ED132xS12
When the low side power device turns on, it will force the potential of pin VS to GND. The existing difference
between the voltage of the bootstrap capacitor VCBS and VCC results in a charging current IBS into the capacitor CBS.
The current IBS is a pulse current and therefore the ESR of the capacitor CBS must be very small in order to avoid
losses in the capacitor that result in lower lifetime of the capacitor. This pin is on high potential again after low
side is turned off and high side is conducting current. But now the bootstrap diode DBS blocks a reverse current,
so that the charges on the capacitor cannot flow back to the capacitor CVCC. The bootstrap diode DBS also takes
over the blocking voltage between pin VB and VCC. The voltage of the bootstrap capacitor can now supply the high
side gate drive sections. It is a general design rule for the location of bootstrap capacitors CBS, that they must be
placed as close as possible to the IC. Otherwise, parasitic resistors and inductances may lead to voltage spikes,
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2ED1322S12M/2ED1321S12M
1200 V half bridge gate driver with integrated bootstrap diode and OCP
which may trigger the undervoltage lockout threshold of the individual high side driver section. However, all
parts of the 2ED132xS12, which have the UVLO also contain a filter at each supply section in order to actively
avoid such undesired UVLO triggers.
The current limiting resistor RBS according to Figure 21 reduces the peak of the pulse current during the low side
power device turn-on. The pulse current will occur at each turn-on of the low side power device, so that with
increasing switching frequency the capacitor CBS is charged more frequently. Therefore a smaller capacitor is
suitable at higher switching frequencies. The bootstrap capacitor is mainly discharged by two effects: The high
side quiescent current and the gate charge of the high side MOSFET to be turned on.
The minimum size of the bootstrap capacitor is given by
푄퐺푇푂푇
퐶퐵푆
=
∆푉퐵푆
VBS is the maximum allowable voltage drop at the bootstrap capacitor within a switching period, typically 1 V.
It is recommended to keep the voltage drop below the undervoltage lockout (UVLO) of the high side and limit
VBS ≤ (VCC – VF– VGSmin– VDSon
)
VGSmin > VBSUV- , VGSmin is the minimum gate source voltage we want to maintain and VBSUV- is the high-side supply
undervoltage negative threshold.
VCC is the IC voltage supply, VF is bootstrapdiode forward voltage and VDSon is drain-source voltage of low side
power device.
Please note, that the value QGTOT may vary to a maximum value based on different factors as explained below and
the capacitor shows voltage dependent derating behavior of its capacitance.
The influencing factors contributing VBS to decrease are:
- Power device turn on required Gate charge (QG)
- Power device gate-source leakage current (ILK_GS
)
- Floating section quiescent current (IQBS
- Floating section leakage current (ILK)
- Bootstrap diode leakage current (ILK_DIODE
- Charge required by the internal level shifters (푄퐿푆): typical 1nC
- Bootstrap capacitor leakage current (ILK_CAP
)
)
)
- High side on time (THON
)
Considering the above,
푄퐺푇푂푇 = 푄퐺 + 푄퐿푆 + (퐼ꢀ퐵푆 + 퐼퐿퐾 + 퐼퐿퐾 + 퐼퐿퐾
+ 퐼퐿퐾 ) ∗ ꢆ퐻푂푁
ꢅ퐴푃
ꢁꢂ
퐷ꢃꢄ퐷퐸
ILK_CAP is only relevant when using an electrolytic capacitor and can be ignored if other types of capacitors are
used. It is strongly recommend using at least one low ESR ceramic capacitor (paralleling electrolytic capacitor
and low ESR ceramic capacitor may result in an efficient solution).
The above CBS equation is valid for pulse by pulse considerations. It is easy to see, that higher capacitance values
are needed, when operating continuously at small duty cycles of low side. The recommended bootstrap
capacitance is therefore in the range up to 4.7 μF for most switching frequencies.
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1200 V half bridge gate driver with integrated bootstrap diode and OCP
5.15
Tolerant to negative transients on input pins
Typically the driver's ground pin is connected close to the source pin of the power device. The microcontroller
which sends the HIN and LIN PWM signals refers to the same ground and in most cases there will be an offset
voltage between the microcontroller ground pin and driver ground because of ground bounce. The 2ED132xS12
can handle negative voltage spikes up to 5 V. Standard half bridge or high-side/low-side drivers only allow
negative voltage levels down to -0.3 V. The 2ED132xS12 has much better noise immunity capability on the input
pins.
Figure 22 Negative voltage tolerance on inputs of upto –5 V
5.16
Negative voltage transient tolerance of VS pin
A common problem in today’s high-power switching converters is the transient response of the switch node’s
voltage as the power switches transition on and off quickly while carrying a large current. A typical 3-phase
inverter circuit is shown in Figure 23, here we define the power switches and diodes of the inverter.
If the high-side switch (e.g., the IGBT Q1 in Figure 24) switches from on to off, while the U phase current is flowing
to an inductive load, a current commutation occurs from high-side switch (Q1) to the diode (D2) in parallel with
the low-side switch of the same inverter leg. At the same instance, the voltage node VS1, swings from the positive
DC bus voltage to the negative DC bus voltage.
DC+ BUS
D3
D1
D5
Q1
Q3
Q5
W
VS3
V
To
Input
Voltage
VS2
U
Load
VS1
D4
D2
D6
Q4
Q2
Q6
DC- BUS
Figure 23 Three phase inverter
Also when the V phase current flows from the inductive load back to the inverter (see Figure 24 C) and D)), and
Q4 IGBT switches on, the current commutation occurs from D3 to Q4. At the same instance, the voltage node, VS2,
swings from the positive DC bus voltage to the negative DC bus voltage.
However, in a real inverter circuit, the VS voltage swing does not stop at the level of the negative DC bus, rather
it swings below the level of the negative DC bus. This undershoot voltage is called “negative VS transient”
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1200 V half bridge gate driver with integrated bootstrap diode and OCP
DC+ BUS
DC+ BUS
DC+ BUS
DC+ BUS
D3
D1
D2
D3
D4
Q1
ON
Q3
OFF
Q1
OFF
Q3
OFF
IU
IV
VS1
VS2
VS1
VS2
IV
IU
D2
Q2
OFF
Q4
ON
Q2
OFF
Q4
OFF
DC- BUS
DC- BUS
DC- BUS
DC- BUS
A)
D)
B)
C)
Figure 24 A) Q1 conducting B) D2 conducting
C) D3 conducting
D) Q4 conducting
The circuit shown in Figure 25-A depicts one leg of the three phase inverter; Figure 25-B and Figure 25-C show a
simplified illustration of the commutation of the current between Q1 and D2. The parasitic inductances in the
power circuit from the die bonding to the PCB tracks are lumped together in LC and LE for each IGBT. When the
high-side switch is on, VS1 is below the DC+ voltage by the voltage drops associated with the power switch and
the parasitic elements of the circuit. When the high-side power switch turns off, the load current momentarily
flows in the low-side freewheeling diode due to the inductive load connected to VS1 (the load is not shown in
these figures). This current flows from the DC- bus (which is connected to the COM pin of the HVIC) to the load
and a negative voltage between VS1 and the DC- Bus is induced (i.e., the COM pin of the HVIC is at a higher potential
than the VS pin).
DC+ BUS
LC1
DC+ BUS
DC+ BUS
+
VLC1
-
D1
D1
Q1
Q2
Q1
OFF
Q1
ON
+
LE1
LC2
IU
VLE1
-
VS1
VS1
VS1
-
IU
VLC2
+
D2
D2
-
Q2
OFF
Q2
OFF
VD2
+
-
LE2
DC- BUS
VLE2
+
DC- BUS
A
DC- BUS
C
B
Figure 25 Figure A shows the Parasitic Elements. Figure B shows the generation of VS positive.
Figure C shows the generation of VS negative
5.17
NTSOA – Negative Transient Safe Operating Area
In a typical motor drive system, dV/dt is typically designed to be in the range of 3 – 5 V / ns. The negative VS
transient voltage can exceed this range during some events such as short circuit and over-current shutdown,
when di/dt is greater than in normal operation.
Infineon’s HVICs have been designed for the robustness required in many of today’s demanding applications. An
indication of the 2ED132xS12’s robustness can be seen in Figure 26, where the 2ED132xS12’s Safe Operating Area
is shown at VBS=15 V based on repetitive negative VS spikes. A negative VS transient voltage falling in the grey
area (outside SOA) may lead to IC permanent damage; viceversa unwanted functional anomalies or permanent
damage to the IC do not appear if negative Vs transients fall inside the SOA.
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1200 V half bridge gate driver with integrated bootstrap diode and OCP
Figure 26 Negative VS transient SOA for 2ED132xS12
Even though the 2ED132xS12 has been shown able to handle these large negative VS transient conditions, it is
highly recommended that the circuit designer always limit the negative VS transients as much as possible by
careful PCB layout and component use.
5.18
PCB layout tips
Distance between high and low voltage components: It’s strongly recommended to place the components tied
to the floating voltage pins (VB and VS) near the respective high voltage portions of the device. Please see the
Case Outline information in this datasheet for the details.
Ground Plane: In order to minimize noise coupling, the ground plane should not be placed under or near the high
voltage floating side.
Gate Drive Loops: Current loops behave like antennas and are able to receive and transmit EM noise (see Figure
27). In order to reduce the EM coupling and improve the power switch turn on/off performance, the gate drive
loops must be reduced as much as possible. Moreover, current can be injected inside the gate drive loop via the
IGBT collector-to-gate parasitic capacitance. The parasitic auto-inductance of the gate loop contributes to
developing a voltage across the gate-emitter, thus increasing the possibility of a self turn-on effect.
Figure 27 Avoid antenna loops
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1200 V half bridge gate driver with integrated bootstrap diode and OCP
Supply Capacitor: It is recommended to place a bypass capacitor (CIN) between the VCC and COM pins. A ceramic
1μF ceramic capacitor is suitable for most applications. This component should be placed as close as possible
to the pins in order to reduce parasitic elements.
Routing and Placement: Power stage PCB parasitic elements can contribute to large negative voltage transients
at the switch node; it is recommended to limit the phase voltage negative transients. In order to avoid such
conditions, it is recommended to 1) minimize the high-side emitter to low-side collector distance, and 2)
minimize the low-side emitter to negative bus rail stray inductance. However, where negative VS spikes remain
excessive, further steps may be taken to reduce the spike. This includes placing a resistor (5 Ω or less) between
the VS pin and the switch node (see Figure 28 - A), and in some cases using a clamping diode between COM and
VS (see Figure 28 - B). See DT04-4 at www.infineon.com for more detailed explanations.
Figure 28 Resistor between the VS pin and the switch node and clamping diode between
COM and VS
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1200 V half bridge gate driver with integrated bootstrap diode and OCP
6
Qualification information1
Table 9
Qualification information
Industrial2
Note: This family of ICs has passed JEDEC’s Industrial
qualification. Consumer qualification level is granted by
extension of the higher Industrial level.
Qualification level
MSL2a3, 260°C
Moisture sensitivity level
ESD
DSO-16-44
(per IPC/JEDEC J-STD-020)
Class C3 (1.0 kV)
(per JESD22-C101)
Class 2 (2 kV)
Charged device model
Human body model
(per JEDEC standard JESD22-A115)
Class II Level A
(per JESD85)
Yes
IC latch-up test
RoHS compliant
1 Qualification standards can be found at Infineon’s web site www.infineon.com
2 Higher qualification ratings may be available should the user have such requirements. Please contact your Infineon sales
representative for further information.
3 Higher MSL ratings may be available for the specific package types listed here. Please contact your Infineon sales representative for
further information.
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1200 V half bridge gate driver with integrated bootstrap diode and OCP
7
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Table 10
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The CoolSiC™ 1200 V, 350 mΩ ~ 14 mΩ SiC MOSFET in TO247-3 or TO247-4 package
build on a state-of-the-art trench semiconductor process optimized to combine
performance with reliability. In comparison to traditional silicon (Si) based switches like
IGBTs and MOSFETs, the SiC MOSFET offers a series of advantages. These include, the
lowest gate charge and device capacitance levels seen in 1200 V switches, no reverse
recovery losses of the internal commutation proof body diode, temperature
independent low switching losses, and threshold-free on-state characteristic.
IMW/Z120R350M1H
IMW/Z120R220M1H
IMW/Z120R140M1H
IMW/Z120R090M1H
IMW/Z120R060M1H
IMW/ZA120R040M1H
IMW/Z120R030M1H
IMW/ZA120R020M1H
IMW/ZA120R014M1H
iMOTION™ Controllers
IRMCK099
iMOTION™ Motor control IC for variable speed drives utilizing sensor-less Field Oriented
Control (FOC) for Permanent Magnet Synchronous Motors (PMSM).
IMC101T
High performance Motor Control IC for variable speed drives based on field oriented control
(FOC) of permanent magnet synchronous motors (PMSM).
Datasheet
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2ED1322S12M/2ED1321S12M
1200 V half bridge gate driver with integrated bootstrap diode and OCP
8
Package details
Figure 29 300mil 16 leads PG-DSO-16-U02
Datasheet
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1200 V half bridge gate driver with integrated bootstrap diode and OCP
9
Part marking information
Front side
Rear side
Figure 30 Marking information PG-DSO-16-U02
Datasheet
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1200 V half bridge gate driver with integrated bootstrap diode and OCP
10
Additional documentation and resources
Several technical documents related to the use of HVICs are available at www.infineon.com; use the Site Search
function and the document number to quickly locate them. Below is a short list of some of these documents.
Application Notes:
Understanding HVIC Datasheet Specifications
HV Floating MOS-Gate Driver ICs
Use Gate Charge to Design the Gate Drive Circuit for SiC MOSFETs and IGBTs
Bootstrap Network Analysis: Focusing on the Integrated Bootstrap Functionality
Design Tips:
Using Monolithic High Voltage Gate Drivers
Alleviating High Side Latch on Problem at Power Up
Keeping the Bootstrap Capacitor Charged in Buck Converters
Managing Transients in Control IC Driven Power Stages
Simple High Side Drive Provides Fast Switching and Continuous On-Time
10.1
Infineon online forum resources
The Gate Driver Forum is live at Infineon Forums (www.infineonforums.com). This online forum is where the
Infineon gate driver IC community comes to the assistance of our customers to provide technical guidance – how
to use gate drivers ICs, existing and new gate driver information, application information, availability of demo
boards, online training materials for over 500 gate driver ICs. The Gate Driver Forum also serves as a repository
of FAQs where the user can review solutions to common or specific issues faced in similar applications.
Register online at the Gate Driver Forum and learn the nuances of efficiently driving a power switch in any given
power electronic application.
Datasheet
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Revision history
Document
version
1.0
Date of release
Description of changes
March 07, 2023
March 16, 2023
Final Datasheet
Updated the photo of package
1.1
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