1EDB7275F [INFINEON]
采用DSO-8 150mil封装的单通道隔离栅极驱动器集成电路;
| 型号： | 1EDB7275F |
| 厂家： | 
Infineon |
| 描述： | 采用DSO-8 150mil封装的单通道隔离栅极驱动器集成电路 栅极驱动 驱动器 |
| 文件： | 总33页 (文件大小：975K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EiceDRIVER™ 1EDBx275F
Single-channel isolated gate driver ICs in 150 mil DSO package
Description
EiceDRIVER™ 1EDBx275F is a family of single-channel isolated gate driver ICs, designed to drive Si, SiC and GaN
power switches.
1EDBx275F is available in an 8-pin DSO package with 4 mm input-to-output creepage distance; it provides
isolation by means of on-chip coreless transformer (CT) technology.
With tight timing specifications, 1EDBx275F is designed for fast-switching medium-to-high power systems.
Excellent common-mode rejection, low part-to-part skew, fast signal propagation and small package size make
1EDBx275F a superior alternative to high-side driving solutions using optocouplers or pulse transformers.
Features
•
•
•
•
•
•
•
•
•
Single-channel isolated gate driver
45 ns input-to-output propagation delay with excellent accuracy (+6/-4 ns)
Separate low impedance source and sink outputs
Fast clamping of parasitics-induced output overshoots under UVLO conditions
Fast start-up times and fast recovery after supply glitches
Optimized UVLO levels (4 V, 8 V, 12 V, 15 V) for Si, SiC and GaN transistors
High common-mode transient immunity (CMTI > 300 V/ns)
Available in 8-pin 150mil DSO package
Fully qualified according JEDEC for industrial applications
Isolation and safety certificates
UL 1577 with VISO = 3000 VRMS
•
Table 1
Part number
1EDB7275F
EiceDRIVER™ 1EDBx275F Portfolio
Peak source / sink current
UVLO ON / OFF
4.2 V / 3.9 V
Isolation certification Package
1EDB8275F
1EDB6275F
1EDB9275F
8.0 V / 7.0 V
UL 1577
(VISO = 3000 VRMS
5 A / 9 A
PG-DSO-8
)
12.2 V / 11.5 V
14.9 V / 14.4 V
EiceDRIVER™ 1EDBx275F
Controller
VDDI
VDDO
High-side
MOSFET
VDD
VDDI
IN+
VDDO
Rgon
PWM
OUT_SRC
OUT_SNK
CVDDI
CVDDO
Rgoff
IN-
GNDI
GNDO
GND
Input-to-output
isolation
Figure 1
Typical application
Final Data Sheet
www.infineon.com
Please read the Important Notice and Warnings at the end of this document
Rev. 2.2
2021-11-08
EiceDRIVER™ 1EDBx275F
Single-channel isolated gate driver ICs in 150 mil DSO package
Potential Applications
•
•
•
•
•
Server and Telecom switch-mode power supplies (SMPS)
EV Off-board chargers
Low-voltage drives and power tools
Solar micro inverter, solar optimizer
Industrial power supplies (SMPS, Residential UPS)
Final Data Sheet
2
Rev.2.2
2021-11-08
EiceDRIVER™ 1EDBx275F
Single-channel isolated gate driver ICs in 150 mil DSO package
Table of Contents
1
Pin configuration and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
2.1
2.2
2.2.1
2.2.2
2.2.3
2.3
2.4
2.5
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Power supply and Undervoltage Lockout (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Input supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Output supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Driver output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Output active clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
CT communication and input to output data transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
Electrical characteristics and parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Isolation specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1
3.2
3.3
3.4
3.5
4
5
Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Layout recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6
6.1
6.2
Application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Driving 600 V CoolGaNTM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Driving 650 V CoolSiCTM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7
Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8
8.1
8.2
Package outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Device numbers and markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Package PG-DSO-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Final Data Sheet
3
Rev. 2.2
2021-11-08
EiceDRIVER™ 1EDBx275F
Single-channel isolated gate driver ICs in 150 mil DSO package
Pin configuration and description
1
Pin configuration and description
VDDI
IN+
1
2
3
4
8
7
6
5
GNDO
OUT_SNK
OUT_SRC
VDDO
1EDBx275F
IN-
GNDI
Figure 2
Table 2
Pin configuration (top side view)
Pin description
Pin Symbol
Description
1
2
3
4
5
6
7
8
VDDI
IN+
Input-side supply voltage (3 V to 15 V)
Non-inverting driver input (active high); if IN+ is low or left open, OUT_SNK is low
Inverting driver input (active low); if IN- is high or left open, OUT_SNK is low
Input-side ground reference
IN-
GNDI
VDDO
Output-side supply voltage (up to 20 V)
OUT_SRC Driver output source, low-impedance switch to VDDO
OUT_SNK Driver output sink, low-impedance switch to GNDO
GNDO
Output-side ground reference
For package drawing details see Chapter 8 Package outline dimensions.
Final Data Sheet
4
Rev.2.2
2021-11-08
EiceDRIVER™ 1EDBx275F
Single-channel isolated gate driver ICs in 150 mil DSO package
Functional description
2
Functional description
2.1
Block diagram
A simplified functional block diagram for the EiceDRIVER™ 1EDBx275F is given in Figure 3.
UVLO
VDDO
5
UVLO
1
2
IN+
6
7
OUT_SRC
OUT_SNK
GNDI
TX
RX
Logic
Logic
VDDI
VDDO
3
IN-
Active
Clamp
GNDI
4
8
GNDO
GNDI
Figure 3
Block diagram
2.2
Power supply and Undervoltage Lockout (UVLO)
Due to the isolation between input and output side, two power domains with independent power management
are required. Undervoltage Lockout (UVLO) functions for both input and output supplies ensure a defined startup
and robust functionality under all operating conditions.
2.2.1
Input supply voltage
The input die is powered via VDDI and supports a wide supply voltage range from 3 V to 15 V. A ceramic bypass
capacitor must be placed between VDDI and GNDI in close proximity to the device; a minimum capacitance of
100 nF is recommended.
Power consumption to some extent depends on switching frequency, as the input signal is converted into a train
of repetitive current pulses to drive the coreless transformer. Due to the chosen robust encoding scheme the
average repetition rate of these pulses and thus the average supply current depends on the
switching frequency, fsw. However, for fsw < 500 kHz this effect is very small.
The Undervoltage Lockout function for the input supply VDDI ensures that, as long as VDDI is below UVLO (e.g. in
startup), no data is transferred to the output side and the gate driver output is held low (Safety Lock-down at
startup). When VDDI exceeds the UVLO level, the PWM input signal is transferred to the output side. If the output
side is ready (not in UVLO condition), the output reacts according to the logic input.
Final Data Sheet
5
Rev.2.2
2021-11-08
EiceDRIVER™ 1EDBx275F
Single-channel isolated gate driver ICs in 150 mil DSO package
Functional description
2.2.2
Output supply voltage
The output die is powered via VDDO (up to 20 V). A ceramic bypass capacitor must be placed between VDDO and
GNDO in close proximity to the device. A minimum capacitance of 20 x Ciss (MOSFET input capacitance) is
recommended to ensure an acceptable ripple (5% of VDDO) on the supply pin.
The minimum supply voltage is set by the Undervoltage Lockout (UVLO) function. The gate driver output can be
switched only, if the output supply voltage (VDDO) exceeds the output-side UVLO. Thus it can be guaranteed that
the switch transistor is not operated, if the driving voltage is too low to achieve a complete and fast transition to
the "on" state. Low driving voltage in fact could cause the power MOSFET to enter its saturation (ohmic) region
with potentially destructive power dissipation; the output UVLO ensures that the switch transistor always stays
within its Safe Operating Area (SOA). Versions with 4 V, 8 V, 12 V, 15 V UVLO thresholds for the output supply are
currently available; Table 3 shows the recommended UVLO levels for different Infineon power switch families.
Table 3
Recommended 1EDBx275F UVLO levels for typical use-cases
Switch family
Switch part number example
Recommended 1EDBx275F
Logic level OptiMOSTM
Normal level OptiMOSTM
CoolMOSTM
BSC010N04LS6, BSZ070N08LS5, ..
1EDB7275F (4 V UVLO)
BSC040N10NS5, BSZ084N08NS5, .. 1EDB8275F (8 V UVLO)
IPP60R099C7, IPB60R600P6, ..
1EDB8275F (8 V UVLO)
1EDB6275F (12 V UVLO for 15V VGS driving)
1EDB9275F (15 V UVLO for 18V VGS driving)
1EDB7275F (4V UVLO)
650 V CoolSiCTM
600 V CoolGaNTM
IMZA65R027M1H, IMW65R107M1H, ..
IGOT60R070D1, IGLD60R070D1, ..
2.2.3
Input stage
The logic driver output state is equal to the non-inverted or inverted input signal state at pins IN+ or IN-,
respectively. The non-inverting input IN+ is internally pulled down to a logic low voltage and the inverting input
is internally pulled up to a logic high voltage. This prevents any switching-on during power-up or in other
situations with insufficient supply voltage.
The input is compatible with LV-TTL levels and provide a hysteresis of typically 0.9 V. This hysteresis is
independent of the supply voltage VDDI
.
Table 4 shows the IN+, IN- driver logic in case of sufficiently high supply voltage. Otherwise the outputs of the
driver are determined by the Undervoltage Lockout (UVLO) and Output Active Clamping functionalities as shown
in Table 5.
Table 4
Logic table in case of sufficient bias power
Inputs Supplies Outputs
DDI, VDDO
Note
IN+
H
IN-
L
V
OUT
H
L
–
x
H
>UVLOVDDx,on (active)
The output is disabled via IN- (active low)
The output is disabled via IN+ (active high)
L
x
L
2.3
Driver output
The rail-to-rail output stage realized with complementary MOS transistors is able to provide a typical 5.4 A
sourcing and 9.8 A sinking peak current for a 15 V supply. The low on-resistance coming together with high driving
current is particularly beneficial for fast switching of very large MOSFETs. With a Ron of 0.95 Ω for the sourcing
pMOS and 0.48 Ω for the sinking nMOS transistor the driver can in most applications be considered as a nearly
Final Data Sheet
6
Rev.2.2
2021-11-08
EiceDRIVER™ 1EDBx275F
Single-channel isolated gate driver ICs in 150 mil DSO package
Functional description
ideal switch. The p-channel sourcing transistor enables real rail-to-rail behavior without suffering from the
voltage drop unavoidably associated with nMOS source follower stages.
In case of floating inputs or insufficient supply voltage not exceeding the UVLO thresholds, the driver output is
actively clamped to the "low" level (GNDO).
2.4
Output active clamping
The Undervoltage Lockout (UVLO) ensures no driver operation for supplies below the UVLO thresholds. However,
this is not sufficient to guarantee that the output of the driver is kept low. Transient-induced current on the
MOSFETs side may pull-up the output node of the driver and the gate voltage causing an unwanted turn-on of the
switch; this is particularly critical in systems using bootstrapping since, during start-up, the supply of the high-
side channel is delayed, while the low-side MOSFETs is already switching. In resonant topologies (as LLC), the
half-bridge switching node may be pulled up after the turn-off of the low-side switch. When this is turned on
again, the dv/dt induced increase of the high-side gate voltage cannot be clamped by the drivers RDSON,sink if the
the boostrap supply is not yet available.
With a fast active clamping circuit in the output stage, EiceDRIVER™ 1EDBx275F ensures safe operation in all
UVLO situations. This structure allows fast reaction and effective clamping of the output pins (OUT). The exact
reaction time depends on the output supply (VDDO) and on the output voltage levels; however, already for very low
supply levels (~1 V), the active clamping is able to react in some tens of ns.
Undervoltage Lockout together with the Output Active Clamping ensure that the output is actively held low in
case of unsufficient output-side supply voltage.
Table 5
Logic table in case of insufficient supply voltages
Inputs Supplies
Output
OUT
L
INx
VDDI
VDDO
1.2 V < VDDO< UVLOVDDO,on
x
> UVLOVDDI,on
2.5
CT communication and input to output data transmission
A coreless transformer (CT) based communication module is used for PWM signal transfer between input and
output. A proven high-resolution pulse repetition scheme in the transmitter combined with a watchdog timeout
at the receiver side enables recovery from communication fails and ensures safe system shutdown in failure
cases.
Final Data Sheet
7
Rev.2.2
2021-11-08
EiceDRIVER™ 1EDBx275F
Single-channel isolated gate driver ICs in 150 mil DSO package
Electrical characteristics and parameters
3
Electrical characteristics and parameters
The absolute maximum ratings are listed in Table 6. Stresses beyond these values may cause permanent damage
to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
3.1
Absolute maximum ratings
Table 6
Absolute maximum ratings
Symbol
Parameter
Values
Unit Note or Test Condition
Min.
-0.3
Typ.
Max.
17
Input supply voltage
Output supply voltage
Voltage at pins IN+, IN-
VDDI
VDDO
VIN
–
–
–
–
–
–
V
V
V
V
V
V
–
-0.3
22
–
-0.3
17
–
-5
–
transient for 50 ns
OUT = low, DC
Voltage at pin OUT_SRC
Voltage at pin OUT_SNK
VOUT_SRC
VDDO-24
VDDO+0.3
VDDO+2
V
DDO-24
OUT = low,
transient for 200 ns
VOUT_SNK
-0.3
-2
–
–
24
24
V
V
OUT = high, DC
OUT = high,
transient for 200 ns
Reverse current peak at pin
OUT_SRC
ISRC_rev
ISNK_rev
-5
–
–
–
–
5
Apk transient for 500 ns
Apk transient for 500 ns
Reverse current peak at pin
OUT_SNK
Junction temperature
Storage temperature
Soldering temperature
ESD capability
TJ
TSTG
-40
-55
–
–
–
–
–
150
150
260
0.5
°C
°C
–
–
TSOL
°C reflow / wave soldering 1)
VESD_CDM
–
kV Charged Device Model
(CDM) 2)
VESD_HBM
–
–
2
kV Human Body Model
(HBM) 3)
1) according to JESD22A111
2) according to ESD-CDM: ANSI/ESDA/JEDEC JS-002
3) according to ESD-HBM: ANSI/ ESDA/JEDEC JS-001 (discharging 100 pF capacitor through 1.5 kΩ resistor)
Final Data Sheet
8
Rev.2.2
2021-11-08
EiceDRIVER™ 1EDBx275F
Single-channel isolated gate driver ICs in 150 mil DSO package
Electrical characteristics and parameters
3.2
Thermal characteristics
Table 7
Thermal characteristics at TA= 25°C
Parameter
Symbol
Min.
Values
Typ.
116
Unit Note or Test Condition
Max.
Thermal resistance junction-
ambient 1)
RthJA25
RthJC25
RthJB25
ΨthJT25
ΨthJB25
–
–
–
–
–
–
K/W 200mW output power
Thermal resistance junction-
case (top) 2)
54
45
9
–
–
–
–
K/W
K/W
K/W
K/W
Thermal resistance junction-
board 3)
Characterization parameter
junction-top 4)
Characterization parameter
36
junction-board 4)
1) obtained by simulating a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in
JESD51-2a
2) obtained by simulating a cold plate test on the package top. No specific JEDEC standard test exists, but a close
description can be found in the ANSI SEMI standard G30-88
3) obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in
JESD51-8
4) estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining
Rth, using a procedure described in JESD51-2a (sections 6 and 7)
3.3
Operating range
Table 8
Operating range
Parameter
Symbol
Values
Unit Note or Test Condition
Min.
3.0
Typ.
Max.
15
Input supply voltage
Output supply voltage
VDDI
–
–
–
–
–
–
V
V
V
V
V
V
Min. defined by UVLO
for 1EDB7275F
for 1EDB8275F
for 1EDB6275F
for 1EDB9275F
–
VDDO
4.5
20
8.5
20
12.8
15.5
-0.3
20
20
Logic input voltage at pins IN+,
IN-
VIN
15
1)
Junction temperature
Ambient temperature
TJ
TA
-40
-40
–
–
150
125
°C
°C
–
1) continuous operation above 125°C may reduce lifetime
Final Data Sheet
9
Rev.2.2
2021-11-08
EiceDRIVER™ 1EDBx275F
Single-channel isolated gate driver ICs in 150 mil DSO package
Electrical characteristics and parameters
3.4
Electrical characteristics
Unless otherwise noted the electrical characteristics are given for VDDI = 3.3 V, VDDO = 12 V (VDDO = 18 V for
1EDB6275F, 1EDB9275F) and no load.
Typical values are given at TJ = 25°C. Min. and max. values are the lower and upper limits valid within the full
operating temperature range.
Table 9
Power supply
Values
Typ.
Parameter
Symbol
Unit
Note or Test Condition
Min.
Max.
I
VDDI quiescent current
IVDDIq
–
0.85
1
mA
mA
no switching
OUT = low, no switching,
VDDO = 12 V
–
–
-
0.65
0.72
0.84
0.85
1.0
OUT = low, no switching,
VDDO = 18 V
IVDDO quiescent current
IVDDOq
mA
mA
OUT = high, no switching,
VDDO = 12 V
1.0
Table 10 Undervoltage Lockout VDDI
Values
Note or
Test Condition
Parameter
Symbol
UVLOVDDI,on
UVLOVDDI,off
Unit
Min.
Typ.
Max.
Undervoltage Lockout (UVLO)
turn-on threshold VDDI
2.7
2.85
3.0
V
–
Undervoltage Lockout (UVLO)
turn-off threshold VDDI
–
2.65
0.2
–
V
V
–
–
UVLO threshold hysteresis VDDI UVLOVDDI, hys
0.15
0.25
Table 11 Undervoltage Lockout VDDO for 1EDB7275F (4 V UVLO option)
Values
Note or
Test Condition
Parameter
Symbol
Unit
Min.
Typ.
Max.
Undervoltage Lockout (UVLO)
turn on threshold VDDO
UVLOVDDO, on
UVLOVDDO, off
UVLOVDDO, hys
4.0
4.2
4.4
V
V
V
–
–
–
Undervoltage Lockout (UVLO)
turn off threshold VDDO
–
3.9
0.3
–
UVLO threshold hysteresis
VDDO
0.2
0.4
Final Data Sheet
10
Rev.2.2
2021-11-08
EiceDRIVER™ 1EDBx275F
Single-channel isolated gate driver ICs in 150 mil DSO package
Electrical characteristics and parameters
Table 12 Undervoltage Lockout VDDO for 1EDB8275F (8 V UVLO option)
Values
Note or
Test Condition
Parameter
Symbol
Unit
Min.
Typ.
Max.
Undervoltage Lockout (UVLO)
turn on threshold VDDO
UVLOVDDO, on
UVLOVDDO, off
UVLOVDDO, hys
7.6
8.0
8.4
V
V
V
–
–
–
Undervoltage Lockout (UVLO)
turn off threshold VDDO
–
7.0
1
–
UVLO threshold hysteresis
VDDO
0.7
1.3
Table 13 Undervoltage Lockout VDDO for 1EDB6275F (12 V UVLO option)
Values
Note or
Test Condition
Parameter
Symbol
Unit
Min.
Typ.
Max.
Undervoltage Lockout (UVLO)
turn on threshold VDDO
UVLOVDDO, on
UVLOVDDO, off
UVLOVDDO, hys
11.7
12.2
12.7
V
V
V
–
–
–
Undervoltage Lockout (UVLO)
turn off threshold VDDO
–
11.5
0.7
–
UVLO threshold hysteresis
VDDO
0.5
0.9
Table 14 Undervoltage Lockout VDDO for 1EDB9275F (15 V UVLO option)
Values
Note or
Test Condition
Parameter
Symbol
Unit
Min.
Typ.
Max.
Undervoltage Lockout (UVLO)
turn on threshold VDDO
UVLOVDDO, on
UVLOVDDO, off
UVLOVDDO, hys
14.4
14.9
15.4
V
V
V
–
–
–
Undervoltage Lockout (UVLO)
turn off threshold VDDO
–
14.4
0.5
–
UVLO threshold hysteresis
VDDO
0.3
0.7
Table 15 Logic inputs IN+, IN-
Parameter
Values
Typ.
Note or
Test Condition
Symbol
Unit
Min.
Max.
Input voltage threshold for
transition LH
VINH
VINL
VIN_hys
IIN+,H
1.9
1
2.2
1.3
0.9
40
2.5
V
V
–
Input voltage threshold for
transition HL
1.6
–
–
Input voltage threshold
hysteresis
–
V
–
High-level input leakage
current at pin IN+
–
70
µA
IN+ tied to VDDI
Final Data Sheet
11
Rev.2.2
2021-11-08
EiceDRIVER™ 1EDBx275F
Single-channel isolated gate driver ICs in 150 mil DSO package
Electrical characteristics and parameters
Table 15 Logic inputs IN+, IN- (cont’d)
Values
Note or
Test Condition
Parameter
Symbol
Unit
Min.
Typ.
Max.
Low-level input leakage
current at pin IN-
IIN-,L
-55
-40
–
µA
IN- tied to GNDI
Input pull-down resistor
Input pull-up resistor
RIN,PD
RIN,PU
–
–
75
75
–
–
kΩ
kΩ
–
–
Table 16 Static output characteristics
Values
Typ.
Note or
Test Condition
Parameter
Symbol
Unit
Min.
Max.
High-level (sourcing) output
resistance
Ron_SRC
0.52
0.95
1.70
Ω
ISNK = 50 mA
V
DDO = 12 V, VOUT = 0 V;
–
–
5
–
–
A
A
see Figure 25,
Figure 26
Peak sourcing output current 1)
ISRC_pk
VDDO = 18 V, VOUT = 0 V;
see Figure 25,
Figure 26
6
Low-level (sinking) output
resistance
Ron_SNK
0.31
0.48
-9
0.88
Ω
A
A
ISRC = 50 mA
VOUT = VDDO = 12 V; see
Figure 25, Figure 26
–
–
Peak sinking output current 1)
ISNK_pk
VOUT = VDDO = 18 V; see
Figure 25, Figure 26
–
-10
–
1) parameter not subject to production test - verified by design / characterization
Table 17 Dynamic characteristics
Values
Note or
Test Condition
Parameter
Symbol
Unit
Min.
Typ.
Max.
IN+ /IN- to output propagation
delay
tPDon, tPDoff
41
45
51
ns see Figure 4
1)
∆tPDon,p-p
∆tPDoff,p-p
–
–
–
–
2
2
ns
Part-to-part skew
1)
ns
Pulse width distortion
tPWD
–
–
–
–
2
ns see Figure 5
2)
|tPDoff - tPDon
|
VDDO = 12 V, CLOAD
=
6.5
8.3
12
16
ns
ns
1.8 nF, see Figure 6
Rise time 3)
trise
VDDO = 18 V, CLOAD
=
1.8 nF, see Figure 6
Final Data Sheet
12
Rev.2.2
2021-11-08
EiceDRIVER™ 1EDBx275F
Single-channel isolated gate driver ICs in 150 mil DSO package
Electrical characteristics and parameters
Table 17 Dynamic characteristics (cont’d)
Values
Note or
Test Condition
Parameter
Symbol
Unit
Min.
Typ.
Max.
VDDO = 12 V, CLOAD
=
–
4.5
8
ns
ns
1.8 nF, see Figure 6
VDDO = 18 V, CLOAD
1.8 nF, see Figure 6
Fall time 3)
tfall
=
–
5
9
Minimum input pulse width
that changes output state
Input-side start-up time 3)
Input-side deactivation time 3)
Output-side start-up time 3)
tPW
15
19
23
ns see Figure 7
µs see Figure 8
tSTART,VDDI
tSTOP,VDDI
tSTART,VDDO
–
–
–
3
300
5
–
–
–
ns see Figure 8
µs see Figure 9
Output-side deactivation time
tSTOP,VDDO
–
125
–
ns see Figure 9
3)
Activation time of output
tCLAMP,OUT
–
20
–
ns see Figure 10
clamping in UVLO condition 3)
1) The parameter gives the difference in propagation delay between different samples switching in the same direction
under same conditions, including same ambient temperature
2) The parameter gives the maximum difference between on and off propagation delay shown from the same sample over
the operating temperature range
3) parameter not subject to production test - verified by design / characterization
Table 18 Common Mode Transient Immunity (CMTI)
Values
Parameter
Symbol
Unit Note or Test Condition
Min.
Typ.
Max.
V
CM = 1500 V; IN- tied to GNDI,
IN+ tied to VDDI (logic high inputs)
CM = 1500 V; IN- tied to GNDI, IN+
tied to GNDI (logic low inputs)
CM = 1500 V; IN- tied to GNDI,
dynamic IN+ (10 MHz square wave)
|CMStatic,H
|
300
–
–
V/ns
V/ns
V/ns
Static Common Mode
Transient Immunity 1) 2)
V
|CMStatic,L
|
300
–
–
Dynamic Common Mode
Transient Immunity 1) 3)
V
|CMDynamic
|
300
–
–
1) minimum slew rate of a common mode voltage that is able to cause a wrong output signal
2) verified by characterization according to VDE0884-11 standard definitions and test-methods
3) verified by characterization with ground reference for the common mode pulse generator connected to the coupler
input-side ground to reflect real applications requirements
Final Data Sheet
13
Rev.2.2
2021-11-08
EiceDRIVER™ 1EDBx275F
Single-channel isolated gate driver ICs in 150 mil DSO package
Electrical characteristics and parameters
3.5
Isolation specifications
This coupler is suitable for rated insulation only within the given safety limiting values. Compliance with the
safety limiting values shall be ensured by means of suitable protective circuits.
Table 19 Input-to-output isolation specifications
Parameter
Symbol Value Unit Note or Test Condition
Nominal input-to-output
clearance 1)
Shortest distance in air between any
input pin and any output pin
CLR
CRP
CTI
4.0
mm
Shortest distance over package surface
mm between any input pin and any output
pin
Nominal input-to-output
creepage 1)
4.0
> 400
< 600
According to DIN EN 60112 (VDE 0303-
11)
Comparative tracking index
V
Material group
–
–
–
–
II
–
–
–
–
According to IEC 60112
Pollution degree
2
According to IEC 60664-1
Overvoltage category per
IEC 60664-1
I -IV
I -III
Rated mains voltage ≤ 150 VRMS
Rated mains voltage ≤ 300 VRMS
–
–
I -II
–
–
Rated mains voltage ≤ 600 VRMS
Climatic category
40/125
/21
–
VTEST = VISO for t = 60 s (qualification);
Input-to-output isolation
voltage
UL1577 2)
VISO
VIOTM
qPD
3000
4242
< 5
VRMS
V
TEST = 1.2 x VISO for t = 1 s (100%
productive tests)
Maximum rated transient
isolation voltage
Vpk VTEST = 1.2 x VIOTM for tini = 1 s
Method b1
pC VPD(ini) = 1.2 x VIOTM for tini = 1 s
VPD(m) = 2065 V for tm = 1 s
Apparent charge
VDE0884-11 3)
Maximum surge isolation
voltage 4)
VIOSM
RIO
6000
Vpk VIOSM_TEST = 1.3 x VIOSM
Isolation resistance input-
to-output 5) 6)
1012
1011
Ω
Ω
VIO = 500 Vdc for t = 60 s, TA = 25 °C
VIO = 500 Vdc for t = 60 s, TA = 125 °C
VIO = 500 Vdc for t = 60 s, TA = TS = 150 °C
109
Ω
Capacitance input-to-
output 5)
CIO
1
pF f = 1 MHz
1) Creepage and clearance requirements depend on the application and related end-equipment isolation standard. Care
should be taken to keep the required creepage and clearance value on printed-circuit-board level
2) see certificate number E509502
3) parameters are tested according to VDE0884-11 specifications but no safety certification is planned
4) the surge test is performed in insulation oil to determine the intrinsic surge immunity of the insulation barrier
5) The parameters apply to the product converted in a two terminals device with all terminals on side 1 connected together
and all terminals on side 2 connected together
6) parameter verified by characterization on a limited amount of samples previously stressed with a dielectric strength test
(VISO
)
Final Data Sheet
14
Rev.2.2
2021-11-08
EiceDRIVER™ 1EDBx275F
Single-channel isolated gate driver ICs in 150 mil DSO package
Electrical characteristics and parameters
Table 20 Safety limiting values
Parameter
Symbol Value Unit Note or Test Condition
Maximum input power dissipation
Maximum output power dissipation
PS_I
40
mW
mW
TA = 25 C, TJ = 150 °C
PS_O
1380
Maximum ambient safety
temperature
Ts
150
°C TS = TJ,max
Final Data Sheet
15
Rev.2.2
2021-11-08
EiceDRIVER™ 1EDBx275F
Single-channel isolated gate driver ICs in 150 mil DSO package
Timing diagrams
4
Timing diagrams
Figure 4 illustrates the input-to-output propagation delays as observed at the capacitively loaded output.
VINH
IN- (low)
IN-
VINL
VINH
IN+
IN+ (high)
VINL
90%
90%
OUT
OUT
10%
10%
tPDon
tPDoff
tPDoff
tPDon
Figure 4
Input-to-output propagation delays (inverting and non-inverting case)
Figure 5 illustrates the pulse width distortion. It depicts the duty cycle distortion of the signal observed at the
driver output due to the mismatch between on and off propagation delay.
IN+
tPWD
OUT
tPDon
tPDoff
Figure 5
Pulse width distortion (unloaded output)
Figure 6 illustrates the rise and fall time as observed at the capacitively loaded output.
90%
10%
90%
10%
OUT
tfall
trise
Figure 6
Rise and fall times
Final Data Sheet
16
Rev.2.2
2021-11-08
EiceDRIVER™ 1EDBx275F
Single-channel isolated gate driver ICs in 150 mil DSO package
Timing diagrams
Figure 7 illustrates the behavior of the deglitch filter that suppresses input pulses with duration shorter than
tPWmin
.
IN- (low)
VINH
VINH
IN+
VINL
VINL
t
PW > tPWmin
tPW < tPWmin
OUT
Figure 7
Minimum pulse that changes the output state
Figure 8 illustrates the input supply UVLO behavior. It depicts the reaction time to UVLO events when VDDI crosses
the UVLO thresholds during rising or falling transitions (power-up, power-down, supply noise).
High logic level
IN+
Low logic level
IN-
High level ( > UVLOVDDO,on )
VDDO
VDDI
OUT
UVLOVDDI,on
UVLOVDDI,off
tSTART,VDDI
tSTOP,VDDI
Figure 8
VDDI UVLO behavior, start-up and deactivation time (unloaded output)
Figure 9 illustrates the output supply UVLO behavior. It depicts the reaction time to UVLO events when VDDO
crosses the UVLO thresholds during rising or falling transitions (power-up, power-down, supply noise).
IN+ high
IN- low
VDDI > UVLOVDDI,on
UVLOVDDO,on
UVLOVDDO,off
VDDO
OUT
tSTART,VDDO
tSTOP,VDDO
Figure 9
VDDO UVLO behavior, start-up and deactivation time (unloaded output)
Final Data Sheet
17
Rev.2.2
2021-11-08
EiceDRIVER™ 1EDBx275F
Single-channel isolated gate driver ICs in 150 mil DSO package
Timing diagrams
Figure 10 illustrates tCLAMP,OUT, the time required to clamp potential output induced overshoots in UVLO
condition (VDDO < UVLOVDDO,on).
VDDO
OUT
1.2V
tCLAMP,OUT
Figure 10 Activation time of output clamping in UVLO conditions (unloaded output)
Final Data Sheet
18
Rev.2.2
2021-11-08
EiceDRIVER™ 1EDBx275F
Single-channel isolated gate driver ICs in 150 mil DSO package
Layout recommendation
5
Layout recommendation
For any fast-switching power system the PCB layout is crucial to achieve optimum performance. Among the many
existing rules, recommendations, guidelines, tips and tricks, the ones of highest importance are listed as follow.
•
•
•
Use low-ESR decoupling capacitances (CVDDI, CVDDO) and place them as close as possible to the driver to
support high peak currents during switching and to ensure stable supply voltages for the driver. The use of
PCB planes at ground potential is also recommended to further reduce the inductance to ground.
Minimize the gate loop inductance by placing the driver as close as possible to the driven transistor and by
ensuring that the gate traces are always placed on top of a PCB plane at ground (GNDO) potential. Minimizing
the power loop inductance is the key measure to limit voltage overshoots and enable fast switching.
In case of boostrapping, minimize the boostrap loop inductance to ensure reliable operation and fast
bootstrap charge. The boostrap capacitor is, in fact, charged every cycle through the bootstrap diode and the
turned-on low-side transistor and the loop is subject to potential high peak charging currents. When this is not
possible, use a split bootstrap capacitor with one part placed in some distance of the driver to avoid induced
noise; if big enough, this acts as a stable supply for the high-side driver decoupling capacitance (placed close
to the driver).
•
•
Pay attention to keep any source of noise (like half-bridge high-current switching traces) away from the driver
to avoid any coupling capacitance.
According to the application requirements, pay attention to keep the needed input-to-output clearance and
creepage on PCB level. To fully benefits from the isolation capabilities of the driver, any trace or plane below
the device must be strictly avoided.
•
Connect the driver ground pin to proper PCB planes to reduce the junction-to-board resistance and support
the spread of heat outside the driver
A layout recommendation for EiceDRIVER™ 1EDBx275F is given in Figure 11.
CVDDI
1EDBx275F
RSNK
RSRC
GNDI
VDDO
Figure 11 Layout recommendation
Final Data Sheet
19
Rev.2.2
2021-11-08
EiceDRIVER™ 1EDBx275F
Single-channel isolated gate driver ICs in 150 mil DSO package
Application notes
6
Application notes
Note: The following information is given as a hint for the implementation of the device only and shall not be regarded
as a description or warranty of a certain functionality, condition or quality of the device.
Due to the input-to-output isolation, EiceDRIVER™ 1EDBx275F is best suited for use as high-side driver. In
particular, the combination with EiceDRIVER™ 1EDNx550B (single-channel gate driver with true differential
inputs), is best suited for half-bridge driving due to perfect matching in timing performances and output
capability.
By making use of the drivers inverting and non-inverting inputs, shoot-through protection can be implemented
as depicted in Figure 12; any undesired overlap of low-side and high-side PWM signals is not propagated at the
transistors input.
This solution is preferable compared to dual-channel gate drivers in case of high-power or high-frequency
designs; here minimizing the gate loop may become a critical requirement that can be more easily fulfilled by
using single-channel solutions.
VBUS
EiceDRIVER™ 1EDBx275F
Controller
VDD
VDD
VDDI
IN+
VDDO
OUT_SRC
OUT_SNK
GNDO
Rgon
Rgoff
PWM1
CVDDI
Q1
IN-
Cboot
GND
GNDI
Dboot
Rboot
EiceDRIVER™ 1EDNx550B
Rin1
Rin2
PWM2
IN+
IN-
VDD
Rgon
Rgoff
OUT_SRC
Q2
GND
OUT_SNK
CVDDO
Rc
Figure 12 Typical application circuit for half-bridge driving
The high CMTI of 300 V/ns, in conjunction with the ability to drive 4-pin Kelvin source transistors, makes the
combination 1EDBx275F, 1EDNx550B ideal to drive GaN and SiC power switches.
6.1
Driving 600 V CoolGaNTM
Figure 13 depicts a 1EDB7275F typical use case driving Infineon´s 600V GaN power switches (CoolGaNTM). The
example shows a soft-switching topology; here, due to acceptable switching speed, unipolar driving is possible
without risk of false triggering of the devices due to switching induced overshoots.
Details of component dimensioning can be found in the EiceDRIVER™ 1EDi-GaN product family datasheet.
Final Data Sheet
20
Rev.2.2
2021-11-08
EiceDRIVER™ 1EDBx275F
Single-channel isolated gate driver ICs in 150 mil DSO package
Application notes
400V
D
EiceDRIVER™ 1EDB7275F
Controller
VDD
8V
560
VDDI
IN+
VDDO
OUT_SRC
OUT_SNK
GNDO
10
2
1.8n
IGT60R070
G
PWM1
SS
100n
IN-
220n
S
GND
GNDI
D
2.2
EiceDRIVER™ 1EDN7550B
33k
33k
560
PWM2
IN+
IN-
VDD
OUT_SRC
OUT_SNK
10
2
IGT60R070
1.8n
G
SS
GND
2.2μ
S
10
Figure 13 Typical application circuit for 600 V CoolGaNTM driving
6.2
Driving 650 V CoolSiCTM
Figure 14 depicts a typical use case for Infineon´s 650 V SiC MOSFETs (CoolSiCTM) in a so-called “totem-pole”
PFC. It consists of a 48mΩ SiC half-bridge driven by 1EDB9275F and 1EDN9550B EiceDRIVERTM; the diode
functions indicated in the power path are usually realized with low-RDS(on) MOSFETs operating as synchronous
rectifiers. 3.3 kW of power can be handled at very high efficiency (above 99%).
Considering a typical 18 V gate-to-source voltage driving, EiceDRIVERTM 1EDB9275F and 1EDN9550B offer an
output UVLO level fitting for 650 V CoolSiCTM. With a typical UVLOVDDO,off of 14.4 V, those drivers ensure that even
in an unsupplied case the transistor (e.g. IMZA65R048M1H in a 3.3 kW totem-pole PFC) stays within the Safe
Operating Area (SOA) with acceptable power dissipation.
In Figure 14 a Schottky diode at the CoolSiCTM gate is recommended to clamp switching induced undershoots on
the gate terminal which may cause a potential drift in the gate threshold voltage Vgs,th over lifetime.
EiceDRIVER™ 1EDB9275F
Controller
VDD
3.3V
VDDI
IN+
VDDO
OUT_SRC
OUT_SNK
GNDO
6.8
PWM1
IMZA65R048M1
100n
IN-
6.8
220n
GND
GNDI
Vin
AC
2.2
EiceDRIVER™ 1EDN9550B
18V
6.8
33k
33k
PWM2
IN+
IN-
VDD
OUT_SRC
OUT_SNK
IMZA65R048M1
GND
6.8
2.2ꢀ
Figure 14 Typical application circuit for 650 V CoolSiCTM driving
Final Data Sheet
21
Rev.2.2
2021-11-08
EiceDRIVER™ 1EDBx275F
Single-channel isolated gate driver ICs in 150 mil DSO package
Typical characteristics
7
Typical characteristics
VDDI = 3.3 V, VDDO = 12 V, TA = 25°C, fsw= 1MHz, no load unless otherwise noted.
1,2
1,1
1,0
0,9
0,8
4.0
3.0
2.0
1.0
0.0
VDDI = 3.3V
VDDI = 5V
VDDI = 8V
VDDI = 12V
VDDI = 15V
VDDI = 17V
square wave input
fsw = 100 KHz
fsw = 1MHz
fsw = 3MHz
no switching
-50
0
50
100
150
-50
50
150
Tj [°C]
Tj [°C]
Typical IVDDIq quiescient
current vs. temperature
Typical IVDDI switching
current vs. temperature
Figure 15 Input-side supply current IVDDI (quiescient and switching current) with temperature
4,0
no switching
fsw = 100 kHz
fsw = 1 MHz
fsw = 3 MHz
3,0
2,0
1,0
0,0
static or square wave input
2
6
10
VDDI [V]
14
18
Typical IVDDI current vs.
input-supply voltage VDDI
Figure 16 Input-side supply current IVDDI (quiescient and switching current) with VDDI
Final Data Sheet
22
Rev.2.2
2021-11-08
EiceDRIVER™ 1EDBx275F
Single-channel isolated gate driver ICs in 150 mil DSO package
Typical characteristics
1,6
1,0
0,8
0,6
0,4
VDDO = 5V
VDDO = 8V
VDDO = 12V
VDDO = 18V
OUT HIGH
VDDO = 5V
VDDO = 8V
VDDO = 12V
VDDO = 18V
OUT LOW
1,4
1,2
1,0
0,8
0,6
0,4
-50
0
50
100
150
-50
0
50
100
150
Tj [°C]
Tj [°C]
Typical IVDDOq quiescient
current(OUT low) vs. temperature
Typical IVDDOq quiescient
current(OUT high) vs. temperature
Figure 17 Output-side supply current IVDDOq (quiescent current) with temperature
1,2
OUT HIGH
OUT LOW
1,0
0,8
0,6
0,4
5
8
11
14
17
20
VDDO [V]
Typical IVDDOq quiescient current
vs. output-supply voltage VDDO
Figure 18 Output-side supply current IVDDOq (quiescient current) with VDDO
Final Data Sheet
23
Rev.2.2
2021-11-08
EiceDRIVER™ 1EDBx275F
Single-channel isolated gate driver ICs in 150 mil DSO package
Typical characteristics
14
12
10
8
no load, VDDO = 12V,
square wave input
fsw = 100KHz
fsw = 1MHz
fsw = 3MHz
VDDO = 4.5V
VDDO = 8V
VDDO = 12V
VDDO = 20V
no load, TA = 25°C,
square wave input
50
40
30
20
10
0
6
4
2
0
-50
50
Tj [°C]
150
0
2
4
6
8
10
fsw [MHz]
Typical IVDDO switching current vs.
temperature
Typical IVDDO switching current vs.
frequency
Figure 19 Output-side supply current IVDDO (switching current without load) with temperature
2.0
1.5
1.0
0.5
0.0
40
30
20
10
0
VDDO = 5V
VDDO = 12V
VDDO = 20V
VDDO = 5V
VDDO = 12V
VDDO = 20V
square wave input,
TA = 25°C, fsw = 100KHz,
series resistance RS = 0 Ω
square wave input,
TA = 25°C, fsw = 1KHz,
series resistance RS = 0 Ω
0
5
10
0
5
10
Cload [nF]
Cload [nF]
Typical IVDDO current vs. capacitive
load (1 KHz frequency)
Typical IVDDO current vs. capacitive
load (100 KHz frequency)
Figure 20 Output-side supply current IVDDO (switching current with load) with temperature
Final Data Sheet
24
Rev.2.2
2021-11-08
EiceDRIVER™ 1EDBx275F
Single-channel isolated gate driver ICs in 150 mil DSO package
Typical characteristics
3.0
ON threshold
OFF threshold
UVLO on
UVLO off
2.5
2.0
1.5
1.0
0.5
2.9
2.7
2.5
-50
0
50
100
150
-50
0
50
Tj [°C]
100
150
Tj [°C]
Typical Undervoltage Lockout
thresholds VDDI vs. temperature
Typical input voltage thresholds vs.
temperature
Figure 21 Logic input thresholds and VDDI UVLO thresholds with temperature
4.5
4.3
4.1
3.9
3.7
8.8
8.4
8.0
7.6
7.2
6.8
6.4
UVLO on
UVLO off
UVLO on
UVLO off
-50
0
50
100
150
-50
0
50
100
150
Tj [°C]
Tj [°C]
Typical Under Voltage Lockout VDDO
thresholds vs. temperature (4 V version)
Typical Under Voltage Lockout VDDO
thresholds vs. temperature (8 V version)
Figure 22 VDDO UVLO thresholds (4 V, 8 V options) with temperature
Final Data Sheet
25
Rev.2.2
2021-11-08
EiceDRIVER™ 1EDBx275F
Single-channel isolated gate driver ICs in 150 mil DSO package
Typical characteristics
Figure 23
VDDO UVLO thresholds (12 V, 15 V options) with temperature
2.0
1.5
1.0
0.5
0.0
50
Ron_src
Ron_snk
ON
OFF
48
45
43
40
-50
0
50
Tj [°C]
100
150
-50
0
50
Tj [°C]
100
150
Typical output resistance vs.
temperature
Typical propagation
delay vs. temperature
Figure 24 Output resistance and propagation delay with temperature
Final Data Sheet
26
Rev.2.2
2021-11-08
EiceDRIVER™ 1EDBx275F
Single-channel isolated gate driver ICs in 150 mil DSO package
Typical characteristics
16
VDDO = 5 V
VDDO = 12 V
VDDO = 20 V
VDDO = 5 V
VDDO = 12 V
VDDO = 20 V
TA = 25°C,
LOAD =150nF,
RS = 0.1 Ω
8
6
4
2
0
14
12
10
8
C
6
4
TA = 25°C, CLOAD =150nF,
series resistance RS = 0.1 Ω
2
0
0
5
10
15
20
0
5
10
15
20
VOUT [V]
VOUT [V]
Typical sourcing output
current vs. output voltage
Typical sinking output
current vs. output voltage
Figure 25 Source and sink current with output voltage
12
ISRC_pk
ISNK_PK
10
8
6
4
VDDO = 12V, TA = 25°C,
CLOAD =150nF,
series resistance RS = 0.1 Ω
2
0
4
8
12
16
20
VDDO [V]
Typical peak output current
vs. supply voltage
Figure 26 Peak source and sink current with supply voltage
Final Data Sheet
27
Rev.2.2
2021-11-08
EiceDRIVER™ 1EDBx275F
Single-channel isolated gate driver ICs in 150 mil DSO package
Typical characteristics
10
8
14
12
10
8
VDDO = 5 V
VDDO = 12 V
VDDO = 20 V
VDDO = 5 V
VDDO = 12 V
VDDO = 20 V
6
4
6
2
4
CLOAD =150nF,
series resistance RS = 0.1 Ω
CLOAD =150nF,
series resistance RS = 0.1 Ω
0
2
-50
0
50
Tj [°C]
100
150
-50
0
50
Tj [°C]
100
150
Typical peak sourcing output
current vs. temperature
Typical peak sinking output
current vs. temperature
Figure 27 Peak source and sink current with temperature
50
30
20
10
0
VDDO = 5V
VDDO = 12V
VDDO =20V
VDDO = 5V
VDDO = 12V
VDDO = 20V
40
30
20
10
TA = 25°C,
series resistance Rs = 0
TA = 25°C,
series resistance Rs = 0 Ω
Ω
0
0
3
5
8
10
0
3
5
8
10
Cload [nF]
Cload [nF]
Typical rise time vs.
capacitive load
Typical fall time vs.
capacitive load
Figure 28 Rise and fall times with capacitive load
Final Data Sheet
28
Rev.2.2
2021-11-08
EiceDRIVER™ 1EDBx275F
Single-channel isolated gate driver ICs in 150 mil DSO package
Typical characteristics
2.5
Rise time
Fall time
2.0
1.5
1.0
0.5
0.0
VDDO = 12V,
no load
-50
0
50
TJ [°C]
100
150
Typical rise and fall times
vs. temperature (no load)
Figure 29 Rise and fall times with temperature
Final Data Sheet
29
Rev.2.2
2021-11-08
EiceDRIVER™ 1EDBx275F
Single-channel isolated gate driver ICs in 150 mil DSO package
Package outline dimensions
8
Package outline dimensions
8.1
Device numbers and markings
Table 21 Device numbers and markings
Part number
1EDB6275F
1EDB7275F
1EDB8275F
1EDB9275F
Orderable part number (OPN)
Device marking
1B6275A
1EDB6275FXUMA1
1EDB7275FXUMA1
1EDB8275FXUMA1
1EDB9275FXUMA1
1B7275A
1B8275A
1B9275A
8.2
Package PG-DSO-8
0.33-0.08
+0.17 x 45°
1.27
C
+0.45
0.8
3 x 1.27 = 3.81
-0.4
0.1 8x
1)
4-0.2
+0.08 2)
0.41
-0.06
A
M
0.25
D C 8x
0.2
6
M
0.25
A
8
1
5
4
D
1)
5-0.2
Index Marking
1) Does not include plastic or metal protrusion
2) Does not include dambar protrusion of 0.127 max. in excess of the lead width dimension
PG-DSO-8-41, -42, -51, -53, -58-PO V06
Figure 30 PG-DSO-8 outline1)
1) Dimensions in mm
Final Data Sheet
30
Rev.2.2
2021-11-08
EiceDRIVER™ 1EDBx275F
Single-channel isolated gate driver ICs in 150 mil DSO package
Package outline dimensions
0.65
1.27
0.65
1.27
Stencil apertures
Copper
Solder mask
PG-DSO-8-41, -42, -51, -53, -58-FP V01
Figure 31 PG-DSO-8 footprint
8
0.3
Index
Marking
6.4
1.75
2.1
PG-DSO-8-41, -42, -51, -53, -58-TP V09
Figure 32 PG-DSO-8 packaging
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant with
government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-
free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
Further information on packages
https://www.infineon.com/packages
Final Data Sheet
31
Rev.2.2
2021-11-08
EiceDRIVER™ 1EDBx275F
Single-channel isolated gate driver ICs in 150 mil DSO package
Revision history
Page or Item
Rev. 2.2, 2021-11-04
Front page
Subjects (major changes since previous revision)
Editorial updates
Table 16
Output current values are rounded
Fixed typo (OUT does not follow VDDI shape)
Fixed typo (OUT_SRC and OUT_SNK flipped)
Figure 8
Figure 11
Updated typical application circuit for 650 V CoolSiCTM updated with the new
Figure 14
1EDN9550B EiceDRIVERTM to drive the low-side MOSFET
Added new VDDI data points for typical input-side quiescient current IVDDIq vs.
temperature
Figure 15
Figure 16
Figure 17
Added typical input-side current IVDDI vs. VDDI
Added new VDDO data points for typical output-side quiescient current IVDDOq
vs. temperature
Figure 18
Added typical output-side quiescient current IVDOq vs. VDDO
Rev. 2.2, 2021-11-08
Removed “UL1577 certification pending” because certification has been
issued
Whole document
Table 1, Table 3, Table 21
Table 1, Table 21
Table 7
Added 1EDB6275F 12 V UVLO variant
Modified UVLO values for 1EDB9275F
Fixed typo in RthJB25
Table 17
Increased propagation delay max (49ns → 51ns)
Added pollution degree, climatic category and emulated VDE0884-11
parameters
Table 19
Table 20
Added safety limiting values table
Updated VDDO UVLO vs. temperature graph for 1EDB9275F, added graph for
1EDB6275F
Table 23
Rev. 2.0, 2020-04-08
Final datasheet created
Final Data Sheet
32
Rev.2.2
2021-11-08
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Document reference
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