TSI205_技术文档

Datasheet

Tsi205 Primary Side Monitor

Features

Description

The Tsi205 is designed to monitor parameters on

the high voltage primary side of an on-card power

system in a distributed power architecture.

•

Input voltage measurement (24 V or 48 V)

10-bit analog-to-digital converter (ADC)

Input voltage measurement accuracy 0.5%

Fuse status monitoring, high and low side

Primary current sensing and measurement

Primary side undervoltage, overvoltage and

brownout detection

In a typical 24 V or 48 V application, the Tsi205

measures input voltage and current and transmits

the digitized values through a serial interface to the

secondary side controller (Tsi257). Input

overvoltage (OV) and undervoltage (UV) detection

are provided, with programmable thresholds set by

external resistors.

•

Input UV shutdown accuracy <1%

Isolated PI-Link interface to secondary side

controller transmits primary voltage, current,

fuse status and input status data

•

Compatible with standard inrush limiters

Self-powered from 24 V or 48 V nominal

The Tsi205 provides on-off control for an isolated

power converter that supplies the intermediate bus

voltage for the card. The Tsi205 monitors the status

of up to four input fuses, both high side and low

side. Fuse status information is transmitted to the

secondary side through the serial PI-Link interface.

Applications

•

Telecom and datacom cards

ATCA (Advanced Telecom Compute

Architecture) systems

•

Industrial controllers

Single board computers

Figure 1 — Typical application circuit

+

0 V

(Battery

return)

R5

EMI

filter

Intermediate

bus (IB) brick

C_IN

Enable

IB rail

Power connections

shown as

-

R4

R3

R1 R2

R17

OP1

Tsi205

VDD

VDDO

ENABLE

TX_H

R16

Seat

SHUNT

SEAT

(short pins)

TX_L

Brick

shutdown

signal

from

Tsi257

BUSOFF

FETA

OP2

UV

C6

R13

C9

VBATT

FUSE_H

FUSE_L

VBG

SENSE_P

SENSE_OUT

SENSE_IN

R15

R12

T1

R19

PI-Link

interface

to Tsi257

NC

R14

R8

C7

SENSE_N

POR

R6

R7

VSS

Isolation

circuit

(see Fig. 7)

VSSO

AUX

BIAS

R9

R10

C2

-48 V A

D1

C1

Primary

Secondary

Fuse A

R11

Inrush

limit

R18

Fuse B

controller

D2

-48 V B

MD502J

Note: High-side fuse monitoring is not shown – refer to Figure 8.

80C6000_MA001_01 April 2006

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Tsi205 Primary Side Monitor

Datasheet

Absolute maximum ratings

Table 1 lists the absolute maximum ratings. Stress

at or beyond these limits is likely to cause

permanent damage to the Tsi205. Exposure to

conditions above recommended operating

conditions, up to and including absolute maximum

ratings for extended periods may affect the Tsi205

performance and reliability.

Table 1 — Absolute maximum ratings

Parameter

Condition

Rating

Maximum input voltage (analog pins)

Maximum input voltage (digital pins)

Current into any pin

Relative to V

-0.3 V to (V

+ 0.3) V

SS

DD

-0.3 V to 6 V

5 mA

SS

Power dissipation (continuous)

Operating temperature range

Junction temperature

TA = 70°C

600 mW

-40°C to +85°C

+150°C

Storage temperature

-65°C to +150°C

+300°C

Lead temperature

(soldering, 10 seconds)

Soldering temperature

Peak body temperature for reflow

260°C

ESD rating (JESD22-A114-B, HBM)

Latch-up testing per JEDEC

2000 V

±100 mA

Recommended operating conditions

Table 2 lists the recommended operating

conditions. The performance is guaranteed within

these conditions. The Tsi205 is ESD sensitive, so

normal ESD handling precautions are

recommended.

Table 2 — Recommended operating conditions

Parameter

Condition

Rating

Operating voltage, VDD (set by internal shunt regulator)

Bypass capacitor

Relative to VSS

VDD to VSS

POR to VSS

+3.3 V nominal

1 μF, ceramic

47 nF, ceramic

-40°C to +85°C

Power-on reset capacitor

Operating temperature range

- 2 -

80C6000_MA001_01 April 2006

Datasheet

Tsi205 Primary Side Monitor

Figure 2 — Pin assignments

32 31 30 29 28 27 26 25

VSS

UV

FUSE_H

FUSE_L

24

23

22

21

20

1

2

3

4

5

6

7

8

SHUNT

SENSE_N

SENSE_OUT

SENSE_P

VBATT

Tsi205

SENSE_IN

AUX

IC_VSS

ENABLE

19 IC_VSS

IC_VSS

IC_VDD

18

17

9

10 11 12 13 14 15 16

32-pin LQFP

5 × 5 mm

MD503D

Table 3 — DC characteristics

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Power supplies

VDD (set by internal shunt

regulator)

V

Temp = -40°C to 125°C

SHUNT pin connected to

VDD pin

3.13

3.3

3.46

V

DD

Supply current

I

Shunt regulator drawing

minimum current

Serial link operating, brick

enabled

—

4

mA

DD

Shunt regulator current

Startup response time

—

40

mA

SR

Supply voltage = 50 V, rise

time = 10 ns;

600

1000

μs

C1 = 1 μF; R5 = 6.2 kΩ

Overvoltage, undervoltage detection

OV threshold

V

Voltage at pin VBATT

Input voltage rising

2.37

2.39

2.42

V

OVH

Brownout threshold

V

Voltage at pin UV

Input voltage decreasing

1.302

1.24

1.312

1.25¹

1.322

1.26

V

BOL

UVT

UV comparator threshold

UV pin voltage

increasing/decreasing

Undervoltage shutdown and restart (voltage at input rail)

(Sheet 1 of 4)

80C6000_MA001_01 April 2006

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Tsi205 Primary Side Monitor

Datasheet

Table 3 — DC characteristics (Continued)

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

UV low threshold

(shutdown)

V

Voltage at input rail

Input voltage decreasing

Set by R3 and R9:

V = V × (R3+R9)/R9

UVL

V

UVL

UV

UV high threshold (startup)

V

Voltage at input rail

Input voltage increasing

Programmed by R3

= V +(I

V

UVH

V

×R3)/

UVL UVHY

UVH

1000 (R3 expressed in kΩ)

UV hysteresis

V

I

Voltage at input rail

Programmed by R3

V

UVHY

V

= (I

×R3)/1000

UVHY

(R3 expressed in kΩ)

Hysteresis current sink

Current sense amplifier

Output range

UV shutdown condition

9.9

11

12.1

μA

UVHY

V

Voltage at SENSE_OUT

0.138

-0.1

—

2.56

2

V

ISENSE

CM

Input range

V

Voltage between SENSE_N

and SENSE_P input pins

and V

SS

Input offset

V

—

1

2

mV

MΩ

dB

OFFSET

Input resistance

DC open loop gain

Unity gain bandwidth

R

10

—

IN

R_LOAD> 50 kΩ

60

C_LOAD< 50 pF

100

kHz

R_LOAD> 50 kΩ

Overcurrent detection

threshold

OC

V

Voltage at SENSE_IN pin

2.15

1.24

2.18

2.21

V

Inrush monitor

Inrush complete

Inrush complete is detected

when voltage between

1.25

1.26

FETA

FETA and V pins

SS

exceeds this threshold

Digital pin voltage levels (except pins TX_H, TX_L)

Output low

Output high

Input low

V

I

= 1 mA

—

2.4

-0.3

2.0

—

0.4

—

V

OL

OH

IL

OH

= -1 mA

0.3 ×

V

DD

Input high

5.25

IH

PI-Link transmit datalink (pins TX_H, TX_L)

(Sheet 2 of 4)

- 4 -

80C6000_MA001_01 April 2006

Datasheet

Tsi205 Primary Side Monitor

Table 3 — DC characteristics (Continued)

Parameter

Symbol

Conditions

Min

-0.2

Typ

Max

0.2

Unit

TX_H to TX_L differential

voltage - both driving logic

one

V

I

= +100 mA

= +300 mA

—

Vdiff

DIFF(11+)

DIFF(11-)

DIFF(00+)

DIFF(00-)

DIFF(01+)

DIFF(01-)

DIFF(10+)

DIFF(10-)

TXH

TXL

TX_H to TX_L differential

voltage - both drive logic

one

I

= -100 mA

= -300 mA

-0.2

-1.4

1.4

—

0.2

-4.0

4.0

Vdiff

TXH

TXL

TX_H to TX_L differential

voltage - both drive logic

zero

I

= +100 mA

= +300 mA

TXH

TXL

TX_H to TX_L differential

voltage - both drive logic

zero

I

= -100 mA

= -300 mA

TXH

TXL

TX_H to TX_L differential

voltage - TX_H drives zero,

TX_L drives one

I

= +100 mA

= +300 mA

TXH

TXL

TX_H to TX_L differential

voltage - TX_H drives zero,

TX_L drives one

I

= -100 mA

= -300 mA

TXH

TXL

TX_H to TX_L differential

voltage - TX_H drives one,

TX_L drives zero

I

= +100 mA

= +300 mA

TXH

TXL

TX_H to TX_L differential

voltage - TX_H drives one,

TX_L drives zero

I

= -100 mA

= -300 mA

1.4

TXH

TXL

Input voltage monitor (at input pins VBATT, SENSE_IN, AUX)

ADC resolution

Voltage at VBATT and AUX

pins

10 bits

bits

Refer to Table 9 on page 22

Input current (voltage at

SENSE_IN pin)

8 bits

Voltage at FUSE_H and

FUSE_L pins

8 bits

Input voltage range for ADC

Zero scale voltage

V

No ADC saturation

0.121

—

0.121

0.119

2.2

2.377

—

V

INLH

ZS10

ZS8

Refer to Figure 3 on page 7

V

—

V

Input resolution (LSB)

Input capacitance

LSB

—

mV

pF

mV

10

8

—

8.8

—

C

V

—

1.24

—

IN

Total voltage conversion

accuracy of ADC

Includes ±½LSB

10

quantization error

—

7.7

ACC1

(Sheet 3 of 4)

80C6000_MA001_01 April 2006

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Tsi205 Primary Side Monitor

Datasheet

Table 3 — DC characteristics (Continued)

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Supply voltage monitor (voltage at input rail)

Supply voltage monitor

resolution

(effective LSB at input rail)

V

Assumes 33:1 resistor

divider ratio

(R4 and R10 in Figure 1)

—

72.6²

mV

LSB2

2

Supply voltage monitor

accuracy (at input rail)

Assumes 33:1 resistor

divider ratio — R4 and R10

in Figure 1

—

218

ACC2

Includes ±½LSB

10

quantization error

Fuse monitoring

FUSE_L fuse failure

detection threshold

V

Voltage at pin FUSE_L

increasing

Threshold = voltage at

VBATT pin × 0.57, ±30 mV

V

FUSE_L

FUSE_H fuse failure

detection threshold

Voltage at pin FUSE_H

decreasing

Threshold = voltage at

VBATT pin × 0.57, ±30 mV

FUSE_H

Voltage comparator (AUX input)

Comparator threshold

V

1.22

1.25

1.28

V

AUXCOMP

(Sheet 4 of 4)

1. Tighter tolerance for UV shutdown is available. Contact Tundra Semiconductor for details.

2. Specified values do not include tolerances for R4 and R10.

= (121 + READ × 2.2) mV ± 1.1 mV

ADC zero and full-scale definition

The ADC conversion is derived by dividing the full

scale minus the zero-scale voltage by 1024. The

where READ is the value in the register.

For 8-bit values, the equation is:

first code point spans ½ of an LSB .

10

V = (V

+ READ × LSB ) ± LSB /2

8 8

ZS8

For 10-bit values, the equation is:

= (119.9 + READ × 8.8) mV ± 4.4 mV

V = (V

+ READ × LSB ) ± LSB /2

10 10

ZS10

- 6 -

80C6000_MA001_01 April 2006

Datasheet

Tsi205 Primary Side Monitor

Figure 3 — ADC zero scale and full scale

Digital

codes

1023

Voltage on

SENSE pins (V)

0

Vzs

V

FS

First transition occurs when Vsense is Vzs + ½ × LSB₁₀

Last transition occurs when Vsense is Vzs + 1022.5 × LSB₁₀

V

is last transition + 1.5 × LSB

FS

10

Table 4 — AC characteristics

Parameter

Filters

Symbol

Condition

Min

Typ

Max

Unit

Undervoltage filter

Brownout filter

T

Input voltage

increasing

155

—

200

235

—

ms

μs

PUV

POV

Undervoltage filter

Brownout filter

Input voltage

decreasing

Overvoltage filter

Input voltage rising or

falling

155

235

ms

Overcurrent filter

Transmission of bit

status

FETA voltage filter

T

Inrush complete

600

155

800

200

950

235

ms

PUV

High-side fuse open filter

Fuse open detection

at FUSE_H

PAGV

Low-side fuse open filter

T

Fuse open detection

at FUSE_L

155

200

235

ms

PBGV

SEAT filter

Seat valid state

40

9.5

600

50

12

60

ms

SEAT filter

Seat invalid state

14.5

950

BUSOFF mask

Mask at startup, after

brick enable

800¹

(Sheet 1 of 2)

80C6000_MA001_01 April 2006

- 7 -

Tsi205 Primary Side Monitor

Datasheet

Table 4 — AC characteristics (Continued)

Parameter

Symbol

Condition

Min

Typ

Max

Unit

BUSOFF filter

Brick shutdown

19

—

25

30

—

ms

Primary brick shutdown

delay

T

After detecting UV

210

μs

PSHDN

1

Primary brick shutdown

delay

T

After receiving

shutdown signal from

Tsi257

19

24

—

ms

PSHDN

Voltage sampling (FUSE_H, FUSE_L, SENSE_IN, VBATT, AUX)

Sampling rate

Primary to secondary link (TX_H, TX_L)

T

0.87

1.3

1.75

66.6

ksamples/s

SMPL

Period of bit

T

22.2

—

μs

Pulse width for logic high

(50% to 50%)

PWH

(3/4)T-10

(3/4)T

(3/4)T+10 ns

Pulse width for logic low

(50% to 50%)

PWL

(¼)T-10

(¼)T

(¼)T+10

ns

Rise time (10% to 90%)

Fall time (10% to 90%)

T

R

0.1

84

—

5.0

ns

T

F

Delay on rising edges

(50% to 50%)

T

140

DR

DF

DR

Delay on falling edges

(50% to 50%)

84

—

140

—

ns

Delay mismatch

- T

±5

DF

(Sheet 2 of 2)

1. 800 ms mask after brick is initially enabled at startup, before response to primary shutdown signal

Figure 4 shows the drive voltage waveform at the

page 9 shows the timing relationship between the

TX_H and TX_L pins.

TX_H and TX_L pins, relative to V . Figure 5 on

SS

Figure 4 — Bit timing - primary to secondary link

T

PWH

PWL

V

IH

V

IL

TR

TF

- 8 -

80C6000_MA001_01 April 2006

Datasheet

Tsi205 Primary Side Monitor

Figure 5 — Delay timing - primary to secondary link

TDF

T

DR

80C6000_MA001_01 April 2006

- 9 -

Tsi205 Primary Side Monitor

Datasheet

Figure 6 — Functional block diagram

1.25 V

1.31 V

2.39 V

50 k

R

BIAS

125 kHz oscillator

Comparator

reference

0.5 V

VBG

-

50 k

R

SEAT

+

OR

gate

50 k

R

-

ENABLE

POR

VDD

+

VDD

3.3 V shunt

regulator

SHUNT

POR

VBATT

x 0.57

FH

TX_H

TX_L

SDIFF

VBATT

x 0.57

FL

Digital logic

VDDO

VSSO

FUSE_H

FUSE_L

ADC_Control

BUSOFF

SENSE

IN

5:1 Mux

10-bit ADC

SENSE

OUT

VBATT

AUX

VBG

SENSE_N

SENSE_P

-

Current

sense

-

OV

2.39 V

2.18 V

1.25 V

+

-

+

OC

To

LOGIC

R

1.31 V

-

+

BO

UV

AUX

+

-

1.25 V

-

+

To

logic

UV

11uA

FETA

VSS

VBG

VSS

Bandgap

+

FETA

-

1.25 V

- 10 -

80C6000_MA001_01 April 2006

Datasheet

Tsi205 Primary Side Monitor

Table 5 — Pin functions

Pin name

Description

1

UV

The voltage at this pin is compared to an internal UV reference of 1.25 V. An external

resistor divider is required to prevent the voltage from exceeding 3.3 V. Hysteresis is

applied using an internal current source of 11 μA.

This pin also feeds a second comparator that has a reference of 1.31 V. This

comparator generates a Brownout warning that is transmitted through the PI-Link

interface to the Tsi257. Decoupling capacitor (1000 pF) is required.

2

3

FUSE_H

FUSE_L

This pin connects to a resistor network to sense failure of a high-side (battery return)

fuse. Refer to Figure 8 on page 20. Failure detection occurs when the voltage falls

below 0.57 × VBATT. Voltage range is 0 to 3.3 V.

This pin can also be used to measure any voltage between 0.121 V and 2.377 V. The

measured voltage at this pin is transmitted to the secondary side as an 8-bit value,

through the PI-Link interface. Decoupling capacitor (1000 pF) is required.

This pin connects to a resistor network to sense failure of a low side (-48 V) fuse. Refer

to Figure 8 on page 20. Failure detection occurs when the voltage rises above 0.57 ×

VBATT. Voltage range is 0 to 3.3 V.

This pin can also be used to measure any voltage between 0.121 V and 2.377 V. The

measured voltage at this pin is transmitted to the secondary side as an 8-bit value,

through the PI-Link interface. Decoupling capacitor (1000 pF) is required.

4

5

VBATT

This pin connects to a resistor divider to measure input voltage (after ORing diodes).

The measured voltage from the ADC is transmitted to the secondary side as a 10-bit

value through the PI-Link interface. Voltage range is 0.121 V to 2.377 V.

This pin also feeds a comparator with a trip level of 2.39 V, to detect overvoltage (OV).

Decoupling capacitor (1000 pF) is required.

SENSE_IN

This pin is normally used to measure the output of the internal current sense amplifier.

The measured voltage is transmitted to the secondary side as an 8-bit value, through

the PI-Link interface. Voltage range is 0.121 V to 2.377 V. This input can also be used

to measure any other voltage within the ADC full scale range.

This pin also feeds a comparator with a trip level of 2.18 V, to detect overcurrent (OC).

Decoupling capacitor (1000 pF) is required.

6

AUX

This pin can be used to measure any voltage in the range 0.121 V to 2.377 V.

The measured voltage from the ADC is transmitted to the secondary side through the

PI-Link interface. Decoupling capacitor (1000 pF) is required.

7

IC_VSS

ENABLE

IC_VSS

NC

Internal connection — connect to VSS

Drives optocoupler to brick enable pin (1 mA nominal)

Internal connection — connect to VSS

No connection allowed

8

9

10

11

12

13

VSS

Connects to -48 V (ground reference for the Tsi205)

Driver for PI-Link interface to Tsi257

TX_H

VSSO

Connect to pin 24 (VSS)

Connects to -48 V (ground reference for Tsi205)

14

15

VDDO

TX_L

Connect to pin 25 (VDD) — 1 μF decoupling is required

Driver for PI-Link interface to Tsi257

(Sheet 1 of 2)

80C6000_MA001_01 April 2006

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Tsi205 Primary Side Monitor

Datasheet

Table 5 — Pin functions (Continued)

Pin name

Description

16

17

18

19

20

21

22

23

NC

No connection allowed

IC_VDD

IC_VSS

SENSE_P

SENSE_OUT

SENSE_N

SHUNT

Internal connection — connect to pin 25 (VDD)

Internal connection — connect to VSS

Positive input to internal current sense amplifier

This pin is the output of the internal current sense amplifier.

Negative input to internal current sense amplifier

This pin connects to the drain of an internal shunt transistor. It normally connects to pin

25 as internal shunt regulator for VDD.

24

25

VSS

VDD

This pin connects to -48 V (ground reference for the Tsi205)

3.3 V power — normally connects to pin 14 and 23

(Tsi205 uses internal shunt regulator and external resistor from 48 V input)

26

27

NC

No connection allowed

POR

This pin connects to an external capacitor for power-on reset — recommended value

is 47 nF.

28

29

BUSOFF

SEAT

This pin connects to an external optocoupler to receive a shutdown signal from the

Tsi257. Logic high on the BUSOFF pin disables the intermediate bus brick.

This pin can be connected as either a high or a low SEAT pin. External resistors must

be used if required to ensure the voltage remains below 3.3 V. The Tsi205 must detect

a valid seat input before it can generate the brick enable signal. A digital debounce is

provided — refer to Table 6 on page 15.

30

31

32

FETA

BIAS

VBG

This pin is used to monitor V

complete. Inrush completion is detected when the voltage exceeds 1.25 V.

of the external inrush FET to detect when inrush is

GS

This pin sets the bias current for the device — refer to Table 8 on page 21 for

recommended bias resistor.

This pin is the 1.2 V bandgap reference output, and is normally left open.

(Sheet 2 of 2)

Functional description

The Tsi205 is a primary side monitoring device

which supports an isolated communication

interface to a secondary side power management

controller. It also provides control for an

intermediate bus power converter. Figure 6 on

page 10 shows the functional block diagram of the

Tsi205.

signal from the secondary side. Resistor dividers

are used to reduce the high voltages to levels

suitable for the Tsi205 inputs.

Primary side current measurement

The Tsi205 has an internally compensated low-

offset current sense amplifier whose gain can be set

by external resistors (R12 and R15 in Figure 1). The

gain is 1 + (R15/R12). Set up the gain in

conjunction with the current sense resistor R18, so

that the output of the current sense amplifier is

Figure 1 on page 1 shows a typical application,

including the isolated interface to the secondary

side using a transformer. Figure 1 also shows the

enable connection to the brick, and the shutdown

- 12 -

80C6000_MA001_01 April 2006

Datasheet

Tsi205 Primary Side Monitor

approximately 2 V at full load. It is recommended to

use a value of approximately 50 kΩ for R15.

hysteresis is provided by switching in a current

source of 11 μA when a UV condition is present.

The UV threshold setpoint in the Tsi205 is very

precise, specified as 1.25 V ±10 mV.

In most applications, the output of the current sense

amplifier (pin SENSE_OUT) is connected to the

sensing input of the 10-bit ADC (pin SENSE_IN —

refer to Figure 1 on page 1). The measured current

value is converted to a voltage, sampled by the

ADC and stored in a register for transmission to the

secondary side. The transmitted current is an 8-bit

value (the two LSBs are discarded).

Note: Tighter tolerance for UV shutdown is

available. Contact Semiconductor for details

The UV condition is used by the Tsi205 to shut

down the brick. The resistor divider must be chosen

so that the voltage at the UV pin is exactly 1.25 V

when the input voltage is at the intended UV

shutdown level. Resistors with 0.1% tolerance are

recommended to maintain high accuracy.

An internal reference is used to generate an

overcurrent (OC) alarm when the SENSE_IN pin of

the ADC reaches 2.18 V. This is a single bit value

and is transmitted to the secondary side. The

Tsi205 does not initiate a shutdown when an OC

alarm is detected.

An additional comparator with a threshold of 1.31 V

is connected to the UV pin and is used to generate

a Brownout signal. The Brownout signal is

transmitted to the secondary side controller through

the PI-Link interface as a warning, but the Tsi205

does not initiate a shutdown on detecting the

Brownout. Because the Brownout signal is derived

from the same resistor divider as the UV shutdown,

the resistor tolerances affect the two signals equally

and guarantee that Brownout is always detected

before the UV shutdown.

Primary side voltage measurement

Primary voltage is monitored after the input fuses

and ORing devices, and is the voltage seen at the

input of the brick. (In most applications, an EMI filter

is used between the Tsi205 and the brick, as shown

in Figure 1. Voltage drop across the EMI filter is

usually very small.) The primary voltage is

connected through a resistor divider into the VBATT

pin, sampled by a 10-bit ADC and stored in a

register for transmission to the secondary side.

The OV threshold is detected by an internal

comparator connected to the voltage measurement

input (VBATT pin), with a value of 2.39 V. This

allows the OV setpoint to be chosen independently

of the UV setpoint.

Choose the resistor divider values so that the

voltage at the VBATT pin is 2.39 V at the intended

OV detection level. OV detection is described more

fully in Primary OV and UV detection on page 13.

Both UV and OV status is transmitted to the

secondary side through the PI-Link interface.

Note: When an OV condition is detected, the

Tsi205 does not normally disable the brick. As a

factory-programmed option, the brick can be shut

down when an OV condition is detected. Refer to

Table 9 on page 22 for details.

Seating

The card seating is determined by monitoring the

voltage on the SEAT pin. An external resistor

divider is used if necessary, depending on the

SEAT option used. The intermediate bus brick is not

turned on unless the SEAT pin is valid. A debounce

is provided, refer to Table 6 on page 15.

Low input shutdown and restart

In most applications using battery backup, the low

input shutdown voltage (LISD) and the restart

voltage (LISDrec) are tightly specified. Overall

equipment specifications dictate the requirements

for each card. When using the Tsi205, the LISD

voltage at the card input is equal to the UV detection

Dual comparators are used for the SEAT input,

which is internally floated at a voltage midway

between VDD and VSS. The SEAT status is

recognized as valid if the SEAT pin is pulled either

high or low. This allows the Tsi205 to detect either

a high or low SEAT connection, to suit different

possible application requirements.

threshold (V

) set by R3 and R9, plus the voltage

UVL

drop in the ORing diodes and input fuse. Choose

values of R3 and R9 that take into account the

voltage drop across the ORing diodes (D1 and D2

in Figure 1 on page 1), fuses and distribution wiring.

Primary OV and UV detection

The Tsi205 monitors the primary voltage using

comparators for undervoltage (UV) and overvoltage

(OV) conditions. The UV threshold is set by a

resistor divider connected into the UV pin. Internal

The restart voltage (LISDrec) is equal to the LISD

threshold plus the hysteresis. The hysteresis is set

by an internal 11 μA current sink connected to the

80C6000_MA001_01 April 2006

- 13 -

Tsi205 Primary Side Monitor

Datasheet

UV pin, as shown in Figure 6 on page 10. The

11 μA current sink is only active during the time

when a UV condition is present. The added current

flows through R3 and raises the UV detection level

regulator. Operating voltage is 3.3 V. Since the

maximum current is 5 mA (including 1 mA for the

optocoupler OP1 — refer to Figure 1 on page 1),

the external resistor must be rated at 1 W for a

supply voltage range from 36 V to 75 V.

(V

) by a voltage equal to (0.011 × R3) V, where

UVH

R3 is expressed in kΩ. For example, if R3 is

301 kΩ, the hysteresis is 3.31 V.

Brick enable drive

The Tsi205 is normally used in conjunction with a

separate inrush limiter device. If that device also

has a brick enable function, only the Tsi205 must

connect to the brick. The Tsi205 monitors the gate-

to-source voltage of the inrush FET through the

FETA pin (via resistor divider R13, R14) to

determine when the inrush is complete.

Using the suggested component values given in

Table 8 on page 21, the LISD is set to 37.08 V and

the LISDrec is set to 40.39 V nominal. Setpoint

accuracy for LISD is ±300 mV (plus the effect of the

tolerances of R3 and R9). Setpoint accuracy for

LISDrec is slightly reduced (±350 mV) due to the

tolerance of the 11 μA current sink (refer to Table 3

on page 3).

The brick is turned on if all of the following are true:

•

SEAT pin is valid

Input voltage is above V

Primary side fuse status

UVH

The status of the primary input fuses is monitored

using two pins (FUSE_H, FUSE_L). A resistor

divider network is used to set the voltage on these

pins. The voltage levels are interpreted by the

Tsi205, and transmitted to the secondary side

through the PI-Link interface. A glitch filter is used

to avoid nuisance fault detection. Refer to Table 4

on page 7 for details.

•

Inrush is complete (FETA pin is >1.25 V)

The brick is turned off if any of the following are true:

•

SEAT pin is invalid

Input voltage is below V

UVL

•

BUSOFF pin is high (after startup mask expires)

Inrush is not complete (FETA pin is <1.25 V)

The voltage of each of these pins is also transmitted

to the secondary side as an 8-bit value. This allows

flexibility for use in other applications.

Glitch filters are used on all these signals to avoid

any possibility of unwanted nuisance shutdown. For

details, refer to Table 6 on page 15, and to Table 4

on page 7.

Secondary side shutdown

The Tsi205 can be used to shut down the brick in

response to a Shutdown signal from the companion

secondary side controller. This allows the

secondary side controller to shut down the

intermediate bus if it detects an unrecoverable fault

in the secondary power converters. For example, if

a point-of-load power converter fails it may not

respond to a shutdown signal at its own enable pin.

Auxiliary voltage measurement

The Tsi205 can measure an additional primary side

voltage using the AUX pin. The voltage at this pin is

converted into a 10-bit value and stored in a register

for transmission to the secondary side. The voltage

at the AUX pin also feeds a comparator with a

reference of 1.25 V.

The AUX pin is intended as a general purpose

input. It can be used to monitor any primary side

signal, such as fan speed.

The Shutdown signal connects to the BUSOFF pin

of the Tsi205 through an optocoupler. This pin has

an internal debounce timer to prevent spurious

events causing a false shutdown - refer to Table 6.

This pin is active high to shut down the brick. When

the optocoupler is on the brick is enabled (through

the ENABLE pin), which ensures that a failed

optocoupler does not cause an undetected fault. A

one second mask is applied to this signal on power

up, since the optocoupler is not active at that time.

Note: The auxiliary voltage measurement is

normally transmitted to the secondary side as an

8-bit value (the two LSBs are discarded). As a

factory-programmed option, the auxiliary voltage

can be transmitted as a 10-bit value. Refer to

Table 9 on page 22 for details.

Decoupling capacitors

Tsi205 power feed

Decoupling

capacitors

(1000 pF)

are

The Tsi205 is designed to power itself from the

primary voltage (usually 24 V or 48 V nominal),

using an external resistor and an internal shunt

recommended on the following pins: UV, VBATT,

FUSE_H, FUSE_L, and AUX.

- 14 -

80C6000_MA001_01 April 2006

Datasheet

Tsi205 Primary Side Monitor

Glitch filters

Glitch filters (digital delays) are applied to the logic

signals in the Tsi205, to prevent incorrect operation

due to short transient spikes or other momentary

events. The values of these filters are shown in

Table 6.

Figure 1 on page 1) immediately starts to discharge

due to the load current drawn by the brick. The UV

detection time is deliberately set to be very short

(200 μs) to ensure that the Tsi205 correctly detects

a UV condition before the voltage drops to the

internal shutdown threshold of the brick. Refer to

Using a Tundra Primary Side Monitor for more

information.

Note: The UV detection filter is much shorter than

the other filters. If -48 V power to the card is

removed suddenly, the input capacitance (C in

IN

Table 6 — Glitch filters - summary

Signal

Brick enable

Brick disable

Comment

BUSOFF

Masked for 800 ms after brick

is enabled

24 ms debounce before brick

is disabled

Initial mask to allow time for

secondary controller to start

SEAT

FETA

UV

50 ms debounce for valid

SEAT to enable brick

10 ms debounce for invalid

SEAT to disable brick

800 ms debounce before

brick is enabled

800 ms debounce before

brick is disabled

200 ms debounce before

brick is enabled

200 μs debounce before

brick is disabled

OV

200 ms debounce for both high and low transitions

PI-Link isolated interface to secondary

The PI-Link interface is designed to transmit power

system status information from the primary side to

the secondary side, while maintaining the required

isolation. Data transmission through the PI-Link is

unidirectional, from primary to secondary. The

PI-Link network is driven by the TX_H and TX_L

pins of the primary side device (for example, the

Tsi205), and connects into the RX_IN input pin of

the secondary side device (for example, the

Tsi257).

RX_IN input pin of the Tsi257. The required

component values for the isolation network are

shown in Table 7. Capacitors C3 and C4 provide

DC blocking. R23 acts as a high frequency filter in

conjunction with the pad input capacitance of the

Tsi257, and C5 provides DC blocking. Data is

transmitted across T1 as pulses of alternating

polarity, and is encoded using pulse position

modulation.

The PI-Link isolated interface transmits the voltage

and current measurement values and the digital

status information to the secondary side device.

The transmitted information is as follows:

In Figure 1 on page 1, the isolated interface

connection is shown as a transformer. A few

additional components are necessary to block DC

and balance the transformer signals for noise

immunity, as shown in Figure 7 on page 16.

Voltage and current sample values

•

Input voltage (10-bit value)

Auxiliary voltage (8-bit or 10-bit value, refer to

Table 9 on page 22)

Note: The components must be physically located

within the dimensions shown in Figure 7 to

guarantee proper operation.

•

Input current (8-bit value)

The PI-Link network is driven by the TX_H and

TX_L pins of the Tsi205, and connects into the

80C6000_MA001_01 April 2006

- 15 -

Tsi205 Primary Side Monitor

Datasheet

•

Voltage at FUSE_L and FUSE_H pins (8-bit

value)

•

Input overvoltage (OV)

SEAT pin invalid

Inrush not complete

Input undervoltage (UV)

Digital status bits (zero = normal, one = fault)

•

Any fault (this bit is set to one if any of the other

bits is set)

Fuse fail (high or low fuse open)

Brownout

Input overcurrent (OC)

Any of the first four bits can be mapped to a GPIO

pin in the Tsi257 secondary side device. Refer to

the Tsi257 Software Reference Manual for detailed

information on configuring the Tsi257 GPIO pins.

•

Figure 7 — PI-Link interface network

2 in. (max)

18 in. (max)

Tsi205

Tsi257

R23

TX_H

(pin 12)

RX_IN

2 : 1

C3

T1

TX_L

(pin 15)

C4

C5

VSS

Network

MD504F

Table 7 — Component values for Figure 7

Component

Value

Tolerance (%)

R23

C3, C4

C5

1 kΩ

1

100 nF, 100 V, ceramic

1 μF, 100 V, ceramic

ESMIT 4153 (Sumida)

10

1

T1

1. http://www.sumida.com/products/pdf/ESMIT_4152_4153_4154.pdf

The recommended transformer meets the isolation

(creepage and clearance) requirements for BASIC

insulation according to IEC60950, for input voltage

ranges of 24 V, 48 V or 60 V nominal (100 V

transient).

To ensure that the complete card meets this

requirement, the brick used for the intermediate bus

and the optocouplers used for isolation must meet

the same requirements. The PCB must maintain

adequate spacing between primary and secondary

for all components and copper traces. It is

recommended to provide an isolation barrier in the

PCB which is free of copper traces on all layers

Note: In case of isolation failure of transformer T1,

the full input voltage will appear across capacitors

C3 and C4. Therefore, capacitors C3 and C4 should

be rated at 100 V.

(including ground planes), with

a

width of

- 16 -

80C6000_MA001_01 April 2006

Datasheet

Tsi205 Primary Side Monitor

approximately 0.1 inches (0.062 inches minimum).

Refer to Designing On-Card Power Circuits for

more details.

Applications information

This section provides information on component

selection, as well as some information on using

additional features of the Tsi205.

OP1). The highest value resistor that can be used

for Rd is as follows:

Rd (max) = (36 V - 3.46 V)/5 mA = 6.51 kΩ.

The closest standard value is 6.2 kΩ. The

maximum power dissipation in this example is

calculated as:

Powering the Tsi205

The Tsi205 contains an internal shunt regulator on

the VDD pin that prevents the voltage on that pin

from exceeding 3.3 V. It is necessary to use an

external resistor Rd (R5 in Figure 1) between the

card supply voltage and the VDD pin. The resistor

allows the device to operate across a wide range of

system supply voltages (typically -36 V to -75 V for

a -48 V system). A capacitor (C1 in Figure 1)

provides filtering of the voltage at VDD.

2

P (max) = (72 V - 3.13 V) /6.2 = 765 mW.

A rating of 1 W is therefore required.

24 V application

For a 24 V application (input voltage range 18 to

36 V), the highest value resistor that can be used

for Rd is as follows:

Rd (max) = (18 V - 3.46 V)/5 mA = 2.91 kΩ.

Resistor Rd must provide the Tsi205 and any other

items powered from VDD (such as the optocoupler

OP1) with sufficient operating current under

minimum supply voltage conditions. The value of

Rd must not allow the maximum shunt regulator

current to be exceeded under maximum supply

voltage conditions.

The closest standard value is 2.87 kΩ. The

maximum power dissipation in this case is

calculated as:

2

P (max) = (36 V - 3.13 V) /2.91 = 376 mW.

A rating of 500 mW is therefore required.

The required resistor value is calculated from:

Rd = (Vs

- VDD

) / (IDD +I )

max load

Resistor selection

This section describes the choice of resistors for

current sense, input voltage measurement and fuse

monitoring.

min

max

where Vs

is the lowest operating input voltage,

min

VDD

is the upper limit of the Tsi205 supply

max

voltage (3.46 V), IDD

required for the Tsi205 to operate (4 mA), and I

is the maximum current

max

load

is any additional load current from the 3.3V outputs

of Tsi205 and between VDD and VSS.

Current sense resistor

Consider the following aspects when choosing the

current sense resistor R

Figure 1):

(shown as R18 in

The minimum wattage required for Rd is:

SENSE

2

P = (Vs

- VDD ) /Rd

max

min

where VDD

voltage (3.13 V) and Vs

input voltage.

is the lower limit of the Tsi205 supply

•

Voltage drop

Accuracy

Measurement resolution

Efficiency and power dissipation

Inductance

Cost

min

is the highest operating

max

In applications where the input voltage may swing

over a very wide range the maximum current may

be exceeded. Consult Tundra for information on

other powering options.

Inrush current control

48 V application

Voltage drop

Higher values of R

drop. The lowest R

voltage drop.

As an example, assume the input voltage ranges

from 36 V to 72 V, and the total current is 5 mA

(4 mA for the Tsi205 and 1 mA for the optocoupler

cause increasing voltage

value gives the least

SENSE

80C6000_MA001_01 April 2006

- 17 -

Tsi205 Primary Side Monitor

Datasheet

The gate voltage of the MOSFET must be

above the gate turn-on threshold at the point

where the voltage at the FETA pin reaches

1.25 V. This avoids incorrectly detecting that

inrush is complete before the MOSFET is fully

turned on.

Accuracy

•

Higher values of R

allow more accurate

SENSE

current measurement, because the voltage offset

and input bias current offsets of the current sense

amplifier are less significant with respect to the

sense voltage. There is also less likelihood of noise

affecting the accuracy.

The impedance of R13 and R14 in series must

be high enough so that it does not affect the

operation of the inrush limiter device.

Measurement resolution

For precise current measurement, choose the

sense resistor to exploit the dynamic range of the

ADC (0.121 V to 2.377 V). Set the gain of the

current sense amplifier so that the measured value

is close to full scale at maximum current. As

described in Primary side current measurement on

page 12, the overcurrent detection threshold occurs

when the measured voltage reaches 2.18 V.

The actual values needed will depend on the inrush

limiter and inrush MOSFET used.

UV resistor divider

The UV pin detects undervoltage conditions at the

input. The voltage at the UV pin is compared to an

internal comparator. Hysteresis is applied by an

internal current source of 11 μA, that is only active

when UV is detected.

Efficiency and power dissipation

At high current levels, the I R loss in R

2

can be

SENSE

significant, and must be considered when choosing

the resistor value and power-dissipation rating

(wattage). Excessive heat in the sense resistor can

also cause the value to drift.

When the UV pin falls below its lower threshold, the

ENABLE pin is pulled low. The ENABLE pin is held

low until the value on the UV pin rises above the

upper threshold (startup), now raised due to the

additional 11 μA current through the upper sense

resistor. The divider resistors are shown as R3 and

R9 in Figure 1 on page 1.

Inductance

If the input current has a significant high frequency

component, R

must have a low inductance.

SENSE

The shutdown threshold voltage when the input

moves from high to low is:

Cost

Using a PC board trace as a sense resistor is an

alternative method for applications where the cost

V

(shutdown) = 1.25 × (R3 + R9)/(R9)

UV

of R

is an issue. However, this method does

SENSE

The startup threshold voltage when the input moves

from low to high is:

not give good initial accuracy, and is temperature

dependent due to the temperature coefficient of

copper resistivity.

V

(startup) = 1.25 × (R3 + R9)/(R9) + (11 μA × R3)

UV

For example, if R3 is chosen to be 301 kΩ and R9

is 10.5 kΩ, the calculated UV shutdown voltage is

37.08 V and the startup voltage is 40.39 V.

Inrush current control

Since the R

resistor is also used by the inrush

SENSE

controller, the value must be suitable for that

device.

Note: The choice of UV resistors also affects the

level where Brownout is detected. This is set to be

5 ±0.5% higher than the value of UV.

Inrush completed detection

Resistors R13 and R14 form a divider to reduce the

voltage seen at the FETA pin. Select the resistor

divider ratio to meet two criteria:

Fuse monitoring

The Tsi205 can detect both a high-side (the 0 V, or

battery return) and a low-side (-48 V) fuse failure.

This is achieved using two input pins on the device,

FUSE_H and FUSE_L. A resistor network is used

to allow the Tsi205 to detect the failure of any fuse

over the range of input voltage.

•

The divider ratio must ensure that the Tsi205

correctly detects when the inrush is complete,

even with the minimum input voltage. This

requires that the voltage at pin FETA is at least

1.25 V above VSS.

•

The voltage at the FETA pin must not exceed

the maximum allowed, even with the maximum

DC input voltage. (It is not necessary to

consider transient input voltages shorter than

the gate time constant.)

Figure 1 on page 1 shows the resistor network for

low side monitoring, consisting of R6, R7 and R8

together with R1 and R2. Normally, the voltage at

the junction of fuse A and ORing diode D1 in

Figure 1 is held at -48 V nominal. The voltage at the

- 18 -

80C6000_MA001_01 April 2006

Datasheet

Tsi205 Primary Side Monitor

V

× R8/(R1 + R6 + R8).

FUSE_L pin of the Tsi205 is also held low by R6, R7

and R8.

in

The above assumes equal voltages at the two

inputs A and B, which is the normal case in most

systems. If the input voltages are different, the

voltage at pin FUSE_L is intermediate between the

two feed voltages, in a ratio set by the values of R1,

R2, R6 and R7. In order to guarantee proper

operation even at the extreme case where one feed

is at -36 V and the other feed is at -75 V, it is

recommended to use the resistor values shown in

Table 8 on page 21.

If fuse A fails open, the voltage at the FUSE_L pin

rises to a value of

V

× R8/(R2 + R7 + R8).

in

This voltage is compared internally against the

voltage on pin VBATT multiplied by 57%, which has

a value of

V

× R10/(R4 + R10) × 0.57.

in

With the recommended resistor values (shown in

Table 8 on page 21), the voltage at FUSE_L is

higher than 57% of the voltage at VBATT, and a

fuse failure is detected.

To monitor high-side as well as low-side fuses

requires the addition of three more resistors, as

shown in Figure 8 on page 20. The added

monitoring components are R20, R21, and R22.

Recommended values for these resistors are also

shown in Table 8 on page 21.

Similarly, if fuse B fails open, the voltage at FUSE_L

rises to a value of

80C6000_MA001_01 April 2006

- 19 -

Tsi205 Primary Side Monitor

Datasheet

Figure 8 — Monitor circuit for high and low input fuses

D4

Fuse RA

Fuse RB

D5

Other components are as

shown in Figure 1 on page 1

0 V

(Battery

return)

R5

R20

R22

R2

R1

Tsi205

VDD

VDDO

SHUNT

SEAT

ENABLE

TX_H

TX_L

BUSOFF

FETA

UV

VBATT

SENSE_N

FUSE_H SENSE_OUT

SENSE_IN

FUSE_L

NC

R8

VBG

SENSE_P

POR

C10

C7

R6

R7

VSS

VSSO

BIAS

R21

AUX

-48 V A

-48 V B

D1

D2

C1

Fuse A

Fuse B

MD505E

Recommended component values

The recommended component values for typical

48 V applications are shown in Table 8. (The

component designations in Table 8 refer to Figure 1

on page 1 and Figure 8 on page 20.)

Note: Many of the component values depend on

the details of the application. Adjust the values

where necessary to suit the input voltage range,

input current and other parameters of your

application.

- 20 -

80C6000_MA001_01 April 2006

Datasheet

Tsi205 Primary Side Monitor

Table 8 — Recommended component values for typical applications

Component

Value

Rating

Comments

1

R1 , R2

100 kΩ

100 V

Low side fuse monitor

UV sense. with R9

R3

301 kΩ

R4

301 kΩ

Input voltage measurement and OV sense, with R10

Power input to VDD

R5

6.2 kΩ, 1 W

301 kΩ

R6, R7

R8

Low side fuse monitor

8.66 kΩ

10.5 kΩ

9.33 kΩ

249 kΩ, 0.1%

2.49 kΩ

R9

UV sense, with R3

R10

R11

R12

Input voltage measurement and OV sense, with R4

Current sense. Sets gain of amplifier, with R15

(recommended values give gain of ×20)

R13

75 kΩ

Detects inrush complete, with R14

Adjust values as necessary to suit inrush controller and

MOSFET — refer to Inrush completed detection on

page 18.

R14

301 kΩ

Detects inrush complete, with R13

Adjust values as necessary to suit inrush controller and

MOSFET — refer to Inrush completed detection on

page 18.

R15

47.5 kΩ

10 kΩ

Sets required gain of current amplifier, with R12

R16

R17

1.5 kΩ

To suit optocoupler

R18

To suit card input current

Refer to Current sense resistor on page 17

Transient protection for SENSE_P input

R19

100 kΩ

R20, R22

R21

301 kΩ

3.32 kΩ

100 V

High-side fuse monitor (refer to Figure 8 on page 20)

(refer to Table 7 on page 16)

R23

R24

301 Ω

1 μF

2

C1

10 V

Decoupling capacitor

POR capacitor

C2

47 nF

C3, C4, C5, T1

(refer to Table 7 on page 16)

C6, C7, C9, C10 1000 pF

OP1, OP2

50 V

HMA121 from Fairchild Semiconductor, or equivalent

80C6000_MA001_01 April 2006

- 21 -

Tsi205 Primary Side Monitor

Datasheet

1. R1 to R4, R14, R19, R20, and R22 must be rated to withstand 100 V. Do not use 0603 or smaller.

2. All capacitors are ceramic.

Ordering options

The Tsi205 is available in two different versions,

according to the behaviour under input overvoltage.

The difference between the two devices is

summarized in Table 9.

Table 9 — Tsi205 versions

Auxiliary voltage transmitted to secondary

through PI-Link

Part number

OV behaviour

Tsi205

When an input OV condition is detected, the

Tsi205 does NOT shut down the brick.

8-bit value

Tsi205-A

When an input OV condition is detected, the

Tsi205-A shuts down the brick.

10-bit value

- 22 -

80C6000_MA001_01 April 2006

Datasheet

Tsi205 Primary Side Monitor

Package information

The Tsi205 is packaged in a 32-lead Low Profile

Quad Flat Package (LQFP). The outline is shown in

Figure 9, Figure 10, Figure 11, and Figure 12.

Dimensions are shown in Table 10 on page 25.

Figure 9 — Package outline - top view

Figure 10 — Package outline - side view

80C6000_MA001_01 April 2006

- 23 -

Tsi205 Primary Side Monitor

Datasheet

Figure 11 — Package outline - detail of pin dimensions

θ2

θ1

θ

θ3

Figure 12 — Package outline - cross-section through pin

- 24 -

80C6000_MA001_01 April 2006

Datasheet

Tsi205 Primary Side Monitor

Figure 13 — Notes for package drawings

Table 10 — Package dimensions (mm)

Dimension

Minimum

Maximum

A

—

1.6

A1

A2

b

0.05

1.35

0.18

0.17

0.1

0.15

1.45

0.27

0.23

0.2

b1

c

c1

D

0.09

0.16

1

7 BSC

D1

e

5 BSC

0.5 BSC

7 BSC

E

E1

L

5 BSC

0.45

0.75

L1

R1

R2

S

1 REF

0.08

—

0.2

0.2 REF

(Sheet 1 of 2)

80C6000_MA001_01 April 2006

- 25 -

Tsi205 Primary Side Monitor

Datasheet

Table 10 — Package dimensions (mm) (Continued)

Dimension

Minimum

Maximum

θ

0°

7°

θ1

θ2

θ3

—

11°

13°

(Sheet 2 of 2)

1. BSC (Basic Spacing between Centers) is the theoretical dimension without

tolerances. REF is a reference dimension.

TUNDRA is a registered trademark of Tundra Semiconductor Corporation (Canada, U.S., and U.K.). TUNDRA, the Tundra logo,

Tsi205, and Silicon Behind the Network, are trademarks of Tundra Semiconductor Corporation. All other registered and unregistered

marks (including trademarks, service marks and logos) are the property of their respective owners. The absence of a mark identifier

is not a representation that a particular product name is not a mark.

Published in Canada

This document contains information that is proprietary to Tundra and may be used for non-commercial purposes within your

organization in support of Tundra products. No other use or transmission of all or any part of this document is permitted without written

permission from Tundra, and must include all copyright and other proprietary notices. Use or transmission of all or any part of this

document in violation of any applicable Canadian or other legislation is hereby expressly prohibited.

User obtains no rights in the information or in any product, process, technology or trademark which it includes or describes, and is

expressly prohibited from modifying the information or creating derivative works without the express written consent of Tundra.

Tundra assumes no responsibility for the accuracy or completeness of the information presented, which is subject to change without

notice. Tundra products may contain design defects or errors known as errata which may cause the product to deviate from published

specifications. Current characterized errata are available on request. In no event will Tundra be liable for any direct, indirect, special,

incidental or consequential damages, including lost profits, lost business or lost data, resulting from the use of or reliance upon the

information, whether or not Tundra has been advised of the possibility of such damages. The information contained in this document

does not affect or change Tundra’s product warranties.

Mention of non-Tundra products or services is for information purposes only and constitutes neither an endorsement nor a

recommendation.

As this information will change over time, please ensure you have the most recent version by contacting a member of the Tundra

technical support team, or by checking the Support section of www.tundra.com.

- 26 -

80C6000_MA001_01 April 2006


型号：	TSI205
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Power Management Circuit,
文件：	总26页 (文件大小：207K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TSI205 [IDT]

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