M901-01-644.5313LF [IDT]
Clock Generator, 644.5313MHz, CQCC36, 9 X 9 MM, CERAMIC, LCC-36;
| 型号： | M901-01-644.5313LF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 644.5313MHz, CQCC36, 9 X 9 MM, CERAMIC, LCC-36 时钟 外围集成电路 晶体 |
| 文件： | 总8页 (文件大小：334K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
P r o d u c t D a t a S h e e t
Integrated
Circuit
Systems, Inc.
M901-01
VCSO BASED CLOCK GENERATOR
GENERAL DESCRIPTION
PIN ASSIGNMENT (9 x 9 mm SMT)
The M901-01 is a PLL (Phase Locked Loop) based
clock generator that uses an internal
VCSO (Voltage Controlled SAW
Oscillator) to produce a very low
jitter output clock. The output clock
(e.g., frequencies of 622.08, 311.04,
155.52, or 77.76MHz with the
M901-01-622.0800) is provided from a
M0
M2
M3
M4
M5
VCC
DNC
DNC
DNC
NC
28
29
30
31
32
33
34
35
36
18
17
16
15
14
13
12
11
10
OUT_EN
nFOUT
FOUT
GND
P1
P0
VCC
GND
LVPECL clock output pair. Output frequency accuracy
is assured by phase-locking the VCSO to an external
input reference frequency (e.g., frequencies of 19.44,
38.80, 77.76, or 155.52MHz with the M901-01-622.0800).
The input reference can either be an external crystal,
utilizing the internal crystal oscillator, or a stable
external clock source such as a packaged crystal
oscillator.
M901-01
( T o p V i e w )
FEATURES
◆ Output clock frequency from 62MHz to 700MHz
(Consult factory for VCSO frequency availability)
Figure 1: Pin Assignment
◆ Low jitter 0.5ps rms, typ. (12kHz-20MHz @622.08MHz)
◆ Ideal for OC-48 (STM-16), Gigabit Ethernet clock ref
Example Output Frequency Configurations *
Ref Clock
Freq
VCSO
Freq 1
(MHz)
Output
Freq
◆ Integrated SAW (surface acoustic wave) delay line
◆ XTAL or LVCMOS reference input
◆ LVPECL output
Application
(MHz)
(MHz)
19.44
622.08
622.08
155.52
156.25
OC-12/48
(STM-4/16)
◆ Single 3.3V power supply
◆ Small 9 x 9 mm SMT (surface mount) package
25.00
625.00
10GbE
Table 1: Example Output Frequency Configurations *
Note1: Specify VCSO center frequency at time of order
BLOCK DIAGRAM
RLOOP CLOOP
RPOST
External
Loop Filter
Components
CPOST
CPOST
RLOOP CLOOP
RPOST
M901-01
OP_IN
RIN
nOP_IN
OP_OUT
nOP_OUT
nVC
VC
Phase
Detector
SAW Delay Line
XTAL_1 / REF_IN
XTAL_2
XTAL
OSC
RIN
Loop Filter
Amplifier
Phase
Shifter
VCSO
M Divider
M1=0
FOUT
nFOUT
P Divider
5
2
M5:2, M 0
P1:0
OUT_EN
Figure 2: Block Diagram
Note *: Other frequencies available. See “Ordering Information” on pg. 8.
M901-01 Datasheet Rev 4.0
Revised 30Jul2004
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400
M901-01
Integrated
Circuit
Systems, Inc.
VCSO BASED
C
LOCK
G
ENERATOR
P r o d u c t D a t a S h e e t
PIN DESCRIPTIONS
Number
1, 2, 3, 10, 14, 26 GND
Name
I/O
Ground
Configuration
Description
Power supply ground connections.
4
9
OP_IN
nOP_IN
Input
External loop filter connections. See Figure 4,
External Loop Filter, on pg. 4.
5
8
nOP_OUT
OP_OUT
Output
6
7
nVC
VC
Input
11, 22, 25, 33
VCC
Power
Power supply connection, connect to +3.3V.
P divider (output divider) inputs P1:0.
Internal pull-down resistor LVCMOS/LVTTL. See 4, Pin Selection of P Divider
Using P1:0 Pins, on pg. 2.
P0
P1
12
13
1
Input
FOUT
nFOUT
15
16
Output
No internal terminator
Clock output pair. Differential LVPECL.
Output Enable:
Logic 1 resets M and P dividers and forces
FOUT to LOW and nFOUT to HIGH.
Logic 0 enables the outputs.
LVCMOS/LVTTL.
1
17
OUT_EN
Input
Internal pull-down resistor
18, 20, 21, 23
24
NC
No connection.
External crystal connection. Also accepts
LVCMOS/LVTTL compatible clock source.
XTAL_1 / REF_IN
Input
Input
External crystal connection. Leave unconnected
when driving pin 27 with external clock reference.
27
XTAL_2
28
29
30
31
M0
M2
M3
M4
1
M divider (feedback divider) inputs M5:2, and M0.
See Table 3, Example Pin Selection of M Divider
Using M5:2, M0 Pins, on pg. 2.
Internal pull-down resistor
Input
1
32
M5
Internal pull-up resistor
19, 34, 35, 36
DNC
Do Not Connect.
Table 2: Pin Descriptions
Note1: For typical values of internal pull-down and pull-up resistors, see DC Characteristics on pg. 6.
DEVICE CONFIGURATION TABLES
Note1:
F
= 622.08 MHz (e.g., M901-01-622.0800)
Note2: FVVCCSSOO = 625.00 MHz (e.g., M901-01-625.0000)
Example Pin Selection of M Divider Using M5:2, M0 Pins
Note3: M5 pin has pull-up resister; M4-M2 and M0 have pull-down.
Note4: M1 bit is always 0 (no M1 pin exists).
Input Clock Freq
M5:0 Pin
(MHz) for Common
Settings
VCSO Freqs
Definition
(Pins 32-28)
FVCSO=
F
=
1
VCSO2
Pin Selection of P Divider Using P1:0 Pins
M5 -M2, M0
622.08
625.00
53 4 3 2 14 0
0 0 0 1 0 0
0 0 1 0 0 0
0 1 0 0 0 0
0 1 1 0 0 1
1 0 0 0 0 0
1 1 1 1 0 1
Output Frequency (MHz)
P Divider
Value
P1:0 Settings
Feedback Divider Value “M”
Example when
(Pin 13 and 12)
1
FVCSO = 622.08
P1
0
P0
0
M = 4
M = 8
155.52 156.25
77.76
1
2
4
8
622.08
311.04
155.52
77.76
0
1
1
0
1
1
M = 16
M = 25
M = 32
M = 61
38.80
Table 4: Pin Selection of P Divider Using P1:0 Pins
Note1: FVCSO = 622.08MHz (e.g., M901-01-622.0800)
25.00
19.44
Table 3: Example Pin Selection of M Divider Using M5:2, M0 Pins
M901-01 Datasheet Rev 4.0
2 of 8
Revised 30Jul2004
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400
M901-01
Integrated
Circuit
Systems, Inc.
VCSO BASED
C
LOCK
G
ENERATOR
P r o d u c t D a t a S h e e t
P Divider and Outputs
FUNCTIONAL DESCRIPTION
The M901-01 provides one differential LVPECL output
pair: FOUT, nFOUT. By using the P divider, the output
frequency can be the VCSO center frequency (Fvcso)
or 1/2, 1/4, or 1/8 Fvcso.
The M901-01 is a PLL (Phase Locked Loop) based
clock generator that generates output clocks synchro-
nized to an input reference clock. The M901-01
combines the flexibility of a VCSO (Voltage Controlled
SAW Oscillator) with the stability of a crystal oscillator.
The P1 and P0 pins select the value for the P divider.
The M901-01 uses a high-Q, narrow tuning range
VCSO with a center frequency that is specified at time
of device order (see Ordering Information on pg. 8).
A suitable reference clock frequency, M Divider setting,
and loop filter configuration must be used to assure
proper operation.
See Table 4, Pin Selection of P Divider Using P1:0
Pins, on pg. 2.
When the P divider is included, the complete
relationship for the output frequency is defined as:
M
----
Fvcso = Fref_in ×
P
Input Reference
Configuration of M and P Dividers
An input clock reference is required. It should be a
stable external clock source, such as a packaged
crystal oscillator or distributed system clock. The clock
reference is applied to the REF_IN input pin, which is
internally applied to the non-inverting input of the phase
detector.
The M and P dividers can be set by pin configuration
using the input pins M0, M2 - M5, P0, and P1. The data on
pins M5:2 and M0 and on pins P1:0 is passed directly to the
M and P dividers.
The divider configuration of the M901-01 is reset and
the outputs disabled when the input pin OUT_EN is set
HIGH. MR is set LOW for divider configuration to be
operational.
See External Crystal Specifications in Application
Information on pg. 4.
Internal PLL Operation
The internal PLL is comprised of a first order, type 3
frequency/phase detector, a SAW delay-line based
VCO (VCSO), and a clock feedback divider.
The clock feedback divider (M Divider) divides the
VCSO frequency and drives the inverting input of the
phase detector, which is compared to the input
reference clock. The PLL is “locked” when the phase
detector inputs are aligned in frequency and phase; the
phase detector output controls the VCSO frequency to
achieve this, and the external loop filter provides
stability to this frequency (and phase) control system.
Hence, the VCSO frequency operates at “M” times the
input reference frequency, thus accomplishing
frequency translation. The external loop filter also acts
as a low pass filter that provides attenuation of clock
jitter on the reference input.
The relationship between the VCSO output frequency,
the M divider, and the input reference frequency is
defined as follows:
Fvcso = Fref_in × M
The product of M and the input frequency must be such
that it falls within the “lock” range of the VCSO.
See APR in AC Characteristics on pg. 6.
M901-01 Datasheet Rev 4.0
3 of 8
Revised 30Jul2004
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400
M901-01
Integrated
Circuit
VCSO BASED
P r o d u c t D a t a S h e e t
Due to the differential signal path design, the
C
LOCK
GENERATOR
Systems, Inc.
APPLICATION INFORMATION
implementation requires two identical complementary
RC filters as shown here.
This section includes information on the optional
external crystal and on the external loop filter.
RLOOP CLOOP
RPOST
The subsections on the loop filter provide example
component values and also briefly describe the SAW
PLL simulator tool and additional application
information available at www.icst.com.
CPOST
CPOST
RLOOP CLOOP
nOP_IN OP_OUT
RPOST
External Crystal Specifications
If an external crystal is used with the on-chip crystal
oscillator circuit (XTAL OSC), the external crystal
should have the following general specifications:
OP_IN
nOP_OUT
nVC
VC
4
9
8
5
6
7
Figure 4: External Loop Filter
Crystal Specifications
Parameter
Crystal Type
Min Typ Max Unit
AT-cut quartz
Example External Loop Filter Component Values
PLL
Damping
R loop C loop R post C post
Bandwidth Factor
Fundamental
Mode of Oscillation
Frequency Range
Equivalent Series Resistance
16
40
50
f
MHz
2.0
2.9
6.2
3.6
400Hz
1.2kHz
2.5kHz
9.9kHz
1.5kΩ 4.70µF 50kΩ 3300pF
4.7kΩ 1.00µF 50kΩ 1500pF
10.0kΩ 1.00µF 50kΩ 470pF
39.0kΩ 0.022µF 20kΩ 470pF
0
ESR
Ω
Spurious Response (non-harmonic)
-40 dBc
CL
Load Capacitance,
parallel load resonant
16
32 pF
Table 6: Example External Loop Filter Component Values
0.1
1.0
PLL Simulator Tool Available
P
Drive Level
mW
0
Table 5: Crystal Specifications
A free PC software utility is available on the ICS web
site. The SAW PLL Simulator is a downloadable
application that simulates PLL jitter and wander transfer
characteristics. This enables the user to set appropriate
external loop component values in a given application.
The external crystal will be applied to the XTAL_1 / REF_IN
and XTAL_2 input pins. External crystal load capacitors
are also required.
Recommended External Crystal Configuration
M901-01
M9xx-0x
Refer to the SAW PLL Simulator Software web page at
www.icst.com/products/calculators/m2000filterSWdesc.htm
for additional information.
XTAL_1 / REF_IN
XTAL_2
C1
C2
XTAL OSC
XTAL
SAW PLL Application Notes Available
The ICS web site (www.icst.com) also has application
notes on:
• PCB layout guidelines (including special detailed
instructions for preventing issues such as external
reference crosstalk)
Figure 3: Recommended External Crystal Configuration
XTAL Load Capacitance Specification = 18 pF
C1
C2
=
=
27 pF
33 pF
• Any new special device application details that may
become available
External load capacitors C1 and C2 present a load of 15 pf
to the crystal (they are seen in series by the crystal through
the common ground connection). With the additional of PCB
trace capacitance and M901-01 input capacitance, the total
load to the crystal is about 18 pf.
• Instructions for using PLL simulator software
• Guidelines for PCB fabrication (including recom-
mended PCB footprint, solder mask, and furnace
profile)
External Loop Filter
To provide stable PLL operation, and thereby a low jitter
output clock, the M901-01 requires the use of an
external loop filter. This is provided via the provided
filter pins (see Figure 4).
Refer to the SAW PLL Application Notes web page at
www.icst.com/products/appnotes/SawPllAppNotes.htm
for application notes and any additional product
information that may become available.
M901-01 Datasheet Rev 4.0
4 of 8
Revised 30Jul2004
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400
M901-01
Integrated
Circuit
Systems, Inc.
VCSO BASED
C
LOCK
G
ENERATOR
P r o d u c t D a t a S h e e t
1
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter
Rating
Unit
VI
Inputs
-0.5 to VCC +0.5
V
VO
VCC
TS
Outputs
-0.5 to VCC +0.5
4.6
V
V
Power Supply Voltage
Storage Temperature
-45 to +100
oC
Table 7: Absolute Maximum Ratings
Note1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional operation of product at these conditions
or any conditions beyond those listed in Recommended Conditions of Operation, DC Characteristics, or
AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability
.
RECOMMENDED CONDITIONS OF OPERATION
Symbol Parameter
Min
Typ
Max Unit
3.135
3.3
3.465
VCC
Positive Supply Voltage
V
TA
Ambient Operating Temperature
oC
oC
0
Commercial
Industrial
+70
+85
-40
Table 8: Recommended Conditions of Operation
M901-01 Datasheet Rev 4.0
5 of 8
Revised 30Jul2004
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400
M901-01
Integrated
Circuit
Systems, Inc.
VCSO BASED
C
LOCK
G
ENERATOR
P r o d u c t D a t a S h e e t
ELECTRICAL SPECIFICATIONS
DC Characteristics
Unless stated otherwise, VCC
= 3.3V +5 = ,
%,TA = 0 oC to +70 oC (commercial), TA = -40 oC to +85 oC (industrial), FVCSO 622-675MHz 1
LVPECL outputs terminated with 50Ω to VCC - 2V
Symbol Parameter
Power Supply VCC Positive Supply Voltage
Min
3.135
Typ
3.3
Max Unit Conditions
3.465
V
200
ICC
VIH
Power Supply Current
Input High Voltage
mA
2
LVCMOS /
LVTTL Input
V
+ 0.3 V
cc
REF_IN, OUT_EN, P0, P1,
M0, M2, M3, M4, M5
0.8
VIL
Input Low Voltage
-0.3
V
VCC = VIN
3.456V
=
Inputs with
Pull-down
IIH
IIL
R
Input High Current
Input Low Current
150
µA
µA
kΩ
µA
µA
kΩ
pF
REF_IN, OUT_EN, P0:P1,
M0, M2, M3, M4
-5
51
51
Internal Pull-down Resistor
Input High Current
Input Low Current
pulldown
VCC = 3.456V
IN = 0 V
Inputs with
Pull-up
IIH
IIL
R
5
V
M5
-150
Internal Pull-up Resistor
Input Capacitance
pullup
All Inputs
4
All Inputs
CIN
Differential
Output
VOH
VOL
VP-P
Output High Voltage
V
- 1.4
V
V
- 1.0 V
cc
cc
FOUT, nFOUT
2
Output Low Voltage
V
- 2.0
- 1.7 V
cc
cc
0.4
0.85
Peak to Peak Output Voltage
V
Table 9: DC Characteristics
Note1: For other VCSO center frequencies, contact ICS
Note2: Single-ended measurement.
AC Characteristics
Unless stated otherwise, VCC
=
3.3V +
5
%,TA = 0 oC to +70 oC (commercial), TA = -40 oC to +85 oC (industrial), FVCSO
Ωto VCC - 2V
=
622-675MHz 1
,
LVPECL outputs terminated with 50
Symbol Parameter
Min
62
Typ
Max
700
Unit
MHz
Test Conditions
FOUT
Output Frequency Range
50
FREF_IN Input Frequency
MHz
ppm
APR
VCSO Pull-Range
±100
±150
Φn
Single Side Band
Phase Noise
1kHz Offset
10kHz Offset
100kHz Offset
-87
-100
-123
0.5
dBc/Hz
dBc/Hz
dBc/Hz
ps
@622.08MHz
1.0
60
J(t)
tDC
tR
Jitter (rms)
12kHz to 20MHz
40
50
Output Duty Cycle, High Time
%
FOUT, nFOUT
FOUT, nFOUT
200
200
400
400
550
550
Output Rise Time
Output Fall Time
ps
ps
20% to 80%
20% to 80%
tF
Table 10: AC Characteristics
Note1: For other VCSO center frequencies, contact ICS
M901-01 Datasheet Rev 4.0
6 of 8
Revised 30Jul2004
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400
M901-01
Integrated
Circuit
Systems, Inc.
VCSO BASED
C
LOCK
G
ENERATOR
P r o d u c t D a t a S h e e t
DEVICE PACKAGE - 9 x 9mm CERAMIC LEADLESS CHIP CARRIER
Mechanical Dimensions:
Refer to the SAW PLL application notes web page at
www.icst.com/products/appnotes/SawPllAppNotes.htm
for application notes, including recommended PCB
footprint, solder mask, and furnace profile.
Figure 5: Device Package - 9 x 9mm Ceramic Leadless Chip Carrier
M901-01 Datasheet Rev 4.0
7 of 8
Revised 30Jul2004
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400
P r o d u c t D a t a S h e e t
M901-01
Integrated
Circuit
Systems, Inc.
VCSO BASED
CLOCK
G
ENERATOR
Standard VCSO Output Frequencies (MHz)*
ORDERING INFORMATION
622.0800
625.0000
627.3296
644.5313
666.5143
669.1281
669.3120
669.3266
669.6429
670.8386
672.1600
690.5692
Part Numbering Scheme
Part Number:
M901-01-xxx.xxxx
Device Number
Temperature
0
to +70 o
C
(commercial)
“I-”==- 40 to +85 o
C (industrial)
VCSO Frequency (MHz)
See Table 11, right. Consult ICS for other frequencies.
Table 11: Standard VCSO Output Frequencies
Figure 6: Part Numbering Scheme
Note *: Fout can equal Fvcso divided by: 1 or 4
Consult ICS for the availability of other PLL frequencies.
Example Part Numbers
PLL Frequency (MHz)
Temperature
commercial
industrial
commercial
industrial
commercial
industrial
commercial
industrial
Order Part Number
M901-01- 622.0800
622.08
M901-01
M901-01- 625.0000
M901-01 625.0000
M901-01- 669.3266
M901-01 669.3266
M901-01- 669.6429
M901-01 669.6429
I 622.0800
625.00
I
669.3266
669.6429
I
I
Table 12: Example Part Numbers
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
M901-01 Datasheet Rev 4.0
8 of 8
Revised 30Jul2004
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400
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