M1040-13I167.3316 [IDT]
PLL/Frequency Synthesis Circuit;
| 型号： | M1040-13I167.3316 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PLL/Frequency Synthesis Circuit |
| 文件： | 总12页 (文件大小：430K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
P r e l i m i n a r y I n f o r m a t i o n
Integrated
Circuit
Systems, Inc.
M1040
VCSO BASED CLOCK PLL WITH AUTOSWITCH
GENERAL DESCRIPTION
The M1040 is a VCSO (Voltage Controlled SAW
Oscillator) based clock generator
PIN ASSIGNMENT (9 x 9 mm SMT)
PLL designed for clock protection,
frequency translation and jitter
attenuation in OC-12/48 class optical
networking systems. It features dual
differential inputs with two modes of
input selection: manual and
MR_SEL1
MR_SEL0
REF_ACK
LOL
P_SEL
INIT
nFOUT0
FOUT0
GND
nFOUT1
FOUT1
VCC
28
29
30
31
32
33
18
17
16
15
14
13
12
11
automatic upon clock failure. The clock multiplication
ratios and output divider ratio are pin selectable. This
device provides two outputs. External loop components
allow the tailoring of PLL loop response.
M1040
NBW
VCC
( T o p V i e w )
DNC
DNC
DNC
34
35
36
10
GND
FEATURES
◆ Integrated SAW (surface acoustic wave) delay line;
low phase jitter of < 0.5ps rms, typical (12kHz to
20MHz)
◆ Output frequencies of 62.5 to 175 MHz *; Two differen-
tial LVPECL outputs (CML, LVDS options available)
Figure 1: Pin Assignment
Example I/O Clock Frequency Combinations
Using M1040-11-155.5200
◆ Loss of Lock (LOL) indicator output
◆ Narrow Bandwidth control input (NBW pin);
Initialization (INIT) input overrides NBW at power-up
◆ Dual reference clock inputs support LVDS, LVPECL,
PLL Ratio
Output Clock
Input Reference
Clock (MHz)
LVCMOS, LVTTL
(Pin Selectable)
(MHz)
(Pin Selectable)
◆ AutoSwitch (AUTO pin) - automatic (non-revertive)
reference clock reselection upon clock failure; Hitless
Switching (HS), Phase Build-out (PBO) options enable
SONET (GR-253)/SDH (G.813) MTIE/TDEV compliance
19.44
77.76
155.52
622.08
8
2
1
155.52
or
77.76
◆ Acknowledge pin (REF_ACK pin) indicates the actively
selected reference input
0.25
Table 1: Example I/O Clock Frequency Combinations
* Specify VCSO center frequency at time of order.
◆ Industrial temperature available
◆ Single 3.3V power supply
◆ Small 9 x 9 mm SMT (surface mount) package
SIMPLIFIED BLOCK DIAGRAM
Loop Filter
M1040
NBW
PLL
Phase
MUX
Detector
DIF_REF0
nDIF_REF0
0
R Div
VCSO
DIF_REF1
nDIF_REF1
1
REF_ACK
REF_SEL
M Divider
0
LOL
Phase
1
AUTO
Detector
Auto
Ref Sel
INIT
LOL
FOUT0
nFOUT0
P Divider
(1 or 2)
M / R Divider
LUT
3
FOUT1
MR_SEL2:0
nFOUT1
P_SEL
Figure 2: Simplified Block Diagram
M1040 Datasheet Rev 0.1
Revised 11Nov2003
M1040 VCSO Based Clock PLL with AutoSwitch
Integrated Circuit Systems, Inc. ● Communications Modules ● www.icst.com ● tel (508) 852-5400
M1040
Integrated
Circuit
Systems, Inc.
VCSO BASED
C
LOCK PLL WITH
A
UTO WITCH
S
P r e l i m i n a r y I n f o r m a t i o n
PIN DESCRIPTIONS
Number Name
1, 2, 3, 10, 14, 26 GND
I/O
Ground
Configuration
Description
Power supply ground connections.
4
9
OP_IN
nOP_IN
Input
External loop filter connections. See Figure 5,
External Loop Filter, on pg. 8.
5
8
nOP_OUT
OP_OUT
Output
6
7
nVC
VC
Input
Power
Output
11, 19, 33
VCC
Power supply connection, connect to +3.3V.
FOUT1
nFOUT1
12
13
No internal terminator
No internal terminator
Clock output pair 1. Differential LVPECL.
FOUT0
nFOUT0
15
16
Output
Input
Clock output pair 0. Differential LVPECL.
Power-on Initialization; LVCMOS/LVTTL:
Logic 1 allows device to enter narrow mode if
selected (in addition must have 8 LOL=0 counts)
Logic 0 forced device into wide bandwidth mode.
1
17
18
INIT
Internal pull-UP resistor
Post-PLL , P divider selection. LVCMOS/LVTTL.
See Table 4, P Divider Selector Values
and Frequencies, on pg. 3.
1
P_SEL
Internal pull-down
2
20
21
nDIF_REF1
DIF_REF1
Biased to Vcc/2
Differential LVPECL/ LVDS
Reference
clock input
pair 1.
Input
Input
Input
Differential LVPECL/ LVDS, or single
ended LVCMOS/ LVTTL
1
1
Internal pull-down resistor
Reference clock input selection. LVCMOS/LVTTL.
Logic 1 selects DIF_REF1/nDIF_REF1 inputs
Logic 0 selects DIF_REF0/nDIF_REF0 inputs
22
REF_SEL
Internal pull-down resistor
3
23
24
nDIF_REF0
DIF_REF0
Biased to Vcc/2
Differential LVPECL/ LVDS
Reference
clock input
pair 0.
Differential LVPECL/ LVDS, or single
ended LVCMOS/ LVTTL
1
1
Internal pull-down resistor
Internal pull-down resistor
Automatic/manual reselection mode for clock input:
Logic 1 automatic reselection upon clock failure
(non-revertive)
25
AUTO
Input
Input
Logic 0 manual selection only (using REF_SEL)
27
28
29
MR_SEL2
MR_SEL1
MR_SEL0
M and R divider value selection. LVCMOS/ LVTTL.
See Table 3, M and R Divider Look-Up Tables (LUT)
on pg. 3.
1
Internal pull-UP resistor
Reference Acknowledgement pin for input mux state;
outputs the currently selected reference input pair:
Logic 1 indicates nDIF_REF1, DIF_REF1
30
31
REF_ACK
LOL
Output
Logic 0 indicates nDIF_REF0, DIF_REF0
4
Loss of Lock indicator output.
Logic 1 indicates loss of lock.
Output
Input
Logic 0 indicates locked condition.
Narrow Bandwidth enable. LVCMOS/LVTTL:
Logic 1 - Narrow loop bandwidth, RIN = 2100kΩ.
Logic 0 - Wide bandwidth, RIN = 100kΩ.
Do Not Connect.
1
32
NBW
DNC
Internal pull-UP resistor
34, 35, 36
Table 2: Pin Descriptions
Note 1: For typical values of internal pull-down and pull-up resistors, see DC Characteristics on pg. 10.
Note 2: Biased to Vcc/2, with 50kΩto Vcc and 50kΩto ground. Float if using DIF_REF1 as LVCMOS input. See DC Characteristics on pg. 10.
Note 3: Biased to Vcc/2, with 50kΩto Vcc and 50kΩto ground. Float if using DIF_REF0 as LVCMOS input. See DC Characteristics on pg. 10.
Note 4: See LVCMOS Outputs in DC Characteristics on pg. 10.
M1040 Datasheet Rev 0.1
2 of 12
Revised 11Nov2003
Integrated Circuit Systems, Inc. ● Communications Modules ● www.icst.com ● tel (508) 852-5400
M1040
Integrated
Circuit
Systems, Inc.
VCSO BASED
C
LOCK PLL WITH
A
UTO WITCH
S
P r e l i m i n a r y I n f o r m a t i o n
DETAILED BLOCK DIAGRAM
RLOOP CLOOP
RPOST
External
Loop Filter
Components
CPOST
CPOST
RLOOP CLOOP
nOP_IN OP_OUT
RPOST
OP_IN
nOP_OUT
nVC
VC
M1040
NBW
PLL
Phase
MUX
SAW Delay Line
RIN
Detector
DIF_REF0
0
Phase
Locked
Loop
R
nDIF_REF0
Divider
RIN
DIF_REF1
nDIF_REF1
Loop Filter
Amplifier
Phase
Shifter
1
(PLL)
VCSO
REF_ACK
M Divider
REF_SEL
0
1
LOL
Phase
AUTO
Detector
Auto
Ref Sel
INIT
LOL
FOUT0
nFOUT0
P Divider
3
M
/ R Divider
LUT
MR_SEL2:0
FOUT1
nFOUT1
P_SEL
Figure 3: Detailed Block Diagram
General Guidelines for M and R Divider Selection
General guidelines for M/R divider selection (see
following pages for more detail):
PLL DIVIDER SELECTION TABLES
M and R Divider Look-Up Tables (LUT)
The MR_SEL2:0 pins select the feedback and reference
divider values M and R to enable adjustment of loop
bandwidth and jitter tolerance. The look-up is defined in
• A lower phase detector frequency should be used for
loop timing applications to assure PLL tracking,
especially during GR-253 jitter tolerance testing. The
recommended maximum phase detector frequency
for loop timing mode is 19.44MHz. The LOL pin should
not be used during loop timing mode.
• When LOL is to be used for system health monitoring,
the phase detector frequency should be 5MHz or
greater. Low phase detector frequencies make LOL
overly sensitive, and higher phase detector
frequencies make LOL less sensitive.
Table 3.
M1040 M/R Divider LUT
Phase Det.
Freq. for
Total
MDiv R Div PLL
Fin for
MR_SEL3:0
155.52MHz
155.52MHz
Ratio VCSO (MHz)
VCSO (MHz)
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
8
64
2
1
8
1
8
1
8
8
8
19.44
19.44
77.76
77.76
155.52
155.52
N/A
19.44
2.43
• The preceding guideline also applies when using the
AutoSwitch Mode, since AutoSwitch uses the LOL
output for clock fault detection.
2
77.76
9.72
16
1
2
1
155.52
19.44
N/A
Post-PLL Divider
8
1
Test Mode1
N/A
0.25
The M1040 also features a post-PLL (P) divider for the
output clocks. It divides the VCSO frequency to produce
one of two selectable output frequencies (1/2 or 1/1 of
the VCSO frequency). That selected frequency appears
on both clock output pairs. The P_SEL pin selects the
value for the P divider.
2
8
622.08
77.76
Table 3: M1040 M/R Divider LUT
Note 1: Factory test mode; do not use.
Table 3 provides example Fin and phase detector
frequencies with 155.52MHz VCSO devices
(e.g., M1040-11-155.5200). See “Ordering Information”
on pg. 12.
P_SEL
P Value
OutpMu1t0F40re-1q1u-1e5n5.c52y
(MHz)
1
0
2
1
77.76
155.52
Table 4: P Divider Selector Values and Frequencies
M1040 Datasheet Rev 0.1
3 of 12
Revised 11Nov2003
Integrated Circuit Systems, Inc. ● Communications Modules ● www.icst.com ● tel (508) 852-5400
M1040
Integrated
Circuit
Systems, Inc.
VCSO BASED
C
LOCK PLL WITH
A
UTO WITCH
S
P r e l i m i n a r y I n f o r m a t i o n
Input Reference Clocks
FUNCTIONAL DESCRIPTION
Two clock reference inputs and a selection mux are
provided. Either reference clock input can accept a
differential clock signal (such as LVPECL or LVDS) or
a single-ended clock input (LVCMOS or LVTTL on the
non-inverting input).
The M1040 is a PLL (Phase Locked Loop) based clock
generator that generates two output clocks synchro-
nized to one of two selectable input reference clocks.
An internal high “Q” SAW delay line provides a low jitter
clock output.
A pin-selected look-up table is used to select the PLL
feedback divider (M Div) and reference divider (R Div)
as shown in Table 3 on pg. 3. The look-up table provides
flexibility in both the overall frequency multiplication
ratio (total PLL ratio) and phase detector frequency.
A single-ended reference clock on the unselected
reference input can cause an increase in output
clock jitter. For this reason, differential reference
inputs are preferred; interference from a differential
input on the non-selected input is minimal.
External loop filter component values influence the PLL
bandwidth, which is used to optimize jitter attenuation
characteristics.
Implementation of single-ended input has been facili-
tated by biasing nDIF_REF0 and nDEF_REF1 to Vcc/2, with
50kΩ to Vcc and 50kΩ to ground. Figure 4 shows the
input clock structure and how it is used with either
LVCMOS / LVTTL inputs or a DC- coupled LVPECL
clock.
The device features dual differential inputs with two
input selection modes: manual and automatic upon
clock failure. (The differential inputs are internally
configured for easy single-ended operation.)
LVCMOS/
LVTTL
VCC
MUX
The M1040 also includes: a Loss of Lock (LOL) indicator,
a reference mux state acknowledge pin (REF_ACK), a
Narrow Bandwidth control input pin (NBW pin), and a
Power-on Initialization (INIT) input (which overrides
NBW=0 to facilitate acquisition of phase lock).
Ω
50k
Ω
50k
0
X
VCC
50k
Ω
1
127
Ω
Ω
VCC
VCC
An automatic input reselection feature, or “AutoSwitch”
is also included in the M1040. When the AutoSwitch
mode is enabled, the device will automatically switch to
the other reference clock input when the currently
selected reference clock fails. Reference selection is
non-revertive, meaning that only one reference
reselection will be made each time that AutoSwitch is
re-enabled.
Ω
50k
82
LVPECL
Ω
Ω
Ω
127
50k
82
50k
Ω
REF_SEL
Figure 4: Input Reference Clocks
Differential Inputs
Differential LVPECL inputs are connected to both
reference input pins in the usual manner. The external
load termination resistors shown in Figure 4 (the 127Ω
and 82Ω resistors) will work for both AC and DC
coupled LVPECL reference clock lines. These provide
In addition to the AutoSwitch feature, Hitless Switching
and Phase Build-out options can be ordered with the
device. The Hitless Switching and Phase Build-out
options help assure SONET/SDH MTIE and TDEV
compliance during either a manual or automatic input
reference reselection.
the 50Ω load termination and the V bias voltage.
TT
Hitless Switching (HS) provides a controlled output
clock phase change during a reference clock
reselection. HS is triggered by a Loss of Lock detection
by the PLL.
Single-ended Inputs
Single-ended inputs (LVCMOS or LVTTL) are
connected to the non-inverting reference input pin
(DIF_REF0 or DIF_REF1). The inverting reference input pin
(nDIF_REF0 or nDIF_REF1) must be left unconnected.
In single-ended operation, when the unused inverting
input pin (nDIF_REF0 or nDEF_REF1) is left floating (not
connected), the input will self-bias at VCC/2.
M1040 Datasheet Rev 0.1
4 of 12
Revised 11Nov2003
Integrated Circuit Systems, Inc. ● Communications Modules ● www.icst.com ● tel (508) 852-5400
M1040
Integrated
Circuit
Systems, Inc.
VCSO BASED
C
LOCK PLL WITH
A
UTO WITCH
S
P r e l i m i n a r y I n f o r m a t i o n
PLL Operation
Loss of Lock Indicator Output Pin
The M1040 is a complete clock PLL. It uses a phase
detector and configurable dividers to synchronize the
output of the VCSO with the selected reference clock.
Under normal device operation, when the PLL is locked,
the LOL Phase Detector drives LOL to logic 0. Under
circumstances when the VCSO cannot lock to the input
(as measured by a greater than 4 ns discrepancy
between the feedback and reference clock rising edges
at the LOL Phase Detector) the LOL output goes to logic
1. The LOL pin will return back to logic 0 when the phase
detector error is less than 2 ns. The loss of lock
indicator is a low current LVCMOS output.
The “M” divider divides the VCSO output frequency,
feeding the result into the plus input of the phase
detector. The output of the “R” divider is fed into the
minus input of the phase detector. The phase detector
compares its two inputs. The phase detector output,
filtered externally, causes the VCSO to increase or
decrease in speed as needed to phase- and
Guidelines Using LOL
frequency-lock the VCSO to the reference input.
As described, the LOL pin indicates when the PLL is
out-of-lock with the input reference. The LOL condition
is also used by the AutoSwitch circuit to detect a lost
reference, as described in following sections. LOL is
also used by the Hitless Switching and Phase Build-out
functions (optional device features). To ensure reliable
operation of LOL and guard against false out-of-lock
indications, the following conditions should be met:
• The phase detector frequency should be no less than
5MHz, and preferably it should be 10MHz or greater.
Phase detector frequency is defined by Fin / R.
A higher phase detector frequency will result in lower
phase error and less chance of false triggering the
The value of the M divider directly affects closed loop
bandwidth.
The relationship between the nominal VCSO center
frequency (Fvcso), the M divider, the R divider, and the
input reference frequency (Fin) is:
M
R
---
Fvcso = Fin ×
For the available M divider and R divider look-up table
combinations, Tables
3
and 4 on pg. 3 list the Total PLL
Ratio as well as Fin when using the M1040-11-155.5200.
(See “Ordering Information”, pg. 12.)
LOL phase detector. Refer to Tables
3 and 4 on pg. 3
Due to the narrow tuning range of the VCSO
for phase detector frequency when using the
(+200ppm), appropriate selection of all of the following
are required for the PLL be able to lock: VCSO center
frequency, input frequency, and divider selections.
M1040-11-155.5200.
• The input reference should have an intrinsic jitter of
less than 1 ns pk-pk. If reference jitter is greater than
1 ns pk-pk, the LOL circuit might falsely trigger. Due
to this limitation, the LOL circuit should not be used in
loop timing mode, nor should it be used with a noisy
reference clock. Likewise, the AutoSwitch, Hitless
Switching, or Phase Build-out features should not be
used in loop timing mode or with a noisy reference
clock, since these features depend on LOL.
Post-PLL Divider
The M1040 features a post-PLL (P) divider. By using
the P Divider, the device’s output frequency (Fout) can
be the VCSO center frequency (Fvcso) or 1/2 Fvcso.
The P_SEL pin selects the value for the P divider: logic 1
sets P to 2, logic 0 sets P to 1. (See Table 5 on pg. 6.)
Reference Acknowledgement (REF_ACK) Output
When the P divider is included, the complete relation-
ship for the output frequency (Fout) is defined as:
The REF_ACK (reference acknowledgement) pin outputs
the value of the reference clock input that is routed to
the phase detector. Logic 1 indicates input pair 1
(nDIF_REF1, DIF_REF1); logic 0 indicates input pair 0
(nDIF_REF0, DIF_REF0). The REF_ACK indicator is an
LVCMOS output.
M
R × P
Fvcso
-----------------
Fout =
= Fin ×
-------------------
P
M1040 Datasheet Rev 0.1
5 of 12
Revised 11Nov2003
Integrated Circuit Systems, Inc. ● Communications Modules ● www.icst.com ● tel (508) 852-5400
M1040
Integrated
Circuit
Systems, Inc.
VCSO BASED
C
LOCK PLL WITH
A
UTO WITCH
S
P r e l i m i n a r y I n f o r m a t i o n
REF_ACK output always indicates the reference selection
status and the LOL output always indicates the PLL lock
status.
AutoSwitch (AUTO) Reference Clock Reselection
This device offers an automatic reference clock
reselection feature for switching input reference clocks
upon a reference clock failure. With the AUTO input pin
set to high and the LOL output low, the device is placed
into automatic reselection (AutoSwitch) mode. Once in
AutoSwitch mode, when LOL then goes high (due to a
reference clock fault), the input clock reference is
automatically reselected internally, as indicated by the
state change of the REF_ACK output. Automatic clock
reselection is made only once (it is non-revertive).
Re-arming of automatic mode requires placing the
device into manual selection (Manual Select) mode
(AUTO pin low) before returning to AutoSwitch mode
(AUTO pin high).
A successful automatic reselection is indicated by a
change of state of the REF_ACK output and a momentary
level high of the LOL output (minimum high time is 10
ns).
If an automatic reselection is made to a non-valid
reference clock (one to which the PLL cannot lock),
the REF_ACK output will change state but the LOL
output will remain high.
No further automatic reselection is made; only one
reselection is made each time the AutoSwitch mode is
armed. AutoSwitch mode is re-armed by placing the
device into Manual Select mode (AUTO pin low) and then
into AutoSwitch mode again (AUTO pin high).
Using the AutoSwitch Feature
Following an automatic reselection and prior to
selecting Manual Select mode (AUTO pin low), the
REF_SEL pin has no control of reference selection.
To prevent an unintential reference reselection,
AutoSwitch mode must not be re-enabled until the
desired state of the REF_SEL pin is set and the LOL output
is low. It is recommended to delay the re-arming of
AutoSwitch mode, following an automatic reselection,
to ensure the PLL is fully locked on the new reference.
In most system configurations, where loop bandwidth is
in the range of 100-1000 Hz and damping factor below
10, a delay of 500 ms should be sufficient. Until the PLL
is fully locked intermittent LOL pulses may occur.
See alsoTable 5, Example AutoSwitch Sequence.
In application, the system is powered up with the device
in Manual Select mode (AUTO pin is set low), allowing
sufficient time for the reference clock and device PLL to
settle. The REF_SEL input selects the reference clock to
be used in Manual Select mode and the initial reference
clock used in AutoSwitch mode. The REF_SEL input state
must be maintained when switching to AutoSwitch
mode (AUTO pin high) and must still be maintained until a
reference fault occurs.
Once a reference fault occurs, the LOL output goes high
and the input reference is automatically reselected. The
Example AutoSwitch Sequence
0 = Low; 1 = High. Example with REF_SEL initially set to 0 (i.e., DIF_REF0 selected)
Selected
Clock Input
REF_SEL
Input
REF_ACK AUTO LOL Conditions
Output Input Output
Initialization
0
0
0
0
0
0
0
0
1
-0-
0
DIF_REF0
DIF_REF0
DIF_REF0
Device power-up. Manual Select mode. DIF_REF0 input selected reference, not yet locked to.
LOL to 0: Device locked to reference (may get intermittent LOL pulses until fully locked).
-1-
AUTO set to 1: Device placed in AutoSwitch mode (with DIF_REF0 as initial reference clock).
Operation & Activation
0
0
1
0
DIF_REF0
Normal operation with AutoSwitch mode armed, with DIF_REF0 as initial reference clock.
DIF_REF0
0
0
0
-1-
1
1
-1-
1
LOL to 1: Clock fault on DIF_REF0, loss of lock indicated by LOL pin, ...
... and immediate automatic reselection to DIF_REF1 (indicated by REF_ACK pin).
-DIF_REF1-
0
1
1
-0-
DIF_REF1
LOL to 0: Device locks to DIF_REF1 (assuming valid clock on DIF_REF1).
Re-initialization
-1-
1
1
1
1
1
0
0
0
DIF_REF1
DIF_REF1
DIF_REF1
REF_SEL set to 1: Prepares for Manual Selection of DIF_REF1 before then re-arming AutoSwitch.
-0-
-1-
AUTO set to 0: Manual Select mode entered briefly, manually selecting DIF_REF1 as reference.
1
AUTO set to 1: Device is placed in AutoSwitch mode (delay recommended to ensure device fully
locked), re-initializing AutoSwitch with DIF_REF1 now specified as the initial reference clock.
Table 5: Example AutoSwitch Sequence
M1040 Datasheet Rev 0.1
6 of 12
Revised 11Nov2003
Integrated Circuit Systems, Inc. ● Communications Modules ● www.icst.com ● tel (508) 852-5400
M1040
Integrated
Circuit
Systems, Inc.
VCSO BASED
C
LOCK PLL WITH
A
UTO WITCH
S
P r e l i m i n a r y I n f o r m a t i o n
HS/PBO Triggers
Optional Hitless Switching and Phase Build-out
The HS function (or the combined HS/PBO function)
is armed after the device locks to the input clock refer-
ence. Once armed, HS is triggered by the occurance of
a Loss of Lock condition. This would typically occur as a
consequence of a clock reference failure, a clock failure
upstream to the M1040, or a M1040 clock reference
mux reselection.
The M1040 is available with a Hitless Switching feature
that is enabled during device manufacturing.
In addition, a Phase Build-out feature is also offered.
These features are offered as device options and are
specified by device order code. Refer to Section ,
“Ordering Information” on pg. 12.
The Hitless Switching feature (with or without Phase
Build-out) is designed for applications where switching
occurs between two stable system reference clocks. It
should not be used in loop timing applications, or when
reference clock jitter is greater than 1 ns pk-pk. Hitless
Switching is triggered by the LOL circuit, which is
activated by a 4 ns phase transient. This magnitude of
phase transient can generated by the CDR (Clock &
Data Recovery unit) in loop timing mode, especially
during a system jitter tolerance test. It can also be
generated by some types of Stratum clock DPLLs
(digital PLL), especially those that do not include a post
de-jitter APLL (analog PLL).
When pin AUTO = 1 (automatic reference
reselection mode) HS is used in conjunction with
input reselection. When AUTO = 0 (manual mode),
HS will still occur upon an input phase transient,
however the clock input is not reselected (this
enables hitless switching when using an external
MUX for clock selection).
HS/PBO Operation
Once triggered, the following HS/PBO sequence
occurs:
1.The HS function disables the PLL Phase Detector
and puts the device into NBW (narrow bandwidth)
mode. The internal resistor Rin is changed to
2100kΩ. See the Narrow Loop Bandwidth Control
Pin (NBW Pin) on pg. 7.
When the Hitless Switching feature is enabled, it is
always triggered by LOL, whether in AutoSwitch mode
(AUTO pin high) or Select mode (AUTO pin low). For
example, in Manual mode, the Hitless Switching feature
operates when LOL goes high even if there is no
reselection of the input mux. This enables the use of an
upstream clock mux (such as on the host card), while
still providing MTIE compliance when readjusting to the
resultant phase change.
2.If included, the PBO function adds to (builds out) the
phase in the clock feedback path (in VCSO clock
cycle increments) to align the feedback clock with
the (new) reference clock input phase.
3.The PLL Phase Detector is enabled, allowing the
PLL to re-lock.
When the M1040 is operating in wide bandwidth mode
(NBW=0), the optional Hitless Switching function puts the
device into narrow bandwidth mode when activated.
This allows the PLL to lock the new input clock phase
gradually. With proper configuration of the external loop
filter, the output clock complies with MTIE and TDEV
specifications for GR-253 (SONET) and ITU G.813
(SDH) during input reference clock changes.
4.Once the PLL Phase Detector feedback and input
clocks are locked to within 2 ns for eight consecutive
cycles, a timer (WBW timer) for resuming wide
bandwidth (in 175 ns) is started.
5.When the WBW timer times out, the device reverts
to wide loop bandwidth mode (i.e., Rin is returned to
100kΩ) and the HS/PBO function is re-armed.
Narrow Loop Bandwidth Control Pin (NBW Pin)
The optional proprietary Phase Build-out (PBO)
A Narrow Loop Bandwidth control pin (NBW pin) is
included to adjust the PLL loop bandwidth. In wide
bandwidth mode (NBW=0), the internal resistor Rin is
100kΩ. With the NBW pin asserted, the internal resistor
Rin is changed to 2100kΩ. This lowers the loop
bandwidth by a factor of about 21 (approximately 2100 /
100) and lowers the damping factor by a factor of about
4.6 (the square root of 21), assuming the same loop
filter components.
function enables the PLL to absorb most of the phase
change of the input clock. The PBO function selects a
new VCSO clock edge for the PLL Phase Detector
feedback clock, selecting the edge closest in phase to
the new input clock phase. This reduces re-lock time,
the generation of wander, and extra output clock cycles.
The Hitless Switching and Phase Build-out functions
are triggered by the LOL circuit. For proper operation,
a low phase detector frequency must be avoided. See
Section , “Guidelines Using LOL” on pg. 5 for
information regarding the phase detector frequency.
M1040 Datasheet Rev 0.1
7 of 12
Revised 11Nov2003
Integrated Circuit Systems, Inc. ● Communications Modules ● www.icst.com ● tel (508) 852-5400
M1040
Integrated
Circuit
Systems, Inc.
VCSO BASED
C
LOCK PLL WITH
A
UTO WITCH
S
P r e l i m i n a r y I n f o r m a t i o n
Because of the differential signal path design, the
implementation consists of two identical
complementary RC filters as shown in
Figure 5.
Power-Up Initialization Function (INIT Pin)
The initialization function provides a short-term override
of the narrow bandwidth mode when the device is
powered up in order to facilitate phase locking.
RLOOP CLOOP
RPOST
When INIT is set to logic 1, initialization is enabled. With
NBW set to logic 1 (narrow bandwidth mode), the
initialization function puts the PLL into wide bandwidth
mode until eight consecutive phase detector cycles
occur without a single LOL event. Once the eight valid
PLL locked states have occurred, the PLL bandwidth is
automatically reduced to narrow bandwidth mode.
CPOST
CPOST
RLOOP CLOOP
nOP_IN OP_OUT
RPOST
OP_IN
nOP_OUT
nVC
VC
When INIT is logic 0, the device is forced into wide
4
9
8
5
6
7
bandwidth mode unconditionally.
Figure 5: External Loop Filter
PLL bandwidth is affected by the total “M” (feedback
External Loop Filter
divider) value, loop filter component values, and other
device parameters. See Table 6, Example External
Loop Filter Component Values, below.
The M1040 requires the use of an external loop filter
components. These are connected to the provided filter
pins (see Figure 5).
PLL Simulator Tool Available
A free PC software utility is available on the ICS website
(www.icst.com). The M2000 Timing Modules PLL
Simulator is a downloadable application that simulates
PLL jitter and wander transfer characteristics. This
enables the user to set appropriate external loop
component values in a given application.
For guidance on device or loop filter implementa-
tion, contact CMBU (Commercial Business Unit)
Product Applications at (508) 852-5400.
1
Example External Loop Filter Component Values
for M1040-yz-155.5200
VCSO Parameters: K
= 200kHz/V, R = 100k
Ω
(pin NBW = 0), VCSO Bandwidth = 700kHz.
Example External Loop Filter Comp. Values Nominal Performance Using These Values
VCO
IN
Device Configuration
MR_SEL2:0 MDiv NBW
FREF
FVCSO
RLOOP
CLOOP
RPOST
CPOST
PLL Loop Damping Passband
Bandwidth
315Hz
Factor Peaking(dB)
(MHz)
(MHz)
19.44 2
77.76 3
77.76 2
155.52 3
155.52 2
155.52
155.52
155.52
155.52
155.52
0 0 0
0 1 0
8
2
0
0
0
0
0
5.4
6.2
3.1
6.0
3.0
0.07
0.05
0.20
0.05
0.20
6.8kΩ
3.9kΩ
10µF
10µF
82kΩ
33kΩ
82kΩ
47kΩ
82kΩ
1000pF
1000pF
1000pF
470pF
715Hz
0 1 1 16
12kΩ 2.2µF
275Hz
1 0 0
1 0 1
1
8
2.7kΩ
5.6kΩ
10µF
4.7µF
980Hz
1000pF
260Hz
Table 6: Example External Loop Filter Component Values
Note 1: KVCO , VCSO Bandwidth, M Divider Value, and External Loop Filter Component Values determine Loop Bandwidth, Damping Factor,
and Passband Peaking. For PLL Simulator software, go to www.icst.com.
Note 2: Optimal for system clock filtering.
Note 3: Optimal for loop timing mode (LOL or Hitless Switching should not be used).
M1040 Datasheet Rev 0.1
8 of 12
Revised 11Nov2003
Integrated Circuit Systems, Inc. ● Communications Modules ● www.icst.com ● tel (508) 852-5400
M1040
Integrated
Circuit
Systems, Inc.
VCSO BASED
C
LOCK PLL WITH
A
UTO WITCH
S
P r e l i m i n a r y I n f o r m a t i o n
1
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter
Rating
Unit
VI
Inputs
-0.5 to VCC +0.5
-0.5 to VCC +0.5
4.6
V
VO
VCC
TS
Outputs
V
V
Power Supply Voltage
Storage Temperature
-45 to +100
oC
Table 7: Absolute Maximum Ratings
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional operation of product at these conditions
or any conditions beyond those listed in Recommended Conditions of Operation, DC Characteristics, or
AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability
.
RECOMMENDED CONDITIONS OF OPERATION
Symbol Parameter
Min
Typ
Max Unit
3.135
3.3
3.465
VCC
Positive Supply Voltage
V
TA
Ambient Operating Temperature
oC
oC
0
Commercial
Industrial
+70
+85
-40
Table 8: Recommended Conditions of Operation
M1040 Datasheet Rev 0.1
9 of 12
Revised 11Nov2003
Integrated Circuit Systems, Inc. ● Communications Modules ● www.icst.com ● tel (508) 852-5400
M1040
Integrated
Circuit
Systems, Inc.
VCSO BASED
C
LOCK PLL WITH
A
UTO WITCH
S
P r e l i m i n a r y I n f o r m a t i o n
ELECTRICAL SPECIFICATIONS
DC Characteristics
Unless stated otherwise, VCC
= 3.3V +5 = 150-175MHz,
%,TA = 0 oC to +70 oC (commercial), TA = -40 oC to +85 oC (industrial), FVCSO = FOUT
LVPECL outputs terminated with 50Ω to VCC - 2V
Symbol Parameter
Power Supply VCC Positive Supply Voltage
Min
3.135
Typ
3.3
Max Unit Conditions
3.465
V
175
225
ICC
VP-P
VCMR
CIN
IIH
Power Supply Current
mA
V
0.15
0.5
All
Differential
Inputs
Peak to Peak Input Voltage
Common Mode Input
DIF_REF0, nDIF_REF0,
DIF_REF1, nDIF_REF1
V
- .85
V
cc
4
Input Capacitance
pF
VCC = VIN
3.456V
=
Differential
Inputs with
Pull-down
Input High Current (Pull-down)
Input Low Current (Pull-down)
Internal Pull-down Resistance
Input High Current (Biased)
Input Low Current (Biased)
150 µA
µA
DIF_REF0, DIF_REF1
IIL
-5
50
R
kΩ
pulldown
VIN
0 to 3.456V
=
150
Differential
Inputs
IIH
IIL
µA
µA
nDIF_REF0, nDIF_REF1
-150
Biased to
VCC/2
See Figure 4
R
Biased to Vcc/2
bias
2
All LVCMOS VIH
/ LVTTL
Input High Voltage
Input Low Voltage
V
+ 0.3 V
cc
AUTO, REF_SEL,, P_SEL,
MR_SEL2, MR_SEL1,
MR_SEL0, INIT, NBW
0.8
4
VIL
-0.3
V
Inputs
CIN
Input Capacitance
Input High Current (Pull-down)
pF
VCC = VIN
3.456V
=
LVCMOS /
LVTTL
IIH
150 µA
AUTO, REF_SEL, P_SEL
IIL
R
Input Low Current (Pull-down)
Internal Pull-down Resistance
Input High Current (Pull-UP)
-5
µA
kΩ
Inputs with
Pull-down
LVCMOS /
LVTTL
50
50
pulldown
VCC = 3.456V
IN = 0 V
IIH
5
µA
V
MR_SEL2, MR_SEL1,
MR_SEL0, INIT, NBW
IIL
R
Input Low Current (Pull-UP)
Internal Pull-UP Resistance
Output High Voltage
-150
µA
kΩ
Inputs with
Pull-UP
pullup
Differential
Outputs
VOH
VOL
VP-P
VOH
V
V
- 1.4
- 2.0
V
V
- 1.0 V
cc
cc
FOUT1, nFOUT1
FOUT0, nFOUT0
Output Low Voltage
- 1.7 V
cc
cc
1
0.4
0.85
VCC
0.4
Peak to Peak Output Voltage
Output High Voltage
V
V
V
2.4
IOH= 1mA
IOL= 1mA
LVCMOS
Outputs
LOL, REF_ACK
GND
VOL
Output Low Voltage
Table 9: DC Characteristics
Note 1: Single-ended measurement. See Figure 6, Input and Output Rise and Fall Time, on pg. 11.
M1040 Datasheet Rev 0.1
10 of 12
Revised 11Nov2003
Integrated Circuit Systems, Inc. ● Communications Modules ● www.icst.com ● tel (508) 852-5400
M1040
Integrated
Circuit
Systems, Inc.
VCSO BASED
C
LOCK PLL WITH
A
UTO WITCH
S
P r e l i m i n a r y I n f o r m a t i o n
ELECTRICAL SPECIFICATIONS (CONTINUED)
AC Characteristics
Unless stated otherwise, VCC
=
3.3V +
5
%,TA = 0 oC to +70 oC (commercial), TA = -40 oC to +85 oC (industrial), FVCSO = FOUT
= 150-175MHz,
LVPECL outputs terminated with 50
Ω to VCC - 2V
Symbol Parameter
Min
Typ
Max Unit Conditions
DIF_REF0, nDIF_REF0,
DIF_REF1, nDIF_REF1
15
700
175
FIN
Input Frequency
MHz
MHz
FOUT0, nFOUT0, FOUT1, nFOUT1
62.5
FOUT
APR
KVCO
Output Frequency
Commercial
Industrial
Absolute Pull-Range
of VCSO
±120
±50
±200
±150
200
ppm
ppm
VCO Gain
kHz/V
Wide Bandwidth
100
2100
700
kΩ
kΩ
kHz
PLL Loop
Constants
RIN
Internal Loop Resistor
1
Narrow Bandwidth
BWVCSO VCSO Bandwidth
Single Side Band
1kHz Offset
10kHz Offset
100kHz Offset
-72
-94
dBc/Hz
dBc/Hz
dBc/Hz
Fin=19.44_MHz
Tot. PLL ratio =
8. See pg. 3
Φn
Phase Noise
@155.52MHz
PhaseNoise
and Jitter
-123
Jitter (rms)
@155.52MHz
0.4
50
0.6
55
J(t)
12kHz to 20MHz
ps
2
45
odc
tR
Output Duty Cycle
%
2
Output Rise Time for
FOUT0, nFOUT0, FOUT1, nFOUT
350
450
550
ps
20% to 80%
20% to 80%
1
2
Output Fall Time for
FOUT0, nFOUT0, FOUT1, nFOUT
350
450
550
tF
ps
1
Table 10: AC Characteristics
Note 1: Parameters needed for PLL Simulator software; see Table 6, Example External Loop Filter Component Values, on pg. 8.
Note 2: See Parameter Measurement Information on pg. 11.
PARAMETER MEASUREMENT INFORMATION
Input and Output Rise and Fall Time
Output Duty Cycle
nFOUT
80%
80%
VP-P
20%
t
F
20%
Clock Inputs
and Outputs
FOUT
t
R
tPW
t
Figure 6: Input and Output Rise and Fall Time
PW
odc =
(Output Pulse Width)
t
PERIOD
Differential Input Level
tPERIOD
V
- 0.85
CC
Figure 8: Output Duty Cycle
nDIF_CLK
V
V
Cross Points
P-P
CMR
DIF_CLK
+ 0.5
Figure 7: Differential Input Level
M1040 Datasheet Rev 0.1
11 of 12
Revised 11Nov2003
Integrated Circuit Systems, Inc. ● Communications Modules ● www.icst.com ● tel (508) 852-5400
P r e l i m i n a r y I n f o r m a t i o n
VCSO BASED
M1040
Integrated
Circuit
Systems, Inc.
CLOCK PLL WITH
A
UTO WITCH
S
DEVICE PACKAGE - 9 x 9mm CERAMIC LEADLESS CHIP CARRIER
Mechanical Dimensions:
Figure 9: Device Package - 9 x 9mm Ceramic Leadless Chip Carrier
Standard VCSO Output Frequencies (MHz)*
ORDERING INFORMATION
155.5200
156.2500
156.8324
161.1328
166.6286
167.2820
167.3280
167.3316
167.7097
168.0400
172.6423
173.3708
Part Numbering Scheme
Part Number:
M1040-1z-xxx.xxxx
Output type
1 = LVPECL
(For CML or LVDS clock output, consult factory)
Hitless Switching / Phase Build-out Options
1 = none
2 = Hitless Switching
Table 11: Standard VCSO Output Frequencies
3 = Hitless Switching with Phase Build-out
Temperature
0
to +70 o
C
(commercial)
“I-”==- 40 to +85 o
C (industrial)
PLL Frequency (MHz)
See Table 11, right. Consult ICS for other frequencies.
Figure 10: Part Numbering Scheme
*
Fout can equal Fvcso divided by: 1 or 2
Consult ICS for the availability of other VCSO frequencies.
Example Part Numbers
VCSO Frequency (MHz)
Temperature
commercial
industrial
commercial
industrial
Order Part Number (Examples)
M1040-11-155.5200
155.52
M1040-11
M1040-11-156.2500
M1040-11 156.2500
I155.5200
156.25
I
Table 12: Example Part Numbers
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
M1040 Datasheet Rev 0.1
12 of 12
Revised 11Nov2003
Integrated Circuit Systems, Inc. ● Communications Modules ● www.icst.com ● tel (508) 852-5400
相关型号：
©2020 ICPDF网 联系我们和版权申明