IDT82V2608BB [IDT]
INVERSE MULTIPLEXING FOR ATM; ATM反向多路复用
| 型号： | IDT82V2608BB |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | INVERSE MULTIPLEXING FOR ATM |
| 文件： | 总98页 (文件大小：1077K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INVERSE MULTIPLEXING FOR ATM
IDT82V2608
Version - 4
December 4, 2006
6024 Silver Creek Valley Road, San Jose, CA 95138
Telephone: (800) 345-7015 • TWX: 910-338-2070 • FAX: (408) 284-2775
Printed in U.S.A.
© 2006 Integrated Device Technology, Inc.
DISCLAIMER
Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance
and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The
Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent, patent rights or other rights, of Integrated Device Technology, Inc.
LIFE SUPPORT POLICY
Integrated Device Technology's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to
such intended use is executed between the manufacturer and an officer of IDT.
1. Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform,
when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any components of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device
or system, or to affect its safety or effectiveness.
Table of Contents
TABLE OF CONTENTS ........................................................................................................................................................... 3
LIST OF TABLES .................................................................................................................................................................... 6
LIST OF FIGURES ................................................................................................................................................................... 8
FEATURES.............................................................................................................................................................................. 9
APPLICATIONS....................................................................................................................................................................... 9
STANDARDS COMPLIANT .................................................................................................................................................... 9
DESCRIPTION......................................................................................................................................................................... 9
FUNCTIONAL BLOCK DIAGRAM........................................................................................................................................ 10
1
2
3
PIN ASSIGNMENT ........................................................................................................................................................ 11
PIN DESCRIPTION ....................................................................................................................................................... 12
INTERFACE .................................................................................................................................................................. 18
3.1
UTOPIA INTERFACE ....................................................................................................................................... 18
3.1.1 Utopia Loopback Function ................................................................................................................... 18
LINE INTERFACE ............................................................................................................................................ 19
3.2.1 Line Interface Work Modes .................................................................................................................. 19
3.2.1.1 Mode0 .................................................................................................................................. 20
3.2.1.2 Mode1~Mode4 ..................................................................................................................... 20
3.2.1.3 Mode5~Mode6 ..................................................................................................................... 22
3.2.1.4 Mode7~Mode10 ................................................................................................................... 22
3.2.1.5 Mode11 ................................................................................................................................ 22
3.2.1.6 Mode12~Mode13 ................................................................................................................. 22
3.2.1.7 Mode14~Mode15 ................................................................................................................. 23
3.2.2 Line Interface Timing Clock Modes...................................................................................................... 23
3.2.3 Line Interface Loopback Function........................................................................................................ 23
EXTERNAL MICROPROCESSOR INTERFACE ............................................................................................. 24
3.3.1 External Microprocessor Interface Selection........................................................................................ 24
3.3.2 Command FIFOs.................................................................................................................................. 24
3.3.3 Registers.............................................................................................................................................. 24
3.3.4 Register Map........................................................................................................................................ 24
3.3.5 Register Description............................................................................................................................. 25
3.3.6 Procedure of Loading Software and Sending Commands................................................................... 27
SRAM INTERFACE .......................................................................................................................................... 29
3.2
3.3
3.4
4
IMA AND UNI FUNCTIONS .......................................................................................................................................... 30
4.1
IMA MODE ....................................................................................................................................................... 30
4.1.1 IMA Frame ........................................................................................................................................... 30
4.1.2 TRL (Timing Reference Link)............................................................................................................... 30
4.1.3 Stuffing Mode....................................................................................................................................... 30
Table of Contents
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December 4, 2006
IDT82V2608
Inverse Multiplexing for ATM
4.1.4 Link Backup.......................................................................................................................................... 30
UNI MODE ....................................................................................................................................................... 30
4.2
5
6
PROGRAMMING INFORMATION FOR IMAOS08 ....................................................................................................... 31
5.1
COMMAND TYPES .......................................................................................................................................... 31
5.1.1 Command Message............................................................................................................................. 31
5.1.2 Command Reply Message................................................................................................................... 31
5.1.3 Alarm Message .................................................................................................................................... 31
COMMAND ENCODING .................................................................................................................................. 32
COMMAND DESCRIPTION ............................................................................................................................. 33
5.2
5.3
IMA OPERATION .......................................................................................................................................................... 69
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
IMA INITIALIZATION ........................................................................................................................................ 69
CONFIGURE A GROUP .................................................................................................................................. 69
START UP A GROUP ...................................................................................................................................... 70
INHIBIT A GROUP/NOT INHIBIT A GROUP ................................................................................................... 70
ADD LINKS TO A GROUP THAT IS IN OPERATIONAL STATE .................................................................... 70
DELETE LINKS ................................................................................................................................................ 70
DEACTIVATE AND RECOVER LINKS ............................................................................................................ 70
RESTART A GROUP ....................................................................................................................................... 70
DELETE A GROUP .......................................................................................................................................... 70
7
8
PMON (PERFORMANCE MONITORING) .................................................................................................................... 71
IMAOS08_SLAVE ......................................................................................................................................................... 73
8.1
GROUP AUTO DETECT .................................................................................................................................. 73
8.1.1 Master Side.......................................................................................................................................... 73
8.1.2 Slave Side............................................................................................................................................ 73
PROGRAMMING INFORMATION FOR IMAOS08_SLAVE ............................................................................ 73
8.2.1 Command types................................................................................................................................... 73
8.2.2 Command Encoding............................................................................................................................. 73
8.2.3 Command Description.......................................................................................................................... 73
8.2
9
JTAG TEST ACCESS PORT ........................................................................................................................................ 80
9.1
9.2
TAP BUS SIGNALS ......................................................................................................................................... 80
INSTRUCTIONS .............................................................................................................................................. 80
10 PHYSICAL AND ELECTRICAL CHARACTERISTICS ............................................................................................... 81
10.1 ABSOLUTE MAXIMUM RATINGS ................................................................................................................... 81
10.2 D.C. CHARACTERISTICS ............................................................................................................................... 81
10.3 A.C. CHARACTERISTICS ............................................................................................................................... 82
10.3.1 Output Loading..................................................................................................................................... 82
10.3.2 System Clock and RST Signal Timing ................................................................................................. 82
10.3.3 Utopia Interface Timing........................................................................................................................ 83
10.3.4 Line Interface Timing............................................................................................................................ 84
10.3.5 Microprocessor Interface Timing ......................................................................................................... 85
10.3.5.1 Interface with Motorola CPU (MPM =0) ............................................................................... 85
10.3.5.2 Interface with Intel CPU (MPM =1)....................................................................................... 87
Table of Contents
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IDT82V2608
Inverse Multiplexing for ATM
10.3.6 SRAM Interface Timing........................................................................................................................ 89
10.3.6.1 Write Cycle Specification...................................................................................................... 89
10.3.6.2 Read Cycle Specification ..................................................................................................... 90
GLOSSARY ........................................................................................................................................................................... 91
INDEX .................................................................................................................................................................................... 95
ORDERING INFORMATION.................................................................................................................................................. 98
Table of Contents
5
December 4, 2006
List of Tables
Table-1
Table-2
Table-3
Table-4
Table-5
Table-6
Table-7
Table-8
Pin Description............................................................................................................................................. 12
Data Rates of Different Modes..................................................................................................................... 20
Pins Used in Multi-Rate Multiplex Mode ...................................................................................................... 22
Register Map................................................................................................................................................ 24
Input FIFO Data Length Register (INPUT_FIFO_LENGTH_REG).............................................................. 25
Output FIFO Data Length Register (OUTPUT_FIFO_LENGTH_REG) ....................................................... 25
Output FIFO Data Register (OUTPUT_FIFO_DATA_REG) ........................................................................ 25
Input FIFO Data Register (INPUT_FIFO_DATA_REG)............................................................................... 25
FIFO Interrupt Enable Register (FIFO_INT_ENABLE_REG) ...................................................................... 26
FIFO Interrupt Status Register (FIFO_STATE_REG).................................................................................. 26
FIFO Interrupt Reset Register (FIFO_INT_RESET_REG) .......................................................................... 26
Output FIFO Internal State Register (OUTPUT_FIFO_INTERNAL_STATE_REG)..................................... 26
Input FIFO Internal State Register (INPUT_FIFO_INTERNAL_STATE_REG) ........................................... 27
Maximum Delay Tolerance Value for Different SRAM Size in T1 Unchannelized Mode............................. 29
Maximum Delay Tolerance Value for Different SRAM Size in E1 Unchannelized Mode............................. 29
Command Encoding .................................................................................................................................... 32
ConfigDev Command (Encoding: 01H)........................................................................................................ 33
ConfigUtopiaIF Command (Encoding: 03H) ................................................................................................ 35
ConfigLoopMode Command (Encoding: 04H)............................................................................................. 36
ConfigGroupPara Command (Encoding: 05H) ............................................................................................ 37
ConfigGroupInterFace Command (Encoding: 06H)..................................................................................... 39
ConfigGroupWorkMode Command (Encoding: 07H)................................................................................... 40
ConfigGSMTimers Command (Encoding: 08H)........................................................................................... 41
ConfigTRLLink Command (Encoding: 09H)................................................................................................. 42
ConfigIFSMPara Command (Encoding: 0AH) ............................................................................................. 43
AddTxLink Command (Encoding: 0BH)....................................................................................................... 44
AddRxLink Command (Encoding: 0CH) ...................................................................................................... 46
ConfigUNILink Command (Encoding: 0DH)................................................................................................. 47
StartGroup Command (Encoding: 0EH) ...................................................................................................... 48
StartLASR Command (Encoding: 0FH) ....................................................................................................... 49
InhibitGrp Command (Encoding: 10H)......................................................................................................... 50
NotInhibitGrp Command (Encoding: 11H) ................................................................................................... 51
RestartGrp Command (Encoding: 12H)....................................................................................................... 52
DeleteGrp Command (Encoding: 13H)........................................................................................................ 53
RecoverLink Command (Encoding: 14H) .................................................................................................... 54
DeleteLink Command (Encoding: 15H) ....................................................................................................... 55
DeactLink Command (Encoding: 16H) ........................................................................................................ 56
GetGroupState Command (Encoding: 17H) ................................................................................................ 57
GetGroupDelayInfo Command (Encoding: 18H) ......................................................................................... 58
GetLinkState Command (Encoding: 19H).................................................................................................... 59
GetGrpPerf Command (Encoding: 1AH)...................................................................................................... 60
Table-9
Table-10
Table-11
Table-12
Table-13
Table-14
Table-15
Table-16
Table-17
Table-18
Table-19
Table-20
Table-21
Table-22
Table-23
Table-24
Table-25
Table-26
Table-27
Table-28
Table-29
Table-30
Table-31
Table-32
Table-33
Table-34
Table-35
Table-36
Table-37
Table-38
Table-39
Table-40
Table-41
List of Tables
6
December 4, 2006
IDT82V2608
Inverse Multiplexing for ATM
Table-42
Table-43
Table-44
Table-45
Table-46
Table-47
Table-48
Table-49
Table-50
Table-51
Table-52
Table-53
Table-54
Table-55
Table-56
Table-57
Table-58
Table-59
Table-60
Table-61
Table-62
Table-63
Table-64
Table-65
Table-66
Table-67
Table-68
Table-69
Table-70
GetLinkPerf Command (Encoding: 1BH)..................................................................................................... 61
GetConfigPara Command (Encoding: 1CH)................................................................................................ 63
GetGrpWorkingPara Command (Encoding: 1DH) ....................................................................................... 64
GetLinkWorkingPara Command (Encoding: 1EH)....................................................................................... 65
StartTestPattern Command (Encoding: 1FH).............................................................................................. 66
GetLoopedTestPattern Command (Encoding: 20H).................................................................................... 67
StopTestPattern Command (Encoding: 21H) .............................................................................................. 68
GetVersionInfo Command (Encoding: 22H) ................................................................................................ 68
Parameters for IMA Group Configuration .................................................................................................... 69
The PMON Parameters ............................................................................................................................... 71
Definitions of Different ICP Cells.................................................................................................................. 71
Failure/Alarm Signals................................................................................................................................... 72
Command Encoding .................................................................................................................................... 73
DeviceInitial Command (Encoding: 01H)..................................................................................................... 74
ConfigSlaveFrame Command (Encoding: 02H) .......................................................................................... 76
ConfigUtopiaIF Command (Encoding: 03H) ................................................................................................ 77
GetVersionInfo Command (Encoding: 22H) ................................................................................................ 78
GroupInitial Command (Encoding: 23H)...................................................................................................... 79
Absolute Maximum Ratings ......................................................................................................................... 81
D.C. Characteristics..................................................................................................................................... 81
System Clock and Reset Timing Parameters .............................................................................................. 82
Utopia Interface Timing Parameters ............................................................................................................ 83
Line Interface Timing Parameters................................................................................................................ 84
Microprocessor Interface Timing Parameter for Motorola CPU Read Cycle ............................................... 85
Microprocessor Interface Timing Parameters for Motorola CPU Write Cycle.............................................. 86
Microprocessor Interface Timing Parameter for Intel CPU Read Cycle....................................................... 87
Microprocessor Interface Timing Parameters for Intel CPU Write Cycle..................................................... 88
SRAM Interface Write Cycle Parameters..................................................................................................... 89
SRAM Interface Read Cycle Parameters .................................................................................................... 90
List of Tables
7
December 4, 2006
List of Figures
Figure-1
Figure-2
Figure-3
Figure-4
Figure-5
Figure-6
Figure-7
Figure-8
Figure-9
Figure-10
Figure-11
Figure-12
Figure-13
Figure-14
Figure-15
Figure-16
Figure-17
Figure-18
Figure-19
Figure-20
Figure-21
Figure-22
Figure-23
Functional Diagram ...................................................................................................................................... 10
IDT82V2608 PBGA208 Package Pin Assignment ....................................................................................... 11
Utopia Loopback .......................................................................................................................................... 18
Line Interface Work Modes .......................................................................................................................... 19
G.802 Mapping Mode .................................................................................................................................. 21
Spaced Mapping Mode ................................................................................................................................ 21
Multiplexing Four 2 MHz Streams into One 8 MHz Stream ......................................................................... 22
Input FIFO Write Process ............................................................................................................................ 27
Output FIFO Read Process ......................................................................................................................... 28
Command Message Format ........................................................................................................................ 31
Command Reply Message Format .............................................................................................................. 31
Alarm Message Format ................................................................................................................................ 31
Reset Signal Timing Diagram ...................................................................................................................... 82
Tx Utopia Interface Timing Diagram ............................................................................................................ 83
Rx Utopia Interface Timing Diagram ............................................................................................................ 83
Line Interface Transmit Timing Diagram ...................................................................................................... 84
Line Interface Receive Timing Diagram ....................................................................................................... 84
Microprocessor Interface Timing Diagram for Motorola CPU Read Cycle ................................................... 85
Microprocessor Interface Timing Diagram for Motorola CPU Write Cycle ................................................... 86
Microprocessor Interface Timing Diagram for Intel CPU Read Cycle .......................................................... 87
Microprocessor Interface Timing Diagram for Intel CPU Write Cycle .......................................................... 88
SRAM Interface Timing Diagram for Write Cycle ......................................................................................... 89
SRAM Interface Timing Diagram for Read Cycle ........................................................................................ 90
List of Figures
8
December 4, 2006
Inverse Multiplexing for ATM
IDT82V2608
–
–
Package: 208 pin PBGA.
3.3V operation / 5V tolerant input.
FEATURES
!
Highlights
–
Provides API command set for convenient configuration and
APPLICATIONS
operation. An embedded controller and a downloaded soft-
ware are used to interpret the commands. Functions can be
added by software upgrading.
–
–
DSLAM concentrator
3G Wireless base station controller (NodeB) and Radio
Network Controller (RNC)
Integrated Access Devices (IAD)
–
–
Supports IMA group auto detect.
Supports link backup so that a backup link can be automati-
cally added when a previously configured link fails.
All the state machines are implemented in hardware.
Advanced cell buffer management algorithm to support ATM
QoS requirements.
–
–
–
STANDARDS COMPLIANT
!
ATM-Forum
!
–
–
Utopia Level 2 Version 1.0, af-phy-0039.000, June 1995.
Inverse Multiplexing for ATM Specification version 1.1, af-phy-
0086.001, March 1999.
Backward compatible with Inverse Multiplexing for ATM Spec-
ification version 1.0, af-phy-0086.000, September 1994.
DS1 Physical Layer Specification, af-phy-0016.000,
September 1994.
Other Features
–
–
–
–
Accommodates up to 4 IMA logical groups.
Supports 8 T1/E1 channelized or unchannelized links.
Supports T1 ISDN links.
Supports MIXED mode: links not assigned to an IMA group
can be used in UNI mode.
–
–
–
–
–
Supports symmetrical and asymmetrical operation.
Supports Common Transmit Clock (CTC) and Independent
Transmit Clock (ITC) timing modes.
E1 Physical Interface Specification, af-phy-0064.000,
September 1996.
!
ITU-T
–
–
–
–
–
–
–
Provides 8 Utopia Level 2 8 bit cell level handshake MPHY
interface to ATM device.
Supports maximum link delay tolerance of up to 212 ms for E1
or 281 ms for T1 (when 512 KB external memory is used).
Provides parameters for MIB (Management Information
Base).
Supports dynamic addition/deletion of links to/from a working
IMA group.
Supports non-multiplexed Intel or Motorola microprocessor
interface.
I.432 B-ISDN User Network Interface PHY specification.
G.804 ATM Cell Mapping into Plesiochronous Digital Hier-
archy (PDH).
G.802 Inter-working between networks based on different
digital hierarchies and speech encoding laws.
I.610 B-ISDN operation and maintenance principles and func-
tions.
–
–
!
!
ANSI
–
ANSI T1.646-1995, Broadband-ISDN-Physical Layer Specifi-
cation for User-Network Interface Including DS1/ATM, 1995.
–
–
–
Loopback capability at both TDM and Utopia ports.
Supports MVIP.
JTAG boundary scan meets IEEE 1149.1.
MVIP
DESCRIPTION
The 8-port IDT82V2608 is a feature-rich device that provides the
solution to implement IMA and UNI logical channels over T1 or E1 links
in all public or private UNI, NNI and B-ICI applications. The chip is
compliant with the ATM Forum IMA specification v1.1 and backward
compatible with IMA specification v1.0.
nels) can be supported at the same time. To interface with most popular
ATM layer chips in the market, IDT82V2608 supports Utopia Level 2
MPHY cell level handshake 8-bit bus interface.
Through a well-defined API command set, IMA function can be easily
designed into various IMA systems and there is little necessity to access
a large amount of registers. A downloaded software is used to interpret
the command set and can be easily upgraded to meet specific require-
ment.
In the chip architecture, up to 8 physically independent T1/E1
streams can be terminated through the utilization of most T1/E1 framers
and LIUs in the market, and up to 4 logical IMA groups (i.e., 4 data chan-
The IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
9
December 4, 2006
DSC-6227-4
2006 Integrated Device Technology, Inc.
IDT82V2608
Inverse Multiplexing for ATM
FUNCTIONAL BLOCK DIAGRAM
Tx
Group
Cell
Link
Cell
FIFO
Tx IMA Data
Processor
TxClk
TxSOC
TSD[8:1]
TC
TSCK[8:1]
TSF[8:1]
TSCFS
FIFOs
TxEnb
TxData[7:0]
TxClav
TxAddr[4:0]
LP3LP2
LP1
TSCCK
Line
Interface
IMA Protocol
Processor
PMON
UTOPIA
RxClk
RxSOC
RSD[8:1]
RSCK[8:1]
RSF[8:1]
RSCFS
RxEnb
RxData[7:0]
RxClav
RxAddr[4:0]
Rx
Group
Cell
Link
Cell
FIFO
Rx IMA Data
Processor
TC
RSCCK
FIFOs
External
SRAM_IF
JTAG
Control Interface
LP1: Utopia loopback
LP2: Line interface internal loopback
LP3: Line interface external loopback
Figure-1 Functional Diagram
Functional Block Diagram
10
December 4, 2006
IDT82V2608
Inverse Multiplexing for ATM
1
PIN ASSIGNMENT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A
B
C
D
E
F
GND
TMS
IC
IC
IC
IC
IC
EMD4 EMD0 EMA18 EMA15 EMA12 EMA11 EMA8 EMA5 EMA1 RxData2 RxData5 RxData7 GND
A
B
C
D
E
F
TDI
TCK
TDO
EMD5 EMD1
EMD6 EMD2
EMD7 EMD3
EMA16 EMA13 EMA10 EMA7 EMA4 EMA0 RxData3 RxData6 RxSOC RxClav
EMA17 EMA14 EMA9 EMA6 EMA3 RxData0 RxData4 RxAddr4 RxAddr3 RxAddr2
EM_OE
EM_CS
EM_WE
TRST
NC
VDD
GND
GND
VDD
EMA2 RxData1 RxAddr1 RxAddr0
RxCLK
RxENB
RSCK1 RSD1
RSCK2 RSD2
RSCK3 RSD3
RSCK4 RSD4
VDD SYSCLK
TxClav TxCLK TxAddr0 TxAddr1
TxAddr2 TxAddr3 TxAddr4 TxSOC
RSF1
RSF2
RSF3
VDD
VDD
GND
G
H
J
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDD
TxData7 TxData6
G
H
J
TxENB
GND TxData5 TxData4 TxData3
GND TxData0 TxData1 TxData2
RSF4
RSF5
RSF6
RSF7
RSD5 RSCK5 GND
RSD6 RSCK6 VDD
RSD7 RSCK7 VDD
RSD8 RSCK8 VDD
K
L
VDD
IC
IC
IC
IC
IC
IC
K
L
CS
A6
A2
D6
D2
NC
13
M
N
P
R
T
A7
A3
D7
D3
D0
14
M
N
P
R
T
RD/DS WR/RW
RSF8 RSCFS RSCCK VDD
VDD
TSF7
TSD6
VDD
TSF6
TSD5
VDD
TSF5
TSD4
GND
GND
VDD
VDD
IC
A1
A4
MPM
D4
A5
A0
TSCCK TSCFS
VDD
TSF8
TSD7
TSF4 TSCK2 TSCK1
VDD
VDD
GND
1
NC
VDD
2
TSD8
TSD3
TSD2
TSD1
TSF2
10
D5
RST
TSF1
11
INT
IC
TSCK8 TSCK7 TSCK6 TSCK5 TSCK4 TSCK3 TSF3
D1
GND
16
3
4
5
6
7
8
9
12
15
Figure-2 IDT82V2608 PBGA208 Package Pin Assignment
(Top View)
PIN ASSIGNMENT
11
December 4, 2006
IDT82V2608
Inverse Multiplexing for ATM
2
PIN DESCRIPTION
Table-1 Pin Description
Name
Pin Number
Input/Output
Description
Global Signals
SYSCLK
E4
I
I
SYSCLK: System Clock
System clock for the IDT82V2608. Default is 20 MHz.
RST
R11
RST: System Reset
System reset signal, low active. After reset, all registers are reset to default values, and both the con-
tents in SRAM and the downloaded software are cleared.
ATM Utopia Interface
TxClk
E14
G14
I
I
I
TxClk: Utopia Transmit Clock
Utopia transmit clock used to transfer data from the ATM layer to the IDT82V2608. The frequency of
the TxClk should be less than or equal to that of the system clock.
Data is sampled on the rising edge of this signal.
TxEnb
TxEnb: Utopia Transmit Enable
Utopia low active signal asserted by the ATM layer device during cycles when TxData contains valid
cell data.
The TxEnb input is sampled on the rising edge of TxClk.
TxAddr4
TxAddr3
TxAddr2
TxAddr1
TxAddr0
F15
F14
F13
E16
E15
TxAddr[4:0]: Utopia Transmit Address
Utopia transmit port address driven from the ATM layer to poll and select an appropriate port.
The TxAddr[4:0] input bus are sampled on the rising edge of TxClk.
TxData7
TxData6
TxData5
TxData4
TxData3
TxData2
TxData1
TxData0
G15
G16
H14
H15
H16
J16
J15
J14
I
TxData[7:0]: Utopia Transmit Data
Utopia 8-bit data bus driven from the ATM layer to the IDT82V2608.
The TxData[7:0] input bus are sampled on the rising edge of TxClk.
TxClav
E13
High-Z
O
TxClav: Utopia Transmit Cell Available
Utopia transmit cell available signal from the IDT82V2608 to the ATM layer. A polled port drives TxClav
only during each cycle following one with its address on the TxAddr lines. The polled port asserts
TxClav high to indicate its corresponding FIFO can accept the transfer of a complete cell, otherwise it
deasserts the signal.
The TxClav output is updated on the rising edge of TxClk.
Note: This pin requires a pull-down resistor.
TxSOC
RxClk
RxEnb
F16
D16
D15
I
I
I
TxSOC: Utopia Transmit Start of Cell
Utopia start of cell signal. It will be driven high by the ATM layer when TxData[7:0] contain the first valid
byte of a cell.
The TxSOC input is sampled on the rising edge of TxClk.
RxClk: Utopia Receive Clock
Utopia receive clock. The frequency of RxClk should be less than or equal to the frequency of the sys-
tem clock.
Data is sampled on the rising edge of this signal.
RxEnb: Utopia Receive Enable
When this pin is low, the received data will be transferred on RxData[7:0] in the following cycles.
The RxEnb input is sampled on the rising edge of RxClk.
PIN DESCRIPTION
12
December 4, 2006
IDT82V2608
Inverse Multiplexing for ATM
Table-1 Pin Description (Continued)
Name
Pin Number
Input/Output
I RxAddr[4:0]: Utopia Receive Address
Description
RxAddr4
RxAddr3
RxAddr2
RxAddr1
RxAddr0
C14
C15
C16
D13
D14
Utopia receive port address driven from the ATM layer to poll and select an appropriate port.
The RxAddr[4:0] input bus are sampled on the rising edge of RxClk.
RxData7
RxData6
RxData5
RxData4
RxData3
RxData2
RxData1
RxData0
A15
B14
A14
C13
B13
A13
D12
C12
High-Z
O
RxData[7:0]: Utopia Receive Data
Utopia 8-bit data bus driven from the IDT82V2608 to the ATM layer.
The RxData[7:0] output bus are updated on the rising edge of RxClk.
RxClav
B16
High-Z
O
RxClav: Utopia Receive Cell Available
Utopia cell available signal. A polled port drives RxClav only during each cycle following one with its
address on the RxAddr lines. The polled port asserts RxClav high to indicate its corresponding FIFO
has a complete cell available for transfer to the ATM layer, otherwise it deasserts the signal.
The RxClav output is updated on the rising edge of RxClk.
Note: This pin requires a pull-down resistor.
RxSOC
B15
High-Z
O
RxSOC: Utopia Receive Start of Cell
Utopia start of cell pulse. It will be driven high when RxData[7:0] contain the first valid byte of a cell.
The RxSOC input is updated on the rising edge of RxClk.
T1/E1 Line Interface
TSD8
TSD7
TSD6
TSD5
TSD4
TSD3
TSD2
TSD1
R3
R4
R5
R6
R7
R8
R9
R10
O
TSDn: Transmit Side Data Output
TSDn contains the transmit data for the n-th link.
The TSDn output is updated on the rising edge of TSCKn or TSCCK if common clock is used.
TSCK8
TSCK7
TSCK6
TSCK5
TSCK4
TSCK3
TSCK2
TSCK1
T3
T4
T5
T6
T7
T8
P9
P10
I
TSCKn: Transmit Side Clock
TSCKn contains the transmit clock for the n-th link.
Note: If unused, TSCKn should be connected to ground.
TSF8
TSF7
TSF6
TSF5
TSF4
TSF3
TSF2
TSF1
P4
P5
P6
P7
P8
T9
T10
T11
I
TSFn: Transmit Side Frame pulse
TSFn is used to delineate each frame for the n-th link.
The TSFn input is sampled on the falling edge of TSCKn or TSCCK if common clock is used.
Note: If unused, TSFn should be connected to ground.
PIN DESCRIPTION
13
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IDT82V2608
Inverse Multiplexing for ATM
Table-1 Pin Description (Continued)
Name
Pin Number
P1
Input/Output
I
Description
TSCCK
TSCCK: Transmit Side Common Clock
TSCCK is the transmit clock for links that are configured in Common Clock Mode.
Note: If unused, TSCCK should be connected to ground.
TSCFS
P2
I
I
TSCFS: Transmit Side Common Frame Pulse
This signal is used to delineate each frame for links that are configured in Common Clock Mode.
The TSCFS input is sampled on the falling edge of TSCCK.
Note: If unused, TSCFS should be connected to ground.
RSD8
RSD7
RSD6
RSD5
RSD4
RSD3
RSD2
RSD1
M2
L2
K2
J2
H2
G2
F2
E2
RSDn: Receive Side Data Input
RSDn contains the receive data for the n-th link.
The RSDn input is sampled on the falling edge of RSCKn or RSCCK if common clock is used.
Note: If unused, RSDn should be connected to ground.
RSCK8
RSCK7
RSCK6
RSCK5
RSCK4
RSCK3
RSCK2
RSCK1
M3
L3
K3
J3
H1
G1
F1
E1
I
RSCKn: Receive Side Clock
RSCKn contains the recovered line clock for the n-th link.
Note: If unused, RSCKn should be connected to ground.
RSF8
RSF7
RSF6
RSF5
RSF4
RSF3
RSF2
RSF1
N1
M1
L1
K1
J1
H3
G3
F3
I
RSFn: Receive Side Frame Pulse
RSFn is used to delineate each frame for the n-th link.
The RSFn input is sampled on the falling edge of RSCKn or RSCCK if common clock is used.
Note: If unused, RSFn should be connected to ground.
RSCCK
N3
N2
I
I
RSCCK: Receive Side Common Clock
RSCCK is the receive clock for links that are configured in Common Clock Mode.
Note: If unused, RSCCK should be connected to ground.
RSCFS
RSCFS: Receive Side Common Frame Pulse
RSCFS is used to delineate each frame for links that are configured in Common Clock Mode.
The RSCFS input is sampled on the falling edge of RSCCK.
Note: if unused, RSCFS should be connected to ground.
Microprocessor Interface
MPM
P15
I
MPM: Microprocessor Interface Mode
Connected to VDD for Intel; connected to GND for Motorola.
PIN DESCRIPTION
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December 4, 2006
IDT82V2608
Inverse Multiplexing for ATM
Table-1 Pin Description (Continued)
Name
Pin Number
M15
Input/Output
I
Description
RD/DS
RD: Read Operation
In parallel Intel microprocessor interface mode, this pin is asserted low by the microprocessor to initiate
a read cycle. Data is output to D[7:0] from the device.
DS: Data Strobe
In parallel Motorola microprocessor interface mode, this pin is the data strobe of the parallel interface.
During a write operation (RW=0), data on D[7:0] is sampled into the device. During a read operation
(RW=1), data is output to D[7:0] from the device.
WR/RW
M16
I
WR: Write Operation
In parallel Intel microprocessor interface mode, this pin is asserted low by the microprocessor to initiate
a write cycle. Data on D[7:0] is sampled into the device during a write operation.
RW: Read/Write Select
In parallel Motorola microprocessor interface mode, this pin is asserted low for write operation and high
for read operation.
D7
D6
D5
D4
D3
D2
D1
D0
P14
P13
R16
R15
R14
R13
T15
T14
I/O
D[7:0]: Data Bus
These pins function as a bi-directional data bus of the microprocessor interface.
A7
A6
A5
A4
A3
A2
A1
A0
M14
M13
N16
N15
N14
N13
N12
P16
I
A[7:0]: Address Bus
These pins function as an address bus of the microprocessor interface.
CS
L13
I
CS: Chip Select
For each read or write operation, this pin must be changed from high to low, and remains low until the
operation is over.
INT
R12
Open_drain INT: Interrupt Request
A low level on this pin indicates that an interrupt is pending inside the chip.
SRAM Interface
EMD[7:0]: Data Bus
Data Input/Output pins for the external SRAM. Used for data exchange between the IDT82V2608 and
the external SRAM.
EMD7
EMD6
EMD5
EMD4
EMD3
EMD2
EMD1
EMD0
D4
C4
B4
A4
D5
C5
B5
A5
I/O
PIN DESCRIPTION
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IDT82V2608
Inverse Multiplexing for ATM
Table-1 Pin Description (Continued)
Name
Pin Number
Input/Output
O EMA[18:0]: Address Bus
Description
EMA18
EMA17
EMA16
EMA15
EMA14
EMA13
EMA12
EMA11
EMA10
EMA9
EMA8
EMA7
EMA6
EMA5
EMA4
EMA3
EMA2
EMA1
EMA0
A6
C7
B7
A7
C8
B8
A8
A9
B9
Address of the external SRAM. Used to select a data entry in the external SRAM.
C9
A10
B10
C10
A11
B11
C11
D11
A12
B12
EM_WE
EM_OE
EM_CS
D6
B6
C6
O
O
O
EM_WE: Write Enable
Write enable signal for the external SRAM. When EM_WE pin and EM_CS pin are both low, data can
be written to the external SRAM.
EM_OE: Output Enable
Output enable signal for the external SRAM. When EM_OE pin and EM_CS pin are both low, data can
be read from the external SRAM.
EM_CS: Chip Select
Chip enable signal for the external SRAM.
JTAG & Scan Interface
TCK
TMS
TDI
C2
B1
B2
D2
I
TCK: JTAG Test Clock
This pin is the input clock for JTAG.
I
TMS: JTAG Test Mode Select
This pin has an internal pull-up resistor.
I
TDI: JTAG Test Data Input
This pin is used to load instructions and data into the test logic and has an internal pull-up resistor.
TDO
High-Z
TDO: JTAG Test Data Output
This is normally high impedance and is used to read all the serial configuration and test data from the
test logic.
TRST
C1
I
TRST: JTAG Test Port Reset
This pin has an internal pull-up resistor.
Power Supplies and Grounds
3.3V Power Supply
VDD
D7,D10,E3,F4,G4,G13,
K4,K13,L4,M4,N4,N5,
N6,N7,N10,N11,P3,
P12,R1,T2
-
GND
A1,A16,D8,D9,G7,G8,
G9,G10,H4,H7,H8,H9,
H10,H13,J4,J7,J8,J9,
J10,J13,K7,K8,K9,
K10,N8,N9,T1,T16
-
Ground
PIN DESCRIPTION
16
December 4, 2006
IDT82V2608
Inverse Multiplexing for ATM
Table-1 Pin Description (Continued)
Name
Pin Number
Input/Output
Description
Others
IC
IC
L16
-
-
-
-
IC: Internal Connected
Internal use. For normal operation, these pins should be connected to VDD.
A2,A3,B3,C3,D3,L15,
P11,T12
IC: Internal Connected
Internal use. For normal operation, these pins should be connected to ground.
IC
K14,K15,K16,L14
IC: Internal Connected
Internal use. For normal operation, these pins should be left open.
NC
D1,R2,T13
NC: No Connection
PIN DESCRIPTION
17
December 4, 2006
IDT82V2608
Inverse Multiplexing for ATM
3.1.1 UTOPIA LOOPBACK FUNCTION
3
INTERFACE
For diagnostic purpose, the capability to loop back all Utopia traffic to
Utopia bus is provided. This loopback is called Utopia loopback and can
be enabled by ConfigLoopMode command. In this mode, cells are
taken from TGCFs (Transmit Group Cell FIFO) and sent to the respec-
tive RGCFs (Receive Group Cell FIFO). When in Utopia loopback mode,
cells will not be transmitted to the line interface. Refer to Figure-3.
3.1 UTOPIA INTERFACE
The Utopia interface operates in Level 2 mode. The IDT82V2608
supports up to 8 Utopia Level 2 ports. Each port is assigned an address
ranging from 0 to 30. The address value of 31 is reserved and should
not be used. All the 31 ports can be individually enabled or disabled by
ConfigUtopiaIF command.
Each IMA group or UNI link corresponds to a port. For each IMA
group, the port address can be assigned by ConfigGroupInterface
command. For each UNI link, the port address can be assigned by
ConfigUNILink command. Inside the device, each port corresponds to
a GCF (Group Cell FIFO) which is 2 cells deep.
UTOPIA Interface
Tx
Group
Cell
Tx
Group
Cell
Rx
Group
Cell
Rx
Group
Cell
The IDT82V2608 uses cell level handshake for cell transfer. One
entire cell is transferred before another port can be selected. The start of
a cell is marked by TxSOC and RxSOC signals in the transmit and the
receive directions respectively. These two signals are active during the
first byte of a cell.
……
FIFO 0
FIFO 1
FIFO 1
FIFO 0
Figure-3 Utopia Loopback
INTERFACE
18
December 4, 2006
IDT82V2608
Inverse Multiplexing for ATM
In channelized mode, all the framing bits and signalling bits are set to
zero in transmit direction. And all the received signalling bits and framing
bits are discarded in receive direction. In unchannelized mode, all bits
are utilized for data transfer.
3.2 LINE INTERFACE
3.2.1 LINE INTERFACE WORK MODES
For different framers, the line interface can be configured to different
Work Mode to adapt to different data format. Figure-4 shows all the 16
Work Modes and Table-2 lists IMA layer data rate for each mode.
Work Mode is selected by AddTxLink or AddRxLink command
when a link is in an IMA group. The Work Mode is selected by ConfigU-
NILink command when a link is used as a UNI link.
IMAtoFramer
InterfaceRate
DataRate
ModeName
Mode0
Mode1
1.5Mb/s
Unchannelized
ISDN
mode
Normal
mode
ISDN
G.802
mapping
Mode2
Mode3
2Mb/s
Spaced mode
T1
mapping
Normal
mode
non-
multi-rate
Mode4
Mode5
ISDN
mode
1.5Mb/s
Normal
mode
Mode6
Mode7
Channelized
ISDN
G.802 mode
mapping
Normal
mode
ISDN
Interface
Mode
multi-rate
T1map
toE1
8Mb/s
four
channel
Mode8
Mode9
Spaced mode
mapping
Normal
Mode10
mode
Mode11
Mode12
Unchannelized
2Mb/s
2Mb/s
Signalling
mode
non-
E1
multi-rate
Normal
mode
Mode13
Mode14
Channelized
Signalling
mode
multi-rate
8Mb/s
Normal
mode
Mode15
Figure-4 Line Interface Work Modes
INTERFACE
19
December 4, 2006
IDT82V2608
Inverse Multiplexing for ATM
Table-2 Data Rates of Different Modes
Mode
IMA Data Rate Per Channel (Maximum)
Interface Clock (Maximum)
Mode0
Mode1
Mode2
Mode3
Mode4
Mode5
Mode6
Mode7
Mode8
Mode9
Mode10
Mode11
Mode12
Mode13
Mode14
Mode15
1.544 Mb/s
1.472 Mb/s
1.536 Mb/s
1.472 Mb/s
1.536 Mb/s
1.472 Mb/s
1.536 Mb/s
1.472 Mb/s
1.536 Mb/s
1.472 Mb/s
1.536 Mb/s
2.048 Mb/s
1.920 Mb/s
1.984 Mb/s
1.920 Mb/s
1.984 Mb/s
1.544 MHz
2.048 MHz
2.048 MHz
2.048 MHz
2.048 MHz
1.544 MHz
1.544 MHz
8.192 MHz
8.192 MHz
8.192 MHz
8.192 MHz
2.048 MHz
2.048 MHz
2.048 MHz
8.192 MHz
8.192 MHz
3.2.1.1 Mode0
Each mapping mode can be further divided into two data modes: T1
ISDN mode and T1 normal mode. The mapping is done in a frame-by-
frame fashion and the unassigned time slots are set to zero.
In this mode, the transmit and receive data are viewed as a contin-
uous 1.544 Mb/s serial stream. There is no concept of time slot in an
unchannelized link. Each eight bits are grouped into an octet with arbi-
trary alignment. The first bit received/transmitted is the most significant
bit of an octet while the last bit is the least significant bit. The 1.544 MHz
data stream clock is provided by the system.
In these modes, the clock for Tx and Rx can be either common clock
or independent clock. If common clock is used, TSCCK and RSCCK are
used as Tx clock and Rx clock respectively, and TSCFS and RSCFS are
used as common frame pulse in Tx and Rx directions respectively. If
independent clock is used, TSCK[i] and RSCK[i] are used as Tx clock
and Rx clock respectively, and TSF[i] and RSF[i] are used as the frame
pulse in Tx and Rx directions respectively.
The 1.544 MHz clock in Tx and Rx directions can be either common
clock or independent clock. If common clock is used, TSCCK and
RSCCK are used as Tx clock and Rx clock respectively, and TSCFS and
RSCFS are used as common frame pulse in Tx and Rx directions
respectively. If independent clock is used, TSCK[i] and RSCK[i] are used
as Tx clock and Rx clock respectively, and TSF[i] and RSF[i] are used as
the frame pulse in Tx and Rx directions respectively.
G.802 Mapping
This mode supports ITU-T Recommendation G.802, which describes
how 24 (or 23, in signalling mode) T1 time slots and one framing bit
(totally 193/185 bits per T1/T1-ISDN frame) are mapped to 32 E1 time
slots (256 bits). This mapping is done by mapping the 24 (or 23 in T1-
ISDN mode) T1 time slots to TS1~TS15 and TS17~TS25 (or
TS17~TS24), and mapping the framing bit to bit 1 of TS26/TS25. TS0,
TS16, TS27/TS26 through TS31 are all unassigned and set to zero
(refer to Figure-5).
3.2.1.2 Mode1~Mode4
In these four modes, the transmit/receive data rate is T1 channelized
while the line interface timing clock is 2.048 MHz (E1 clock). Thus the
mapping between T1 frame and E1 frame is needed. Two mapping
modes can be used: G.802 mapping mode and spaced mapping mode.
INTERFACE
20
December 4, 2006
IDT82V2608
Inverse Multiplexing for ATM
Frame A
Frame B
1.5 MT1
stream
F
A
1
1
2
2
14 15 16 17 18
23 24
F
B
1
u
2
u
23 24
F
C
1
2
u
0
u
u
u
u
2 ME1
stream
14 15 16 17 18
24 25 26 27 28
31
0
1
2
E1
E1
Framing
time slot
signalling
time slot
FB
X
X
X
X
X
X
X
1. X=unused bit
2.u=unassignedtimeslot
3. FA, F
B
and F
C
are T1 framing bits for frame A, B and C respectively.
Figure-5 G.802 Mapping Mode
Spaced Mapping
int(n) is the largest integer no greater than n. The framing bit is assigned
to the first bit of TS0. This distribution of unassigned time slots averages
out the idle time slots and optimizes the framer’s slip buffer’s usage.
In this mode, T1 to E1 mapping makes every fourth time slot unas-
signed (i.e., 4, 8, 12, 16, 20, 24 and 28). Refer to Figure-6. Suppose T1
time slot x is mapped to E1 time slot y. We have y=x+int((x-1)/3), where
Frame A
Frame B
1.5 MT1
Stream
F
A
1
2
3
4
5
6
7
8
9
22 23 24
F
B
1
2
23 24 F
C
1
2
u
u
u
2 M
Stream
0
1
2
3
4
5
6
7
8
9
27 28 29 30 31
0
1
2
31
F
B
X
X
X
X
X
X
X
F
A
X
X
X
X
X
X
X
1. X=unused bits
2.u=unassignedtimeslot
3. F , F and F are T1 framing bits for frame A, B and C respectively.
A
B
C
4. Mapping rule: If T1 time slot x is mapped to E1 time slot y, y= x+int(x/3). Here int(n) is
the largest integer no greaterthan n.
Figure-6 Spaced Mapping Mode
INTERFACE
21
December 4, 2006
IDT82V2608
Inverse Multiplexing for ATM
T1 ISDN Mode
1st 2 Mbps stream
2nd 2 Mbps stream
3rd 2 Mbps stream
4th 2 Mbps stream
8 Mbps stream
Byte0
Byte0
Byte0
Byte0
Byte1
Byte1
Byte1
Byte1
Byte2
Byte2
Byte2
Byte2
The T1 ISDN mode corresponds to the use of 23 time slots to
transmit data, that is, T1 data is not transmitted during the framing bit
and time slot 24. Therefore, only 23 time slots are considered useful and
are mapped while time slot 24 and the framing bit are meaningless and
are not mapped.
0
1
2
3
4
5
6
7
8
9
10 11
T1 Normal Mode
In this mode, data is not transmitted during the framing bit. The other
24 time slots are useful.
Figure-7 Multiplexing Four 2 MHz Streams into One 8
MHz Stream
3.2.1.3 Mode5~Mode6
T1 Multi-Rate Mode
In these modes, the transmit/receive data rate is T1 channelized, and
the line interface timing clock is 1.544 MHz (T1 clock). The ISDN mode
and normal mode are defined in T1 ISDN Mode and T1 Normal Mode on
page 22.
Since there are two T1 to E1 mapping methods that can be used as
described in G.802 Mapping and Spaced Mapping on page 20, two new
modes can be derived when multiplexing is further used. Again, T1
ISDN data mode and T1 normal mode can be applied, thus we have 4
more modes: mode7~mode10.
In these modes, the clock for Tx and Rx can be either common clock
or independent clock. If common clock is used, TSCCK and RSCCK are
used as Tx clock and Rx clock respectively, and TSCFS and RSCFS are
used as common frame pulse in Tx and Rx directions respectively. If
independent clock is used, TSCK[i] and RSCK[i] are used as Tx clock
and Rx clock respectively, and TSF[i] and RSF[i] are used as the frame
pulse in Tx and Rx directions respectively.
3.2.1.5 Mode11
In this mode, the transmit and receive data are viewed as a contin-
uous 2.048 Mb/s serial stream. There is no concept of time slot in an
unchannelized link. Each eight bits are grouped into an octet. TSF or
TSCFS signal determine whether the data stream is in byte alignment or
not. The first bit received/transmitted is the most significant bit of an
octet while the last bit is the least significant bit. The 2.048 MHz data
stream clock is provided by the system.
3.2.1.4 Mode7~Mode10
In these modes, only TSCCK and RSCCK are used to input the
8.192 MHz clock in Tx and Rx directions respectively, and TSCFS and
RSCFS are used as common frame pulse in Tx and Rx directions
respectively. All the TSCK[i], TSF[i], RSCK[i] and RSF[i] pins are not
used and should be connected to ground. The unused RSD pins should
also be connected to ground.
In this mode, the clock for Tx and Rx can be either common clock or
independent clock. If common clock is used, TSCCK and RSCCK are
used as Tx clock and Rx clock respectively. If independent clock is used,
the clock for the i-th link comes from TSCK[i] and RSCK[i] in Tx and Rx
directions respectively.
The data pins used for multiplexing are shown in the table below:
In Common Clock Mode, the TSCFS signal is used for byte align-
ment pulse for the transmitted bit stream while in Independent Clock
Mode, the TSF[i] signal is used for byte alignment pulse for the i-th
transmit link.
Table-3 Pins Used in Multi-Rate Multiplex Mode
Tx Pin Name
Rx Pin Name
Multiplexed Channel
The frequency for TSF[i] (or TSCSF) is the result of TSCK[i] (or
TSCCK) divided by 256 and the pulse width of this signal is one cycle of
TSCK[i] or TSCCK signal.
TSD[1]
TSD[2]
RSD[1]
RSD[2]
channel 1~channel 4
channel 5~channel 8
3.2.1.6 Mode12~Mode13
Multi-rate
These two modes are E1 non-multi-rate combined with different
signalling modes. The non-multi-rate is the channelized generic E1 inter-
face, i.e., a 2.048 MHz channel is divided into 32 sub-channels (also
called time slots), and these sub-channels are used to exchange data.
Multi-rate is used for multiplexing four E1 streams into one high-
speed stream. Figure-7 shows four 2.048 MHz E1 streams multiplexed
into a single 8.192 MHz stream through one data pin. The multiplexing
uses the round-robin technology. The system provides 8.192 MHz
common clock and 8 kHz common frame pulse.
In these modes, the clock for Tx and Rx can be either common clock
or independent clock. If common clock is used, TSCCK and RSCCK are
used as Tx clock and Rx clock respectively, and TSCFS and RSCFS are
used as common frame pulse in Tx and Rx directions respectively. If
independent clock is used, TSCK[i] and RSCK[i] are used as Tx clock
and Rx clock respectively, and TSF[i] and RSF[i] are used as the frame
pulse in Tx and Rx directions respectively.
For T1 channel, before multiplexing, a mapping from each T1 frame
to E1 frame is first done. Then the mapped 4 E1 channels are multi-
plexed into one 8.192 MHz stream as shown in Figure-7.
INTERFACE
22
December 4, 2006
IDT82V2608
Inverse Multiplexing for ATM
Channelized Non-Multi-Rate E1
command and AddRxLink command can be used to configure the clock
mode in the transmit and receive directions respectively. In UNI mode,
ConfigUNILink command can be used to configure the clock mode.
In this mode, the system provides 2.048 MHz clock and 8 kHz frame
pulse for E1 bit stream exchange between the IDT82V2608 and the line
interface. The E1 time slot 0 is not used for data exchange while time
slot 16 may or may not be used for data exchange, depending on
Signalling or Non-Signalling mode.
If a link is configured in Common Clock Mode, TSCCK and RSCCK
are used as Tx clock and Rx clock respectively, and TSCFS and RSCFS
are used as common frame pulse in Tx and Rx directions respectively.
Signalling and Non-Signalling
If a link is configured in Independent Clock Mode, TSCK[i] and
RSCK[i] are used as Tx clock and Rx clock respectively, and TSF[i] and
RSF[i] are used as the frame pulse in Tx and Rx directions respectively.
In signalling mode, time slot 0 and time slot 16 are not used for data
exchange between the IDT82V2608 and the line interface. In non-
signalling mode, only time slot 0 is not used for data exchange.
These two timing clock modes can be configured at the same time,
i.e., some links can work in Common Clock Mode while other links can
work in Independent Clock Mode.
3.2.1.7 Mode14~Mode15
The multi-rate concept is defined in Multi-rate on page 22, and the
signalling and non-signalling concepts are defined in Signalling and
Non-Signalling on page 23. The system provides 8.192 MHz common
clock and 8 kHz common frame pulse.
The line interface mode7~mode10 and mode14~mode15 cannot be
used in Independent Clock Mode.
3.2.3 LINE INTERFACE LOOPBACK FUNCTION
In these modes, only the TSCCK and RSCCK pins are used to input
the 8.192 MHz clock in Tx and Rx directions respectively, and TSCFS
and RSCFS are used as common frame pulse in Tx and Rx directions
respectively. The TSCK[i], TSF[i], RSCK[i] and RSF[i] pins are not used
and should be connected to ground. The unused RSD pins should also
be connected to ground.
The line interface supports two line loopback functions, one is
external loopback mode and the other is internal loopback mode. The
two loopback modes can be selected by ConfigLoopMode command.
In external loopback mode, all the data received at the line side is
looped back to the transmit side and is transmitted out. When this func-
tion is enabled, all the links will be in external loopback mode. Data will
not be transmitted to the Utopia interface.
The data pins used for multiplexing are shown in Table-3.
3.2.2 LINE INTERFACE TIMING CLOCK MODES
In internal loopback mode, the data transmitted are also sent to the
receive side. When this function is enabled, all the links will be in internal
loopback mode. Data will not be transmitted to the FE Utopia interface.
Two timing clock modes can be selected. One is Common Clock
Mode, the other is Independent Clock Mode. The timing clock mode can
be individually configured for each link. In IMA mode, AddTxLink
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3.3.2 COMMAND FIFOS
3.3 EXTERNAL MICROPROCESSOR INTERFACE
The embedded controller uses two FIFOs to communicate with the
external microprocessor. One is Input FIFO, which is used to receive
commands and data from the external microprocessor; the other is
Output FIFO, which is used to send data to the external microprocessor.
The lengths of these two FIFOs are both 16 bytes. These two FIFOs can
only be accessed through registers.
The IDT82V2608 uses an embedded controller and a downloaded
1
software (IMAOS08 or IMAOS08_Slave ) to communicate with the
external microprocessor. The external microprocessor sends commands
to configure the device and read feedbacks. The downloaded software
interprets these commands and the embedded controller executes
these commands. This relieves programmers from accessing vast regis-
ters. Just by accessing a few registers, programmers can use a set of
well-defined commands to communicate with IDT82V2608.
3.3.3 REGISTERS
The IDT82V2608 provides 9 registers for the external micropro-
cessor to load software to the device, send commands and read feed-
backs.
3.3.1 EXTERNAL MICROPROCESSOR INTERFACE SELECTION
The IDT82V2608 supports both non-multiplexed Intel and non-multi-
plexed Motorola microprocessor interfaces. For Intel microprocessor
interface, the MPM pin should be connected to VDD; for Motorola micro-
processor interface, the MPM pin should be connected to ground.
3.3.4 REGISTER MAP
1. IMAOS08 is used when the device is in normal communication while
IMAOS08_Slave is used when the device operates in Slave Mode. Refer to8.1
Group Auto Detect.
Table-4 Register Map
Address
Map
Register
R/W
(Hex)
b7
b6
b5
b4
b3
b2
b1
b0
00
01
INPUT_FIFO_LENGTH_REG R/W
-
-
-
-
-
-
Input_Message_Length[4:0]
Output_Message_Length[4:0]
OUTPUT_FIFO_LENGTH_R
EG
R
02
03
04
OUTPUT_FIFO_DATA_REG
INPUT_FIFO_DATA_REG
FIFO_INT_ENABLE_REG
R
Output_Data[7:0]
Input_Data[7:0]
R/W
R/W
-
-
-
-
-
-
-
-
Input_FIFO_ Input_FIFO_ov Output_FIFO_msg
empty_int_en erflow_int_en _available_int_en
05
06
FIFO_STATE_REG
R
HW_version
-
Input_FIFO_ Input_FIFO_ov Output_FIFO_msg
empty_state
erflow_state
_available_state
FIFO_INT_RESET_REG
W
-
-
Input_FIFO_ov Output_FIFO_msg
erflow&empty_i _available_int_rst
nt_rst
07
08
OUTPUT_FIFO_INTERNAL_
STATE_REG
R
R
-
-
-
-
-
-
Output_remain_msg_length[4:0]
INPUT_FIFO_INTERNAL_ST
ATE_REG
Input_remain_msg_length[4:0]
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3.3.5 REGISTER DESCRIPTION
Table-5 Input FIFO Data Length Register (INPUT_FIFO_LENGTH_REG)
(R/W, Address=00H)
Symbol
Position
Default
Description
-
7-5
4-0
0
0
Reserved.
Input_Message_Length[4:0]
These 5 bits contain the message length in the Input FIFO which should be written after the mes-
sage is sent to the Input FIFO. The valid length is from 0 to 16 bytes.
Table-6 Output FIFO Data Length Register (OUTPUT_FIFO_LENGTH_REG)
(R, Address=01H)
Symbol
Position
Default
Description
-
7-5
4-0
0
0
Reserved.
Output_Message_Length[4:0]
These 5 bits contain the length of the message in the Output FIFO. Valid length is from 0 to 16
bytes.
Table-7 Output FIFO Data Register (OUTPUT_FIFO_DATA_REG)
(R, Address=02H)
Symbol
Position
Default
Description
Output_Data[7:0]
7-0
0
These bits contain the data from the message Output FIFO. The complete message can be
retrieved by continuously reading this register.
Table-8 Input FIFO Data Register (INPUT_FIFO_DATA_REG)
(R/W, Address=03H)
Symbol
Position
Default
Description
Input_Data[7:0]
7-0
0
These bits contain data to be sent to the Input FIFO. By continuously writing to this register, a
complete message can be sent. Before the message is sent, the Input_FIFO_empty_state bit in
the EP_interrupt status register should be polled to see whether the Input FIFO is available for
writing. After the message is sent, the message length should be written to the EP_Tx_length reg-
ister.
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Table-9 FIFO Interrupt Enable Register (FIFO_INT_ENABLE_REG)
(R/W, Address=04H)
Symbol
Position
Default
Description
-
7-3
2
0
0
Reserved.
Input_FIFO_empty_int_en
Input FIFO empty interrupt enable
0: Interrupt disabled
1: Interrupt enabled
Input_FIFO_overflow_int_en
1
0
0
0
Input FIFO overflow interrupt enable
0: Interrupt disabled
1: Interrupt enabled
Output_FIFO_msg_available_int_en
Output FIFO message available interrupt enable
0: Interrupt disabled
1: Interrupt enabled
Table-10 FIFO Interrupt Status Register (FIFO_STATE_REG)
(R, Address=05H)
Symbol
Position
Default
Description
HW_version
7-3
1
Current device version. For revision A and B, these bits are ‘0000’. For revision C, these bits are
‘0001’.
Input_FIFO_empty_state
Input_FIFO_overflow_state
2
1
0
1
0
0
Input FIFO availability status
0: Input FIFO is not available for writing.
1: Input FIFO is available for writing.
Input FIFO overflow status
0: Input FIFO is not full.
1: Input FIFO is full.
Output_FIFO_msg_available_state
Output FIFO message availability status
0: No message is in the Output FIFO.
1: A message is in the Output FIFO.
Table-11 FIFO Interrupt Reset Register (FIFO_INT_RESET_REG)
(W, Address=06H)
Symbol
Position
Default
Description
-
7-2
1
0
0
0
Reserved.
Input_FIFO_overflow&empty_int_rst
Output_FIFO_msg_available_int_rst
Write ‘1’ to clear the Input_FIFO_overflow_state status and Input_FIFO_empty_state status.
Write ‘1’ to clear the Output_FIFO_msg_available_state status.
0
Table-12 Output FIFO Internal State Register (OUTPUT_FIFO_INTERNAL_STATE_REG)
(R, Address=07H)
Symbol
Position
Default
Description
-
7-5
4-0
0
0
Reserved.
Output_remain_msg_length[4:0]
The length of the message remaining in the Output FIFO to be read by the external microproces-
sor.
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Table-13 Input FIFO Internal State Register (INPUT_FIFO_INTERNAL_STATE_REG)
(R, Address=08H)
Symbol
Position
Default
Description
-
7-5
4-0
0
0
Reserved.
The length of the message remaining in the Input FIFO to be processed by the IDT82V2608.
Input_remain_msg_length[4:0]
3.3.6 PROCEDURE OF LOADING SOFTWARE AND SENDING
COMMANDS
is the same with that of sending the commands. Figure-8 shows the
Input-FIFO write process and Figure-9 shows the Output-FIFO read
process.
After chip reset, the IMAOS08 or IMAOS08_Slave (a binary file
shipped with the chip) should be loaded to the IDT82V2608 to interpret
commands. The procedure of loading the IMAOS08 or IMAOS08_Slave
InputFIFOWriteProcess
write_message(char *message,char L)
{
ReadInput_FIFO_empty_statebitof
FIFO_STATE_REGregister
wait(INPUT_FIFO_EMPTY_STATE_EVENT);
write_reg(FIFO_INT_RESET_REG,0x02);
Input_FIFO_empty_state
bit is set?
N
Y
CleartheInput_FIFO_empty_statebit
for(i=0;i<L;i++)
{
write_reg(INPUT_FIFO_DATA_REG,message[i]);
}
Write L(L<=16)bytesinto Input_FIFO
Writevalue Linto
INPUT_FIFO_LENGTH_REGregister
write_reg(INPUT_FIFO_LENGTH_REG,L);
}
Figure-8 Input FIFO Write Process
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Output FIFO Read Process
read_message(char *message,char *L)
{
Read
Output_FIFO_msg_available_state bit
of FIFO_STATE_REG register
wait(OUTPUT_FIFO_MSG_AVAILABLE_STATE_EVENT);
write_reg(FIFO_INT_RESET_REG,0x01);
Output_FIFO_msg_
available_state
bit is set?
N
Y
Clear the
Output_FIFO_msg_available_state bit
*L = 0x1f&(read_reg(OUTPUT_FIFO_LENGTH_REG));
Read Message Length L from
OUTPUT_FIFO_LENGTH_REG
register
for(i=0;i<*L;i++)
{
message[i] =
read_reg((OUTPUT_FIFO_DATA_REG);
Read L bytes from
OUTPUT_FIFO_DATA_REG register
}
}
Figure-9 Output FIFO Read Process
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The size of the SRAM can be selected from 2K byte to 512 Kbyte.
When the minimum 2K byte memory is selected, only 11 address pins
will be used. Different memory size will affect different delay compensa-
tion capability. Table-14 and Table-15 show memory size vs. maximum
delay tolerance in T1 and E1 unchannelized modes respectively.
3.4 SRAM INTERFACE
The SRAM interface has an 8-bit wide data bus, EMD[7:0], and a 19-
bit wide address bus, EMA[18:0]. The minimum throughput is 4 Mbyte/s
and the minimum access time is 40ns.
When both EM_WE pin and EM_CS pin are low, data can be written to the
external SRAM. When both EM_OE pin and EM_CS pin are low, data can be
read from the external SRAM.
Table-14 Maximum Delay Tolerance Value for Different SRAM Size in T1 Unchannelized Mode
SRAM Used
(Kbyte)
Maximum Delay Tolerance
Address Bus Used
(ms)
512
256
128
64
32
16
8
281
141
70
EMA[18:0]
EMA[17:0]
EMA[16:0]
EMA[15:0]
EMA[14:0]
EMA[13:0]
EMA[12:0]
EMA[11:0]
EMA[10:0]
35
17.58
8.79
4.39
2.20
1.10
4
2
Table-15 Maximum Delay Tolerance Value for Different SRAM Size in E1 Unchannelized Mode
SRAM Used
(Kbyte)
Maximum Delay Tolerance
(ms)
Address Bus Used
512
256
128
64
32
16
8
212
106
EMA[18:0]
EMA[17:0]
EMA[16:0]
EMA[15:0]
EMA[14:0]
EMA[13:0]
EMA[12:0]
EMA[11:0]
EMA[10:0]
53
26.5
13.25
6.625
3.31
1.66
0.83
4
2
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Stuff Indication (LSI) field of the ICP cell. The stuff cell event will occur
on the same frame on all the links. However, the pre-defined ICP offset
will determine at which cell in the frame the stuff event will occur.
1
4
IMA AND UNI FUNCTIONS
The IDT82V2608 is capable of combining the transport bandwidth of
multiple links into one single logical link. The logical link is called a
group. The IDT82V2608 supports up to 4 independent groups with each
group capable of supporting from 1 to 8 links. Links that are assigned to
an IMA group are called in IMA mode while links that are not assigned to
any IMA group can be used in UNI mode.
In ITC mode, a stuff cell is added to the TRL the same way as in CTC
mode, that is, it is added after every 2048 ICP, filler and ATM layer cells.
On all other links in the group, stuff cells are added as necessary to
compensate for timing differences between the TRL and other links of
the group.
4.1 IMA MODE
In an IMA group, if at least one of the links uses independent clock
pin as its clock input, stuff mode can only be set as ITC. If all the links
within the group use common clock pin (i.e., TSCCK and RSCCK) as
their clock input, stuff mode can be set as either CTC or ITC. For details
about the two clock modes, please refer to 3.2.2 Line Interface Timing
Clock Modes.
4.1.1 IMA FRAME
An IMA frame is defined as M consecutive cells, numbered from 0 to
M-1 on each link, across all the links in an IMA group. It is generated by
inserting an ICP cell after every M-1 cells per link. Values of M supported
are 32, 64, 128 and 256, which can be programmed for all the links in a
group by ConfigGroupPara command. The ICP cell occurs within the
frame at the ICP cell offset position and should be at the same position
throughout the frame. The ICP offset is programmable on a per-link
basis by AddTxLink command.
4.1.4 LINK BACKUP
The group link backup function is used to add a link to the group for
backup in case of link failure. This function is only enabled when the
device is working in symmetry mode.
The link to be added to the group is specified as backup link or non-
backup link in ‘AddLink’ command (i.e., AddTxLink and AddRxLink
commands). Note that only one backup link is supported in each group.
If several links are specified as backup links, only the last added backup
link is regarded as a backup link.
4.1.2 TRL (TIMING REFERENCE LINK)
Within an IMA group, a TRL should be selected to pass synchroniza-
tion from the transmit to the receive end. The TRL can be selected by
ConfigTRLLink command.
4.1.3 STUFFING MODE
When a link failure event occurred, the IDT82V2608 will automati-
cally pick up a backup link and activate it.
The insertion of stuff cells is to compensate for timing differences
between links within an IMA group.
4.2 UNI MODE
There are two kinds of stuffing method: CTC (Common Transmit
Clock) mode and ITC (Independent Transmit Clock) mode. The stuffing
method is selected by ConfigGroupWorkMode command.
ConfigDev command and ConfigUNILink command are used to
configure a UNI link. ConfigDev command can be used to configure TC
Work Mode, TC Alpha and Delta value and LCD threshold. ConfigU-
NILink command can be used to configure link physical ID, Tx and Rx
Utopia port, line interface Work Mode and clock mode.
In CTC mode, a stuff cell is added after every 2048 ICP, filler and
ATM layer cells. The stuff cell is generated by repeating the ICP cell.
Both the ICP cell and the stuff cell are identified as ICP cells via the Link
When a link is configured in UNI mode, IMA functions are bypassed.
ATM cells are simply transmitted from the Utopia interface to the line
interface.
1.
Chapter 4, 5, 6 and 7 are specific to IMAOS08. Details about
IMAOS08_Slave are provided in Chapter 8.
IMA AND UNI FUNCTIONS
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5
PROGRAMMING INFORMATION FOR IMAOS08
5.1 COMMAND TYPES
There are three types of messages:
1.Command message (external MPU⇒embedded controller)
2.Reply message (embedded controller⇒external MPU)
3.Notification message (embedded controller⇒external MPU)
The formats of the three types of messages are different.
5.1.1 COMMAND MESSAGE
1 byte
1 byte
at most 14 bytes
Command Handler
Command Type
Command Parameters
Figure-10 Command Message Format
Command Handler
From 0~126 defined by user’s driver. It is the sequence number of
the sent message.
Command Type
The encoding of the command. Refer to 5.2 Command Encoding.
Command Parameters
The Parameters of the command.
5.1.2 COMMAND REPLY MESSAGE
1 byte
at most 14 byte
Command Reply Handler
Command Replies
Figure-11 Command Reply Message Format
Command Reply Handler
The original Command Handler plus 128.
Command Replies
The replies of the original command.
5.1.3 ALARM MESSAGE
1 byte
1 byte
1 byte
Alarm Handler
Link ID /Group ID
Alarm Type
Figure-12 Alarm Message Format
Alarm Handler
FFH.
Link ID /Group ID
The link ID or group ID.
Alarm Type
The sequence in Table-53 Failure/Alarm Signals on page 72.
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5.2 COMMAND ENCODING
(1)
Table-16 Command Encoding
Command Encoding
Command Name
01H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
ConfigDev
ConfigUtopiaIF
ConfigLoopMode
ConfigGroupPara
ConfigGroupInterFace
ConfigGroupWorkMode
ConfigGSMTimers
ConfigTRLLink
ConfigIFSMPara
AddTxLink
AddRxLink
ConfigUNILink
StartGroup
StartLASR
InhibitGrp
NotInhibitGrp
RestartGrp
DeleteGrp
RecoverLink
DeleteLink
DeactLink
GetGroupState
GetGroupDelayInfo
GetLinkState
GetGrpPerf
GetLinkPerf
GetConfigPara
GetGrpWorkingPara
GetLinkWorkingPara
StartTestPattern
GetLoopedTestPattern
StopTestPattern
GetVersionInfo
1. IMAOS will be in unknown state if the user sends a value not listed in this table.
PROGRAMMING INFORMATION for IMAOS08
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5.3 COMMAND DESCRIPTION
Each command description contains two parts: Command Parame-
ters and Command Reply. In the Command Parameters part, a figure is
used to illustrate the byte sequence of the parameters. All the parameter
descriptions are listed below the figure. In the Command Reply part,
another figure is used to illustrate the reply sequence in the reply
message. The reply description is listed below the figure. For detailed
information about the packet of command message and reply message,
refer to page 31.
Table-17 ConfigDev Command (Encoding: 01H)
This is the first command to be issued. If this command is not issued, the default value will be used.
Command Parameters
1-2
3
4
5
6
7
8
SysClk
Tin
Texit
No
TCWorkMode
TCAlpha&Delta
TCLCD_Threshold
Byte Sequence
Parameter Name
Default
Description
1-2
SysClk
4E20H
SysClk=Frequency of System Clock (Hz)/1000. For example, if the system clock is 20 MHz, this value
would be 20000.
Unit: sys-ticks in 1 ms (MSB first)
Note: Wrong configuration will make IMAOS’s timer work improperly.
3
4
Tin
2H
Timer of entering failure alarm state. When a defect persists for a period set by this timer, the
IDT82V2608 will enter failure alarm state.
Unit: 1 s
Texit
0AH
Timer of exiting failure alarm state. If a defect no longer exists for a period set by this timer, the
IDT82V2608 will exit failure alarm state.
Unit: 1 s
5
6
No
0H
7H
Reserved. Write 0 to this field.
TCWorkMode
Bit Position
Description
7~3
2
Don’t Care
1: Enable Tx TC scrambling (default);
0: Disable Tx TC scrambling
1
0
1: Enable Rx TC HEC error correct control (default);
0: Disable Rx TC HEC error correct control
1: Enable Rx TC de-scrambling (default);
0: Disable Rx TC de-scrambling
7
TCAlpha&Delta
67H
Bit Position
Description
Delta value. Valid is 0~15.
7-4
3-0
Alpha value. Valid is 0~15.
Alpha value is the number of consecutive incorrect HEC fields for the Rx cell synchronization state
machine to exit sync state.
Delta value is the number of consecutive correct HEC fields for the Rx cell synchronization state machine
to enter sync state.
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Table-17 ConfigDev Command (Encoding: 01H) (Continued)
8
TCLCD_Threshold
68H
0~255
LCD threshold. If the OCD anomaly persists for the time set by this parameter, LCD defect will be
reported.
Unit: one cell’s transmission time
Command Reply
1
Ack
Byte Sequence
Reply Name
Description
1
Ack
0: OK;
1: Invalid parameter (length of the command is incorrect);
Others: Internal error. The chip should be reset.
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Table-18 ConfigUtopiaIF Command (Encoding: 03H)
Command Parameters
1-4
5-8
Rx Utopia port enable
Tx Utopia port enable
Byte Sequence
Parameter Name
Default
Description
1-4
Tx Utopia port
enable
00000000H Every bit of the 4 bytes enables a Utopia Tx port
(MSB byte first, LSB byte last).
0: Disable the port;
1: Enable the port
This 4 bytes parameter enables or disables each of the 31 Utopia port (port 31 is reserved and should not
be used). The 4 bytes can be regarded as a sequence of 32 bits. The most significant bit in byte 1 (the
first byte sent to embedded controller) is bit 31. The least significant bit of byte 4 (the last byte sent) is bit
0.
5-8
Rx Utopia port
enable
00000000H Every bit of the 4 bytes enables a Utopia Rx port
(MSB byte first, LSB byte last).
0: Disable the port;
1: Enable the port
The meaning of this parameter is similar to the Utopia Tx port enable field. See above.
Command Reply
1
Ack
Byte Sequence
Reply Name
Description
1
Ack
0: OK;
1: Invalid parameter (length of the command is incorrect);
Others: Internal error. The chip should be reset.
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Table-19 ConfigLoopMode Command (Encoding: 04H)
Command Parameters
1
Loop mode
Byte Sequence
Parameter Name
Default
Description
1
Loop mode
0H
0: Disable all the loopback functions;
1: Enable line interface internal loopback mode;
2: Enable line interface external loopback mode;
3: Enable Utopia loopback mode;
Others: The same as 0.
Command Reply
1
Ack
Byte Sequence
Reply Name
Description
1
Ack
0: OK;
1: Invalid parameter (length of the command is incorrect);
Others: Internal error. The chip should be reset.
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Table-20 ConfigGroupPara Command (Encoding: 05H)
This is the first command to configure a physical group. Other configuration commands prior to this command would make the group work improperly.
Command Parameters
1
2
3
4
5-6
7
8
9
Group ID
NE IMA ID
M for Tx (Mtx)
Acceptable M for Max delay com- Version Backward
Ptx
Prx
Rx (Mrx)
pensation value
Compatibility
Byte Sequence
Parameter Name
Default
Description
1
Group ID
NA
(Not Avail-
able)
The physical group ID (0~3)
This is the physical identification of an IMA group. Each Group ID is unique in the IDT82V2608 and
should not be equal to any Channel ID that has been assigned to a UNI link. There are altogether 4 phys-
ical groups. This group ID can be any value from 0~3. Note that this Group ID is not the same as IMA ID
which is used to identify a logical IMA group and can be any value from 0~255.
2
3
NE IMA ID
0H
0H
0~255
This is the logical ID of a physical IMA group, which is packaged in ICP cells and is sent to the FE to indi-
cate which group a link belongs to.
M for Tx (Mtx)
0: 32 (default);
1: 64;
2: 128;
3: 256
This is the IMA frame length that this group will use at the transmit end. There are altogether 4 frame
lengths that can be selected: 32, 64, 128 and 256.
Note: Mtx must be right, otherwise IMAOS will work improperly.
4
Acceptable M for
Rx (Mrx)
NA
Bit
Meaning
3
1: Accept M=256
0: Do not accept M=256
2
1
0
1: Accept M=128
0: Do not accept M=128
1: Accept M=64
0: Do not accept M=64
1: Accept M=32
0: Do not accept M=32
This is the acceptable IMA frame length of the receive end.
Note: Mrx must be right, otherwise IMAOS will work improperly.
5-6
Max delay compen-
sation value
NA
NA
0~1024 cells
This is the maximum cells delay that can be tolerated.
This value is constrained by the size of the external SRAM and it shall be no more than 1024 cells. Refer
to 3.4 SRAM Interface.
Note: If the value exceeds 1024, IMAOS will work improperly.
7
Version Backward
Compatibility
0: No;
1: Yes
Version backward compatibility indicates whether version 1.0 is supported when the FE’s group is using
IMA 1.0. By default, the chip works in version 1.1 and does not support backward compatibility.
PROGRAMMING INFORMATION for IMAOS08
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Table-20 ConfigGroupPara Command (Encoding: 05H) (Continued)
8
Ptx
NA
1~8
The minimum number of active Tx links for the GSM to move to operational state. This implies that the Tx
links to be configured should be no less than this number.
Note: If this value is larger than the link numbers that will be added later, this IMA group’s state machine
will stop at Insufficient-Link state.
9
Prx
NA
1~8
The minimum number of active Rx links for the GSM to move to operational state. This implies that the Rx
links to be configured should be no less than this number.
In SCSO mode, if Prx is not equal to Ptx, Ptx is used as Prx.
Note: If this value is larger than the link numbers that will be added later, this IMA group’s state machine
will stop at Insufficient-Link state.
Command Reply
1
Ack
Byte Sequence
Reply Name
Description
1
Ack
0: OK;
1: Invalid parameter;
Others: Internal error. The chip should be reset.
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Table-21 ConfigGroupInterFace Command (Encoding: 06H)
This command should follow the ConfigGroupPara command.
Command Parameters
1
2
3
Group ID
Tx Utopia port
Rx Utopia port
Byte Sequence
Parameter Name
Default
Description
1
Group ID
NA
The physical group ID (0~3).
This is the same Group ID in ConfigGroupPara command.
2
Tx Utopia port
Rx Utopia port
1FH
0~30
The Utopia port address for data transmit. Port 31 is reserved and should not be used.
Note: The upper 3 bits are Don’t Care.
3
1FH
0~30
The Utopia port address for data receive. Port 31 is reserved and should not be used.
Note: The upper 3 bits are Don’t Care.
Command Reply
1
Ack
Byte Sequence
Reply Name
Description
1
Ack
0: OK;
1: Invalid parameter;
2: The physical group is not configurable (should issue ConfigGroupPara command first);
Others: Internal error. The chip should be reset.
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Table-22 ConfigGroupWorkMode Command (Encoding: 07H)
This should be the third command issued to configure a group, i.e., this command should follow ConfigGroupInterface command.
Command Parameters
1
2
3
4
Group ID
Symmetry mode
Stuff mode
Stuff adv mode
Byte Sequence
Parameter Name
Default
Description
1
Group ID
NA
The physical group ID (0~3).
This is the same Group ID in ConfigGroupPara command.
2
3
Symmetry mode
Stuff mode
NA
0: SCSO (Symmetrical Configuration and Symmetrical Operation);
1: SCAO (Symmetrical Configuration and Asymmetrical Operation);
2: ACAO (Asymmetrical Configuration and Asymmetrical Operation)
Note: Value exceeding 2 will be regarded as 0.
1H
1H
0: ITC (Independent Transmit Clock stuff insertion);
1: CTC (Common Transmit Clock stuff insertion)
If at least one of the links uses independent clock pin as its clock input, stuff mode can only be set as ITC.
If all the links within the group use common clock pin (i.e., TSCCK and RSCCK) as their clock input, stuff
mode can be set as either CTC or ITC.
Note: Wrong configuration will lead to wrong ICP cells.
4
Stuff adv mode
0: Pre-notify the stuff event 1 frame ahead;
1: Pre-notify the stuff event 4 frames ahead.
ICP stuff cell indication. It tells the FE the distance (unit is IMA frame) between the current ICP cell and
the forthcoming stuff ICP cell.
Note: The upper 7 bits are Don’t Care.
Command Reply
1
Ack
Byte Sequence
Reply Name
Description
1
Ack
0: OK;
1: Invalid parameter;
2: The physical group is not configurable;
Others: Internal error. The chip should be reset.
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Table-23 ConfigGSMTimers Command (Encoding: 08H)
Command Parameters
1
2
3
4
5
Group ID
Timer for GSM start- Timer for GSM Con-
up Ack figure Abort
Timer for GSM to
report Rx=Active
Timer for GSM to
report Tx=Active
Byte Sequence
Parameter Name
Default
Description
1
2
Group ID
NA
4H
Any value is OK. All the groups in the device share the same Timer values.
Timer for GSM
start-up Ack
1~255
Unit: 250 ms
This timer will start when the GSM enters start-up Ack state. If there is no response from the FE after a
period set by this timer, the GSM will return from start-up Ack to start-up state.
If 0 is sent, it will be interpreted as 1*250 ms by the embedded controller.
3
Timer for GSM
Configure Abort
4H
4H
4H
1~255
Unit: 250 ms
This timer will start when the GSM enters start-up Abort state. After a period set by this timer, the GSM
will return to start-up state.
If 0 is sent, it will be interpreted as 1*250 ms by the embedded controller.
4
Timer for GSM to
report Rx=Active
1~255
Unit: 250 ms
This timer will start when all the Rx links are reported Usable. If either all the configured links are being
reported Tx=Usable by the FE or the timer expires, all the Rx links will be brought to Active state.
If 0 is sent, it will be interpreted as 1*250 ms by the embedded controller.
5
Timer for GSM to
report Tx=Active
1~255
Unit: 250 ms
This timer will start when all the Tx links are reported Usable. If either all the configured links are being
reported Rx=Active by the FE or the timer expires, all the Tx links will be brought to Active state.
If 0 is sent, it will be interpreted as 1*250 ms by the embedded controller.
Command Reply
1
Ack
Byte Sequence
Reply Name
Description
1
Ack
0: OK;
1: Invalid parameter;
2: The physical group is not configurable;
Others: Internal error. The chip should be reset.
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Table-24 ConfigTRLLink Command (Encoding: 09H)
Command Parameters
1
2
Group ID
TxTRL
Byte Sequence
Parameter Name
Default
Description
1
Group ID
NA
The physical group ID (0~3).
This is the same Group ID in ConfigGroupPara command.
2
TxTRL
0H
0~7
The TRL link selected for this group. Data on TSD1 pin is deemed data on Tx link 0; Data on TSD2 pin is
deemed data on Tx link 1 and so on.
This link should have been added to the group, otherwise the group will fail to start up. If the TRL link has
been configured previously, this command is used to change the TRL link.
Command Reply
1
Ack
Byte Sequence
Reply Name
Description
Ack
0: OK;
1: Invalid parameter;
2: The physical group is not configurable;
Others: Internal error. The chip should be reset.
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Table-25 ConfigIFSMPara Command (Encoding: 0AH)
Command Parameters
1
2
Group ID
Alpha&Beta&Gamma
Byte Sequence
Parameter Name
Default
Description
1
Group ID
NA
The physical group ID (0~3).
This is the same Group ID in ConfigGroupPara command.
2
Alpha&Beta&Gam
ma
91H
Bit
Meaning
Alpha value. Default is 2.
7-6
5-3
2-0
Beta value. Default is 2.
Gamma value. Default is 1.
Alpha value is the number of consecutive invalid ICP cells for the IFSM state machine to exit SYNC state.
Beta is the number of consecutive errored ICP cells for the IFSM state machine to exit SYNC state.
Gamma is the number of consecutive valid ICP cells for the IFSM state machine to enter SYNC state.
Command Reply
1
Ack
Byte Sequence
Reply Name
Description
1
Ack
0: OK;
1: Invalid parameter;
2: The physical group is not configurable;
Others: Internal error. The chip should be reset.
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Table-26 AddTxLink Command (Encoding: 0BH)
Command Parameters
1
2
3
4
5
6
7
Group ID
Tx link physical ID
Tx line interface
Work Mode
Tx line interface
clock
Tx link logical ID
Tx link ICP offset
Backup function
Byte Sequence
Parameter Name
Default
Description
1
Group ID
NA
The physical group ID (0~3).
This is the same Group ID in ConfigGroupPara command.
2
3
4
Tx link physical ID
NA
0FH
0H
0~7
The Tx link that will be configured to this group. Data on TSD1 pin is deemed data on Tx link 0; Data on
TSD2 pin is deemed data on Tx link 1 and so on.
Note: If the value exceeds 7, IMAOS will work improperly.
Tx line interface
Work Mode
Mode0~Mode15
Line interface Work Mode for this link.
Note: If the value exceeds 15, IMAOS will work improperly.
Tx line interface
clock
0: Common Clock Mode;
1: Independent Clock Mode
Line interface clock input mode. The line interface mode7~mode10 and mode14~mode15 cannot be
used in Independent Clock Mode.
Note: IMAOS does not check this value. Value exceeding 1 will cause wrong configuration.
5
6
7
Tx link logical ID
Tx link ICP offset
Backup function
0H
0H
NA
0~31
The logical Tx link # designated to that physical link. It is used for Tx ICP cell.
Note: IMAOS does not check this value. If this value is wrong, IMAOS will work improperly.
The ICP offset over that Tx link
The ICP cell offset of the IMA frame on that link. This value should be smaller than the Tx frame length.
Note: If this value is wrong, IMAOS will work improperly.
0: No;
1: Yes
Whether this is a backup link or not. When other links failed, this link will be automatically added to the
group.
Note1: Only one backup link is supported in each group. If several links are specified as backup links,
only the last added backup link is regarded as a backup link.
Note2: If a backup link is added after the StartGroup or StartLASR command, a StartLASR command
should be issued to make this backup link take effect.
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Table-26 AddTxLink Command (Encoding: 0BH) (Continued)
Command Reply
1
Ack
Byte Sequence
Reply Name
Description
Ack
0: OK;
1: Invalid parameter;
2: The physical group is not configurable;
3: Tx physical link is used by other groups;
4: Tx ICP offset is larger than M;
5: Link logical ID is used by other links in this group;
Others: Internal error. The chip should be reset.
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Table-27 AddRxLink Command (Encoding: 0CH)
Command Parameters
1
2
3
4
5
Group ID
Rx link physical ID
Rx line interface
Work Mode
Rx line interface
clock
Backup function
Byte Sequence
Parameter Name
Default
Description
1
Group ID
NA
The physical group ID (0~3).
This is the same Group ID in ConfigGroupPara command.
2
3
4
Rx link physical ID
NA
0~7
The Rx link that will be configured to this group. Data on RSD1 pin is deemed data on Rx link 0; Data on
RSD2 pin is deemed data on Rx link 1 and so on.
Note: If the value exceeds 7, IMAOS will work improperly.
Rx line interface
Work Mode
0FH
0H
Mode0~mode15
Line interface Work Mode for this link.
Note: If the value exceeds 15, IMAOS will work improperly.
Rx line interface
clock
0: Common Clock Mode;
1: Independent Clock Mode
Line interface clock input mode. The line interface mode7~mode10 and mode14~mode15 cannot be
used in Independent Clock Mode.
Note: IMAOS does not check this value. Value exceeding 1 will cause wrong configuration.
5
Backup function
NA
0: No;
1: Yes
Whether this is a backup link or not. When other links fail, this link will be automatically added to the
group.
Note: Only one backup link is supported in each group. If several links are specified as backup links, only
the last added backup link is regarded as a backup link.
Command Reply
1
Ack
Byte Sequence
Reply Name
Description
1
Ack
0: OK;
1: Invalid parameter;
2: The physical group is not configurable;
3: The Rx physical link is used by other groups;
Others: Internal error. The chip should be reset.
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Table-28 ConfigUNILink Command (Encoding: 0DH)
Command Parameters
1
2
3
4
5
6
Channel ID
Link physical #
Tx Utopia Port
Rx Utopia Port
link line interface
Work Mode
link line interface
clock
Byte Sequence
Parameter Name
Default
Description
1
Channel ID
NA
0~7
The internally used channel for this UNI link. Each Channel ID is unique and should not be equal to any
Group ID that has been assigned. It is recommended that Channel ID be used from 7 down to 0. As a
Group ID is from 0 to 3, it is better for a Channel ID to be from 4 to 7 unless all the values from 4 to 7 are
taken.
2
3
4
5
6
Link physical #
Tx Utopia Port
Rx Utopia Port
NA
1FH
1FH
0FH
0H
0~7
The physical link to be used in UNI mode.
Note: If the value exceeds 7, the performance cannot be guaranteed.
0~30
The Utopia port address for data transmit. Port 31 is reserved and should not be used.
Note: The upper 3 bits are Don’t Care.
0~30
The Utopia port address for data receive. Port 31 is reserved and should not be used.
Note: The upper 3 bits are Don’t Care.
link line interface
Work Mode
Mode0~mode15
Line interface Work Mode for this link.
Note: If the value exceeds 15, IMAOS will work improperly.
link line interface
clock
0: Common Clock Mode;
1: Independent Clock Mode
Line interface clock input mode. The line interface mode7~mode10 and mode14~mode15 cannot be
used in Independent Clock Mode.
Note: IMAOS does not check this value. Value exceeding 1 will cause wrong configuration.
Command Reply
1
Ack
Byte Sequence
Reply Name
Description
1
Ack
0: OK;
1: The link is busy or Channel ID is over 15;
Others: Internal error. The chip should be reset.
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Table-29 StartGroup Command (Encoding: 0EH)
This command is used to start a configured group.
Command Parameters
1
Group ID
Byte Sequence
Parameter Name
Default
Description
The valid physical group that has been configured.
1
Group ID
NA
This is the same Group ID in ConfigGroupPara command.
Command Reply
1
Ack
Byte Sequence
Reply Name
Description
1
Ack
0: Acknowledge;
1: Invalid parameter;
2: The group is not configured;
Others: Internal error. The chip should be reset.
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Table-30 StartLASR Command (Encoding: 0FH)
This command is used to start LASR procedure on one or more links. The links here may be new links or links with failure/fault/inhibiting condition. This command may
combine with AddTxLink and AddRxLink commands.
Command Parameters
1
Group ID
Byte Sequence
Parameter Name
Default
Description
1
Group ID
NA
The physical group ID (0~3).
Valid physical group that has been configured and is in OPERATIONAL state.
Command Reply
1
Ack
Byte Sequence
Reply Name
Description
1
Ack
0: Acknowledge;
1: Invalid parameter;
2: The group is not configured;
3: The Previous LASR is not finished;
Others: Internal error. The chip should be reset.
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Table-31 InhibitGrp Command (Encoding: 10H)
This command is used to inhibit a group. Once a group is inhibited by this command, it will go to BLOCKED state instead of the OPERATIONAL state when sufficient
links exist in the group. If the group is already in OPERATIONAL state, the GSM will transition to BLOCKED state.
Command Parameters
1
Group ID
Byte Sequence
Parameter Name
Default
Description
1
Group ID
NA
The physical group ID (0~3).
The physical group to be inhibited.
Command Reply
1
Ack
Byte Sequence
Reply Name
Description
1
Ack
0: Acknowledge;
1: Invalid parameter;
Others: Internal error. The chip should be reset.
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Table-32 NotInhibitGrp Command (Encoding: 11H)
This command is used to clear the inhibiting status. If a group is in BLOCKED state, the GSM will go to OPERATIONAL state.
Command Parameters
1
Group ID
Byte Sequence
Parameter Name
Default
Description
1
Group ID
NA
The physical group ID (0~3).
The physical group to be uninhibited.
Command Reply
1
Ack
Byte Sequence
Reply Name
Description
1
Ack
0: Acknowledge;
1: Invalid parameter;
Others: Internal error. The chip should be reset.
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Table-33 RestartGrp Command (Encoding: 12H)
This command is used to restart the specified group. The GSM will go back to Start-up state and all the Tx and Rx links will go back to Unusable state.
Command Parameters
1
Group ID
Byte Sequence
Parameter Name
Default
Description
1
Group ID
NA
The physical group ID (0~3).
The physical group to be restarted.
Command Reply
1
Ack
Byte Sequence
Reply Name
Description
1
Ack
0: Acknowledge;
1: Invalid parameter;
2: The group is not configured;
Others: Internal error. The chip should be reset.
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Table-34 DeleteGrp Command (Encoding: 13H)
This command is used to delete the specified group and all its links at once. Upon the issue of this command, the GSM will go back to Not Configured state and all the
links will transition to Not In Group state.
Command Parameters
1
Group ID
Byte Sequence
Parameter Name
Default
Description
1
Group ID
NA
The physical group ID (0~3).
The physical group to be deleted.
Command Reply
1
Ack
Byte Sequence
Reply Name
Description
1
Ack
0: Acknowledge;
1: Invalid parameter (length of the command is incorrect or Group ID is over 3);
Others: Internal error. The chip should be reset.
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Table-35 RecoverLink Command (Encoding: 14H)
This command is used to tell the IDT82V2608 that a link is no longer in fault state or cancel the inhibition made by “DeactLink” command. This command should com-
bine with a “StartLASR” command in order to recover the link physically.
Command Parameters
1
2
3
Group ID
Link physical ID
Direction
Byte Sequence
Parameter Name
Default
Description
1
Group ID
NA
NA
NA
The physical group ID (0~3).
The physical group that contains the link to be recovered by this command.
2
3
Link physical ID
Direction
0~7
The physical link to be recovered. The link should belong to the group, and was previously deactivated.
0: Rx;
1: Tx;
2: Both
Note1: If the group is in symmetry mode, both links should be recovered;
Note2: If the value exceeds 2, IMAOS will work improperly.
Command Reply
1
Ack
Byte Sequence
Reply Name
Description
1
Ack
0: OK;
1: Invalid parameter;
2: The link does not belong to that group;
Others: Internal error. The chip should be reset.
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Table-36 DeleteLink Command (Encoding: 15H)
This command is used to delete a link from a group.
Command Parameters
1
2
3
Group ID /Channel ID
Link physical ID
Direction
Byte Sequence
Parameter Name
Default
Description
The physical group ID (0~3) or Channel ID (0~7).
1
Group ID /Channel
ID
NA
The physical group that contains the link to be deleted or Channel ID of the UNI link to be deleted.
2
3
Link physical ID
NA
NA
0~7
Physical link to be deleted. The link should belong to the group.
Direction
0: Rx;
1: Tx;
2: Both
Note1: If the group is in symmetry mode, both directions are deleted and the direction value is ignored. If
it is a UNI link, this parameter is ignored.
Note2: If the value exceeds 2, IMAOS will work improperly.
Command Reply
1
Ack
Byte Sequence
Reply Name
Description
1
Ack
0: Acknowledge;
1: Invalid parameter;
2: The link does not belong to that group;
Others: Internal error. The chip should be reset.
After the link has both ends deleted, the link is in UNI mode, which is the default Work Mode of a link. The “GetLink-
State” command can be used to poll the link state.
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Table-37 DeactLink Command (Encoding: 16H)
This command is to make a link go to Unusable state due to user defined fault condition or that user just wants to inhibit it.
Command Parameters
1
2
3
4
Group ID
Link physical ID
Reason
Direction
Byte Sequence
Parameter Name
Default
Description
1
Group ID
NA
The physical group ID (0~3)
The physical group that contains the link to be deactivated by this command.
2
Link physical ID
NA
0~7
Physical link to be deactivated. The link should belong to the group.
Note: If the value exceeds 7, the performance cannot be guaranteed.
3
4
Reason
NA
NA
0: Inhibition; 1: Fault
Direction
0: Rx;
1: Tx;
2: Both
Note1: If the group is in symmetry mode, both directions are deactivated and the direction value is
ignored.
Note2: If the value exceeds 2, IMAOS will work improperly.
Command Reply
1
Ack
Byte Sequence
Reply Name
Description
1
Ack
0: Acknowledge;
1: Invalid parameter;
2: The link does not belong to that group;
Others: Internal error. The chip should be reset.
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Table-38 GetGroupState Command (Encoding: 17H)
Command Parameters
1
Group ID
Byte Sequence
Parameter Name
Description
1
Group ID
The physical group ID (0~3).
Command Reply
1
2
3
4
Ack
NEGSMState
FEGSMState
NEGTSMState
Byte Sequence
Reply Name
Description
1
Ack
0: Acknowledge;
1: Invalid parameter;
2: Information not available;
Others: Internal error. The chip should be reset.
Note: If Ack is not equal to 0, values for the following fields will not be returned.
2
3
4
NEGSMState
FEGSMState
NEGTSMState
Bits 3:0: NE Group State
0000: Start-up;
0001: Start-up-Ack;
0010: Config-Aborted - Unsupported M;
0011: Config-Aborted - Incompatible Group Symmetry;
0100: Config-Aborted - Unsupported IMA Version;
0101, 0110: Reserved for other Config-Aborted reasons in a future version of the IMA specification;
0111: Config-Aborted - Other reasons;
1000: Insufficient-Links;
1001: Blocked;
1010: Operational;
Others: Reserved for later use in a future version of the IMA specification.
Bits 3:0: FE Group State
0000: Start-up;
0001: Start-up-Ack;
0010: Config-Aborted - Unsupported M;
0011: Config-Aborted - Incompatible Group Symmetry;
0100: Config-Aborted - Unsupported IMA Version;
0101, 0110: Reserved for other Config-Aborted reasons in a future version of the IMA specification;
0111: Config-Aborted - Other reasons;
1000: Insufficient-Links;
1001: Blocked;
1010: Operational;
Others: Reserved for later use in a future version of the IMA specification.
0: GTSM is down;
1: GTSM is up.
NE GTSM state.
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Table-39 GetGroupDelayInfo Command (Encoding: 18H)
Command Parameters
1
Group ID
Byte Sequence
Parameter Name
Description
1
Group ID
The physical group ID (0~3).
Command Reply
1
2-3
Ack
MaxDiffDelayOfGroupLinks
Byte Sequence
Reply Name
Description
1
Ack
0: Acknowledge;
1: Invalid parameter;
2: The info is not available;
Others: Internal error. The chip should be reset.
Note: If Ack is not equal to 0, the value for the following field will not be returned.
2-3
MaxDiffDelayOf- The maximum delay value between any two links in that group. (MSB byte first)
GroupLinks (cells)
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Table-40 GetLinkState Command (Encoding: 19H)
Command Parameters
1
Physical link #
Byte Sequence
Parameter Name
Description
1
Physical link #
0~7
The # of the physical link.
Command Reply
1
2
3
4
5
6
7
Ack
NERxState
NETxState
FERxState
FETxState
TC State
IMA SYNC State
Byte Sequence
Reply Name
Description
1
Ack
0: Acknowledge;
1: Invalid parameter;
Others: Internal error. The chip should be reset.
Note1: For a UNI link, only the TC State value is meaningful. Other values are all meaningless.
Note2: If Ack is not equal to 0, values for the following fields will not be returned.
2
NERxState
0x00: not in any group;
0x01: Unusable-No-reason;
0x02: Unusable-Fault;
0x03: Unusable-Misconnected;
0x04: Unusable-Inhibited;
0x05: Unusable-Failed;
0x06: Usable;
0x07: Active.
The NE Rx LSM State.
The same as above.
3
4
5
6
7
NETxState
FERxState
FETxState
TC State
The NE Tx LSM State.
The same as above.
The FE Rx LSM State.
The same as above.
The FE Tx LSM State.
Bit2:
0: Not TC sync;
1: TC sync.
Other bits: Don’t Care
IMA Sync State
Bit5: 0: Not IMA sync state;
1: IMA sync state.
Other bits: Don’t Care
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Table-41 GetGrpPerf Command (Encoding: 1AH)
Command Parameters
1
Group ID
Byte Sequence
Parameter Name
Description
1
Group ID
The physical group ID (0~3).
Command Reply
1
2-3
Ack
Value
Byte Sequence
Reply Name
Description
1
Ack
0: Acknowledge;
1: Invalid parameter;
2: Info not available;
Others: Internal error. The chip should be reset.
Note: If Ack is not equal to 0, the value for the following field will not be returned.
2-3
Value
value of GR-UAS-IMA (For detailed definition, refer to Table-51)
(MSB byte first)
If Ack is equal to 0, the value of IMAGrpUnavaiSec will be returned. If the performance parameter is not retrieved after a
long period, it might reach the maximum value. In this case, the value is held.
If Ack is not 0, the value will be 0.
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Table-42 GetLinkPerf Command (Encoding: 1BH)
Command Parameters
1
2
Physical link #
Type
Byte Sequence
Parameter Name
Description
1
Physical link #
0~7
The # of the physical link.
2
Type
The performance types (For detailed description of these performance types, please refer to Table-51):
Performance Type
Parameters
0
SES-IMA
SES-IMA-FE
UAS-IMA
UAS-IMA-FE
Tx-UUS-IMA
Rx-UUS-IMA
Tx-UUS-IMA-FE
Rx-UUS-IMA-FE
OCD_TC
1
2
3
HCS_ERR_TC
IV-IMA
Rx-Stuff-IMA
Tx-Stuff-IMA
OIF-IMA
Command Reply
1
2-10
Ack
Value
Byte Sequence
Reply Name
Description
1
Ack
0: Acknowledge;
1: Invalid parameter;
2: Info not available;
Others: Internal error. The chip should be reset.
Note: If Ack is not equal to 0, the value for the following field will not be returned.
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Table-42 GetLinkPerf Command (Encoding: 1BH) (Continued)
2-10
Value
The counter value of the performance parameter according to Type (MSB first).
The returned value occupies 9 bytes. Different parameters take different number of bytes.
Performance Type
Parameters
Bytes
0
SES-IMA
SES-IMA-FE
UAS-IMA
2
2
2
2
1
2
2
2
2
1
3
3
3
3
3
3
UAS-IMA-FE
0
1
Tx-UUS-IMA
Rx-UUS-IMA
Tx-UUS-IMA-FE
Rx-UUS-IMA-FE
0
2
3
OCD_TC
HCS_ERR_TC
IV-IMA
Rx-Stuff-IMA
Tx-Stuff-IMA
OIF-IMA
Note: If the performance parameters are not retrieved after a long period, they might reach the maximum value. In this
case, the values are held.
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Table-43 GetConfigPara Command (Encoding: 1CH)
This command is used to get the parameters as shown in the parameter list of a command (designated by Command ID), i.e., get the configured information or default
information as a command’s parameter list designated.
Command Parameters
1
2
Command ID
Group ID
Byte Sequence
Parameter Name
Description
1
Command ID
The command encoding of the commands below:
• ConfigDev
• ConfigUTOPIAIF
• ConfigLoopMode
• ConfigGroupPara
• ConfigGroupInterface
• ConfigGroupWorkMode
• ConfigGSMTimers
• ConfigTRL
• ConfigIFSMpara
Note: If the value is not one from above, IMAOS will work improperly.
2
Group ID
The Group ID (If command ID is ‘ConfigDev’, do not care this parameter, that is, any value will do.)
If the command (such as ConfigDev command) has no Group ID parameter, this field should be set to 0 and will be
ignored by the embedded controller.
Command Reply
1
2
3
4-12
Ack
Command ID sent before
Group ID sent before
Parameter sent before
Byte Sequence
Reply Name
Description
1
Ack
0: Acknowledge;
1: Invalid parameter;
2: Info not available;
Others: Internal error. The chip should be reset.
Note1: If Ack is not equal to 0, values for the following fields will not be returned.
Note2: If Ack for this command is equal to 0 but the Ack for the command sent before is not equal to 0, values for the
following fields are undetermined.
2
3
Command ID sent The command ID sent before.
before
Group ID sent
before
The Group ID sent before.
For ConfigDev command, this byte has no meaning.
4-12
Parameter sent
before
This field contains all the parameters that were sent previously excluding the Group ID, as it is returned in byte 3.
The length of this field depends on the Command ID and the sequence is the same as the input.
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Table-44 GetGrpWorkingPara Command (Encoding: 1DH)
Command Parameters
1
Group ID
Byte Sequence
Parameter Name
Description
1
Group ID
The physical group ID (0~3).
Command Reply
1
2
3
4
5
6
7
8
Ack
NE IMA ID
FE IMA ID
Mtx
Mrx
Version now used
Tx TRL
Rx TRL
Byte Sequence
Reply Name
Description
1
Ack
0: Acknowledge;
1: Invalid parameter;
2: Info not available;
Others: Internal error. The chip should be reset.
Note: If Ack is not equal to 0, values for the following fields will not be returned.
2
3
4
5
6
NE IMA ID
FE IMA ID
Mtx
The IMA ID in the ICP cell transmitted to the FE from the NE.
The IMA ID in the ICP cell that the NE received from the FE.
The IMA frame length the NE is using.
Mrx
The IMA frame length the FE is using.
Version now used 0: Both ends are 1.1;
1: The FE is 1.0 and the NE is 1.0 compatible.
7
8
Tx TRL
Rx TRL
The physical link # used for Tx TRL.
The physical link # the FE used for TRL.
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Table-45 GetLinkWorkingPara Command (Encoding: 1EH)
Command Parameters
1
Physical link #
Byte Sequence
Parameter Name
Description
1
Physical link #
0~7.
The # of the physical link.
Command Reply
1
2
3
4
5
6
Ack
Mode
Group ID /UNI mode
Utopia Tx port
TxLink ID / UNI
mode Utopia Rx port
RxLink ID
Tx ICP offset
Byte Sequence
Reply Name
Description
1
Ack
0: Acknowledge;
1: Invalid parameter;
2: Info not available;
Others: Internal error. The chip should be reset.
Note: If Ack is not equal to 0, values for the following fields will not be returned.
2
Mode
0: UNI;
1: IMA mode – Only Rx used;
2: IMA mode – Only Tx used;
3: IMA mode – Both Tx and Rx are used.
3
4
Group ID /UNI
mode Utopia Tx
port
If Mode is IMA, this value means which physical group at the NE the link belongs to;
If mode is UNI, this value is the Utopia Tx port address.
TxLink ID / UNI
mode Utopia Rx
port
If Mode is IMA, this value means the logical link # assigned (0~31),
If mode is UNI, this value is the Utopia Rx port address.
5
6
RxLink ID
The logical link ID the FE is using.
Tx ICP offset
0~255 (in IMA mode; not used in UNI mode).
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Table-46 StartTestPattern Command (Encoding: 1FH)
Command Parameters
1
2
3
Group ID
Physical link #
Pattern
Byte Sequence
Parameter Name
Description
1
2
Group ID
The physical group ID (0~3)
Physical link #
0~7
The # of the physical link.
3
Pattern
0~FFH, and FFH is not recommended.
This byte is used to define the pattern for testing purpose.
Command Reply
1
Ack
Byte Sequence
Reply Name
Description
Ack
0: Acknowledge;
1: Invalid parameter;
2: The link does not belong to the group;
Others: Internal error. The chip should be reset.
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Table-47 GetLoopedTestPattern Command (Encoding: 20H)
Command Parameters
1
2
Group ID
Physical link #
Byte Sequence
Parameter Name
Description
1
2
Group ID
The physical group ID (0~3)
Physical link #
0~7
The # of the physical link.
Command Reply
1
2
Ack
Pattern
Byte Sequence
Reply Name
Description
Ack
1
0: Acknowledge;
1: Invalid parameter;
2: The link does not belong to the group;
Others: Internal error. The chip should be reset.
Note: If Ack is not equal to 0, the value for the following field will not be returned.
Pattern
1
The FE looped test pattern over that link
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Table-48 StopTestPattern Command (Encoding: 21H)
Command Parameters
1
Group ID
Byte Sequence
Parameter Name
Description
1
Group ID
The physical group ID (0~3)
Command Reply
1
Ack
Byte Sequence
Reply Name
Description
1
Ack
0: OK;
1: Invalid parameter;
Others: Internal error. The chip should be reset.
Table-49 GetVersionInfo Command (Encoding: 22H)
Command Parameters
No.
Command Reply
1
2
3
Ack
SW_ver_majority
SW_ver_minority
Byte Sequence
Reply Name
Description
1
Ack
0: OK;
Others: Internal error. The chip should be reset.
Note: If Ack is not equal to 0, values for the following fields will not be returned.
2
3
SW_ver_majority The integer part of the IMAOS version. For example, if the current version is 1.12, the returned value will be 1.
SW_ver_minority The fractional part of the IMAOS version. For example, if the current version is 1.12, the returned value will be 12.
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6.2 CONFIGURE A GROUP
6
IMA OPERATION
After a group is configured, an ID (IMA ID) is allocated to a physical
group, links are assigned to that group and other parameters needed for
the group’s proper operation are set. The IMA ID should not be changed
during the whole life cycle of the group except that the group is
restarted. Table-50 is the list of group parameters that should be config-
ured.
This chapter is a brief introduction of how a group and links are
configured, started, inhibited, deleted and so on.
6.1 IMA INITIALIZATION
ConfigDev command is the first command to be issued to initialize
the device. If this command is not issued, the default value will be used.
Table-50 Parameters for IMA Group Configuration
Parameter Name
Description
Group ID
The physical group ID used for this IMA group.
The IMA group logical ID#.
NE IMA ID
M for Tx (Mtx)
The frame length that the NE Tx would like to use.
Acceptable M for Rx (Mrx)
Max delay compensation value (cells)
Version Backward Compatibility
TxUtopia port
The frame length proposed by the FE Tx that the NE Rx can accept.
The maximum different link delay value a group is expected to have.
Whether IMA 1.0 is supported
The Utopia address where ATM traffic comes from
RxUtopia port
The Utopia address where ATM traffic goes
Symmetry mode
The group link’s configuration and operation mode.
Timing clock mode
The transmission timing clock mode.
Stuff mode
The SICP insertion method.
Stuff adv mode
The stuff pre-notify mode. Valid value is 1 or 4.
Timer for GSM start up Ack
Timer for GSM Configure Abort
Timer for GSM to report Rx=active
Timer for GSM to report Tx=active
Tx TRL
This is the timer for GSM to return from start-up Ack to start-up state when there is no response from the FE.
This is the timer for GSM to return from start-up Abort state to start-up state.
This is the timer for Group wide start-up procedure to report Rx=Active state.
This is the timer for Group wide start-up procedure to report Tx=Active state.
The transmit timing reference link. (Physical ID)
Alpha
The number of consecutive invalid ICP cells for the IFSM state machine to exit SYNC state. Default value is 2.
The number of consecutive errored ICP cells for the IFSM state machine to exit SYNC state. Default value is 2.
The number of consecutive valid ICP cells for the IFSM state machine to enter SYNC state. Default value is 1.
The minimum number of active Tx links for the group to enter operational state
The minimum number of active Rx links for the group to enter operational state
The physical links’ ID used for transmission.
Beta
Gamma
Ptx
Prx
All the Tx links’ physical IDs
All the Tx links’ logical IDs
All the Rx links’ physical IDs
All Tx links’ line interface Work Mode
All Rx links’ line interface Work Mode
All Tx links’ line interface clock mode
All Rx links’ line interface Work Mode
The logical link ID for each Tx link.
The physical links’ ID used for receiving.
The line interface Work Mode for each Tx link.
The line interface Work Mode for each Rx link.
The line interface clock mode for each Tx link.
The line interface clock mode for each Rx link.
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Table-50 Parameters for IMA Group Configuration (Continued)
Tx links’ ICP offsets
The ICP cell location within the IMA frame transmitted over each Tx link.
All Tx links’ backup property
All Rx links’ backup property
The Tx link added to the group is a backup link or not.
The Rx link added to the group is a backup link or not.
6.3 START UP A GROUP
6.7 DEACTIVATE AND RECOVER LINKS
A group can be started by StartGroup command. At IMA group start-
up, the NE and the FE exchange their configuration parameters. When
both ends accept the parameters proposed by the other end, they enter
an intermediate state to wait for Ptx and Prx links to enter active state.
The group can then enter operational state.
Links are deactivated because of link fault, failure (Rx failed) or inhi-
bition while links are recovered because defect no longer exists or inhibi-
tion is cancelled.
The deactivation-recovering of a link is done by the IDT82V2608
automatically according to the FE notification (Remote Failure Indicator
in ICP cell) or by the embedded controller (issue commands like
DeactLink and RecoverLink commands) due to link fault or inhibition or
no longer link fault or inhibition.
6.4 INHIBIT A GROUP/NOT INHIBIT A GROUP
The inhibition of a group is the shut down of the group for a reason
other than insufficient links.
6.8 RESTART A GROUP
A group can be inhibited by InhibitGrp command.
After a group is started, the parameters of the group can be reconfig-
ured at any time, which will cause the group to be restarted automati-
cally. However, a group can also be restarted by RestartGrp command.
When a group is restarted, the GSM transits to Start-up state from any
other states except Not Configured state. If the GSM is in Operational
state, the group may be blocked and all the links be inhibited before
restart.
A group inhibition state can be cancelled by NotInhibitGrp
command.
6.5 ADD LINKS TO A GROUP THAT IS IN OPERA-
TIONAL STATE
The LASR (Link Addition and Slow Recovery) procedure is to be
started when new links are to be inserted or links are to be recovered
from a group.
6.9 DELETE A GROUP
When a group is deleted from any other state by DeleteGrp
command, the GSM enters Not Configured state and all the links
belonging to that group will also be deleted and unassigned.
The LASR procedure can be started by StartLASR command.
6.6 DELETE LINKS
A link can be removed by DeleteLink command. The deletion proce-
dure can be initiated from both the Tx and Rx side.
IMA OPERATION
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7
PMON (PERFORMANCE MONITORING)
The PMON module uses counters for performance monitoring and
failure/alarms integration. Table-51 shows the performance parameters
that the IDT82V2608 implements. Table-53 lists the failure/alarm signals
sent by alarm messages.
Table-51 The PMON Parameters
Parameter
SES-IMA
Link/Group
Link
Definition
Retrieve
Count of NE Severely Errored Seconds.
Count of FE Severely Errored Seconds.
Count of NE UnAvailable Seconds.
Count of FE UnAvailable Seconds.
Count of NE Tx Unusable seconds.
Count of NE Rx Unusable seconds.
Count of FE Tx UnUsable Seconds.
Count of FE Rx UnUsable Seconds.
SES-IMA-FE
UAS-IMA
Link
Link
Link
Link
Link
Link
Link
Link
Link
Link
UAS-IMA-FE
Tx-UUS-IMA
Rx-UUS-IMA
Tx-UUS-IMA-FE
Rx-UUS-IMA-FE
OCD_TC
GetLinkPerf command
Count of link out of cell delineation entrances.
Count of Cell header sequence error.
Count of ICP Violations.
HCS_ERR_TC
IV-IMA
Three types of ICP invalid signals will cause the IV-IMA. They are: Errored ICP, invalid ICP and
missing ICP. (See Table-52 for definitions). The IV-IMA is counted only during Non-SES-IMA or
Non-UAS-IMA period.
Rx-Stuff-IMA
Tx-Stuff-IMA
OIF-IMA
Link
Count of received Stuff ICP cells over one link.
Link
Count of transmitted Stuff ICP cells over one link.
Link
Count of Out of IMA Frame anomalies except during SES-IMA or UAS-IMA conditions.
Count of Seconds when GTSM is down.
GR-UAS-IMA
Group
GetGrpPerf command
Table-52 Definitions of Different ICP Cells
ICP Cell Type
Definition
Errored ICP
Invalid ICP
Cell with a HEC or CRC-10 error at expected ICP frame position and is not a Missing ICP cell.
Cell with good HEC and CRC-10 and CID=ICP at expected frame position but with one of the following unexpected errors:
•
•
•
•
•
•
Unexpected IMA label
Unexpected LID
Unexpected IMA ID
Received M≠ expected M
Unexpected IMA frame sequence number
Unexpected ICP cell offset
Missing ICP
Cell located at ICP cell location with:
•
•
No HEC error but without IMA OAM cell header or
No HEC error and with IMA OAM cell header but the CID≠ ICP.
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Table-53 Failure/Alarm Signals
Sequence
Name
Link /Group
Link
Implement
Definition
01H
02H
03H
04H
05H
06H
07H
LCD
SW
SW
SW
SW
SW
SW
SW
Loss of Cell Delineation.
Loss of IMA Frame.
LIF
Link
Link
Link
Link
Link
Group
LODS
RFI-IMA
Link Out of Delay Synchronization.
Persistence of an RDI-IMA defect at the NE.
When the FE reports Tx-Unusable.
When the FE reports Rx-Unusable.
Tx-Unusable-FE
Rx-Unusable-FE
Start-up-FE
When the FE is starting-up (the declaration of this failure alarm may be delayed to
ensure the FE remains in Start-up).
08H
09H
0AH
0BH
0CH
0DH
Config-Aborted
Group
Group
Group
Group
Group
Group
SW
SW
SW
SW
SW
SW
When the FE tries to use unacceptable configuration parameters.
When the FE reports unacceptable configuration parameters.
When less than Ptx transmit or Prx receive links are Active.
When the FE reports that less than Ptx transmit or Prx receive links are Active.
When the FE reports that it is blocked.
Config-Aborted-FE
Insufficient-Links
Insufficient-Links-FE
Blocked-FE
GR-Timing-Mismatch
When the FE transmit clock mode is different from the NE transmit clock mode.
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8.2 PROGRAMMING INFORMATION FOR
IMAOS08_SLAVE
8
IMAOS08_SLAVE
The previous chapters 4, 5, 6 and 7 are specific to IMAOS08. Details
about IMAOS08_Slave are provided in this chapter.
8.2.1 COMMAND TYPES
Refer to 5.1 Command Types.
8.2.2 COMMAND ENCODING
When IMAOS08_Slave is downloaded, the device supports the
Group Auto Detect function and operates in Slave Mode.
8.1 GROUP AUTO DETECT
Table-54 Command Encoding
Command Encoding
The group auto detect function can be used to configure and start a
group from one end while forcing the other end’s group to follow this
end’s group configuration and start-up procedure, that is, the other end’s
group can be brought into operational state automatically. The two ends
are called Master Side and Slave Side separately.
Command Name
DeviceInitial
01H
02H
03H
22H
23H
ConfigSlaveFrame
ConfigUtopiaIF
GetVersionInfo
GroupInitial
8.1.1 MASTER SIDE
The Master Side should download IMAOS08 and work in symmetry
mode. Up to 4 groups can be started at the Master side.
The configuration of the Master Side is the same as that in normal
Work Mode.
8.2.3 COMMAND DESCRIPTION
Each command description contains two parts: the Command
Parameters and the Command Reply. In the Command Parameters
part, a figure is used to illustrate the byte sequence of the parameters.
All the parameters description are listed below the figure. In the
Command Reply part, a figure is used to illustrate the reply sequence in
the reply message. The reply description is listed below the figure. For
detailed information about the packet of command message and reply
message, refer to page 31.
8.1.2 SLAVE SIDE
The Slave Side should download IMAOS08_Slave.
After power-on or reset, the Slave Side should be initialized by
issuing the DeviceInitial, ConfigSlaveFrame, ConfigUtopiaIF and Grou-
pInitial commands. Only after the Slave Side has been initialized will the
Slave Side start to detect the far end’s start-up procedure.
After the far end has started up, the Slave Side will be brought into
operational state automatically without any need of local group configu-
ration and management.
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Table-55 DeviceInitial Command (Encoding: 01H)
This is the first command to be issued. If this command is not issued, the default value will be used.
Command Parameters
1-2
3
4
5
6
7
8
SysClk
Tin
Texit
No
TCWorkMode
TCAlpha&Delta
TCLCD_Threshold
Byte Sequence
Parameter Name
Default
Description
1-2
SysClk
4E20H
SysClk=Frequency of System Clock (Hz)/1000. For example, if the system clock is 20 MHz, this value
would be 20000.
Unit: sys-ticks in 1 ms (MSB first)
Note: Wrong configuration will make IMAOS_Slave’s timer work improperly.
3
4
Tin
2H
Timer of entering failure alarm state. When a defect persists for a period set by this timer, the
IDT82V2608 will enter failure alarm state.
Unit: 250 ms
Texit
0AH
Timer of exiting failure alarm state. If a defect no longer exists for a period set by this timer, the
IDT82V2608 will exit failure alarm state.
Unit: 250 ms
5
6
No
0H
7H
Reserved. Write 0 to this field.
TCWorkMode
Bit Position
Description
7~3
2
Don’t Care
1: Enable Tx TC scrambling (default);
0: Disable Tx TC scrambling
1
0
1: Enable Rx TC HEC error correct control (default);
0: Disable Rx TC HEC error correct control
1: Enable Rx TC de-scrambling (default);
0: Disable Rx TC de-scrambling
7
TCAlpha&Delta
67H
Bit Position
Description
Delta value. Valid is 0~15.
7-4
3-0
Alpha value. Valid is 0~15.
Alpha value is the number of consecutive incorrect HEC fields for the Rx cell synchronization state
machine to exit sync state.
Delta value is the number of consecutive correct HEC fields for the Rx cell synchronization state machine
to enter sync state.
8
TCLCD_Threshold
68H
0~255
LCD threshold. If the OCD anomaly persists for the time set by this parameter, LCD defect will be
reported.
Unit: one cell’s transmission time
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Table-55 DeviceInitial Command (Encoding: 01H) (Continued)
Command Reply
1
Ack
Byte Sequence
Reply Name
Description
1
Ack
0: OK;
1: Invalid parameter (length of the command is incorrect);
Others: Internal error. The chip should be reset.
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Table-56 ConfigSlaveFrame Command (Encoding: 02H)
Command Parameters
1
2
line interface Work Mode
line interface clock mode
Byte Sequence
Parameter Name
Default
Description
1
line interface
Work Mode
0FH
Mode0~mode15
Line interface Work Mode for all the links.
2
line interface
clock mode
0H
0: Common Clock Mode;
1: Independent Clock Mode
Line interface clock input mode for all the links. Line interface mode7~mode10 and mode14~mode15
cannot be used in Independent Clock Mode.
Command Reply
1
Ack
Byte Sequence
Reply Name
Description
1
Ack
0: OK;
1: Invalid parameter (length of the command is incorrect).
Others: Internal error. The chip should be reset.
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Table-57 ConfigUtopiaIF Command (Encoding: 03H)
Command Parameters
1-4
5-8
Rx Utopia port enable
Tx Utopia port enable
Byte Sequence
Parameter Name
Default
Description
1-4
Tx Utopia port
enable
00000000H Every bit of the 4 bytes enables a Utopia Tx port
(MSB byte first, LSB byte last).
0: Disable the port;
1: Enable the port
This 4 bytes parameter enables or disables each of the 31 Utopia port (port 31 is reserved and should not
be used). The 4 bytes can be regarded as a sequence of 32 bits. The most significant bit in byte 1 (the
first byte sent to embedded controller) is bit 31. The least significant bit of byte 4 (the last byte sent) is bit
0.
5-8
Rx Utopia port
enable
00000000H Every bit of the 4 bytes enables a Utopia Rx port
(MSB byte first, LSB byte last).
0: Disable the port;
1: Enable the port
The meaning of this parameter is similar to the Utopia Tx port enable field. See above.
Command Reply
1
Ack
Byte Sequence
Reply Name
Description
1
Ack
0: OK;
1: Invalid parameter (length of the command is incorrect);
Others: Internal error. The chip should be reset.
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Table-58 GetVersionInfo Command (Encoding: 22H)
Command Parameters
No.
Command Reply
1
2
3
Ack
SW_ver_majority
SW_ver_minority
Byte Sequence
Reply Name
Description
1
Ack
0: OK;
Others: Internal error. The chip should be reset.
Note: If Ack is not equal to 0, values for the following fields will not be returned.
2
3
SW_ver_majority(1) The integer part of the version. For example, if the current version is 2.12, the returned value will be 2.
SW_ver_minority The fractional part of the version. For example, if the current version is 2.12, the returned value will be 12.
1. For IMAOS08, the returned value is an odd number. For IMAOS08_Slave, the returned value is an even number.
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Table-59 GroupInitial Command (Encoding: 23H)
Command Parameters
1
2
3
4-5
Group ID
Tx Utopia port
Rx Utopia port
Max delay compensation value
Byte Sequence
Parameter Name
Default
Description
1
Group ID
NA
The physical group ID (0~3).
The Group ID follows the IMA ID of the Master Side. Note that the IMA ID of the Master Side should not
exceed 3.
2
3
Tx Utopia port
Rx Utopia port
1FH
0~30
The Utopia port address for data transmit. Port 31 is reserved and should not be used.
Note: The upper 3 bits are Don’t Care.
1FH
NA
0~30
The Utopia port address for data receive. Port 31 is reserved and should not be used.
Note: The upper 3 bits are Don’t Care.
4-5
Max delay compen-
sation value
0~1024 cells
This is the maximum cells delay that can be tolerated.
This value is constrained by the size of the external SRAM and it shall be no more than 1024 cells. Refer
to 3.4 SRAM Interface.
Note: If the value exceeds 1024, IMAOS_Slave will work improperly.
Command Reply
1
Ack
Byte Sequence
Reply Name
Description
1
Ack
0: OK;
1: Invalid parameter;
Others: Internal error. The chip should be reset.
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9.2 INSTRUCTIONS
9
JTAG TEST ACCESS PORT
Meet the IEEE standard [13] which requires at least EXTEST,
BYPASS, IDCODE and SAMPLE instructions are implemented. The
IDT82V2608 identification code is 104B8067 hexadecimal.
9.1 TAP BUS SIGNALS
The interface from the board to the on-chip Test Access Port is the
TAP bus, which consists of five signals:
!
The standard bus: TDI, TDO, TCK, TMS.
!
TRST: Test reset. Reset the TAP controller. The signal is
specified as optional in the IEEE spec. TRST is an active low
signal that resets all flip-flops of TAP asynchronously.
JTAG TEST ACCESS PORT
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10 PHYSICAL AND ELECTRICAL CHARACTERISTICS
10.1 ABSOLUTE MAXIMUM RATINGS
Table-60 Absolute Maximum Ratings
Parameter
Min
Max
Storage temperature
-65 °C
-0.3 V
-0.3 V
-0.3 V
+150 °C
4.6 V
Voltage on VDD with reference to GND
Voltage on input pin
5.25 V
Voltage on output pin
VDD+0.3 V
230 °C
Maximum lead temperature for soldering during 10 s
ESD Performance (HBM)
2000 V
100 mA
Latch-up current on any pin
Maximum junction temperature
150 °C
10.2 D.C. CHARACTERISTICS
@ TA= -40 to +85°C.
Table-61 D.C. Characteristics
Parameter
VDD
Description
Core Power Supply
Min
Typ
Max
Unit
Test Conditions
2.97
3.3
3.63
0.40
V
V
VOL
VOH
VT+
VT-
Output Low Voltage
Output High Voltage
Input High Voltage(2)
Input Low Voltage
Input Hysteresis Voltage
Input Low Current
Input Low Current
Input High Current
Operating current
VDD=min, IOL=4 mA or 6 mA(1)
VDD=min, IOH= 4 mA or 6 mA
2.4
V
2.0
V
0.83
0.17
-20
-1
V
VTH
IILPU
IIL
0.65
-55
0
1.17
-200
+1
V
uA
uA
uA
mA
VIL=GND
VIL=GND
IIH
-2
0
+2
VIH=+5 V
IDDOP1
160
VDD=3.63 V, SYSClk=25 MHz
1. The output driving capacity of all the embedded memory output pins are 4mA while the output driving capacity of all the other output pins are 6mA.
2. All the input pins are schmitt-trigger pins.
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10.3 A.C. CHARACTERISTICS
@ TA=-40 to +85 °C, VDD=3.3 V±10%
10.3.1 OUTPUT LOADING
Default load capacitance on output is 50 pF.
Microprocessor interface and Utopia interface outputs are loaded by 100 pF.
10.3.2 SYSTEM CLOCK AND RST SIGNAL TIMING
Table-62 System Clock and Reset Timing Parameters
Parameter
tSYSCLK
Description
Min
Max
Unit
The system clock cycle time
The system clock duty cycle
The RST pulse width
40
40
1
54
60
ns
%
DSYSCLK
tRST
ms
tRST
RST
Figure-13 Reset Signal Timing Diagram
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10.3.3 UTOPIA INTERFACE TIMING
Table-63 Utopia Interface Timing Parameters
Parameter
Description
Min
Max
Unit
(1)
ftxCLK
frxCLK
tCLAV
tUTS
tUTH
tURCO
tURS
tURH
tP
Utopia Tx interface clock frequency
Utopia Rx interface clock frequency
fSYSCLK
MHz
MHz
fSYSCLK
20
TxClav and RxClav valid from rising edge of TxClk and RxClk respectively
TxEnb, TxSOC, TxData and TxAddr to TxClk setup time
TxEnb, TxSOC, TxData and TxAddr to TxClk hold time
RxClav, RxSOC, RxData valid from rising edge of RxClk
RxAddr, RxEnb to RxClk setup time
6
1
ns
ns
ns
ns
ns
ns
20
6
1
2
RxAddr, RxEnb to RxClk hold time
Width of pull-down pulse after TxClav or RxClav is deasserted.
1.
f
is the frequency of the system clock the chip uses.
SYSCLK
tCLAV
tCLAV
TxClk
tP
TxClav
tUTS
tUTH
TxEnb, TxSOC, TxData, TxAddr
Figure-14 Tx Utopia Interface Timing Diagram
tURCO
RxClk
RxSOC, RxData
tURS
tURH
RxEnb, RxAddr
RxClav
tCLAV
tP
tCLAV
Figure-15 Rx Utopia Interface Timing Diagram
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10.3.4 LINE INTERFACE TIMING
Table-64 Line Interface Timing Parameters
Parameter
Description
Min
Max
Unit
DCK
The TSCK, TSCCK, RSCK and RSCCK clock duty cycle
E1 mode transmit direction clock frequency
E1 mode receive direction clock frequency
T1 mode transmit direction clock frequency
T1 mode receive direction clock frequency
TSD valid from TSCK
40
60
%
fTSCKE1
fRSCKE1
fTSCKT1
fRSCKT1
tFDCO
tFS
8.192
8.192
8.192
8.192
20
MHz
MHz
MHz
MHz
ns
TSF, TSCFS to TSCK set up time;
RSD, RSF, RSCFS to RSCK set up time
10
5
ns
tFH
TSF, TSCFS to TSCK hold time;
ns
RSD, RSF, RSCFS to RSCK hold time
tFS
tFH
TSF, TSCFS
TSCK, TSCCK
TSD
tFDCO
bit7
bit6
bit5
Figure-16 Line Interface Transmit Timing Diagram
tFS
tFH
RSF, RSCFS
RSCK, RSCCK
RSD
bit7
bit6
bit5
Figure-17 Line Interface Receive Timing Diagram
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10.3.5 MICROPROCESSOR INTERFACE TIMING
10.3.5.1Interface with Motorola CPU (MPM =0)
Read Cycle Specification
Table-65 Microprocessor Interface Timing Parameter for Motorola CPU Read Cycle
Symbol
Parameter
Min
Max
Unit
tRC
tDW
Read cycle time
240
235
ns
ns
ns
ns
ns
ns
ns
ns
ns
Valid read signal width
tRWV
tRWH
tAV
RW available time after valid read signal falling edge
RW hold time after valid read signal falling edge
Address available time after valid read signal falling edge
Address hold time after valid read signal falling edge
Data propagation delay after valid read signal falling edge
Read out data hold time after valid read signal rising edge
Recovery time from read cycle
10
10
135
135
tADH
tPRD
tDH
205
20
5
5
tRecovery
tRC
tRecovery
tDW
DS+CS
tRWH
tADH
tRWV
tAV
RW
Valid Address
A[x:0]
tDH
tPRD
READ D[7:0]
Valid Data
Figure-18 Microprocessor Interface Timing Diagram for Motorola CPU Read Cycle
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Write Cycle Specification
Table-66 Microprocessor Interface Timing Parameters for Motorola CPU Write Cycle
Symbol
Parameter
Min
Max
Unit
tWC
tDW
Write cycle time
240
235
ns
ns
ns
ns
ns
ns
ns
ns
ns
Valid write signal width
tRWV
tRWH
tAV
RW available time after valid write signal falling edge
RW hold time after valid write signal falling edge
Address available time after valid write signal falling edge
Address hold time after valid write signal falling edge
Data propagation delay after valid write signal falling edge
Data hold time after valid write signal rising edge
Recovery time from write cycle
10
10
50
165
165
tAH
tDV
tDHW
tRecovery
165
5
tRecovery
tWC
tDW
DS+CS
RW
tRWH
tRWV
tAH
tAV
Valid
Address
A[x:0]
tDHW
tDV
Valid Data
Write D[7:0]
Figure-19 Microprocessor Interface Timing Diagram for Motorola CPU Write Cycle
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10.3.5.2Interface with Intel CPU (MPM =1)
Read Cycle Specification
Table-67 Microprocessor Interface Timing Parameter for Intel CPU Read Cycle
Symbol
Parameter
Min
Max
Unit
tRC
tRDW
tAV
Read cycle time
240
235
ns
ns
ns
ns
ns
ns
ns
Valid read signal width
Address available time after valid read signal falling edge
Address hold time after valid read signal falling edge
Data propagation delay after valid read signal falling edge
Read out data hold time after valid read signal rising edge
Recovery time from read cycle
10
tAH
135
tPRD
tDH
205
20
5
5
tRecovery
tRC
tRecovery
tRDW
tAH
CS+RD
tAV
A[x:0]
Valid Address
tDH
tPRD
READ D[7:0]
Valid Data
Note: WR should be tied to high
Figure-20 Microprocessor Interface Timing Diagram for Intel CPU Read Cycle
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Write Cycle Specification
Table-68 Microprocessor Interface Timing Parameters for Intel CPU Write Cycle
Symbol
Parameter
Min
Max
Unit
tWC
tWRW
tAV
Write cycle time
240
235
ns
ns
ns
ns
ns
ns
ns
Valid write signal width
Address available time after valid write signal falling edge
Address hold time after valid write signal falling edge
Data available time after valid write signal falling edge
Data hold time after valid write signal falling edge
Recovery time from write cycle
10
50
tAH
165
tDV
tDHW
tRecovery
165
5
tRecovery
tWC
tWRW
WR+CS
tAH
tAV
Valid Address
tDHW
A[x:0]
tDV
Write D[7:0]
Valid Data
Note: RD should be tied to high
Figure-21 Microprocessor Interface Timing Diagram for Intel CPU Write Cycle
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10.3.6 SRAM INTERFACE TIMING
10.3.6.1Write Cycle Specification
Table-69 SRAM Interface Write Cycle Parameters
Symbol
Description
Min
Max
Unit
tWC
tAS
Write cycle time
40
3
ns
ns
ns
ns
ns
ns
Address set up time
Address hold time
Write pulse width
Data valid to end of write
Data hold time
20
tAH
tWP
tDW
tDH
1
20
7
0
tWC
EMA
EM_CS
tAS
tAH
tWP
EM_WE
tDW
tDH
EMD
Valid Data
EM_OE
Figure-22 SRAM Interface Timing Diagram for Write Cycle
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10.3.6.2Read Cycle Specification
Table-70 SRAM Interface Read Cycle Parameters
Symbol
Description
Min
Max
Unit
tRC
tAA
Read cycle time
40
ns
ns
ns
Address Access time
EM_CS Access time
EM_OE Access time
20
20
20
7
tCA
tOA
tCHZ
tOHZ
Delay from disabled EM_CS to data bus high impedance
Delay from disabled EM_OE to data bus high impedance
ns
ns
7
tRC
EMA
tAA
tCHZ
tOHZ
EM_CS
EM_OE
tCA
tOA
EM_WE
EMD
Valid Data
Figure-23 SRAM Interface Timing Diagram for Read Cycle
PHYSICAL AND ELECTRICAL CHARACTERISTICS
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Glossary
Active State
Anomaly
API
—
—
A link state indicating that the link is ready for transmitting or receiving ATM cells in the specified direction, either Tx or Rx. Each
direction may enter active state asynchronously.
Discrepancy between the actual and desired characteristic of an item. An anomaly may or may not affect an item to perform a
required function.
—
—
Application Programming Interface
Asymmetrical Config-
uration
This is an IMA configuration scheme. In this configuration mode, the physical links that are assigned to an IMA group are not
required to be configured in both Tx and Rx directions. That is, some of the physical links may be configured to use both directions
while others may only use one direction (Tx or Rx).
Asymmetrical Opera-
tion
—
This is an ATM traffic transfer mode of an IMA group. In this mode, the physical link can be used to transfer data in one direction and
does not care the other direction’s Tx and Rx state. That is, when the Tx state of end A and Rx state of end B have both entered
active state, end A starts to transfer data to end B and end B starts to receive. In this case, end A does not care whether end A’s Rx
state is active or not and end B does not care whether end B’s Tx state is active or not.
ATM
—
—
—
Asynchronous Transfer Mode
ATM Layer Cells
Blocked State
Cells (ATM formatted) that are exchanged between ATM layer and IMA sublayer. It is also called application data.
This is a group state indicating that the group has been inhibited from transiting into OPERATIONAL state for some administrative
purposes.
Config-Aborted
—
—
This is a group state indicating that the group has rejected the group parameters proposed by the FE IMA group.
Common Transmit
Clock (CTC)
This is a configuration where the transmit clocks of all the physical links within an IMA group are derived from the same clock source.
Data Round-Robin
—
—
This is the data transfer method IMA used to deliver cells from ATM layer to multiple transmit links within an IMA group, or the data
play-out method that the IMA used to form a consecutive cell stream from multiple receive links within an IMA group.
Defect
A defect may be caused by successive anomaly of an item to perform a required function. The defect may or may not lead to main-
tenance action depending on the results of additional analysis.
ES
—
—
Errored Seconds
Far End (FE)
Two communication entities are considered to be two communication ends. Mostly, one is called Near-End (NE) and the other is
called Far-End (FE).
Filler Cell
—
—
—
—
—
This is a kind of OAM cell used by IMA layer. It is used to fill in the IMA frame when no cells are available at the ATM layer. Thus filler
cell is used for cell rate decoupling at IMA sublayer (like idle cell used in TC layer).
Group State Machine
(GSM)
This is the state machine that determines the behavior of the IMA group.
Group Traffic State
Machine (GTSM)
This state machine controls when to exchange ATM layer cell between the ATM layer and the IMA layer
Group Wide Proce-
dure (GWP)
This refers to the Group Start-up and LASR procedures performed by the IMA unit to synchronize the activation of IMA links within
the IMA group.
Header Error Check
(HEC)
This is used for checking the correctness of the ATM cell header.
Glossary
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ICP Offset
—
—
—
The ICP cell is used for IMA frame synchronization. The ICP offset is used to tell the receive side the ICP cell’s position in an IMA
frame and the receive side can make use of this information to figure out the first cell of the frame.
ICP Cell
The ICP cell is a kind of OAM cell. It can be used by the IMA sublayer to delineate the IMA frame. Also, it conveys information about
the status or configuration parameters of each end.
ICP Stuff
The ICP stuff is two consecutive ICP cells at the ICP offset position. The ICP stuff is inserted by repeating the ICP cell. The purpose
of the ICP stuff is to decrease the IMA data cell rate of fast links at the transmit side. When an ICP stuff is inserted into an IMA frame,
the frame length will become M+1, with M being the frame length without ICP stuff.
IMA Frame Synchro-
nization Mechanism
(IFSM)
—
This is a state machine used for receiving IMA frame synchronization. It is an analogy to the cell delineation mechanism defined in
ITU-T recommendation I.432.
IMA
—
—
Inverse Multiplexing for ATM
IMA Frame
The IMA frame is a cell stream transmitted over IMA links within an IMA group. There are altogether M cells in one IMA frame without
ICP stuff. M could be 32, 64, 128 or 256. In each IMA frame, there are one ICP cell, ATM layer cells and IMA Filler cells. The ICP
cells occur at the offset position specified in the ICP cell (the offset may be different for different links).
IMA Group
IMA Link
—
—
The IMA group is a number of links at one end that are used to establish an IMA virtual link to the other end.
An IMA link is a unidirectional logical link of a physical link’s Tx or Rx direction. The IMA link is identified by the value of LID field of
the ICP cells carried over that IMA link. Thus a physical link that connects two ends (A and B) may consist of two IMA links, one from
A to B and the other from B to A.
IMA Sublayer
—
—
The IMA is a sublayer part of the Physical layer and located between the interface specific Transmission Convergence (TC) sublayer
and the ATM layer.
IMA Virtual Link
This is a data communication channel between two communication ends (two IMA units) over a number of physical links; These links
are also called an IMA group.
IMAOS08
—
—
—
A downloaded software used when the device is in normal communication.
IMAOS08_Slave
A downloaded software used when the device operates in Slave Mode. It supports the Group Auto Detect function.
Independent Trans-
mit Clock (ITC)
This is a configuration where there is at least one IMA link within an IMA group that has its transmit clock derived from a clock source
that is different from that of other IMA links. The IMA transmitter may indicate that it is in the ITC mode even if all of the transmit
clocks of the links are derived from the same source.
In Group
Inhibiting
—
—
This is an event indicating that a link has been configured into an IMA group.
This represents the action to voluntarily disable the capacity of the group or the link to carry ATM layer cells for reasons other than
reported problems.
Insufficient-Links
LASR
—
—
—
Group state indicating that the group does not have sufficient links in the Active state to be in the Operational state.
This stands for Link Addition and Slow Recovery procedure.
LCD
Loss of Cell Delineation defect. The LCD defect is reported when the OCD anomaly persists for the time specified in ITU-T Recom-
mendation I.432 [30]. The LCD defect is cleared when the OCD anomaly has not been detected for the period of time specified in
ITU-T Recommendation I.432.
LID
—
Link Identifier. The LID field in the ICP cell is used to identify an IMA link on which the ICP cells are transmitted. The LID is been used
to determine the round-robin order to retrieve cells from the incoming IMA links at the IMA receiver.
LIF
—
—
—
Loss of IMA Frame defect. The LIF defect is the occurrence of persistent OIF anomalies for at least 2 IMA frames.
The term “link” refers to an IMA link in this data sheet, unless the context clearly refers to a physical link.
Link
Link Defect
A link defect is the occurrence of the persistent detection of an anomaly at the Interface Specific Transmission Convergence sub-
layer. LOS, LOF/OOF, AIS, LOC and LCD defects are examples of link defects reported at the Interface Specific Transmission Con-
vergence sublayer.
Glossary
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LODS
Inverse Multiplexing for ATM
—
Link Out Of Delay Synchronization defect. The LODS is a link event indicating that the link is not synchronized with the other links
within the IMA group.
LOF
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Loss Of Frame
LOS
Loss Of Signal
LSB
Least Significant Bit
LSI
Link Stuff Indication
LSM
Link State Machine
M
IMA frame size
MIB
Management Information Base
MPU
MicroProcessor Unit
MSB
Most Significant Bit
NE
Near-End (local end)
Not Configured
Not in Group
OAM
This is a group state indicating that the group does not exist yet.
This is used as an event or a state indicating that a link is no longer configured within an IMA group.
Operations And Maintenance
OCD
Out of Cell Delineation anomaly. As specified in ITU-T Recommendation I.432 [30], an OCD anomaly is reported upon the occur-
rence of Alpha (α) consecutive cells with incorrect HEC, and it is no longer reported after detecting Delta (δ) consecutive cells with
correct HEC.
OIF
—
—
—
—
Out of IMA Frame anomaly
OOF
Out Of Frame
Operational
Physical Link
Group state indicating that the group has sufficient links in both Tx and Rx directions to carry ATM layer cells.
This is the link being used by the IMA unit to transmit and receive ATM cells. The IMA unit may use physical links in one or both
directions.
Prx
—
—
—
—
—
—
—
—
—
—
—
Minimum number of links required to be active in the receive direction for the IMA group to move into the Operational state.
Minimum number of links required to be active in the transmit direction for the IMA group to move into the Operational state.
Remote Defect Indicator
Ptx
RDI
RFI
Remote Failure Indicator
Rx
Receive (side)
SES
Severely Errored Seconds
SICP Cell
Stuff Event
Start-up
Start-up-Ack
Stuff ICP cell. One of the 2 ICP cells comprising a stuff event.
This is a repetition of an ICP cell over one IMA link to compensate for timing difference with other links within the IMA group.
This is a group state indicating that the group is waiting to see the FE in Start-up.
This is a group transitional state, when both groups are in start-up and the FE group parameters have been accepted.
Symmetrical Configu-
ration
This is an IMA group configuration scheme. In this configuration mode, physical links that are assigned to an IMA group are required
to be configured in both Tx and Rx directions.
Symmetrical Opera-
tion
—
This is an ATM traffic mode of an IMA group. In this mode, the physical link can be used to transfer data only when the link’s NE’s Tx
and Rx and FE’s Tx and Rx are all in active state.
Glossary
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TAP bus
TC
—
—
—
—
—
—
Test Access Port bus
Transmission Convergence
Timing Reference Link.
Transmit (side)
TRL
Tx
UAS
UnAvailable Seconds
UAS-IMA
UnAvailable Seconds for IMA. Interval during which the IMA receiver is declared unavailable. The period of unavailability begins at
the onset of 10 continuous SES-IMA, including the first 10 seconds to enter the UAS-IMA condition. The period of unavailability ends
at the onset of 10 continuous seconds with no SES-IMA, excluding the last 10 seconds to exit the UAS-IMA condition.
Unusable
Usable
UUS
—
—
—
This is a link state indicating the link is not in use due to fault, inhibition, etc.
This is a link state indicating the link is ready to operate in the specified direction, but it is waiting to move to Active.
UnUsable Seconds. Number of seconds during which the link state is Unusable.
Glossary
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Index
StopTestPattern ..........................................................................68
command description ...................................................................33, 73
command set list and their encoding ..................................................32
Config-Aborted ....................................................................................72
Config-Aborted-FE ..............................................................................72
ConfigDev command ...................................................................30, 33
ConfigGroupInterFace command ................................................18, 39
ConfigGroupPara command ...............................................................37
ConfigGroupWorkMode command .....................................................40
ConfigGSMTimers command .............................................................41
ConfigIFSMPara command ................................................................43
ConfigLoopMode command .................................................. 18, 23, 36
ConfigSlaveFrame command .............................................................76
ConfigTRLLink command ............................................................30, 42
ConfigUNILink command ......................................... 18, 19, 23, 30, 47
configure a group ................................................................................69
ConfigUtopiaIF command ..................................................... 18, 35, 77
A
A.C. characteristics ............................................................................ 82
absolute maximum ratings ................................................................. 81
add links to a group ............................................................................ 70
AddRxLink command ..................................................... 19, 23, 30, 46
AddTxLink command ..................................................... 19, 23, 30, 44
B
Blocked-FE ......................................................................................... 72
C
command
AddRxLink .............................................................. 19, 23, 30, 46
AddTxLink .............................................................. 19, 23, 30, 44
ConfigDev .............................................................................30, 33
ConfigGroupInterFace ..........................................................18, 39
ConfigGroupPara ....................................................................... 37
ConfigGroupWorkMode .............................................................. 40
ConfigGSMTimers ...................................................................... 41
ConfigIFSMPara ......................................................................... 43
ConfigLoopMode ...........................................................18, 23, 36
ConfigSlaveFrame ...................................................................... 76
ConfigTRLLink ......................................................................30, 42
ConfigUNILink ..................................................18, 19, 23, 30, 47
ConfigUtopiaIF ..............................................................18, 35, 77
DeactLink .............................................................................56, 70
DeleteGrp .............................................................................53, 70
DeleteLink ............................................................................55, 70
DeviceInitial ................................................................................ 74
GetConfigPara ............................................................................ 63
GetGroupDelayInfo .................................................................... 58
GetGroupState ........................................................................... 57
GetGrpPerf ................................................................................. 60
GetGrpWorkingPara ................................................................... 64
GetLinkPerf ................................................................................ 61
GetLinkState ............................................................................... 59
GetLinkWorkingPara .................................................................. 65
GetLoopedTestPattern ............................................................... 67
GetVersionInfo .....................................................................68, 78
GroupInitial ................................................................................. 79
InhibitGrp ..............................................................................50, 70
NotInhibitGrp ........................................................................51, 70
RecoverLink .........................................................................54, 70
RestartGrp ............................................................................52, 70
StartGroup ............................................................................48, 70
StartLASR ............................................................................49, 70
StartTestPattern ......................................................................... 66
D
D.C. characteristics .............................................................................81
deactivate links ...................................................................................70
DeactLink command ....................................................................56, 70
delete a group .....................................................................................70
delete links ..........................................................................................70
DeleteGrp command ....................................................................53, 70
DeleteLink command ...................................................................55, 70
DeviceInitial command ........................................................................74
E
errored ICP .........................................................................................71
F
failure/alarm signal
Blocked-FE .................................................................................72
Config-Aborted ............................................................................72
Config-Aborted-FE ......................................................................72
GR-Timing-Mismatch ..................................................................72
Insufficient-Links .........................................................................72
Insufficient-Links-FE ...................................................................72
LCD .............................................................................................72
LIF ...............................................................................................72
LODS ..........................................................................................72
RFI-IMA .......................................................................................72
Rx-Unusable-FE .........................................................................72
Start-up-FE .................................................................................72
Tx-Unusable-FE ..........................................................................72
FIFO_INT_ENABLE_REG register .....................................................26
Index
95
December 4, 2006
IDT82V2608
Inverse Multiplexing for ATM
FIFO_INT_RESET_REG register ....................................................... 26
FIFO_STATE_REG register ............................................................... 26
J
JTAG & Scan interface ................................................................16, 80
JTAG instructions ............................................................................... 80
G
G.802 mapping ................................................................................... 20
GetConfigPara command ................................................................... 63
GetGroupDelayInfo command ............................................................58
GetGroupState command .................................................................. 57
GetGrpPerf command ........................................................................ 60
GetGrpWorkingPara command .......................................................... 64
GetLinkPerf command ........................................................................ 61
GetLinkState command ...................................................................... 59
GetLinkWorkingPara command ......................................................... 65
GetLoopedTestPattern command ...................................................... 67
GetVersionInfo command ............................................................ 68, 78
global signals ...................................................................................... 12
glossary .............................................................................................. 91
group auto detect
L
LCD .................................................................................................... 72
LIF ...................................................................................................... 72
line interface .................................................................................13, 19
external loopback ....................................................................... 23
internal loopback ........................................................................ 23
loopback ..................................................................................... 23
external loopback ............................................................... 23
internal loopback ................................................................ 23
timing clock mode ...................................................................... 23
line interface timing ............................................................................ 84
line interface timing clock mode ......................................................... 23
line interface Work Mode
mode0 ........................................................................................ 20
mode1~mode4 ........................................................................... 20
mode11 ...................................................................................... 22
mode12 and mode13 ................................................................. 22
mode14 and mode15 ................................................................. 23
mode5 and mode6 ..................................................................... 22
mode7~mode10 ......................................................................... 22
link backup ......................................................................................... 30
LODS ................................................................................................. 72
loopback ............................................................................................. 23
line interface ............................................................................... 23
Utopia loopback ......................................................................... 18
master side ................................................................................. 73
slave side ................................................................................... 73
GroupInitial command ........................................................................ 79
GR-Timing-Mismatch ......................................................................... 72
GR-UAS-IMA ...................................................................................... 71
H
HCS_ERR_TC ............................................................................ 61, 71
I
IMA frame ........................................................................................... 30
IMA initialization ................................................................................. 69
IMA mode ........................................................................................... 30
IMA operation ..................................................................................... 69
IMAOS08 ...............................................................................24, 27, 73
IMAOS08_Slave ....................................................................24, 27, 73
inhibit a group ..................................................................................... 70
InhibitGrp command .................................................................... 50, 70
INPUT_FIFO_DATA_REG register .................................................... 25
INPUT_FIFO_INTERNAL_STATE_REG register .............................. 27
INPUT_FIFO_LENGTH_REG register ............................................... 25
Insufficient-Links ................................................................................. 72
Insufficient-Links-FE ........................................................................... 72
Intel
M
mapping
G.802 mapping .......................................................................... 20
spaced mapping ......................................................................... 21
master side ........................................................................................ 73
maximum delay tolerance .................................................................. 29
SRAM size ................................................................................. 29
microprocessor interface ..............................................................14, 24
microprocessor interface timing
Intel ............................................................................................ 87
Motorola ..................................................................................... 85
missing ICP ........................................................................................ 71
mode
IMA mode ................................................................................... 30
UNI mode ................................................................................... 30
Motorola
microprocessor interface timing ................................................. 85
multi-rate ............................................................................................ 22
microprocessor interface timing .................................................. 87
interface
JTAG & Scan .............................................................................. 80
JTAG & Scan interface ............................................................... 16
line interface ........................................................................ 13, 19
microprocessor ........................................................................... 24
microprocessor interface ............................................................14
SRAM interface ................................................................... 15, 29
Utopia interface .......................................................................... 18
invalid ICP .......................................................................................... 71
IV-IMA ......................................................................................... 61, 71
N
not inhibit a group .............................................................................. 70
NotInhibitGrp command ...............................................................51, 70
Index
96
December 4, 2006
IDT82V2608
Inverse Multiplexing for ATM
RestartGrp command ...................................................................52, 70
RFI-IMA .............................................................................................. 72
Rx-Stuff-IMA ................................................................................61, 71
Rx-Unusable-FE ................................................................................ 72
Rx-UUS-IMA ................................................................................61, 71
Rx-UUS-IMA-FE ..........................................................................61, 71
O
OCD_TC ...................................................................................... 61, 71
OIF-IMA ....................................................................................... 61, 71
OUTPUT_FIFO_DATA_REG register ................................................ 25
OUTPUT_FIFO_INTERNAL_STATE_REG register .......................... 26
OUTPUT_FIFO_LENGTH_REG register ........................................... 25
S
P
SES-IMA ......................................................................................61, 71
SES-IMA-FE ................................................................................61, 71
slave side ........................................................................................... 73
spaced mapping ................................................................................. 21
SRAM interface ............................................................................15, 29
SRAM interface timing ....................................................................... 89
SRAM size
maximum delay tolerance .......................................................... 29
start up a group .................................................................................. 70
StartGroup command ...................................................................48, 70
StartLASR command ...................................................................49, 70
StartTestPattern command ................................................................ 66
Start-up-FE ........................................................................................ 72
StopTestPattern command ................................................................ 68
stuffing mode ..................................................................................... 30
CTC ............................................................................................ 30
ITC ............................................................................................. 30
performance monitoring ..................................................................... 71
physical and electrical characteristics ................................................ 81
pin description
global signals .............................................................................. 12
JTAG & Scan interface ............................................................... 16
line interface ............................................................................... 13
microprocessor interface ............................................................14
others ......................................................................................... 17
power supplies and grounds ....................................................... 16
SRAM interface .......................................................................... 15
PMON ................................................................................................. 71
PMON parameters
GR-UAS-IMA .............................................................................. 71
HCS_ERR_TC ..................................................................... 61, 71
IV-IMA ................................................................................. 61, 71
OCD_TC .............................................................................. 61, 71
OIF-IMA ............................................................................... 61, 71
Rx-Stuff-IMA ........................................................................ 61, 71
Rx-UUS-IMA ........................................................................ 61, 71
Rx-UUS-IMA-FE .................................................................. 61, 71
SES-IMA .............................................................................. 61, 71
SES-IMA-FE ........................................................................ 61, 71
Tx-Stuff-IMA ........................................................................ 61, 71
Tx-UUS-IMA ........................................................................ 61, 71
Tx-UUS-IMA-FE .................................................................. 61, 71
UAS-IMA .............................................................................. 61, 71
UAS-IMA-FE ........................................................................ 61, 71
power supplies and grounds .............................................................. 16
T
T1 ISDN mode ................................................................................... 22
T1 normal mode ................................................................................. 22
timing
line interface timing .................................................................... 84
microprocessor interface timing
Intel .................................................................................... 87
Motorola ............................................................................. 85
SRAM interface timing ............................................................... 89
Utopia interface timing ............................................................... 83
timing clock mode
line interface ............................................................................... 23
timing reference link ........................................................................... 30
TRL .................................................................................................... 30
Tx-Stuff-IMA .................................................................................61, 71
Tx-Unusable-FE ................................................................................. 72
Tx-UUS-IMA .................................................................................61, 71
Tx-UUS-IMA-FE ...........................................................................61, 71
R
recover links ....................................................................................... 70
RecoverLink command ................................................................ 54, 70
register
FIFO_INT_ENABLE_REG .......................................................... 26
FIFO_INT_RESET_REG ............................................................26
FIFO_STATE_REG .................................................................... 26
INPUT_FIFO_DATA_REG ......................................................... 25
INPUT_FIFO_INTERNAL_STATE_REG ................................... 27
INPUT_FIFO_LENGTH_REG .................................................... 25
OUTPUT_FIFO_DATA_REG ..................................................... 25
OUTPUT_FIFO_INTERNAL_STATE_REG ............................... 26
OUTPUT_FIFO_LENGTH_REG ................................................ 25
register description ............................................................................. 25
register list and map ........................................................................... 24
restart a group .................................................................................... 70
U
UAS-IMA ......................................................................................61, 71
UAS-IMA-FE ................................................................................61, 71
UNI mode ........................................................................................... 30
Utopia interface .................................................................................. 18
Utopia interface timing ....................................................................... 83
Utopia loopback ................................................................................. 18
Index
97
December 4, 2006
IDT82V2608
Inverse Multiplexing for ATM
ORDERING INFORMATION
IDT
XXXXXXX
XX
X
Device Type
Package
Process/Temperature Range
BLANK
BB
Industrial (-40 °C to +85 °C)
Plastic Ball Grid Array (PBGA, BB208)
Inverse Multiplexing for ATM
82V2608
Data Sheet Document History
12/04/2006
04/07/2006
12/08/2003
10/17/2003
Page 33
Pages 9, 26, 41, 65, 72, 80
Page 1
Pages 1, 9, 10, 22, 25, 28, 36, 38, 65, 74, 75
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