IDT7M1001S40C [IDT]
128K x 8 64K x 8 CMOS DUAL-PORT STATIC RAM MODULE; 128K ×8 64K ×8 CMOS双口静态RAM模块
| 型号： | IDT7M1001S40C |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 128K x 8 64K x 8 CMOS DUAL-PORT STATIC RAM MODULE |
| 文件： | 总11页 (文件大小：175K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT7M1001
IDT7M1003
128K x 8
64K x 8
CMOS DUAL-PORT
STATIC RAM MODULE
Integrated Device Technology, Inc.
FEATURES
• High-density 1M/512K CMOS Dual-Port Static RAM
module
• Fast access times:
—Commercial 35, 40ns
—Military 40, 50ns
DESCRIPTION:
The IDT7M1001/IDT7M1003 is a 128K x 8/64K x 8 high-
speed CMOS Dual-Port Static RAM module constructed on a
multilayer ceramic substrate using eight IDT7006 (16K x 8)
Dual-Port RAMs and two IDT FCT138 decoders or depopu-
lated using only four IDT7006s and two decoders.
• Fully asynchronous read/write operation from either port
• Full on-chip hardware support of semaphore signaling
between ports
• Surface mounted LCC (leadless chip carriers) compo-
nents on a 64-pin sidebraze DIP (Dual In-line Package)
• Multiple Vcc and GND pins for maximum noise immunity
• Single 5V (±10%) power supply
• Input/outputs directly TTL-compatible
This moduleprovidestwoindependentportswithseparate
control, address, and I/O pins that permit independent and
asynchronous access for reads or writes to any location in
memory. System performance is enhanced by facilitating
port-to-port communication via semaphore (SEM) “hand-
shake” signaling. The IDT7M1001/1003 module is designed
to be used as stand-alone Dual-Port RAM where on-chip
hardware port arbitration is not needed. It is the users re-
sponsibility to ensure data integrity when simultaneously
accessing the same memory location from both ports.
The IDT7M1001/1003 module is packaged on a multilayer
co-fired ceramic 64-pin DIP (Dual In-line Package) with di-
mensions of only 3.2" x 0.62" x 0.38". Maximum access times
as fast as 35ns over the commercial temperature range are
available.
All inputs and outputs of the IDT7M1001/1003 are TTL-
compatible and operate from a single 5V supply. Fully asyn-
chronouscircuitryisused, requiringnoclocksorrefreshingfor
operation of the module.
All IDT military module semiconductor components are
manufacured in compliance with the latest revision of MIL-
STD-883, Class B, making them ideally suited to applications
demanding the highest level of performance and reliability.
PIN CONFIGURATION(1)
VCC
R/WL
OEL
CSL
SEML
A0L
A1L
GND
A2L
A3L
A4L
A5L
A6L
1
2
3
4
5
6
7
8
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
GND
R/WR
OER
CSR
SEMR
A0R
A1R
A2R
A3R
A4R
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
A5R
A6R
A7R
A8R
A7L
A8L
A9L
A9R
A10R
A11R
A12R
A13R
A14R
A15R
A16R
GND
I/O0R
I/O1R
I/O2R
I/O3R
I/O4R
I/O5R
I/O6R
I/O7R
VCC
A10L
A11L
A12L
A13L
A14L
A15L
A16L
I/O0L
I/O1L
I/O2L
I/O3L
I/O4L
I/O5L
I/O6L
I/O7L
PIN NAMES
Left Port
Right Port
Description
A (0–16)L
I/O (0–7)L
R/WL
A (0–16)R
I/O (0–7)R
R/WR
Address Inputs
Data Inputs/Outputs
Read/Write Enables
Chip Select
CSL
CSR
OEL
OER
Output Enable
Semaphore Control
Power
SEML
SEMR
VCC
GND
Ground
GND 32
2804 drw 01
2804 tbl 01
DIP
TOP VIEW
NOTE:
1. For the IDT7M1003 (64K x 8) version, Pins 23 and 43 must be connected
to GND for proper operation of the module.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
MARCH 1995
1995 Integrated Device Technology, Inc.
DSC-7066/5
7.5
1
IDT7M1001/1003
128K/64K x 8 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTIONAL BLOCK DIAGRAM
7M1001
5
7006
7006
7006
7006
CSL CSR
R_I/O0-7
CSL
CSR
CSL CSR
CSL CSR
L_A16
L_A15
L_A14
R_R/W
R_OE
R_A0-13
74FCT138
L_CS
R_CS
74FCT138
L_A0-13
L_OE
R_A14
R_A15
R_A16
L_R/W
L_I/O0-7
CSL
CSR
CSL CSR
7006
CSL CSR
7006
CSL
CSR
7006
7006
R_SEM
L_SEM
2804 drw 02
7M1003
R_I/O0-7
L_A15
L_A14
R_R/W
R_OE
R_A0-13
74FCT138
L_CS
R_CS
74FCT138
L_A0-13
L_OE
R_A14
R_A15
L_R/W
L_I/O0-7
CSL
CSR
CSL CSR
7006
CSL CSR
7006
CSL
CSR
7006
7006
R_SEM
L_SEM
2804 drw 03
7.5
2
IDT7M1001/1003
128K/64K x 8 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Symbol
Rating
Commercial
Military
Unit
Ambient
VTERM Terminal Voltage –0.5 to +7.0 –0.5 to +7.0
V
Grade
Temperature
–55°C to +125°C
0°C to +70°C
GND
0V
VCC
with Respect to
GND
Military
5.0V ± 10%
5.0V ± 10%
TA
Operating
0 to +70
–55 to +125 °C
Commercial
0V
Temperature
2804 tbl 04
TBIAS
TSTG
IOUT
Temperature
Under Bias
–55 to +125 –65 to +135 °C
–55 to +125 –65 to +150 °C
Storage
Temperature
DC Output
Current
50
50
mA
RECOMMENDED DC OPERATING
CONDITIONS
2804 tbl 02
NOTE:
1. StressesgreaterthanthoselistedunderABSOLUTEMAXIMUMRATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
Symbol
VCC
Parameter
Min.
4.5
0
Typ.
Max. Unit
Supply Voltage
Supply Voltage
Input High Voltage
5.0
5.5
0
V
V
V
GND
VIH
0
-
2.2
6.0
0.8
VIL
Input Low Voltage –0.5(1)b
b
-
V
CAPACITANCE(1) (TA = +25°C, f = 1.0MHz)
2804 tbl 05
NOTE:
1. VIL (min.) = –3.0V for pulse width less than 20ns.
Symbol
Parameter
Test Conditions
Max. Unit
CIN1
Input Capacitance
(CS or SEM)
VIN = 0V
15
pF
CIN2
Input Capacitance
(Data, Address,
VIN = 0V
100
pF
All Other Controls)
COUT
Output Capacitance
(Data)
VOUT = 0V
100
pF
2804 tbl 03
NOTE:
1. This parameter is guaranteed by design but not tested.
DC ELECTRICAL CHARACTERISTICS
(VCC = 5V ± 10%, TA = –55°C to +125°C or 0°C to +70°C)
Commercial
Military
Symbol
Parameter
Test Conditions
Min. Max.(1) Max.(2) Min. Max.(1) Max.(2) Unit
ICC2
Dynamic Operating
Current (Both Ports Active)
VCC = Max., CS ≤ VIL, SEM ≥ VIH
Outputs Open, f = fMAX
—
—
—
940
750
565
660
470
285
—
—
—
1130 790 mA
ICC1
ISB1
Standby Supply
Current (One Port Active)
VCC = Max., L_CS or R_CS ≥ VIH
Outputs Open, f = fMAX
905
685
565 mA
345 mA
Standby Supply
VCC = Max., L_CS and R_CS ≥ VIH
Current (TTL Levels)
Outputs Open, f = fMAX
L_SEM and R_SEM ≥ VCC –0.2V
ISB2
Full Standby Supply
Current (CMOS Levels)
L_CS and R_CS ≥ VCC –0.2V
VIN > VCC 0.2V or < 0.2V
—
125
65
—
245
125 mA
L_SEM and R_SEM ≥ VCC –0.2V
2804 tbl 06
NOTES:
1. IDT7M1001 (128K x 8) version only.
2. IDT7M1003 (64K x 8) version only.
7.5
3
IDT7M1001/1003
128K/64K x 8 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS
(VCC=5.0V ± 10%, TA = –55°C to +125°C and 0°C to +70°C)
IDT7M1001
IDT7M1003
Symbol
Parameter
Test Conditions
VCC = Max.
Min.
Max.
Min.
Max.
Unit
|ILI|
Input Leakage
(Address, Data & Other Controls) VIN = GND to VCC
—
—
—
80
—
40
10
40
µA
|ILI|
Input Leakage
(CS and SEM)
VCC = Max.
VIN = GND to VCC
10
80
—
—
µA
µA
|ILO|
Output Leakage
(Data)
VCC = Max.
CS ≥ VIH, VOUT = GND to VCC
VOL
VOH
Output Low Voltage
Output High Voltage
VCC = Min.
VCC = Min.
IOL = 4mA
—
0.4
—
—
0.4
—
V
IOH = –4mA
2.4
2.4
V
2804 tbl 07
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
5ns
1.5V
1.5V
See Figures 1 and 2
2804 tbl 08
+5 V
+5 V
480 Ω
480 Ω
DATAOUT
DATAOUT
255Ω
30 pF*
255Ω
5 pF*
2804 drw 04
2804 drw 05
Figure 2. Output Load
Figure 1. Output Load
(for tCLZ, tCHZ, tOLZ. tOHZ, tWHZ, tOW)
*Including scope and jig.
7.5
4
IDT7M1001/1003
128K/64K x 8 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(VCC = 5.0V ± 10%, TA = -55°C to +125°C and 0°C to +70°C)
–35
Max.
–40
–50
Max.
Symbol
Parameter
Min.
Min.
Max.
Min.
Unit
Read Cycle
tRC
tAA
Read Cycle Time
35
—
—
—
3
—
35
35
20
—
—
20
—
20
—
50
—
40
—
—
—
3
—
40
40
25
—
—
20
—
20
—
50
—
50
—
—
—
3
—
50
50
30
—
—
25
—
25
—
50
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
(2)
tACS
tOE
tOH
Chip Select Access Time
Output Enable Access Time
Output Hold From Address Change
Chip Select to Output in Low-Z
Chip Deselect to Output in High-Z
Output Enable to Output in Low-Z
Output Disable to Output in High-Z
Chip Select to Power-Up Time
Chip Disable to Power-Down Time
SEM Flag Update Pulse (OE or SEM)
(1)
tCLZ
3
3
3
(1)
tCHZ
—
3
—
3
—
3
(1)
tOLZ
tOHZ
(1)
—
0
—
0
—
0
(1)
tPU
(1)
tPD
—
15
—
15
—
15
tSOP
Write Cycle
tWC
tCW
tAW
Write Cycle Time
35
30
30
5
—
—
—
—
—
—
—
—
—
20
20
—
—
—
40
35
35
5
—
—
—
—
—
—
—
—
—
20
20
—
—
—
50
40
40
5
—
—
—
—
—
—
—
—
—
25
25
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(2)
Chip Select to End-of-Write
Address Valid to End-of-Write
Address Set-up to Write Pulse Time
Address Set-up to CS Time
Write Pulse Width
(3)
tAS1
tAS2
tWP
0
0
0
30
0
35
0
40
0
(4)
tWR
tDW
Write Recovery Time
Data Valid to End-of-Write
Data Hold Time
25
0
30
0
35
0
(4)
tDH
(1)
(1)
tOHZ
Output Disable to Output in High-Z
Write Enable to Output in High-Z
Output Active from End-of-Write
SEM Flag Write to Read Time
SEM Flag Contention Window
—
—
0
—
—
0
—
—
0
tWHZ
(1, 4)
tOW
tSWRD
tSPS
15
15
15
15
15
15
Port-to-Port Delay Timing
(5)
tWDD
Write Pulse to Data Delay
Write Data Valid to Read Data Valid
—
—
60
45
—
—
65
50
—
—
70
55
ns
(5)
tDDD
ns
NOTES:
2804 tbl 09
1. This parameter is guaranteed by design but not tested.
2. To access RAM CS ≤ VIL and SEM ≥ VIH. To access semaphore, CS ≥ VIH and SEM ≤ VIL.
3. tAS1= 0 if R/W is asserted LOW simultaneously with or after the CS LOW transition.
4. For CS controlled write cycles, tWR= 5ns, tDH= 5ns, tOW= 5ns.
5. Port-to-Port delay through the RAM cells from the writing port to the reading port.
7.5
5
IDT7M1001/1003
128K/64K x 8 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO. 1 (EITHER SIDE)(1,2,4)
tRC
ADDRESS
AA
tOH
t
t OH
DATA OUT
DATA VALID
PREVIOUS DATA VALID
2804 drw 06
TIMING WAVEFORM OF READ CYCLE NO. 2 (EITHER SIDE)(1,3,5)
tACS
CS
(6)
tCHZ
t OE
OE
(6)
tOHZ
(6)
tOLZ
DATA OUT
DATA VALID
(6)
CLZ
t
(6)
tPU
(6)
tPD
ICC
CURRENT
50%
50%
ISB
2804 drw 07
NOTES:
1. R/W is HIGH for Read Cycles
2. Device is continuously enabled. CS = LOW. This waveform cannot be used for semaphore reads.
3. Addresses valid prior to or coincident with CS transition LOW.
4. OE = LOW.
5. To access RAM, CS = LOW, SEM = H. To access semaphore, CS = HIGH and SEM = LOW.
6. This parameter is guaranteed by design but not tested.
7.5
6
IDT7M1001/1003
128K/64K x 8 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (R/ CONTROLLED TIMING)(1,3,5,8)
W
t
WC
ADDRESS
(9)
OHZ
t
OE
CS
t
AW
(6)
(7)
tWR
(2)
WP
t
AS
t
R/W
(9)
OW
t
(9)
WHZ
t
(4)
DATA OUT
DATA IN
(4)
t
DW
t DH
DATA VALID
2804 drw 08
NOTES:
1. R/W is HIGH for Read Cycles
2. Device is continuously enabled. CS = LOW. UB or LB = LOW. This waveform cannot be used for semaphore reads.
3. Addresses valid prior to or coincident with CS transition low.
4. OE = LOW.
5. To access RAM, CS = LOW, UB or LB = LOW, SEM = H. To access semaphore, CS = HIGH and SEM = LOW.
6. Timing depends on which enable signal is asserted last.
7. Timing depends on which enable signal is de-asserted first.
8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to
be placed on the bus for the required tDW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse width
be as short as the specified tWP.
9. This parameter is guaranteed by design but not tested.
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (
CONTROLLED TIMING)(1,3,5,8)
CS
t WC
ADDRESS
t AW
CS
(6)
t AS
(7)
(2)
tWR
WP
t
LB
UB
or
R/W
t DW
t DH
DATA IN
DATA VALID
2804 drw 09
NOTES:
1. R/W must be HIGH during all address transitions.
2. A write occurs during the overlap (tWP) of a LOW UB or LB and a LOW CS and a LOW R/W for memory array writing cycle.
3. tWR is measured from the earlier of CS or R/W (or SEM or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CS or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
6. Timing depends on which enable signal is asserted last.
7. Timing depends on which enable signal is de-asserted first.
8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data
to be placed on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can
be as short as the specified tWP.
9. This parameter is guaranteed by design but not tested.
7.5
7
IDT7M1001/1003
128K/64K x 8 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING (EITHER SIDE)(1)
t
OH
t
AA
VALID ADDRESS
VALID ADDRESS
A0 - A2
t
ACS
t
AW
t WR
t WP
SEM
t
SOP
t
DW
DATAOUT
VALID
DATA
0
DATA IN VALID
t
DH
t
WP
t
AS
R/W
OE
tOE
t
SWRD
t
SOP
WRITE CYCLE
READ CYCLE
2804 drw 10
NOTE:
1. CS = HIGH for the duration of the above timing (both write and read cycle).
TIMING WAVEFORM OF SEMAPHORE CONTENTION(1,3,4)
MATCH
A0A - A2A
R/WA
SIDE(2) “A”
SEM A
t SPS
A0B - A2B
MATCH
SIDE(2) “B”
R/WB
SEM B
2804 drw 11
NOTES:
1. D0R = D0L = LOW, L_CS = R_CS = HIGH. Semaphore Flag is released form both sides (reads as ones from both sides) at cycle start.
2. "A" may be either left or right port. "B" is the opposite port from "A".
3. This parameter is measured from R/WA or SEMA going HIGH to R/WB or SEMB going HIGH.
4. If tSPS is violated, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.
7.5
8
IDT7M1001/1003
128K/64K x 8 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT DELAY(1)
t WC
ADDR R
R/W R
MATCH
t WP
t DH
t DW
DATA IN R
ADDR L
VALID
MATCH
t WDD
DATA OUT L
VALID
t DDD
NOTE:
READ CYCLE
RIGHT PORT
1. L_CS = R_CS = LOW.
WRITE CYCLE LEFT PORT
2804 drw 12
TRUTH TABLES
TABLE I: NON-CONTENTION READ/WRITE CONTROL(1)
Inputs(1)
Outputs
I/O0 - I/O7
High-Z
R/
Mode
CS
H
W
OE
X
SEM
H
X
Deselected: Power Down
Write to Both Bytes
Read Both Bytes
L
L
H
X
X
H
DATAIN
DATAOUT
High-Z
L
L
H
X
H
X
Outputs Disabled
2804 tbl 10
NOTE:
1. AOL — A12 ≠ A0R — A12R
TABLE II: SEMAPHORE READ/WRITE CONTROL(1)
Inputs
Outputs
I/O0 - I/O7
DATAOUT
DATAIN
—
R/
Mode
CS
W
OE
SEM
H
X
H
L
X
X
L
L
L
Read Data in Semaphore Flag
Write DIN0 into Semaphore Flag
Not Allowed
L
X
2804 tbl 11
NOTE:
1. AOL — A12 ≠ A0R — A12R
SEMAPHORE OPERATION
For more details regarding semaphores & semaphore operations, please consult the IDT7006 datasheet.
7.5
9
IDT7M1001/1003
128K/64K x 8 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PACKAGE DIMENSIONS
7M1001
3.190
3.210
0.615
0.635
0.605
0.625
TOP VIEW
PIN1
0.380
MAX.
0.330
MAX.
0.007
0.013
0.010
0.050
SIDE VIEW
0.015
0.022
0.035
0.060
0.100
TYP.
0.125
0.175
SIDE VIEW
BOTTOM VIEW
2804 drw 13
7M1003
3.190
3.210
0.615
0.635
0.605
0.625
TOP VIEW
PIN1
0.380
MAX.
0.310
MAX.
0.007
0.013
0.010
0.070
SIDE VIEW
0.015
0.022
0.035
0.060
0.100
TYP.
0.125
0.175
SIDE VIEW
BOTTOM VIEW
2804 drw 14
7.5
10
IDT7M1001/1003
128K/64K x 8 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
XXXX
Device
type
A
999
Speed
A
A
Power
Package
Process/
Temperature
range
BLANK Commercial (0°C to +70°C)
B
Military (-55°C to +125°C)
Semiconductor components compliant to
MIL-STD-883, Class B
C
Sidebraze DIP (Dual In-line Package)
35
40
50
(Commercial Only)
Nanoseconds
(Military Only)
S
Standard Power
7M1001 128K x 8 Dual-Port Static RAM Module
7M1003 64K x 8 Dual-Port Static RAM Module
2804 drw 15
7.5
11
相关型号：
IDT7M1002S100GB
Multi-Port SRAM Module, 16KX32, 100ns, CMOS, CPGA121, 1.300 X 1.300 INCH, CERAMIC, PGA-121
IDT
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