IDT79RV4700100GH [IDT]
RISC Microprocessor, 64-Bit, 100MHz, CMOS, CPGA179, PGA-179;
| 型号： | IDT79RV4700100GH |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | RISC Microprocessor, 64-Bit, 100MHz, CMOS, CPGA179, PGA-179 时钟 外围集成电路 |
| 文件： | 总1页 (文件大小：26K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT79RV4700 SyncOut to SyncIn
Design Considerations
TECHNICAL
NOTE
TN-29
Integrated Device Technology, Inc.
By Salahuddin Ameer
2. The delay should not exceed one MasterClock
period of 2ns, which is used to accommodate any
mismatch in the internal buffer delays between Master-
Clock and SyncIn.
3. The SyncIn signal must be clean and jitter free to
ensure the proper working of the PLL.
4. The rise and fall time of the SyncIn signal must
match that of MasterClock. Otherwise, a delta time
phase shift could occur between MasterClock and SyncIn
at 1.5V level (trigger point of the R4700 input buffer). The
result is Tclock will appear delta time earlier than it
should.
Introduction
The purpose of this technical note is to provide impor-
tant data to board designers using the IDT79RV4700
processor. The information presented here will assist a
designer using the processor’s SyncOut and SyncIn
signals to minimize the skew between I/O signals and
clocks and ensure the proper functioning of the on-chip
PLL in their design.
IDT79R4700 PLL Clock Interface Signals
The Clock interface uses two input signals: Master-
Clock and SyncIn and four output signals: MasterOut,
SyncOut, Rclock(1:0)1, and Tclock(1:0)2.
All processor timings are based on the single Master-
Clock input signal. By multiplying MasterClock two
times, the processor generates the pipeline clock, Pclock.
To generate Sclock3, which determines the processor’s
bus frequency, Pclock is divided by the number (2
through 8) that is programmed during the boot-mode
initialization sequence. The processor drives both Rclock
and Tclock.
Delay = D
RV4 7 0 0
Syn cOu t
Syn cIn
Delay = D
The Tclock and Rclock signals are identical to
Sclock in frequency. In phase, however, Rclock leads by
25% of Sclock’s cycle time. Two interface signals, SyncIn
and SyncOut (refer to Chapter 10 of the IDT79RV4700
Hardware User’s Manual, for more details and timing
diagrams), provide a delay between Tclock and Rclock
and the I/O signals (SysAd, SysCmd and Control signals),
to compensate for buffer and board external clock delays.
Rclock
Tclock
Delay = D
Figure 1. Illustration of Delays between RV4700 Processor Signals
The Need for Compensation
Buffers add delays to Tclock and Rclock and are
required to increase the fanout of these signals. To
compensate for these delays, a delay must also be added
between SyncOut and SyncIn. Buffer placement for
these signals is illustrated in Figure 1.
Are there other precautions?
Besides the SyncOut and SyncIn delay issue,
careful attention to other signals must also be given when
connecting loads. It is important to try and not exceed two
loads, to allow maximum design margin.
How much delay time between SyncOut and SyncIn is
required?
When determining delay time requirements, the
following four conditions should be taken into account:
1. The same delay of the clock buffers D.
Conclusion
Through this technical note, details regarding the
relationship between the PLL clocks and synchronization
with the external interface circuitry, using SyncOut and
SyncIn, have been presented. This data will assist board
designers who are using the R4700’s SyncOut and
SyncIn signals to minimize the skew between I/O signals
and clocks and ensure the proper functioning of the on-
chip PLL in their designs.
1. Two identical receive clocks that are at the interface fre-
quency.
2. Two identical transmit clocks that are at the interface fre-
quency.
3. An internal clock used by the processor to sample data at
the system interface and to clock data into the processor sys-
tem interface output registers.
More details on the IDT79RV4700 processor can be
obtained in both the IDT79RV4700 Hardware User’s
Manual and in the IDT79R4700/IDT79RV4700 64-Bit
RISC Microprocessor data sheet.
1998 Integrated Device Technology, Inc.
February 1998
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