IDT74FCT543AD [IDT]
FAST CMOS OCTAL LATCHED TRANSCEIVER; 快速CMOS八路锁存收发器型号: | IDT74FCT543AD |
厂家: | INTEGRATED DEVICE TECHNOLOGY |
描述: | FAST CMOS OCTAL LATCHED TRANSCEIVER |
文件: | 总7页 (文件大小:75K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
IDT54/74FCT543
IDT54/74FCT543A
IDT54/74FCT543C
FAST CMOS
OCTAL LATCHED
TRANSCEIVER
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• IDT54/74FCT543 equivalent to FAST speed
• IDT54/74FCT543A 25% faster than FAST
• IDT54/74FCT543C 40% faster than FAST
• Equivalent to FAST output drive over full temperature
and voltage supply extremes
• IOL = 64mA (commercial), 48mA (military)
• Separate controls for data flow in each direction
• Back-to-back latches for storage
• CMOS power levels (1mW typ. static)
• Substantially lower input current levels than FAST
(5µA max.)
• TTL input and output level compatible
• CMOS output level compatible
The IDT54/74FCT543/A/C is a non-inverting octal trans-
ceiver built using an advanced dual metal CMOS technology.
These devices contain two sets of eight D-type latches with
separate input and output controls for each set. For data flow
fromAtoB, forexample, theA-to-BEnable(CEAB)inputmust
be LOW in order to enter data from A0–A7 or to take data from
B0–B7, as indicated in the Function Table. With CEAB LOW,
a LOW signal on the A-to-B Latch Enable (LEAB) input makes
the A-to-B latches transparent; a subsequent LOW-to-HIGH
transition of the LEAB signal puts the A latches in the storage
mode and their outputs no longer change with the A inputs.
With CEAB and OEAB both LOW, the 3-state B output buffers
are active and reflect the data present at the output of the A
latches. Control of data from B to A is similar, but uses the
CEBA, LEBA and OEBA inputs.
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B
FUNCTIONAL BLOCK DIAGRAMS
DETAIL A
B0
D
Q
LE
Q
D
A0
LE
A1
A2
A3
A4
A5
A6
A7
B1
B2
B3
B4
B5
DETAIL A x 7
B6
B7
OEBA
OEAB
CEAB
CEBA
LEBA
LEAB
2614 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST is a registered trademark of National Semiconductor Co.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
MAY 1992
1992 Integrated Device Technology, Inc.
7.17
DSC-4602/3
1
IDT54/74FCT543/A/C
FAST CMOS OCTAL LATCHED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
IDT54/74FCT861 10-BIT TRANSCEIVERS
INDEX
1
24
Vcc
CEBA
B0
B1
B2
LEBA
OEBA
A0
23
22
2
4
3
2
28 27 26
3
5
25
24
23
22
21
20
19
B1
B2
B3
NC
B4
B5
B6
A1
A2
A3
1
P24-1, 21
4
6
A1
A2
A3
A4
D24-1,
SO24-2
&
5
20
19
18
17
16
15
14
13
7
NC
8
6
L28-1
B3
B4
9
7
A4
A5
A6
E24-1
10
11
8
A5
B5
B6
9
6
A
12 13 14 15 16 17 18
10
11
12
A7
CEAB
GND
B7
LEAB
OEAB
2614 drw 02
DIP/SOIC/CERPACK
TOP VIEW
LCC
TOP VIEW
PIN DESCRIPTION
Pin Names
FUNCTION TABLE (1,2)
For A-to-B (Symmetric with B-to-A)
Latch
Description
Output
Buffers
OEAB
OEBA
CEAB
CEBA
LEAB
LEBA
A0–A7
B0–B7
A-to-B Output Enable Input (Active LOW)
B-to-A Output Enable Input (Active LOW)
A-to-B Enable Input (Active LOW)
Inputs
Status
A-to-B
B0–B7
CEAB
LEAB
—
H
OEAB
H
—
—
L
—
—
H
L
Storing
High Z
B-to-A Enable Input (Active LOW)
Storing
—
—
A-to-B Latch Enable Input (Active LOW)
B-to-A Latch Enable Input (Active LOW)
A-to-B Data Inputs or B-to-A 3-State Outputs
B-to-A Data Inputs or A-to-B 3-State Outputs
—
L
High Z
Transparent
Storing
Current A Inputs
L
H
L
Previous* A Inputs
NOTES:
2614 tbl 01
2614 tbl 02
1. * Before LEAB LOW-to-HIGH Transition
H = HIGH Voltage Level
L = LOW Voltage Level
— = Don’t Care or Irrelevant
2. A-to-B data flow shown; B-to-A flow control is the same, except using
CEBA, LEBA and OEBA.
LOGIC SYMBOL
LEAB CEAB CEBA LEBA
A0
B0
B1
A1
A2
B2
A3
B3
A4
B4
A5
B5
A6
B6
A7
B7
OEBA
OEAB
2614 drw 03
7.17
2
IDT54/74FCT543/A/C
FAST CMOS OCTAL LATCHED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol Parameter(1)
Conditions Typ. Max. Unit
Symbol
Rating
Commercial
Military
Unit
(2)
VTERM
Terminal Voltage
with Respect
to GND
–0.5 to +7.0 –0.5 to +7.0
V
CIN
CI/O
Input Capacitance VIN = 0V
I/O Capacitance VOUT = 0V
6
8
10
12
pF
pF
(3)
NOTE:
2614 tbl 04
VTERM
Terminal Voltage
with Respect
to GND
–0.5 to VCC –0.5 to VCC
V
1. This parameter is guaranteed by characterization data and not tested.
TA
Operating
0 to +70
–55 to +125 °C
Temperature
TBIAS
TSTG
Temperature
Under Bias
–55 to +125 –65 to +135 °C
–55 to +125 –65 to +150 °C
Storage
Temperature
PT
Power Dissipation
DC Output Current
0.5
0.5
W
IOUT
120
120
mA
NOTES:
2614 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage
may exceed VCC by +0.5V unless otherwise noted.
2. Inputs and VCC terminals only.
3. Outputs and I/O terminals only.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V, VHC = VCC – 0.2V
Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%
Symbol
VIH
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current
(Except I/O pins)
Input LOW Current
(Except I/O pins)
Input HIGH Current
(I/O pins Only)
Test Conditions(1)
Min.
2.0
—
Typ.(2)
Max.
—
Unit
V
Guaranteed Logic HIGH Level
—
VIL
Guaranteed Logic LOW Level
VCC = Max.
—
0.8
V
IIH
VI = VCC
VI = 2.7V
VI = 0.5V
VI = GND
VI = VCC
VI = 2.7V
VI = 0.5V
VI = GND
—
—
5
µA
—
—
5(4)
–5(4)
–5
IIL
IIH
IIL
—
—
µA
µA
µA
—
—
VCC = Max.
—
—
15
—
—
15(4)
–15(4)
–15
–1.2
—
Input LOW Current
(I/O pins Only)
—
—
—
—
VIK
IOS
Clamp Diode Voltage
Short Circuit Current
Output HIGH Voltage
VCC = Min., IN = –18mA
VCC = Max.(3), VO = GND
—
–0.7
–120
VCC
VCC
4.3
4.3
GND
GND
0.3
0.3
V
mA
V
–60
VHC
VOH
VCC = 3V, VIN = VLC or VHC, IOH = –32µA
—
(4)
VCC = Min.
IOH = –300µA
VHC
2.4
2.4
—
—
VIN = VIH or VIL
IOH = –12mA MIL.
IOH = –15mA COM’L.
—
—
VOL
Output LOW Voltage
VCC = 3V, VIN = VLC or VHC, IOL = 300µA
VLC
V
(4)
VCC = Min.
IOL = 300µA
—
VLC
VIN = VIH or VIL
IOL = 48mA MIL.(5)
IOL = 64mA COM’L.(5)
—
0.55
0.55
—
NOTES:
2614 tbl 05
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. This parameter is guaranteed but not tested.
5. These are maximum IOL values per output, for 8 outputs turned on simultaneously. Total maximum IOL (all outputs) is 512mA for commercial and 384mA
for military. Derate IOL for number of outputs exceeding 8 turned on simultaneously.
7.17
3
IDT54/74FCT543/A/C
FAST CMOS OCTAL LATCHED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS VLC = 0.2V; VHC = VCC – 0.2V
Symbol
Parameter
Test Conditions(1)
Min.
Typ.(2)
Max.
Unit
ICC
Quiescent Power
VCC = Max.
—
0.2
1.5
mA
Supply Current
VIN ≥ VHC; VIN ≤ VLC
VCC = Max., VIN = 3.4V(3)
∆ICC
Quiescent Power Supply
Current TTL Inputs HIGH
—
—
0.5
2.0
mA
ICCD
Dynamic Power Supply Current(4)
VCC = Max., Outputs Open
CEAB and OEAB = GND
CEBA = VCC
VIN ≥ VHC
VIN ≤ VLC
0.15
0.25
mA/
MHz
One Input Toggling
50% Duty Cycle
IC
Total Power Supply Current(6)
VCC = Max., Outputs Open
fCP = 10MHz (LEAB)
50% Duty Cycle
VIN ≥ VHC
VIN ≤ VLC
(FCT)
—
1.7
4.0
mA
CEAB and OEAB = GND
CEBA = VCC
One Bit Toggling
at fi = 5MHz
50% Duty Cycle
VIN = 3.4V
VIN = GND
—
—
2.2
7.0
6.0
VCC = Max., Outputs Open
fCP = 10MHz (LEAB)
50% Duty Cycle
VIN ≥ VHC
VIN ≤ VLC
(FCT)
12.8(5)
CEAB and OEAB = GND
CEBA = VCC
Eight Bits Toggling
at fi = 5MHz
VIN = 3.4V
VIN = GND
—
9.2
21.8(5)
50% Duty Cycle
NOTES:
2614 tbl 06
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V); all other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT +IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD(fCP/2 + fiNi)
ICC = Quiescent Current
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
7.17
4
IDT54/74FCT543/A/C
FAST CMOS OCTAL LATCHED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT543
IDT54/74FCT543A
IDT54/74FCT543C
Com’l.
Mil.
Com’l.
Mil.
Com’l.
Mil.
(2)
(2)
(2)
(2)
(2)
(2)
Symbol
tPLH
tPHL
Parameter
Propagation Delay
Transparent Mode
Condition(1) Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
CL = 50pF
RL = 500Ω
2.5 8.5 2.5 10.0 2.5 6.5 2.5 7.5 2.5 5.3 2.5 6.1 ns
An to Bn or Bn to An
tPLH
tPHL
Propagation Delay
LEBA to An, LEAB to Bn
2.5 12.5 2.5 14.0 2.5 8.0 2.5 9.0 2.5 7.0 2.5 8.0 ns
2.0 12.0 2.0 14.0 2.0 9.0 2.0 10.0 2.0 8.0 2.0 9.0 ns
tPZH
tPZL
Output Enable Time
OEBA or OEAB to An or Bn
CEBA or CEAB to An or Bn
tPHZ
tPLZ
Output Disable Time
OEBA or OEAB to An or Bn
CEBA or CEAB to An or Bn
2.0 9.0 2.0 13.0 2.0 7.5 2.0 8.5 2.0 6.5 2.0 7.5 ns
tSU
tH
Set-up Time, HIGH or LOW
An or Bn to LEBA or LEAB
3.0
2.0
5.0
—
—
—
3.0
2.0
5.0
—
—
—
2.0
2.0
5.0
—
—
—
2.0
2.0
5.0
—
—
—
2.0
2.0
5.0
—
—
—
2.0
2.0
5.0
—
—
—
ns
ns
ns
Hold Time, HIGH or LOW
An or Bn to LEBA or LEAB
tW
LEBA or LEAB Pulse Width
LOW
NOTES:
2513 tbl 07
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
7.17
5
IDT54/74FCT543/A/C
FAST CMOS OCTAL LATCHED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
VCC
SWITCH POSITION
Test
Switch
Closed
Open
7.0V
Open Drain
Disable Low
Enable Low
500Ω
VOUT
VIN
Pulse
Generator
D.U.T.
All Other Tests
50pF
CL
500Ω
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
2614 tbl 08
R T
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
3V
1.5V
0V
DATA
INPUT
tSU
t H
LOW-HIGH-LOW
1.5V
3V
1.5V
0V
TIMING
INPUT
PULSE
t W
ASYNCHRONOUS CONTROL
t REM
PRESET
CLEAR
ETC.
3V
1.5V
0V
HIGH-LOW-HIGH
PULSE
1.5V
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
3V
1.5V
0V
t H
tSU
PROPAGATION DELAY
ENABLE AND DISABLE TIMES
ENABLE
DISABLE
3V
3V
CONTROL
INPUT
1.5V
0V
SAME PHASE
INPUT TRANSITION
1.5V
0V
tPZL
tPLZ
tPHL
tPLH
3.5V
1.5V
3.5V
OUTPUT
NORMALLY
LOW
VOH
SWITCH
CLOSED
OUTPUT
1.5V
0.3V
0.3V
VOL
VOH
tPZH
tPHZ
VOL
tPLH
tPHL
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
3V
1.5V
0V
OPPOSITE PHASE
INPUT TRANSITION
1.5V
0V
0V
NOTES
2614 drw 05
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0 MHz; ZO ≤ 50Ω; tF ≤ 2.5ns;
tR ≤ 2.5ns.
7.17
6
IDT54/74FCT543/A/C
FAST CMOS OCTAL LATCHED TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
XX
FCT XXXX
X
X
Device
Type
Package
Process
Temperature
Range
Blank
B
Commercial
MIL-STD-883, Class B
P
Plastic DIP
D
CERDIP
L
SO
E
Leadless Chip Carrier
Small Outline IC
CERPACK
Octal Registered Transceiver
Fast Octal Registered Transceiver
Super Fast Octal Registered Transceiver
543
543A
543C
54
74
-55°C to +125°C
0° to +70°C
2614 drw 04
7.17
7
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