IDT74FCT3907SO [IDT]

3.3V PENTIUM⑩ CLOCK SYNTHESIZER; 3.3V PENTIUM⑩时钟合成器
IDT74FCT3907SO
型号: IDT74FCT3907SO
厂家: INTEGRATED DEVICE TECHNOLOGY    INTEGRATED DEVICE TECHNOLOGY
描述:

3.3V PENTIUM⑩ CLOCK SYNTHESIZER
3.3V PENTIUM⑩时钟合成器

时钟
文件: 总7页 (文件大小:108K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
IDT74FCT3907
ADVANCE INFORMATION  
3.3V PENTIUM™  
CLOCK SYNTHESIZER  
Integrated Device Technology, Inc.  
FEATURES:  
DESCRIPTION:  
The IDT74FCT3907 Clock synthesizer is built using ad-  
vanced dual metal CMOS technology. This device uses a  
14.31818 MHz crystal input to synthesize the various  
motherboard clock frequencies.  
The output frequencies supported by the IDT74FCT3907  
are as follows:  
• 0.5 MICRON CMOS Technology  
• Generates keyboard, floppy disk, system reference, PCI  
and CPU clocks  
• 6 copies of PCI clock & 4 copies of CPU clock available  
• 14.31818MHz crystal input  
• CPU clock output skew <250ps  
Bus clock output skew <500ps  
• 0.03% output frequency accuracy  
• Power-on reset  
Reference clocks (2) = 14.31818MHz  
Keyboard clock (1) = 12MHz  
Floppy disk clock (1) = 24MHz  
CPU clock (4) = 50/60/66.66 MHz (Selectable by SEL pins)  
Bus clock (6) = CPU clock ÷ 2  
• Selectable CPU clock frequency (50/60/66.66MHz)  
• Internal loop filter  
• VCC = 3.3 ±0.3V  
• Available in 28 pin SOIC  
• Supports Pentium™ processor based designs  
• Meets Intel Pentium™ processor 3.3V Clock Driver  
specification (External Draft 1.0)  
The SEL0, 1 pins are used to choose appropriate CPUCLK  
and PCICLK frequencies or to put the device in a test mode.  
In the test mode, the device outputs various divisors of the test  
clock frequency. Refer to the function table in this datasheet  
for details on the different operating modes.  
FUNCTIONAL BLOCK DIAGRAM  
1
KBCLK (12MHz)  
Peripheral  
X1  
Clock  
Oscillator  
(14.31818 MHz)  
Synthesizer  
Block  
X2  
1
FDCLK (24MHz)  
4
CPUCLK 0-3  
CPU  
SEL0, 1  
Clock  
Synthesizer  
Block  
6
PCICLK 0-5  
2
REF CLK 0,1 (14.31818 MHz)  
OE  
3245 drw 01  
The IDT logo is a registered trademark of Integrated Device Technology, Inc.  
Pentium™ is a trademark of Intel Corp.  
COMMERCIAL TEMPERATURE RANGES  
AUGUST 1995  
©1995 Integrated Device Technology, Inc.  
DSC-4662/-  
9.10  
1
3.3V PC CLOCK SYNTHESIZER  
COMMERCIAL TEMPERATURE RANGES  
PIN CONFIGURATION  
ABSOLUTE MAXIMUM RATINGS(1)  
Symbol  
Rating  
Commercial  
Unit  
(2)  
Terminal Voltage  
with Respect to GND  
Terminal Voltage  
with Respect to GND  
VTERM  
–0.5 to +4.6  
V
VCC  
X1  
1
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
REFCLK0  
(3)  
VTERM  
–0.5 to VCC  
+ 0.5  
V
2
REFCLK1  
VCC  
3
X2  
TA  
Operating Temperature  
Temperature Under Bias  
Storage Temperature  
DC Output Current  
0 to 70  
0 to +70  
°C  
°C  
°C  
4
GND  
OE  
KBCLK  
FDCLK  
GND  
TBIAS  
TSTG  
IOUT  
5
–55 to +125  
–60 to +60  
6
CPUCLK0  
CPUCLK1  
VCC  
mA  
7
PCICLK2  
SO28-2  
3245 tbl 01  
NOTES:  
8
PCICLK3  
VCC  
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-  
INGS may cause permanent damage to the device. This is a stress rating  
only and functional operation of the device at these or any other conditions  
above those indicated in the operational sections of this specification is  
not implied. Exposure to absolute maximum rating conditions for ex-  
tended periods may affect reliability.  
9
CPUCLK2  
CPUCLK3  
GND  
10  
11  
12  
PCICLK4  
PCICLK5  
SEL1  
GND  
2. Vcc terminals.  
3. Input, Output and I/O terminals.  
SEL0  
13  
14  
16  
15  
PCICLK1  
PCICLK0  
VCC  
3245 drw 02  
CAPACITANCE (TA = +25°C, f = 1.0MHz)  
Symbol  
Parameter(1)  
Input  
Conditions  
Typ. Max. Unit  
CIN  
VIN = 0V  
4.5  
6.0  
pF  
Capacitance  
I/O  
CI/O  
VOUT = 0V  
5.5  
8.0  
pF  
Capacitance  
3245 lnk 02  
NOTE:  
1. This parameter is measured at characterization but not tested.  
PIN DESCRIPTION  
Pin Name  
X1  
I/O  
I
Description  
14.31818 MHz Crystal Input. This is also the test clock input.  
14.31818 MHz Crystal Output  
CPUCLK Control Inputs  
X2  
O
I
SEL0, 1  
KBCLK  
O
O
O
O
O
I
Keyboard Clock (12MHz)  
Floppy Disk Clock (24MHz)  
Reference Clocks (14.31818 MHz)  
CPU Clocks  
FDCLK  
REFCLK 0, 1  
CPUCLK 0-3  
PCICLK 0-5  
OE  
PCI Bus Clocks  
Output Enable  
3245 tbl 03  
FUNCTION TABLE  
OE  
SEL0  
SEL1  
INPUT CLK  
14.31818MHz  
14.31818MHz  
14.31818MHz  
14.31818MHz  
TCLK (Test Clock)  
CPUCLK  
Hi-Z  
PCICLK  
Hi-Z  
REFCLK  
Hi-Z  
FDCLK  
Hi-Z  
KBCLK  
0
X
0
0
1
1
X
0
1
0
1
Hi-Z  
1
50MHz  
60MHz  
66.66MHz  
TCLK/2  
CPUCLK/2  
CPUCLK/2  
CPUCLK/2  
TCLK/4  
14.31818MHz  
14.31818MHz  
14.31818MHz  
TCLK  
24MHz  
24MHz  
24MHz  
TCLK/4  
12MHz  
12MHz  
12MHz  
TCLK/8  
1
1
1
3245tbl04  
9.10  
2
3.3V PC CLOCK SYNTHESIZER  
COMMERCIAL TEMPERATURE RANGES  
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE  
Following Conditions Apply Unless Otherwise Specified:  
Commercial: TA = 0°C to 70°C, VCC = 3.3V ± 0.3V  
Symbol  
Parameter  
Test Conditions(1)  
Min.  
Typ.(2)  
Max.  
Unit  
VIH  
Input HIGH Level (Input pins)  
Guaranteed Logic HIGH Level  
2.0  
5.5  
V
Input HIGH Level (I/O pins)  
Input LOW Level  
2.0  
VCC+0.5  
0.8  
VIL  
IIH  
IIL  
Guaranteed Logic LOW Level  
–0.5  
V
(Input and I/O pins)  
Input HIGH Current (Input pins)(5)  
Input HIGH Current (I/O pins)(5)  
Input LOW Current (Input pins)(5)  
Input LOW Current (I/O pins)(5)  
VCC = Max.  
VCC = Max.  
VI = 5.5V  
VI = VCC  
±1  
±1  
µA  
VI = GND  
VI = GND  
VO = VCC  
VO = GND  
±1  
±1  
IOZH  
IOZL  
VIK  
High Impedance Output Current  
±1  
µA  
(6)  
(
(3-State Output pins)  
±1  
Clamp Diode Voltage  
Output HIGH Voltage  
VCC = Min., IIN = –18mA  
VCC–0.2  
–0.7  
–1.2  
V
V
VOH  
VCC = Min.  
IOH = –0.1mA  
VIN = VIH or VIL  
VCC = Min.  
IOH = –8mA COM'L. VCC–0.6V  
3.0  
VOL  
Output LOW Voltage  
IOL = 0.1mA  
0.2  
0.5  
–206  
–195  
4.0  
V
VIN = VIH or VIL  
IOL = 8mA  
0.3  
–135  
–135  
3.0  
IOS  
Short Circuit Current(4,6)  
Short Circuit Current(4,7)  
VCC = Max., VO = GND(3)  
VCC = Max., VO = GND(3)  
VCC = Max., VIN = GND or VCC  
–43  
–34  
mA  
mA  
IOS  
ICCZ  
Quiescent Power Supply Current  
mA  
3245 tbl 05  
NOTES:  
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.  
2. Typical values are at Vcc = 3.3V, +25°C ambient.  
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.  
4. This parameter is guaranteed but not tested.  
5. The test limit for this parameter is ±5µA at TA = –55°C.  
6. Applies to CPUCLK.  
7. Applies to PCICLK.  
DYNAMIC OUTPUT DRIVE CHARACTERISTICS  
Symbol  
Parameter  
Test Conditions(1)  
Min.  
Typ.(2)  
Max.  
Unit  
IODH  
CPUCLK Output HIGH Current  
VIN = VIH or VIL, VCC = 3.135V  
–23  
mA  
(3.3V –5%)  
VOUT = 2.4V  
VCC = 3.465V  
(3.3V +5%)  
VCC = 3.135V  
–109  
IODH  
IODL  
IODL  
PCICLK Output HIGH Current  
CPUCLK Output LOW Current  
PCICLK Output LOW Current  
VIN = VIH or VIL,  
VOUT = 2.4V  
–14.5  
–100  
mA  
mA  
VCC = 3.465V  
VCC = 3.135V  
VCC = 3.465V  
VCC = 3.135V  
VCC = 3.465V  
VIN = VIH or VIL,  
VOUT = 0.4V  
16  
40  
VIN = VIH or VIL,  
VOUT = 0.4V  
9.4  
mA  
38  
3245 tbl 06  
NOTES:  
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.  
2. Typical values are at Vcc = 3.3V, +25°C ambient.  
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.  
4. This parameter is guaranteed but not tested.  
5. The test limit for this parameter is ±5µA at TA = –55°C.  
9.10  
3
3.3V PC CLOCK SYNTHESIZER  
COMMERCIAL TEMPERATURE RANGES  
OSCILLATOR CHARACTERISTICS OVER OPERATING RANGE  
Symbol  
Parameter  
Test Conditions(1)  
Min.  
Typ.(2)  
Max.  
Unit  
CX1  
X1 Input Capacitance  
20  
pF  
CX2  
IIH  
X2 Output Capacitance  
X1 Input HIGH Current  
X1 Input LOW Current  
X2 Output HIGH Current  
X2 Output LOW Current  
20  
5
pF  
µA  
µA  
mA  
VCC = Max., VIN = VCC  
IIL  
VCC = Max., VIN = GND  
VOUT = VCC  
–5  
–1  
1
IODH  
IODL  
VOUT = GND  
mA  
3245 tbl 07  
NOTES:  
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.  
2. Typical values are at Vcc = 3.3V, +25°C ambient.  
3. This parameter is guaranteed but not tested.  
POWER SUPPLY CHARACTERISTICS  
Symbol  
Parameter  
Test Conditions(1)  
Min. Typ.(2) Max. Unit  
Quiescent Power Supply Current  
TTL Inputs HIGH  
VCC = Max.  
VIN = VCC –0.6V  
2.0  
30  
µA  
ICC  
IC  
Total Power Supply Current  
VCC = Max.  
CPUCLK = 50MHz  
CPUCLK = 60MHz  
CPUCLK = 66.66MHz  
VIN = VCC  
VIN = GND  
mA  
Outputs Open  
50% Duty Cycle  
OE = VCC  
3245 tbl 08  
NOTES:  
1. Typical values are at VCC = 3.3V, +25°C ambient.  
2. Per TTL driven input (VIN = VCC -0.6V); all other inputs at VCC or GND.  
9.10  
4
3.3V PC CLOCK SYNTHESIZER  
COMMERCIAL TEMPERATURE RANGES  
74FCT3907  
SWITCHING CHARACTERISTICS OVER OPERATING RANGE  
66.66MHz  
60MHz  
50MHz  
(2)  
(2)  
(2)  
Condition(1)  
Unit  
Min.  
Max. Min.  
Max. Min.  
Max.  
Symbol  
Parameter  
tCPU  
CPUCLK Period  
TBD  
15  
4
16.7  
20  
4
ns  
tCPUH  
CPUCLK HIGH Time(3)  
CPUCLK LOW Time(4)  
CPUCLK Rise, Fall Times (Between 0.4V & 2.4V)  
CPUCLK Output Skew  
CPUCLK Pulse Skew  
4
4
ns  
ns  
ns  
ps  
ps  
tCPUL  
4
4
tR1, tF1  
tSK1(o)  
tSK1(p)  
0.8  
2.0  
250  
0.8  
2.0  
250  
0.8  
2.0  
250  
|tPLH-tPHL|  
tPCI  
PCICLK Period  
30  
12  
12  
0.5  
33.3  
13.3  
13.3  
0.5  
40  
16  
16  
0.5  
ns  
ns  
ns  
ns  
ps  
ps  
tPCIH  
PCICLK HIGH Time  
tPCIL  
PCICLK LOW Time  
tR2, tF2  
tSK2(o)  
tSK2(p)  
PCICLK Rise, Fall Time (Between 0.4V & 2.4V)  
PCICLK Output Skew  
2.0  
500  
2.0  
500  
2.0  
500  
PCICLK Pulse Skew  
|tPLH-tPHL|  
tSK3(o)  
tPS  
CPUCLK to PCICLK Output Delay  
CPUCLK, PCICLK Period Stability  
CPUCLK Lock Time  
1.0  
5.0  
250  
2
1.0  
5.0  
250  
2
1.0  
5.0  
250  
2
ns  
ps  
tCLOCK  
tPLOCK  
ms  
ms  
ns  
PCICLK Lock Time  
3
3
3
tPZL  
tPZH  
Output Enable Time OE to KBCLK,  
FDCLK, REFCLK, CPUCLK, PCICLK (Test Mode)  
Output Disable Time OE to KBCLK,  
1.5  
8.0  
1.5  
8.0  
1.5  
8.0  
tPLZ  
tPHZ  
1.5  
8.0  
1.5  
8.0  
1.5  
8.0  
ns  
FDCLK, REFCLK, CPUCLK, PCICLK (Test Mode)  
3245 tbl 09  
NOTES:  
1. See test circuit and waveforms.  
2. Minimum limits are guaranteed but not tested on Propagation Delays.  
9.10  
5
3.3V PC CLOCK SYNTHESIZER  
COMMERCIAL TEMPERATURE RANGES  
TEST WAVEFORMS  
PULSE WIDTH, RISE/FALL TIMES  
PROPAGATION DELAY, OUTPUT SKEW  
tCPUH,tPCIH  
1.5V  
2.4V  
1.5V  
0.4V  
X1  
CPUCLK  
PCICLK  
tPD2  
1.5V  
1.5V  
tCPUL, tPCIL  
tR  
tF  
tSK1(O)  
3245 drw 04  
tSK2(O)  
tSK3(O)  
3245 drw 03  
ENABLE AND DISABLE TIMES  
ENABLE  
DISABLE  
3V  
CONTROL  
INPUT  
1.5V  
0V  
tPZL  
tPLZ  
3V  
1.5V  
3V  
OUTPUT  
NORMALLY  
LOW  
SWITCH  
6V  
0.3V  
0.3V  
VOL  
tPZH  
tPHZ  
VOH  
OUTPUT  
NORMALLY  
HIGH  
SWITCH  
GND  
1.5V  
0V  
0V  
3245drw05  
NOTES:  
1. Diagram shown for input Control Enable-LOW and input Control Disable-  
HIGH  
2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns  
9.10  
6
3.3V PC CLOCK SYNTHESIZER  
COMMERCIAL TEMPERATURE RANGES  
ORDERING INFORMATION  
X
XXXX  
IDT  
XX  
FCT  
X
Process  
Package  
Temp. Range  
Device Type  
Blank  
SO  
Commercial  
Small Outline IC  
3.3V Clock Synthesizer  
0°C to +70°C  
3907  
74  
3245 drw 06  
9.10  
7

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