IDT74FCT299ATQB [IDT]
FAST CMOS 8-INPUT UNIVERSAL SHIFT REGISTER; FAST CMOS 8输入通用移位寄存器
| 型号： | IDT74FCT299ATQB |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FAST CMOS 8-INPUT UNIVERSAL SHIFT REGISTER |
| 文件： | 总7页 (文件大小：113K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT54/74FCT299T/AT/CT
FAST CMOS
8-INPUT UNIVERSAL
SHIFT REGISTER
Integrated Device Technology, Inc.
DESCRIPTION:
FEATURES:
TheIDT54/74FCT299T/AT/CTarebuiltusinganadvanced
dual metal CMOS technology. The IDT54/74FCT299T/AT/
CT are 8-input universal shift/storage registers with 3-state
outputs. Four modes of operation are possible: hold (store),
shift left, shift right and load data. The parallel load inputs and
flip-flop outputs are multiplexed to reduce the total number of
packagepins. Additionaloutputsareprovidedforflip-flopsQ0
andQ7 toalloweasyserialcascading. AseparateactiveLOW
Master Reset is used to reset the register.
• Std., A and C speed grades
• Low input and output leakage ≤1µA (max.)
• CMOS power levels
• True TTL input and output compatibility
– VOH = 3.3V (typ.)
– VOL = 0.3V (typ.)
• High drive outputs (-15mA IOH, 48mA IOL)
• Power off disable outputs permit “live insertion”
• Meets or exceeds JEDEC standard 18 specifications
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B
and DESC listed (dual marked)
• Available in DIP, SOIC, QSOP, CERPACK and LCC
packages
FUNCTIONAL BLOCK DIAGRAM
S1
S0
DS7
DS0
CP
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
CP
CP
CP
CP
CP
CP
CP
CP
CD
CD
CD
CD
CD
CD
CD
CD
Q0
Q7
MR
OE1
OE2
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
2632 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
APRIL 1995
1995 Integrated Device Technology, Inc.
6.11
DSC-4205/4
1
IDT54/74FCT299T/AT/CT
FAST CMOS 8-INPUT UNIVERSAL SHIFT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
INDEX
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
S0
OE1
OE2
I/O6
I/O4
I/O2
I/O0
Q0
Vcc
S1
DS7
Q7
I/O7
I/O5
I/O3
I/O1
CP
3
2
20 19
18
P20-1
D20-1
SO20-2
SO20-8
&
I/O
I/O
I/O
I/O
Q
6
4
2
0
0
4
5
6
7
8
DS
Q7
7
1
17
16
15
14
L20-2
I/O
I/O
I/O
7
5
E20-1
3
10 11 12 13
9
MR
GND
DS0
2632 drw 02
2632 drw 03
LCC
TOP VIEW
DIP/SOIC/QSOP/CERPACK
TOP VIEW
PIN DESCRIPTION
FUNCTION TABLE(1)
Pin Names
CP
Description
Clock Pulse Input (Active Edge Rising)
Serial Data Input for Right Shift
Serial Data Input for Left Shift
Inputs
S1
X
H
L
S0
X
H
H
L
CP
X
↑
Response
Asynchronous Reset Q0–Q7 = LOW
Parallel Load; I/On → Qn
Shift Right; DS0 → Q0, Q0 → Q1, etc.
Shift Left; DS7 → Q7, Q7→ Q6, etc.
Hold
MR
DS0
L
DS7
H
H
S0, S1
MR
Mode Select Inputs
↑
Asynchronous Master Reset Input (Active LOW)
3-State Output Enable Inputs (Active LOW)
Parallel Data Inputs or 3-State Parallel Outputs
Serial Outputs
H
H
L
↑
OE1, OE2
I/O0–I/O7
O0, O7
H
L
X
NOTE:
2632 tbl 02
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
2632 tbl 01
↑ = LOW-to-HIGH clock transition
ABSOLUTE MAXIMUM RATINGS(1)
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Rating
Commercial
Military
Unit
Symbol
Parameter(1)
Conditions Typ. Max. Unit
(2)
VTERM
Terminal Voltage
with Respect to
GND
–0.5 to +7.0 –0.5 to +7.0
V
C
IN
Input
Capacitance
Output
V
IN = 0V
6
8
10
pF
COUT
V
OUT = 0V
12
pF
(3)
VTERM
Terminal Voltage
with Respect to
GND
–0.5 to
–0.5 to
V
Capacitance
VCC +0.5
VCC +0.5
2632 lnk 04
NOTE:
1. This parameter is measured at characterization but not tested.
TA
Operating
0 to +70
–55 to +125 °C
Temperature
Temperature
Under Bias
Storage
TBIAS
TSTG
–55 to +125 –65 to +135 °C
–55 to +125 –65 to +150 °C
Temperature
Power Dissipation
PT
0.5
0.5
W
IOUT
DC Output
Current
–60 to +120 –60 to +120 mA
2632 lnk 03
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGSmaycausepermanentdamagetothedevice. Thisisastressrating
only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditionsforextendedperiodsmayaffectreliability. Noterminalvoltage
may exceed VCC by +0.5V unless otherwise noted.
2. Input and VCC terminals only.
3. Outputs and I/O terminals only.
6.11
2
IDT54/74FCT299T/AT/CT
FAST CMOS 8-INPUT UNIVERSAL SHIFT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: TA = 0°C to +70°C, VCC = 5.0V ± 5%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10%
Symbol
VIH
VIL
Parameter
Test Conditions(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
VCC = Max., VI = 2.7V
Min.
2.0
—
Typ.(2)
Max.
—
Unit
V
Input HIGH Level
—
Input LOW Level
—
0.8
±1
V
IIH
Input HIGH Current(4)
Input LOW Current(4)
Input HIGH Current(4)
Clamp Diode Voltage
Short Circuit Current
Output HIGH Voltage
—
—
µA
µA
µA
V
IIL
VCC = Max., VI = 0.5V
—
—
±1
II
VCC = Max., VI = Vcc (Max.)
—
—
±1
VIK
IOS
VOH
VCC = Min., IN = –18mA
VCC = Max.,(3) VO = GND
—
–0.7
–120
3.3
–1.2
–225
—
–60
2.4
mA
V
VCC = Min.
IOH = –6mA MIL.
VIN = VIH or VIL
IOH = –8mA COM'L.
IOH = –12mA MIL.
IOH= –15mA COM'L.
IOL = 32mA MIL.
2.0
—
3.0
0.3
—
—
0.5
±1
V
V
VOL
IOFF
Output LOW Voltage
VCC = Min.
VIN = VIH or VIL
IOL = 48mA COM'L.
Input/Output Power Off
Leakage(5)
VCC = 0V, VIN or VO ≤ 4.5V
—
µA
VH
Input Hysteresis
—
—
—
200
—
1
mV
mA
ICC
Quiescent Power
Supply Current
VCC = Max.
VIN = GND or VCC
0.01
NOTES:
2632 tbl 05
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. The test limit for this parameter is ±5µA at TA = -55°C.
5. This parameter is guaranteed but not tested.
6.11
3
IDT54/74FCT299T/AT/CT
FAST CMOS 8-INPUT UNIVERSAL SHIFT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions(1)
Min.
Typ.(2)
Max.
Unit
∆ICC
Quiescent Power Supply
Current TTL Inputs HIGH
Vcc = Max.
—
0.5
2.0
mA
VIN = 3.4V(3)
ICCD
Dynamic Power Supply
Current (4)
Vcc = Max.
Outputs Open
VIN = VCC
VIN = GND
—
0.15
0.25 mA/MHz
OE1 = OE2 = GND
MR = VCC
S0 = S1 = VCC
DS0 = DS1 = GND
One Input Toggling
50% Duty Cycle
IC
Total Power Supply
Current (6)
Vcc = Max.
Outputs Open
fCP = 10MHz
VIN = VCC
VIN = GND
—
1.5
3.5
mA
50% Duty Cycle
OE1 = OE2 = GND
MR = VCC
S0 = S1 = VCC
DS0 = DS7 = GND
One Bit Toggling
at fi = 5MHz
VIN = 3.4V
VIN = GND
—
—
2.0
3.8
5.5
50% Duty Cycle
Vcc = Max.
Outputs Open
fCP = 10MHz
VIN = VCC
VIN = GND
7.3(5)
50% Duty Cycle
OE1 = OE2 = GND
MR = VCC
S0 = S1 = VCC
DS0 = DS7 = GND
Eight Bits Toggling
at fi = 2.5MHz
50% Duty Cycle
VIN = 3.4V
VIN = GND
—
6.0
16.3(5)
NOTES:
2632 tbl 06
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V); all other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fiNi)
ICC = Quiescent Current
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Output Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
6.11
4
IDT54/74FCT299T/AT/CT
FAST CMOS 8-INPUT UNIVERSAL SHIFT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT299T
IDT54/74FCT299AT
IDT54/74FCT299CT
Com’l.
Mil.
Com’l.
Mil.
Com’l.
Mil.
(2)
(2)
(2)
(2)
(2)
(2)
Symbol
Parameter
Condition(1) Min.
Max. Min.
Max. Min.
Max. Min.
Max. Min.
9.5
Max. Min.
Max. Unit
tPLH
tPHL
Propagation Delay
CP to Q0 or Q7
CL = 50pF
RL = 500Ω
2.0 10.0 2.0 14.0 2.0
2.0 12.0 2.0 12.0 2.0
2.0 10.0 2.0 10.5 2.0
2.0 15.0 2.0 15.0 2.0
1.5 11.0 1.5 15.0 1.5
7.2
7.2
7.2
8.7
6.5
6.0
—
2.0
2.0
6.5
6.5
6.5
6.5
6.5
6.0
—
2.0 7.5
2.0 7.5
2.0 7.5
2.0 7.5
1.5 7.5
1.5 6.5
ns
ns
ns
ns
ns
ns
ns
tPLH
tPHL
Propagation Delay
CP to I/On
2.0
2.0
9.5
9.5
2.0
2.0
2.0
1.5
1.5
3.5
tPHL
Propagation Delay
MR to Q0 or Q7
tPHL
Propagation Delay
MR to I/On
2.0 11.5
tPZH
tPZL
Output Enable Time
OEn to I/On
1.5
1.5
4.0
7.5
6.5
—
tPHZ
tPLZ
Output Disable Time
OEn to I/On
1.5
7.5
7.0
—
1.5
7.5
9.0
—
1.5
3.5
tSU
tSU
tH
Set-up Time HIGH
or LOW
S0 or S1 to CP
4.0
4.5
1.0
1.5
6.0
—
—
—
—
—
Set-up Time HIGH
or LOW I/On,
DS0 or DS7 to CP
5.5
1.0
1.5
7.0
—
—
—
—
5.5
1.0
1.5
7.0
—
—
—
—
4.0
1.0
1.5
5.0
—
—
—
—
4.5
1.0
1.5
6.0
—
—
—
—
4.0
1.0
1.5
5.0
—
—
—
—
ns
ns
ns
ns
Hold Time HIGH
or LOW
S0 or S1 to CP
tH
Hold Time HIGH
or LOW I/On,
DS0 or DS7 to CP
tW
CP Pulse Width
HIGH or LOW
tw
MR Pulse Width
LOW
Recovery Time
7.0
7.0
—
—
7.0
7.0
—
—
5.0
5.0
—
—
6.0
6.0
—
—
5.0
5.0
—
—
6.0
6.0
—
—
ns
ns
tREM
NOTES:
2619 tbl 07
1. See test circuit and waveforms.
2. Minimum units are guaranteed but not tested on Propagation Delays.
6.11
5
IDT54/74FCT299T/AT/CT
FAST CMOS 8-INPUT UNIVERSAL SHIFT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
VCC
SWITCH POSITION
Test
Switch
7.0V
Open Drain
Disable Low
Closed
500Ω
500Ω
Enable Low
VOUT
VIN
Open
Pulse
Generator
All Other Tests
DEFINITIONS:
CL= Load capacitance: includes jig and probe capacitance.
D.U.T.
2632 lnk 08
50pF
C L
RT = Termination resistance: should be equal to ZOUT of the Pulse
T
R
Generator.
2632 drw 04
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
3V
DATA
1.5V
INPUT
0V
LOW-HIGH-LOW
PULSE
tH
tSU
1.5V
1.5V
3V
1.5V
0V
TIMING
INPUT
tW
ASYNCHRONOUS CONTROL
tREM
PRESET
3V
1.5V
0V
CLEAR
HIGH-LOW-HIGH
PULSE
ETC.
SYNCHRONOUS CONTROL
PRESET
2632 drw 06
3V
1.5V
0V
CLEAR
tSU
tH
CLOCK ENABLE
ETC.
2632 drw 05
PROPAGATION DELAY
ENABLE AND DISABLE TIMES
ENABLE
DISABLE
3V
1.5V
0V
3V
SAME PHASE
CONTROL
INPUT
1.5V
0V
INPUT TRANSITION
tPLH
tPHL
tPHL
tPZL
tPLZ
VOH
1.5V
VOL
OUTPUT
3.5V
1.5V
3.5V
VOL
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
tPLH
0.3V
0.3V
3V
1.5V
0V
tPZH
tPHZ
OPPOSITE PHASE
INPUT TRANSITION
VOH
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
1.5V
0V
2632 drw 07
0V
2632 drw 08
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-
HIGH
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns
6.11
6
IDT54/74FCT299T/AT/CT
FAST CMOS 8-INPUT UNIVERSAL SHIFT REGISTER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
X
X
IDT
XX
X
XXXX
FCT
Process
Temperature
Range
Family
Device Type Package
Blank
B
Commercial
MIL-STD-883, Class B
Plastic DIP
P
CERDIP
D
Small Outline IC
Leadless Chip Carrier
CERPACK
SO
L
E
Q
Quarter-size Small Outline Package
299T
299AT
299CT
8-Input Universal Shift Register
Blank
High Drive
54
74
–55
°C to +125°C
0
°
C to +70°C
2632 drw 09
6.11
7
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