IDT72V3680L10PF [IDT]
3.3 VOLT HIGH-DENSITY SUPERSYNC⑩ II 36-BIT FIFO; 3.3伏高密度SUPERSYNC ™ II 36位的FIFO
| 型号： | IDT72V3680L10PF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 3.3 VOLT HIGH-DENSITY SUPERSYNC⑩ II 36-BIT FIFO |
| 文件： | 总36页 (文件大小：563K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3 VOLT HIGH-DENSITY SUPERSYNC™ II 36-BIT FIFO
1,024 x 36, 2,048 x 36
IDT72V3640,IDT72V3650
IDT72V3660,IDT72V3670
IDT72V3680, IDT72V3690
IDT72V36100,IDT72V36110
4,096 x 36, 8,192 x 36
16,384 x 36, 32,768 x 36
65,536 x36, 131,072 x 36
• Zero latency retransmit
• Auto power down minimizes standby power consumption
• Master Reset clears entire FIFO
• Partial Reset clears data, but retains programmable settings
• Empty, Full and Half-Full flags signal FIFO status
• Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of eight preselected offsets
• Selectable synchronous/asynchronous timing modes for Almost-
Empty and Almost-Full flags
• Program programmable flags by either serial or parallel means
• Select IDT Standard timing (using EF and FF flags) or First Word
Fall Through timing (using OR and IR flags)
• Output enable puts data outputs into high impedance state
• Easily expandable in depth and width
• Independent Read and Write Clocks (permit reading and writing
simultaneously)
• Available in the 128-pin Thin Quad Flat Pack (TQFP)
• High-performance submicron CMOS technology
• Industrial temperature range (–40°C to +85°C) is available
FEATURES:
• Choose among the following memory organizations:Commercial
IDT72V3640
IDT72V3650
IDT72V3660
IDT72V3670
IDT72V3680
IDT72V3690
IDT72V36100
IDT72V36110
1,024 x 36
2,048 x 36
4,096 x 36
8,192 x 36
16,384 x 36
32,768 x 36
65,536 x 36
131,072 x 36
• 133 MHz operation (7.5 ns read/write cycle time)
• User selectable input and output port bus-sizing
- x36 in to x36 out
- x36 in to x18 out
- x36 in to x9 out
- x18 in to x36 out
- x9 in to x36 out
• Big-Endian/Little-Endian user selectable byte representation
• 5V input tolerant
• Fixed, low first word latency
FUNCTIONALBLOCKDIAGRAM
D0 -Dn (x36, x18 or x9)
LD SEN
WEN
WCLK
INPUT REGISTER
OFFSET REGISTER
FF/IR
PAF
EF/OR
PAE
HF
FLAG
LOGIC
WRITE CONTROL
LOGIC
FWFT/SI
PFM
RAM ARRAY
1,024 x 36, 2,048 x 36
4,096 x 36, 8,192 x 36
16,384 x 36, 32,768 x 36
65,536 x 36, 131,072 x36
FSEL0
FSEL1
WRITE POINTER
READ POINTER
BE
CONTROL
LOGIC
IP
READ
CONTROL
LOGIC
RT
RM
BM
IW
OW
OUTPUT REGISTER
BUS
CONFIGURATION
MRS
PRS
RESET
LOGIC
RCLK
REN
4667 drw 01
Q0 -Qn (x36, x18 or x9)
OE
The SuperSync II FIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
APRIL 2001
1
2001 Integrated Device Technology, Inc.
DSC-4667/3
TM
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
Bus-MatchingSyncFIFOsareparticularlyappropriatefornetwork,video,
telecommunications,datacommunicationsandotherapplicationsthatneedto
bufferlargeamountsofdataandmatchbussesofunequalsizes.
EachFIFOhas a data inputport(Dn)anda data outputport(Qn), bothof
whichcanassumeeithera36-bit, 18-bitora9-bitwidthasdeterminedbythe
stateofexternalcontrolpinsInputWidth(IW),OutputWidth(OW),andBus-
Matching(BM)pinduringtheMasterResetcycle.
TheinputportiscontrolledbyaWriteClock(WCLK)inputandaWriteEnable
(WEN)input. DataiswrittenintotheFIFOoneveryrisingedgeofWCLKwhen
WENisasserted.TheoutputportiscontrolledbyaReadClock(RCLK)input
andReadEnable(REN)input. DataisreadfromtheFIFOoneveryrisingedge
DESCRIPTION:
The IDT72V3640/72V3650/72V3660/72V3670/72V3680/72V3690/
72V36100/72V36110 are exceptionally deep, high speed, CMOS First-In-
First-Out(FIFO)memorieswithclockedreadandwritecontrolsandaflexible
Bus-Matching x36/x18/x9 data flow. These FIFOs offer several key user
benefits:
• Flexible x36/x18/x9 Bus-Matching on both read and write ports
• The period required by the retransmit operation is fixed and short.
• Thefirstworddatalatencyperiod,fromthetimethefirstwordiswrittentoan
emptyFIFOtothe time itcanbe read, is fixedandshort.
• Highdensityofferingsupto4Mbit
PIN CONFIGURATIONS
INDEX
WEN
SEN
DNC(1)
OE
1
2
3
4
102
VCC
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
VCC
Q35
Q34
Q33
Q32
GND
GND
Q31
Q30
Q29
Q28
Q27
Q26
VCC
DNC(1)
IW
D35
D34
5
6
7
8
9
D33
D32
10
11
12
13
14
15
16
17
18
VCC
D31
D30
GND
D29
D28
VCC
Q25
Q24
GND
GND
Q23
Q22
Q21
Q20
Q19
Q18
GND
Q17
Q16
D27
D26
D25
D24
D23
GND
D22
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
VCC
D21
D20
D19
D18
GND
VCC
D17
D16
D15
D14
D13
VCC
Q15
Q14
Q13
Q12
VCC
GND
Q11
Q10
D12
GND
D11
4667 drw 02
TQFP (PK128-1, order code: PF)
TOP VIEW
NOTE:
1. DNC = Do Not Connect.
2
TM
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
provided,sothatPAEcanbesettoswitchatapredefinednumberoflocations
from the empty boundary and the PAF threshold can also be set at similar
predefinedvaluesfromthefullboundary. Thedefaultoffsetvaluesaresetduring
Master Reset by the state of the FSEL0, FSEL1, and LD pins.
For serial programming, SEN together with LD on each rising edge of
WCLK,areusedtoloadtheoffsetregistersviatheSerialInput(SI). Forparallel
programming,WENtogetherwithLDoneachrisingedgeofWCLK,areused
toloadtheoffsetregistersviaDn. RENtogetherwithLDoneachrisingedge
ofRCLKcanbeusedtoreadtheoffsetsinparallelfromQnregardlessofwhether
serialorparalleloffsetloadinghasbeenselected.
DESCRIPTION (CONTINUED)
ofRCLKwhenRENisasserted. AnOutputEnable(OE)inputisprovidedfor
three-statecontroloftheoutputs.
ThefrequenciesofboththeRCLKandtheWCLKsignalsmayvaryfrom0
tofMAXwithcompleteindependence. Therearenorestrictionsonthefrequency
oftheoneclockinputwithrespecttotheother.
Therearetwopossibletimingmodesofoperationwiththesedevices:IDT
Standard mode and First Word Fall Through (FWFT) mode.
InIDTStandardmode,thefirstwordwrittentoanemptyFIFOwillnotappear
onthedataoutputlinesunlessaspecificreadoperationisperformed.Aread
operation,whichconsistsofactivatingRENandenablingarisingRCLKedge,
willshiftthewordfrominternalmemorytothedataoutputlines.
InFWFTmode,thefirstwordwrittentoanemptyFIFOisclockeddirectly
tothedataoutputlinesafterthreetransitionsoftheRCLKsignal.ARENdoes
not have to be asserted for accessing the first word. However, subsequent
wordswrittentotheFIFOdorequireaLOWonRENforaccess. Thestateof
theFWFT/SIinputduringMasterResetdeterminesthetimingmodeinuse.
ForapplicationsrequiringmoredatastoragecapacitythanasingleFIFO
canprovide,theFWFTtimingmodepermitsdepthexpansionbychainingFIFOs
inseries(i.e.thedataoutputsofoneFIFOareconnectedtothecorresponding
data inputs of the next). No external logic is required.
These FIFOs have five flagpins, EF/OR (EmptyFlagorOutputReady),
FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable
Almost-Emptyflag)andPAF(ProgrammableAlmost-Fullflag). TheEFandFF
functions are selected in IDT Standard mode. The IR and OR functions are
selected in FWFT mode. HF, PAE and PAF are always available for use,
irrespectiveoftimingmode.
PAEandPAFcanbeprogrammedindependentlytoswitchatanypointin
memory. Programmableoffsetsdeterminetheflagswitchingthresholdandcan
beloadedbytwomethods:parallelorserial. Eightdefaultoffsetsettingsarealso
DuringMasterReset(MRS)thefollowingeventsoccur: thereadandwrite
pointers are set to the first location of the FIFO. The FWFT pin selects IDT
Standardmode orFWFTmode.
The Partial Reset (PRS) also sets the read and write pointers to the first
location of the memory. However, the timing mode, programmable flag
programmingmethod,anddefaultorprogrammedoffsetsettingsexistingbefore
PartialResetremainunchanged.Theflagsareupdatedaccordingtothetiming
modeandoffsetsineffect. PRSisusefulforresettingadeviceinmid-operation,
whenreprogrammingprogrammableflagswouldbeundesirable.
ItisalsopossibletoselectthetimingmodeofthePAE(ProgrammableAlmost-
Empty flag) and PAF (Programmable Almost-Full flag) outputs. The timing
modescanbesettobeeitherasynchronousorsynchronousforthePAEand
PAFflags.
IfasynchronousPAE/PAFconfigurationisselected, thePAEisasserted
LOWontheLOW-to-HIGHtransitionofRCLK.PAEisresettoHIGHontheLOW-
to-HIGHtransitionofWCLK.Similarly,thePAFisassertedLOWontheLOW-
to-HIGHtransitionofWCLKandPAF is resettoHIGHonthe LOW-to-HIGH
transitionofRCLK.
IfsynchronousPAE/PAFconfigurationisselected,thePAEisassertedand
updated on the rising edge of RCLK only and not WCLK. Similarly, PAF is
PARTIAL RESET (PRS) MASTER RESET (MRS)
READ CLOCK (RCLK)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
READ ENABLE (REN)
IDT
OUTPUT ENABLE (OE)
LOAD (LD)
(x36, x18, x9) DATA IN (D - D
72V3640
72V3650
72V3660
72V3670
72V3680
72V3690
72V36100
72V36110
0
n)
(x36, x18, x9) DATA OUT (Q0 - Qn)
RETRANSMIT (RT)
SERIAL ENABLE(SEN)
FIRST WORD FALL THROUGH/SERIAL INPUT
(FWFT/SI)
EMPTY FLAG/OUTPUT READY (EF/OR)
PROGRAMMABLE ALMOST-EMPTY (PAE)
HALF-FULL FLAG (HF)
FULL FLAG/INPUT READY (FF/IR)
BIG-ENDIAN/LITTLE-ENDIAN (BE)
INTERSPERSED/
PROGRAMMABLE ALMOST-FULL (PAF)
NON-INTERSPERSED PARITY (IP)
4667 drw 03
OUTPUT WIDTH (OW)
INPUT WIDTH (IW)
BUS-
MATCHING
(BM)
Figure 1. Single Device Configuration Signal Flow Diagram
3
TM
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
assertedandupdatedontherisingedgeofWCLKonlyandnotRCLK.Themode
desiredisconfiguredduringMasterResetbythestateoftheProgrammableFlag
Mode (PFM) pin.
TheRetransmitfunctionallowsdatatoberereadfromtheFIFOmorethan
once. ALOWontheRTinputduringarisingRCLKedgeinitiatesaretransmit
operationbysettingthereadpointertothefirstlocationofthememoryarray.
Azero-latencyretransmittimingmodecanbeselectedusingtheRetransmit
timing Mode pin (RM). During Master Reset, a LOW on RM will select zero
latency retransmit. A HIGH on RM during Master Reset will select normal
latency.
If zero latency retransmit operation is selected, the first data word to be
retransmittedwillbeplacedontheoutputregisterwithrespecttothesameRCLK
edgethatinitiatedtheretransmitbasedonRTbeingLOW.
RefertoFigure11and12forRetransmitTimingwithnormallatency. Refer
to Figure 13 and 14 for Zero Latency Retransmit Timing.
bereadoutoftheFIFOfirst,followedbytheleastsignificantbyte.IfLittle-Endian
formatisselected,thentheleastsignificantbyteofthelongwordwrittenintothe
FIFOwillbereadoutfirst,followedbythemostsignificantbyte.Themodedesired
isconfiguredduringmasterresetbythestateoftheBig-Endian(BE)pin.See
Figure 4 for Bus-Matching Byte Arrangement.
TheInterspersed/Non-InterspersedParity(IP)bitfunctionallowstheuser
to select the parity bit in the word loaded into the parallel port (D0-Dn) when
programmingtheflagoffsets.IfInterspersedParitymodeisselected,thenthe
FIFOwillassumethattheparitybitislocatedinbitpositionsD8,D17,D26and
D35duringtheparallelprogrammingoftheflagoffsets. IfNon-Interspersed
Paritymode is selected, thenD8, D17andD26are assumedtobe validbits
andD32,D33,D34andD35areignored. IPmodeisselectedduring Master
ResetbythestateoftheIPinputpin.InterspersedParitycontrolonlyhas an
effectduringparallelprogrammingoftheoffsetregisters.Itdoesnoteffectthedata
writtentoandreadfromthe FIFO.
Thedevicecanbeconfiguredwithdifferentinputandoutputbuswidthsas
shown in Table 1.
ABig-Endian/Little-Endiandatawordformatis provided.This functionis
usefulwhendataiswrittenintotheFIFOinlongwordformat(x36/x18)andread
outoftheFIFOinsmallword(x18/x9)format.IfBig-Endianmodeisselected,
thenthemostsignificantbyte(word)ofthelongwordwrittenintotheFIFOwill
If,atanytime,theFIFOisnotactivelyperforminganoperation,thechipwill
automaticallypowerdown.Onceinthepowerdownstate,thestandbysupply
currentconsumptionisminimized. Initiatinganyoperation(byactivatingcontrol
inputs)willimmediatelytakethedeviceoutofthepowerdownstate.
The IDT72V3640/72V3650/72V3660/72V3670/72V3680/72V3690/
72V36100/72V36110arefabricatedusingIDT’shighspeedsubmicronCMOS
technology.
TABLE 1 BUS-MATCHING CONFIGURATION MODES
BM
IW
OW
Write Port Width
Read Port Width
L
H
H
H
H
L
L
L
H
H
L
L
H
L
H
x36
x36
x36
x18
x9
x36
x18
x9
x36
x36
NOTE:
1. Pin status during Master Reset.
4
TM
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
PINDESCRIPTION
Symbol
Name
I/O
Description
D0–D35 DataInputs
I
I
Data inputs for a 36-, 18- or 9-bit bus. When in 18- or 9-bit mode, the unused input pins are in a don’t care state.
MRS
MasterReset
MRSinitializesthereadandwritepointerstozeroandsetstheoutputregistertoall zeroes.DuringMasterReset,the
FIFOisconfiguredforeitherFWFTorIDTStandardmode,Bus-Matchingconfigurations,oneofeightprogrammable
flagdefaultsettings,serialorparallelprogrammingoftheoffsetsettings,Big-Endian/Little-Endianformat, zero
latencytimingmode,interspersedparity,andsynchronousversusasynchronousprogrammableflagtimingmodes.
PRS
RT
PartialReset
Retransmit
I
I
PRSinitializesthereadandwritepointerstozeroandsetstheoutputregistertoall zeroes.DuringPartialReset,the
existingmode(IDTorFWFT),programmingmethod(serialorparallel),andprogrammableflagsettingsareallretained.
RT assertedonthe risingedge ofRCLKinitializes the READpointertozero, sets the EFflagtoLOW(OR toHIGH
inFWFTmode)anddoesnotdisturbthewritepointer,programmingmethod,existingtimingmodeorprogrammable
flagsettings.RTisusefultorereaddatafromthefirstphysicallocationoftheFIFO.
FWFT/SI FirstWordFall
I
DuringMasterReset,selects FirstWordFallThroughorIDTStandardmode.AfterMasterReset,this pin
functionsasaserialinputforloadingoffsetregisters.
Through/Serial In
(1)
OW
OutputWidth
InputWidth
I
I
I
I
This pin, alongwithIWandBM, selects the bus widthofthe readport. See Table 1forbus size configuration.
This pin, alongwithOWandMB, selects the bus widthofthe write port. See Table 1forbus size configuration.
BMworkswithIWandOWtoselectthebussizesforbothwriteandreadports. SeeTable1forbussizeconfiguration.
(1)
IW
(1)
BM
Bus-Matching
(1)
BE
Big-Endian/
Little-Endian
During Master Reset, a LOW on BE will select Big-Endian operation. A HIGH onBE during Master Reset
willselectLittle-Endianformat.
(1)
RM
RetransmitTiming
Mode
I
I
I
DuringMasterReset,aLOWonRMwillselectzerolatencyRetransmittimingMode.AHIGHonRMwillselect
normallatencymode.
(1)
PFM
Programmable
Flag Mode
DuringMasterReset,aLOWonPFMwillselectAsynchronous Programmableflagtimingmode.AHIGHonPFM
willselectSynchronousProgrammableflagtimingmode.
IP(1)
InterspersedParity
DuringMasterReset,aLOWonIPwillselectNon-InterspersedParitymode.A HIGHwillselectInterspersedParity
mode.InterspersedParitycontrolonlyhasaneffectduringparallelprogrammingoftheoffsetregisters.Itdoesnoteffect
the data writtentoandreadfromthe FIFO.
FSEL0(1) FlagSelectBit0
FSEL1(1) FlagSelectBit1
I
I
I
DuringMasterReset,thisinputalongwithFSEL1andtheLDpin,willselectthedefaultoffsetvaluesfortheprogrammable
flags PAE andPAF. There are uptoeightpossible settings available.
DuringMasterReset,thisinputalongwithFSEL0andtheLDpinwillselectthedefaultoffsetvaluesfortheprogrammable
flags PAE andPAF. There are uptoeightpossible settings available.
WhenenabledbyWEN,therisingedgeofWCLKwritesdataintotheFIFOandoffsetsinto theprogrammableregisters
forparallelprogramming, andwhenenabledbySEN, the risingedge ofWCLKwrites one bitofdata intothe
programmableregisterforserialprogramming.
WCLK
WriteClock
WEN
RCLK
WriteEnable
ReadClock
I
I
WENenablesWCLKforwritingdataintotheFIFOmemoryandoffsetregisters.
WhenenabledbyREN,therisingedgeofRCLKreadsdatafromtheFIFO memoryandoffsetsfromtheprogrammable
registers.
REN
OE
SEN
LD
ReadEnable
OutputEnable
SerialEnable
Load
I
I
I
I
RENenables RCLKforreadingdatafromtheFIFOmemoryandoffsetregisters.
OEcontrolstheoutputimpedanceofQn.
SENenablesserialloadingofprogrammableflagoffsets.
Thisisadualpurposepin.DuringMasterReset,thestateoftheLD inputalongwithFSEL0andFSEL1,determines
oneofeightdefaultoffsetvaluesforthePAEandPAFflags,alongwiththemethodbywhichtheseoffsetregisterscan
beprogrammed,parallelorserial(seeTable2).AfterMasterReset,thispinenableswritingtoandreadingfromthe
offsetregisters.
FF/IR
Full Flag/
O
In the IDT Standard mode, the FF function is selected. FF indicates whether or Input Ready not theFIFOmemory
isfull. IntheFWFTmode,theIRfunctionisselected. IRindicateswhetherornotthereisspaceavailableforwriting
totheFIFOmemory.
EF/OR
PAF
PAE
HF
EmptyFlag/
O
O
O
Inthe IDTStandardmode, the EFfunctionis selected. EF indicates whetherornotthe FIFOmemoryis empty.
InFWFTmode,theOR functionisselected.ORindicateswhetherornotthereisvaliddataavailableattheoutputs.
PAF goes HIGHifthenumberoffreelocations intheFIFOmemoryis morethanoffsetm,whichis storedinthe
FullOffsetregister. PAF goes LOWifthe numberoffree locations inthe FIFOmemoryis less thanorequaltom.
PAEgoesLOWifthenumberofwordsintheFIFOmemoryislessthanoffsetn,whichisstoredintheEmptyOffset
register. PAE goes HIGH if the number of words in the FIFO memory is greater than or equal to offset n.
HF indicates whethertheFIFOmemoryis moreorless thanhalf-full.
OutputReady
Programmable
Almost-FullFlag
Programmable
Almost-EmptyFlag
Half-FullFlag
O
O
Q0–Q35 DataOutputs
Data outputs for an 36-, 18- or 9-bit bus. When in 18- or 9-bit mode, the unused output pins are in a don’t care
state.Outputsarenot5VtolerantregardlessofthestateofOE.
NOTE:
1. Inputs should not change state after Master Reset.
5
TM
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
Rating
Com’l & Ind’l
Unit
(2)
VTERM
TerminalVoltage
–0.5to+4.5
V
Symbol
Parameter
Min.
Typ.
Max. Unit
with respect to GND
(1)
VCC
SupplyVoltageCom’l/Ind’l
SupplyVoltageCom’l/Ind’l
InputHighVoltageCom’l/Ind’l
InputLowVoltageCom’l/Ind’l
3.15
0
3.3
0
3.45
0
V
V
TSTG
IOUT
Storage
Temperature
–55to+125
–50to+50
°C
GND
(2)
VIH
2.0
—
0
—
—
—
5.5
0.8
70
V
DCOutputCurrent
mA
(3)
VIL
V
NOTES:
TA
TA
OperatingTemperature
Commercial
°C
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
OperatingTemperature
Industrial
-40
—
85
°C
NOTES:
2. VCC terminal only.
1. VCC = 3.3V ± 0.15V, JEDEC JESD8-A compliant.
2. Outputs are not 5V tolerant.
3. 1.5V undershoots are allowed for 10ns once per cycle.
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 3.3V ± 0.15V, TA = 0°C to +70°C;Industrial: VCC = 3.3V ± 0.15V, TA = -40°C to +85°C; JEDEC JESD8-A compliant)
IDT72V3640L
IDT72V3650L
IDT72V3660L
IDT72V3670L
IDT72V3680L
IDT72V3690L
IDT72V36100L
IDT72V36110L
Commercial and Industrial(1)
tCLK = 7.5, 10, 15 ns
Symbol
Parameter
Min.
Max.
Unit
(2)
ILI
InputLeakageCurrent
OutputLeakageCurrent
–1
–10
2.4
—
—
—
1
µ A
µA
V
(3)
ILO
10
—
0.4
40
15
VOH
Output Logic “1” Voltage, IOH = –2 mA
Output Logic “0” Voltage, IOL = 8 mA
Active Power Supply Current
StandbyCurrent
VOL
V
ICC1(4,5,6)
ICC2(4,7)
mA
mA
NOTES:
1. Industrial temperature range product for the 15ns speed grade is available as a standard device. All other speed grades are available by special order.
2. Measurements with 0.4 ≤ VIN ≤ VCC.
3. OE ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
4. Tested with outputs open (IOUT = 0).
5. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.
6. Typical ICC1 = 4.2 + 1.4*fS + 0.02*CL*fS (in mA) with VCC = 3.3V, tA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2,
CL = capacitive load (in pF).
7. All Inputs = VCC - 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
CAPACITANCE(TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Conditions
Max.
Unit
(2)
CIN
Input
VIN = 0V
10
pF
Capacitance
(1,2)
COUT
Output
VOUT = 0V
10
pF
Capacitance
NOTES:
1. With output deselected, (OE ≥ VIH).
2. Characterized values, not currently tested.
6
TM
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
ACELECTRICALCHARACTERISTICS(1)
(Commercial: VCC = 3.3V ± 0.15V, TA = 0°C to +70°C;Industrial: VCC = 3.3V ± 0.15V, TA = -40°C to +85°C; JEDEC JESD8-A compliant)
Commercial
Com’l & Ind’l(2)
IDT72V3640L15
IDT72V3650L15
IDT72V3660L15
IDT72V3670L15
IDT72V3680L15
IDT72V3690L15
IDT72V36100L15
IDT72V36110L15
IDT72V3640L7.5
IDT72V3650L7.5
IDT72V3660L7.5
IDT72V3670L7.5
IDT72V3680L7.5
IDT72V3690L7.5
IDT72V3640L10
IDT72V3650L10
IDT72V3660L10
IDT72V3670L10
IDT72V3680L10
IDT72V3690L10
IDT72V36100L10
IDT72V36110L10
IDT72V36100L7.5
IDT72V36110L7.5
Symbol
fS
Parameter
Clock Cycle Frequency
Min.
—
2
Max.
Min.
—
2
Max.
Min.
—
2
Max.
Unit
MHz
ns
133.3
5
100
6.5
—
—
—
—
—
—
—
—
—
—
—
—
15
66.7
10
—
—
—
—
—
—
—
—
—
—
—
—
15
—
—
8
tA
DataAccessTime
Clock Cycle Time
Clock High Time
Clock Low Time
DataSetupTime
DataHoldTime
tCLK
tCLKH
tCLKL
tDS
7.5
3.5
3.5
2.5
0.5
2.5
0.5
3.5
0.5
10
—
—
—
—
—
—
—
—
—
—
—
—
15
—
—
6
10
15
6
ns
4.5
4.5
3.5
0.5
3.5
0.5
3.5
0.5
10
ns
6
ns
4
ns
tDH
1
ns
tENS
tENH
tLDS
tLDH
tRS
EnableSetupTime
EnableHoldTime
LoadSetupTime
LoadHoldTime
4
ns
1
ns
4
ns
1
ns
(3)
ResetPulseWidth
15
15
15
—
4
ns
tRSS
tRSR
tRSF
tRTS
tOLZ
tOE
ResetSetupTime
15
15
ns
ResetRecoveryTime
ResettoFlagandOutputTime
RetransmitSetupTime
10
10
ns
—
3.5
0
—
3.5
0
ns
—
—
6
ns
(4)
OutputEnabletoOutputinLowZ
OutputEnabletoOutputValid
0
ns
2
2
2
ns
(4)
tOHZ
tWFF
tREF
tPAFA
OutputEnabletoOutputinHighZ
Write Clock to FF or IR
Read Clock to EF or OR
ClocktoAsynchronousProgrammable
Almost-FullFlag
2
6
2
6
2
8
ns
—
—
—
5
—
—
—
6.5
6.5
16
—
—
—
10
10
20
ns
5
ns
12.5
ns
tPAFS
tPAEA
tPAES
WriteClocktoSynchronousProgrammable
Almost-FullFlag
—
—
—
5
12.5
5
—
—
—
6.5
16
—
—
—
10
20
10
ns
ns
ns
ClocktoAsynchronousProgrammable
Almost-EmptyFlag
ReadClocktoSynchronousProgrammable
Almost-EmptyFlag
6.5
tHF
Clock to HF
Skew time between RCLK and WCLK for
—
5
12.5
—
—
7
16
—
9
20
ns
ns
tSKEW1
—
—
EF/OR and FF/IR
tSKEW2
Skew time between RCLK and WCLK for
7
—
10
—
14
—
ns
PAE and PAF
NOTES:
1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.
2. Industrial temperature range is available by special order for speed grades faster than 15ns.
3. Pulse widths less than minimum values are not allowed.
4. Values guaranteed by design, not currently tested.
7
TM
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
AC TEST LOADS - 7.5ns Speed Grade
ACTESTCONDITIONS
InputPulseLevels
GND to 3.0V
3ns(1)
InputRise/FallTimes
1.5V
InputTimingReferenceLevels
OutputReferenceLevels
OutputLoadfortCLK =10ns,15ns
OutputLoadfortCLK=7.5ns
1.5V
1.5V
50
Ω
SeeFigure2a
See Figure 2b & 2c
Z0 = 50Ω
I/O
NOTE:
4667 drw04a
1. For 133MHz operation input rise/fall times are 1.5ns.
Figure 2b. AC Test Load
ACTESTLOADS-10ns,15nsSpeedGrades
6
5
4
3
2
1
3.3V
330Ω
D.U.T.
30pF*
510Ω
4667 drw04
20 30 50 80 100
Capacitance (pF)
200
4667 drw04b
Figure 2a. Output Load
* Includes jig and scope capacitances.
Figure 2c. Lumped Capacitive Load, Typical Derating
8
TM
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
writes for the IDT72V36100 and 131,072 writes for the IDT72V36110,
respectively.
FUNCTIONALDESCRIPTION
If the FIFO is full, the first read operation will cause FF to go HIGH.
SubsequentreadoperationswillcausePAFandHFtogoHIGHattheconditions
describedinTable3.Iffurtherreadoperationsoccur,withoutwriteoperations,
PAE will go LOW when there are n words in the FIFO, where n is the empty
offsetvalue.ContinuingreadoperationswillcausetheFIFOtobecomeempty.
WhenthelastwordhasbeenreadfromtheFIFO,theEFwillgoLOWinhibiting
further read operations. REN is ignored when the FIFO is empty.
WhenconfiguredinIDTStandardmode,theEFandFFoutputsaredouble
register-bufferedoutputs.
TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH
(FWFT) MODE
The IDT72V3640/72V3650/72V3660/72V3670/72V3680/72V3690/
72V36100/72V36110supporttwodifferenttimingmodes ofoperation:IDT
Standardmode orFirstWordFallThrough(FWFT)mode. The selectionof
whichmodewilloperateisdeterminedduringMasterReset,bythestateofthe
FWFT/SIinput.
If,atthetimeofMasterReset,FWFT/SIisLOW,thenIDTStandardmode
willbeselected. This modeuses theEmptyFlag(EF)toindicatewhetheror
notthereareanywordspresentintheFIFO.ItalsousestheFullFlagfunction
(FF)toindicatewhetherornottheFIFOhasanyfreespaceforwriting. InIDT
Standard mode, every word read from the FIFO, including the first, must be
requested using the Read Enable (REN) and RCLK.
If,atthetimeofMasterReset,FWFT/SIisHIGH,thenFWFTmodewillbe
selected. ThismodeusesOutputReady(OR)toindicatewhetherornotthere
isvaliddataatthedataoutputs(Qn). ItalsousesInputReady(IR)toindicate
whether or not the FIFO has any free space for writing. In the FWFT mode,
thefirstwordwrittentoanemptyFIFOgoesdirectlytoQnafterthreeRCLKrising
edges,REN=LOWisnotnecessary. Subsequentwordsmustbeaccessed
using the Read Enable (REN) and RCLK.
Relevanttimingdiagrams forIDTStandardmodecanbefoundinFigure
7,8,11 and 13.
FIRST WORD FALL THROUGH MODE (FWFT)
In this mode, the status flags, IR, PAF, HF, PAE, and OR operate in the
manneroutlinedinTable4.TowritedataintototheFIFO,WENmustbeLOW.
DatapresentedtotheDATAINlineswillbeclockedintotheFIFOonsubsequent
transitionsofWCLK.Afterthefirstwriteisperformed,theOutputReady(OR)
flagwillgoLOW.SubsequentwriteswillcontinuetofilluptheFIFO.PAEwillgo
HIGHaftern+2wordshavebeenloadedintotheFIFO,wherenistheempty
offsetvalue.ThedefaultsettingforthesevaluesarestatedinthefootnoteofTable
2.Thisparameterisalsouserprogrammable.SeesectiononProgrammable
FlagOffsetLoading.
Varioussignals,bothinputandoutputsignalsoperatedifferentlydepending
onwhichtimingmodeisineffect.
If one continued to write data into the FIFO, and we assumed no read
operationsweretakingplace,theHFwouldtoggletoLOWoncethe514thword
fortheIDT72V3640,1,026thwordfortheIDT72V3650,2,050thwordforthe
IDT72V3660, 4,098th word for the IDT72V3670, 8,194th word for the
IDT72V3680, 16,386th word for the IDT72V3690, 32,770th word for the
IDT72V36100 and 65,538th word for the IDT72V36110, respectively was
writtenintotheFIFO. ContinuingtowritedataintotheFIFOwillcausethePAF
togoLOW.Again,ifnoreadsareperformed, thePAFwillgoLOWafter(1,025-m)
writesfortheIDT72V3640, (2,049-m)writesfortheIDT72V3650,(4,097-m)
writesfortheIDT72V3660 and(8,193-m)writesfortheIDT72V3670,16,385
writesfortheIDT72V3680,32,769writesfortheIDT72V3690,65,537writes
fortheIDT72V36100and131,073writesfortheIDT72V36110,wheremisthe
fulloffsetvalue. Thedefaultsettingforthesevaluesarestatedinthefootnote
of Table 2.
WhentheFIFOisfull,theInputReady(IR)flagwillgoHIGH,inhibitingfurther
writeoperations. Ifnoreadsareperformedafterareset,IRwillgoHIGHafter
Dwrites tothe FIFO. D=1,025writes forthe IDT72V3640, 2,049writes for
the IDT72V3650, 4,097 writes for the IDT72V3660 and 8,193 writes for the
IDT72V3670,16,385 writes for the IDT72V3680, 32,769 writes for the
IDT72V3690,65,537writesfortheIDT72V36100and131,073writesforthe
IDT72V36110,respectively.NotethattheadditionalwordinFWFTmodeisdue
tothecapacityofthememoryplusoutputregister.
IftheFIFOisfull,thefirstreadoperationwillcausethe IRflagtogoLOW.
Subsequent read operations will cause the PAF and HF to go HIGH at the
conditionsdescribedinTable4.Iffurtherreadoperationsoccur,withoutwrite
operations,thePAEwillgoLOWwhentherearen+1wordsintheFIFO,where
nistheemptyoffsetvalue.ContinuingreadoperationswillcausetheFIFOto
becomeempty.WhenthelastwordhasbeenreadfromtheFIFO,OR willgo
HIGHinhibitingfurtherreadoperations.RENisignoredwhentheFIFOisempty.
When configured in FWFT mode, the OR flag output is triple register-
buffered,andtheIRflagoutputisdoubleregister-buffered.
IDT STANDARD MODE
In this mode, the status flags, FF, PAF, HF, PAE, and EF operate in the
manneroutlinedinTable3.TowritedataintototheFIFO,WriteEnable(WEN)
mustbeLOW.DatapresentedtotheDATAINlineswillbeclockedintotheFIFO
on subsequent transitions of the Write Clock (WCLK). After the first write is
performed,theEmptyFlag(EF)willgoHIGH.Subsequentwriteswillcontinue
tofilluptheFIFO.TheProgrammableAlmost-Emptyflag(PAE)willgoHIGH
aftern+1wordshavebeenloadedintotheFIFO,wherenistheemptyoffset
value.ThedefaultsettingforthesevaluesarestatedinthefootnoteofTable2.
Thisparameterisalsouserprogrammable.SeesectiononProgrammableFlag
OffsetLoading.
If one continued to write data into the FIFO, and we assumed no read
operationsweretakingplace,theHalf-Fullflag(HF)wouldtoggletoLOWonce
the 513rdwordforIDT72V3640,1,025thwordforIDT72V3650,2,049thword
for IDT72V3660, 4,097th word for IDT72V3670, 8,193th word for the
IDT72V3680, 16,385th word for the IDT72V3690, 32,769th word for the
IDT72V36100 and 65,537th word for the IDT72V36110, respectively was
written into the FIFO. Continuing to write data into the FIFO will cause the
Programmable Almost-Full flag (PAF) to go LOW. Again, if no reads are
performed, thePAF willgoLOWafter(1,024-m)writesfortheIDT72V3640,
(2,048-m)writesfortheIDT72V3650,(4,096-m)writesfortheIDT72V3660,
(8,192-m)writesfortheIDT72V3670,(16,384-m)writesfortheIDT72V3680,
(32,768-m)writesfortheIDT72V3690,(65,536-m)writesfortheIDT72V36100
and(131,072-m)writesfortheIDT72V36110. Theoffset“m”isthefulloffset
value.ThedefaultsettingforthesevaluesarestatedinthefootnoteofTable2.
Thisparameterisalsouserprogrammable.SeesectiononProgrammableFlag
OffsetLoading.
WhentheFIFOisfull,theFullFlag(FF)willgoLOW,inhibitingfurtherwrite
operations. Ifnoreadsareperformedafterareset,FFwillgoLOWafterDwrites
to the FIFO. D = 1,024 writes for the IDT72V3640, 2,048 writes for the
IDT72V3650,4,096writesfortheIDT72V3660,8,192writesfortheIDT72V3670,
16,384writesfortheIDT72V3680,32,768writesfortheIDT72V3690,65,536
RelevanttimingdiagramsforFWFTmodecanbefoundinFigure9,10,12,
and 14.
9
TM
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
PROGRAMMING FLAG OFFSETS
TABLE 2 DEFAULT PROGRAMMABLE
FullandEmptyFlagoffsetvaluesareuserprogrammable.TheIDT72V3640/
72V3650/72V3660/72V3670/72V3680/72V3690/72V36100/72V36110have
internalregistersfortheseoffsets.Thereareeightdefaultoffsetvaluesselectable
duringMasterReset. TheseoffsetvaluesareshowninTable2.Offsetvalues
can also be programmed into the FIFO in one of two ways; serial or parallel
loadingmethod.TheselectionoftheloadingmethodisdoneusingtheLD(Load)
pin.DuringMasterReset,thestateoftheLDinputdetermineswhetherserial
orparallelflagoffsetprogrammingis enabled. AHIGHonLD duringMaster
Resetselectsserialloadingofoffsetvalues. ALOWonLDduringMasterReset
selectsparallelloadingofoffsetvalues.
InadditiontoloadingoffsetvaluesintotheFIFO,itisalsopossibletoread
thecurrentoffsetvalues.Offsetvaluescanbereadviatheparalleloutputport
Q0-Qn,regardlessoftheprogrammingmodeselected(serialorparallel).Itis
notpossibletoreadtheoffsetvaluesinserialfashion.
Figure3,ProgrammableFlagOffsetProgrammingSequence,summaries
thecontrolpinsandsequenceforbothserialandparallelprogrammingmodes.
Foramoredetaileddescription,seediscussionthatfollows.
FLAG OFFSETS
IDT72V3640, 72V3650
LD
L
L
L
L
H
H
H
H
FSEL1
FSEL0
Offsets n,m
H
L
L
H
L
H
L
H
L
H
L
H
L
L
H
H
511
255
127
63
31
15
7
3
LD
FSEL1
FSEL0
Program Mode
(3)
H
X
X
Serial
(4)
L
X
X
Parallel
Theoffsetregistersmaybeprogrammed(andreprogrammed)anytimeafter
MasterReset,regardlessofwhetherserialorparallelprogramminghasbeen
selected. Validprogrammingranges are from0toD-1.
IDT72V3660, 72V3670, 72V3680, 72V3690
LD
H
L
L
L
FSEL1
FSEL0
Offsets n,m
L
H
L
L
L
H
L
H
L
H
H
1,023
511
255
127
63
SYNCHRONOUS vs ASYNCHRONOUS PROGRAMMABLE FLAG TIM-
ING SELECTION
The IDT72V3640/72V3650/72V3660/72V3670/72V3680/72V3690/
72V36100/72V36110canbeconfiguredduringtheMasterResetcycle with
either synchronousorasynchronoustimingforPAFandPAEflagsbyuseof
the PFM pin.
If synchronous PAF/PAE configuration is selected (PFM, HIGH during
MRS),thePAFisassertedandupdatedontherisingedgeofWCLKonlyand
notRCLK. Similarly,PAEisassertedandupdatedontherisingedgeofRCLK
onlyandnotWCLK.Fordetailtimingdiagrams,seeFigure17forsynchronous
PAF timingandFigure18forsynchronous PAEtiming.
L
L
H
H
L
H
H
H
31
15
7
H
LD
H
L
FSEL1
FSEL0
Program Mode
(3)
X
X
X
X
Serial
Parallel
(4)
If asynchronous PAF/PAE configuration is selected (PFM, LOW during
MRS),thePAFisassertedLOWontheLOW-to-HIGHtransitionofWCLKand
PAFisresettoHIGHontheLOW-to-HIGHtransitionofRCLK. Similarly,PAE
isassertedLOWontheLOW-to-HIGHtransitionofRCLK.PAEisresettoHIGH
ontheLOW-to-HIGHtransitionofWCLK.Fordetailtimingdiagrams,seeFigure
19forasynchronousPAFtimingandFigure20forasynchronousPAEtiming.
IDT72V36100, 72V36110
LD
L
L
FSEL1
FSEL0
Offsets n,m
16,383
8,191
4,095
2,047
1,023
511
H
L
H
H
L
L
H
L
L
H
H
L
L
H
H
H
H
L
L
H
H
L
255
127
LD
H
L
FSEL1
FSEL0
Program Mode
(3)
X
X
X
X
Serial
(4)
Parallel
NOTES:
1. n = empty offset for PAE.
2. m = full offset for PAF.
3. As well as selecting serial programming mode, one of the default values will also
be loaded depending on the state of FSEL0 & FSEL1.
4. As well as selecting parallel programming mode, one of the default values will
also be loaded depending on the state of FSEL0 & FSEL1.
10
TABLE 3
STATUS FLAGS FOR IDT STANDARD MODE
IDT72V3640
IDT72V3650
IDT72V3660
HF
FF PAF
PAE EF
IDT72V3670
0
0
H
H
H
L
L
L
0
0
H
H
H
H
H
H
H
H
L
1 to n(1)
1 to n(1)
1 to n(1)
1 to n(1)
H
H
H
H
H
L
Number of
Words in
FIFO
(n+1) to 1,024
(n+1) to 512
(n+1) to 2,048
(n+1) to 4,096
H
H
H
H
1,025 to (2048-(m+1))
513 to (1,024-(m+1))
2,049 to (4,096-(m+1))
4,097 to (8,192-(m+1))
(2048-m)
to 2,047
(1024-m) to 1,023
1,024
(4,096-m) to 4,095
4,096
(8,192-m)
to 8,191
H
L
L
2,048
L
8,192
L
FF PAF
PAE EF
HF
IDT72V3680
IDT72V3690
IDT72V36100
0
IDT72V36110
0
H
H
H
L
L
L
L
0
0
H
H
H
H
H
H
H
H
L
1 to n(1)
1 to n
1 to n(1)
1 to n (1)
Number of
Words in
FIFO
(1)
H
H
H
H
H
H
H
H
H
(n+1) to 8,192
(n+1) to 16,384
(n+1) to 32,768
32,769 to (65,536-(m+1))
(n+1) to 65,536
65,537 to (131,072-(m+1))
8,193 to (16,384-(m+1))
16,385 to (32,768-(m+1))
to 16,383
H
L
L
(16,384-m)
(32,768-m) to 32,767
32,768
to 65,535
to 131,071
(65,536-m)
(131,072-m)
L
L
16,384
65,536
131,072
NOTE:
1. See table 2 for values for n, m.
TABLE 4
STATUS FLAGS FOR FWFT MODE
IDT72V3670
IDT72V3640
IDT72V3650
HF
IDT72V3660
IR PAF
PAE OR
0
0
0
H
H
H
L
L
H
L
L
L
L
L
0
L
L
L
L
H
H
H
H
L
1 to n+1
1 to n+1
1 to n+1
1 to n+1
L
Number of
Words in
FIFO
(n+2) to 1,025
(n+2) to 2,049
(n+2) to 4,097
(n+2) to 513
H
H
H
H
514 to (1,025-(m+1))
1,026 to (2,049-(m+1))
(2,049-m) to 2,048
2,049
2,050 to (4,097-(m+1))
4,098 to (8,193-(m+1))
to 4,096
to 8,192
(4,097-m)
(8,193-m)
(1,025-m)
L
L
to 1,024
H
L
1,025
4,097
8,193
L
HF
IDT72V3690
IR PAF
PAE OR
IDT72V36110
IDT72V3680
0
IDT72V36100
H
H
H
L
L
H
0
0
0
L
L
L
L
H
H
H
H
L
1 to n+1
1 to n+1
1 to n+1
L
Number of
Words in
FIFO
1 to n+1
L
H
H
H
H
L
(n+2) to 8,193
8,194 to (16,385-(m+1))
(n+2) to 16,385
(n+2) to 32,769
32,770 to (65,537-(m+1))
(65,537-m) to 65,536
65,537
(n+2) to 65,537
65,538 to (131,073-(m+1))
(131,073-m) to 131,072
131,073
L
16,386 to (32,769-(m+1))
L
L
L
L
(16,385-m)
(32,769-m)
to 16,384
to 32,768
H
L
L
16,385
32,769
4667 drw 05
NOTE:
1. See table 2 for values for n, m.
TM
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
IDT72V3640
IDT72V3650
IDT72V3660
IDT72V3670
IDT72V3680
IDT72V3690
IDT72V36100
IDT72V36110
WCLK RCLK
LD
WEN
REN
SEN
Parallel write to registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
X
0
0
1
1
Full Offset (MSB)
Parallel read from registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
X
0
0
1
1
0
1
1
0
Full Offset (MSB)
Serial shift into registers:
X
20 bits for the 72V3640
22 bits for the 72V3650
24 bits for the 72V3660
26 bits for the 72V3670
28 bits for the 72V3680
30 bits for the 72V3690
32 bits for the 72V36100
34 bits for the 72V36110
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
X
X
X
X
1
1
1
No Operation
Write Memory
1
1
1
0
X
1
X
0
1
X
X
X
X
X
Read Memory
No Operation
X
4667 drw 06
NOTES:
1. The programming method can only be selected at Master Reset.
2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
3. The programming sequence applies to both IDT Standard and FWFT modes.
Figure 3. Programmable Flag Offset Programming Sequence
12
TM
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
1st Parallel Offset Write/Read Cycle
# of Bits Used:
D/Q35
D/Q19
D/Q0
D/Q17
D/Q8
10 bits for the IDT72V3640
11 bits for the IDT72V3650
12 bits for the IDT72V3660
13 bits for the IDT72V3670
14 bits for the IDT72V3680
15 bits for the IDT72V3690
16 bits for the IDT72V36100
17 bits for the IDT72V36110
Note: All unused bits of the
LSB & MSB are don’t care
EMPTY OFFSET REGISTER (PAE)
Non-Interspersed
Parity
1
1
15 14
9
17 16
16 15
13 12 11 10
8
8
7
7
6
6
5
5
4
4
3
3
2
2
Interspersed
Parity
17
13 12 11 10 9
14
# of Bits Used
2nd Parallel Offset Write/Read Cycle
D/Q35
D/Q19
D/Q0
D/Q17
D/Q8
FULL OFFSET REGISTER (PAF)
Non-Interspersed
Parity
15 14
14
9
1
1
17 16
15
13 12 11 10
8
8
7
7
6
6
5
5
4
4
3 2
Interspersed
Parity
17
13 12 11 10 9
16
3 2
# of Bits Used
IDT72V3640/50/60/70/80/90/100/110
x36 Bus Width
1st Parallel Offset Write/Read Cycle
D/Q17
Data Inputs/Outputs
D/Q16
D/Q0
1st Parallel Offset Write/Read Cycle
D/Q17
EMPTY OFFSET (LSB) REGISTER (PAE)
Non-Interspersed
Parity
Data Inputs/Outputs
4
4
3
3
2
2
1
1
16 15 14 13 12 11 10
15 14 11
9
8
8
7
7
6
6
5
5
D/Q0
D/Q16
Interspersed
Parity
9
10
16
13 12
EMPTY OFFSET (LSB) REGISTER (PAE)
Non-Interspersed
Parity
D/Q8
# of Bits Used
16 15 14 13 12 11 10
13 12 10
9
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
2nd Parallel Offset Write/Read Cycle
16
Interspersed
Parity
15 14
11
9
8
D/Q17
D/Q8
D/Q16
# of Bits Used
Data Inputs/Outputs
D/Q0
EMPTY OFFSET (MSB) REGISTER (PAE)
17
17
2nd Parallel Offset Write/Read Cycle
D/Q17
3rd Parallel Offset Write/Read Cycle
Data Inputs/Outputs
D/Q17
D/Q16
D/Q0
Data Inputs/Outputs
D/Q0
D/Q16
FULL OFFSET (LSB) REGISTER (PAF)
FULL OFFSET (LSB) REGISTER (PAF)
16 15 14
12 11
13
10
9
9
8
7
7
6
6
5
5
4
4
3
2
2
1
16 15 14
12 11
13
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
1
1
16 15
14 13 12 11 10
1
8
3
16 15
14 13 12 11 10
2
D/Q8
D/Q8
4th Parallel Offset Write/Read Cycle
D/Q17
D/Q16
Data Inputs/Outputs
D/Q0
FULL OFFSET (MSB) REGISTER (PAF)
17
17
IDT72V3640/50/60/70/80/90/100
x18 Bus Width
IDT72V36110
x18 Bus Width
4667 drw 07
Figure 3. Programmable Flag Offset Programming Sequence (Continued)
13
TM
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
1st Parallel Offset Write/Read Cycle
D/Q8
1st Parallel Offset Write/Read Cycle
D/Q8
D/Q0
1
D/Q0
EMPTY OFFSET REGISTER (PAE)
EMPTY OFFSET REGISTER (PAE)
7
6
5
4
3
2
10
2
7
6
5
4
3
2
1
8
8
2nd Parallel Offset Write/Read Cycle
D/Q8
D/Q0
9
EMPTY OFFSET REGISTER (PAE)
2nd Parallel Offset Write/Read Cycle
D/Q8
16
14 12 11
10
15
13
D/Q0
9
EMPTY OFFSET REGISTER (PAE)
3rd Parallel Offset Write/Read Cycle
D/Q8
16
14 12 11
15
13
D/Q0
17
EMPTY OFFSET REGISTER (PAE)
3rd Parallel Offset Write/Read Cycle
D/Q8
4th Parallel Offset Write/Read Cycle
D/Q8
D/Q0
1
D/Q0
1
FULL OFFSET REGISTER (PAF)
FULL OFFSET REGISTER (PAF)
5
8
7
6
4
3
5
2
8
7
6
4
3
5th Parallel Offset Write/Read Cycle
D/Q8
D/Q0
9
FULL OFFSET REGISTER (PAF)
4th Parallel Offset Write/Read Cycle
D/Q8
16
14 12 11
10
15
13
D/Q0
9
FULL OFFSET REGISTER (PAF)
6th Parallel Offset Write/Read Cycle
D/Q8
16
14 12 11
10
15
13
D/Q0
17
FULL OFFSET REGISTER (PAF)
IDT72V3640/50/60/70/80/90/100
x9 Bus Width
IDT72V36110
x9 Bus Width
# of Bits Used:
10 bits for the IDT72V3640
11 bits for the IDT72V3650
12 bits for the IDT72V3660
13 bits for the IDT72V3670
14 bits for the IDT72V3680
15 bits for the IDT72V3690
16 bits for the IDT72V36100
17 bits for the IDT72V36110
Note: All unused bits of the
LSB & MSB are don’t care
4667 drw07a
Figure 3. Programmable Flag Offset Programming Sequence (Continued)
14
TM
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
SERIAL PROGRAMMING MODE
Write operations to the FIFO are allowed before and during the parallel
IfSerialProgrammingmodehasbeenselected,asdescribedabove,then programmingsequence.Inthiscase,theprogrammingofalloffsetregistersdoes
programmingofPAEandPAFvaluescanbeachievedbyusingacombination nothavetooccuratonetime. One,twoormoreoffsetregisterscanbewritten
oftheLD,SEN,WCLKandSIinputpins.ProgrammingPAEandPAFproceeds andthenbybringingLDHIGH,writeoperationscanberedirectedtotheFIFO
as follows: whenLD andSEN are setLOW,data onthe SIinputare written, memory.WhenLDissetLOWagain,andWENisLOW,thenextoffsetregister
onebitforeachWCLKrisingedge,startingwiththeEmptyOffsetLSBandending insequenceiswrittento.AsanalternativetoholdingWENLOWandtoggling
withtheFullOffsetMSB. Atotalof20bitsfortheIDT72V3640,22bitsforthe LD, parallel programming can also be interrupted by setting LD LOW and
IDT72V3650,24bitsfortheIDT72V3660,26bitsfortheIDT72V3670,28bits togglingWEN.
fortheIDT72V3680,30bitsfortheIDT72V3690,32bitsfortheIDT72V36100
and34bitsfortheIDT72V36110.SeeFigure15,SerialLoadingofProgram- during the programming process. From the time parallel programming has
mableFlagRegisters,forthetimingdiagramforthismode. begun,aprogrammableflagoutputwillnotbevaliduntiltheappropriateoffset
Notethatthestatusofaprogrammableflag(PAEorPAF)outputisinvalid
Using the serial method, individual registers cannot be programmed wordhasbeenwrittentotheregister(s)pertainingtothatflag.Measuringfrom
selectively. PAEandPAFcanshowavalidstatusonlyafterthecompleteset therisingWCLKedgethatachievestheabovecriteria;PAFwillbevalidafter
of bits (for all offset registers) has been entered. The registers can be twomorerisingWCLKedgesplustPAF,PAEwillbevalidafterthenexttworising
reprogrammedaslongasthecompletesetofnewoffsetbitsisentered. When RCLK edges plus tPAE plus tSKEW2.
LD is LOW and SEN is HIGH, no serial write to the registers can occur.
The act of reading the offset registers employs a dedicated read offset
Write operations to the FIFO are allowed before and during the serial registerpointer. ThecontentsoftheoffsetregisterscanbereadontheQ0-Qn
programmingsequence. Inthiscase,theprogrammingofalloffsetbitsdoes pinswhenLDissetLOWandRENissetLOW.Forx36outputbuswidth,data
nothavetooccuratonce. AselectnumberofbitscanbewrittentotheSIinput are read via Qn from the Empty Offset Register on the first LOW-to-HIGH
andthen,bybringingLDandSENHIGH,datacanbewrittentoFIFOmemory transitionofRCLK.UponthesecondLOW-to-HIGHtransitionofRCLK,dataare
via Dn by toggling WEN. When WEN is brought HIGH with LD and SEN readfromthe FullOffsetRegister. The thirdtransitionofRCLKreads, once
restoredtoaLOW,thenextoffsetbitinsequenceiswrittentotheregistersvia again,fromtheEmptyOffsetRegister.Forx18outputbuswidth,atotaloffour
SI. Ifaninterruptionofserialprogrammingisdesired,itissufficienteithertoset readcyclesarerequiredtoobtainthevaluesoftheoffsetregisters.Startingwith
LDLOWanddeactivateSENortosetSENLOWanddeactivateLD. OnceLD theEmptyOffsetRegisterLSBandfinishingwiththeFullOffsetRegisterMSB.
andSENarebothrestoredtoaLOWlevel,serialoffsetprogrammingcontinues. Forx9outputbuswidth,atotalofsixreadcyclesmustbeperformedontheoffset
Fromthetimeserialprogramminghasbegun,neitherprogrammableflag registers.SeeFigure3,ProgrammableFlagOffsetProgrammingSequence.
willbevaliduntilthefullsetofbitsrequiredtofillalltheoffsetregistershasbeen SeeFigure17, ParallelReadofProgrammableFlagRegisters,forthetiming
written. MeasuringfromtherisingWCLKedgethatachievestheabovecriteria; diagramforthismode.
PAFwillbevalidaftertwomorerisingWCLKedgesplustPAF,PAEwillbevalid
Itispermissibletointerrupttheoffsetregisterreadsequencewithreadsor
writestotheFIFO. TheinterruptionisaccomplishedbydeassertingREN,LD,
afterthe nexttworisingRCLKedges plus tPAE plus tSKEW2.
ItisonlypossibletoreadtheflagoffsetvaluesviatheparalleloutputportQn. orbothtogether.WhenRENandLDarerestoredtoaLOW level,readingof
theoffsetregisterscontinueswhereitleftoff.Itshouldbenoted,andcareshould
PARALLELMODE
IfParallelProgrammingmodehasbeenselected,asdescribedabove,then the data wordthatwas presentonthe outputlines Qnwillbe overwritten.
programmingofPAEandPAFvaluescanbeachievedbyusingacombination Parallelreadingofthe offsetregisters is always permittedregardless of
betakenfromthefactthatwhenaparallelreadoftheflagoffsetsisperformed,
of the LD, WCLK , WEN and Dn input pins. Programming PAE and PAF whichtimingmode (IDTStandardorFWFTmodes)has beenselected.
proceedsasfollows: LDandWENmustbesetLOW.Forx36bitinputbuswidth,
dataontheinputsDnarewrittenintotheEmptyOffsetRegisteronthefirstLOW- RETRANSMITOPERATION
to-HIGH transition of WCLK. Upon the second LOW-to-HIGH transition of
The Retransmit operation allows data that has already been read to be
WCLK,dataarewrittenintotheFullOffsetRegister.ThethirdtransitionofWCLK accessedagain. Thereare2modesofRetransmitoperation,normallatency
writes,onceagain,totheEmptyOffsetRegister. Forx18bitinputbuswidth, andzerolatency. TherearetwostagestoRetransmit:first,asetupprocedure
dataontheinputsDnarewrittenintotheEmptyOffsetRegisterLSBonthefirst that resets the read pointer to the first location of memory, then the actual
LOW-to-HIGHtransitionofWCLK.Uponthe2ndLOW-to-HIGHtransitionof retransmit,whichconsistsofreadingoutthememorycontents,startingatthe
WCLKdataarewrittenintotheEmptyOffsetRegisterMSB.Thethirdtransition beginningofmemory.
ofWCLKwritestotheFullOffsetRegisterLSB,thefourthtransitionofWCLKthen
RetransmitsetupisinitiatedbyholdingRTLOWduringarisingRCLKedge.
writestotheFullOffsetRegisterMSB.ThefifthtransitionofWCLKwritesonce RENandWENmustbeHIGHbeforebringingRTLOW. Whenzerolatencyis
againtotheEmptyOffsetRegisterLSB. Atotaloffourwritestotheoffsetregisters utilized,RENdoesnotneedtobeHIGHbeforebringingRTLOW. Atleasttwowords,
isrequiredtoloadvaluesusingax18inputbuswidth.Foraninputbuswidth butnomorethanD-2wordsshouldhavebeenwrittenintotheFIFO,andread
ofx9bits,atotalofsixwritecyclestotheoffsetregistersisrequiredtoloadvalues. fromtheFIFO,betweenReset(MasterorPartial)andthetimeofRetransmit
See Figure 3, Programmable Flag Offset Programming Sequence. See setup. D=1,024forthe IDT72V3640, 2,048forthe IDT72V3650, 4,096for
Figure 16, Parallel Loading of Programmable Flag Registers, forthe timing the IDT72V3660, 8,192 for the IDT72V3670, 16,384 for the IDT72V3680,
diagramforthismode.
32,768fortheIDT72V3690,65,536fortheIDT72V36100and131,072forthe
Theactofwritingoffsetsinparallelemploysadedicatedwriteoffsetregister IDT72V36110. InFWFTmode, D=1,025forthe IDT72V2640, 2,049forthe
pointer. The act of reading offsets employs a dedicated read offset register IDT72V3650,4,097fortheIDT72V3660,8,193fortheIDT72V3670,16,385
pointer.Thetwopointersoperateindependently;however,areadandawrite fortheIDT72V3680,32,769fortheIDT72V3690,65,537fortheIDT72V36100
shouldnotbeperformedsimultaneouslytotheoffsetregisters. AMasterReset and 131,073 for the IDT72V36110.
initializesbothpointerstotheEmptyOffset(LSB)register.APartialResethas
noeffectonthepositionofthesepointers.
IfIDTStandardmodeisselected,theFIFOwillmarkthebeginningofthe
RetransmitsetupbysettingEFLOW. Thechangeinlevelwillonlybenoticeable
15
TM
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
ifEF was HIGHbefore setup. Duringthis period, the internalreadpointeris
initializedtothefirstlocationoftheRAMarray.
For either IDT Standard mode or FWFT mode, updating of the PAE, HF
and PAF flags begin with the rising edge of RCLK that RT is setup. PAE is
WhenEFgoesHIGH,Retransmitsetupiscompleteandreadoperations synchronizedtoRCLK,thusonthesecondrisingedgeofRCLKafterRTissetup,
maybeginstartingwiththefirstlocationinmemory. SinceIDTStandardmode thePAEflagwillbeupdated. HFisasynchronous,thustherisingedgeofRCLK
isselected,everywordreadincludingthefirstwordfollowingRetransmitsetup thatRTissetupwillupdateHF. PAFissynchronizedtoWCLK,thusthesecond
requires a LOW on REN to enable the rising edge of RCLK. See Figure 11, risingedgeofWCLKthatoccurstSKEW aftertherisingedgeofRCLKthatRT
Retransmit Timing (IDT Standard Mode), forthe relevanttimingdiagram.
is setup will update PAF. RT is synchronized to RCLK.
IfFWFTmodeisselected,theFIFOwillmarkthebeginningoftheRetransmit
TheRetransmitfunctionhastheoptionoftwomodesofoperation,either
setupbysettingOR HIGH.Duringthis period,theinternalreadpointeris set “normal latency” or “zero latency”. Figure 11 and Figure 12 mentioned
tothefirstlocationoftheRAMarray. previously, relate to “normal latency”. Figure 13 and Figure 14 show “zero
WhenORgoesLOW,Retransmitsetupiscomplete;atthesametime,the latency”retransmitoperation.Zerolatencybasicallymeansthatthefirstdata
contentsofthefirstlocationappearontheoutputs. SinceFWFTmodeisselected, wordtoberetransmitted,isplacedontotheoutputregisterwithrespecttothe
thefirstwordappearsontheoutputs,noLOWonRENisnecessary.Reading RCLKpulsethatinitiatedtheretransmit.
all subsequent words requires a LOW on REN to enable the rising edge of
RCLK.SeeFigure12,RetransmitTiming(FWFTMode),fortherelevanttiming
diagram.
16
TM
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
isselected,everywordreadincludingthefirstwordfollowingRetransmitsetup
requires a LOW on REN to enable the rising edge of RCLK. See Figure 11,
Retransmit Timing (IDT Standard Mode), forthe relevanttimingdiagram.
IfFWFTmodeisselected,theFIFOwillmarkthebeginningoftheRetransmit
setupbysettingOR HIGH.Duringthis period,theinternalreadpointeris set
tothefirstlocationoftheRAMarray.
SIGNALDESCRIPTION
INPUTS:
DATA IN (D0 - Dn)
Datainputsfor36-bitwidedata(D0-D35),datainputsfor18-bitwidedata
(D0 - D17) or data inputs for 9-bit wide data (D0 - D8).
WhenORgoesLOW,Retransmitsetupiscomplete;atthesametime,the
contentsofthefirstlocationappearontheoutputs. SinceFWFTmodeisselected,
thefirstwordappearsontheoutputs,noLOWonRENisnecessary.Reading
all subsequent words requires a LOW on REN to enable the rising edge of
RCLK.SeeFigure12,RetransmitTiming(FWFTMode),fortherelevanttiming
diagram.
In Retransmit operation, zero latency mode can be selected using the
RetransmitMode(RM)pinduringaMasterReset. Thiscanbeappliedtoboth
IDT Standard mode and FWFT mode.
CONTROLS:
MASTER RESET ( MRS )
AMasterResetisaccomplishedwhenevertheMRSinputistakentoaLOW
state.Thisoperationsetstheinternalreadandwritepointerstothefirstlocation
oftheRAMarray.PAEwill goLOW, PAFwillgoHIGH,and HFwillgoHIGH.
If FWFT/SI is LOW during Master Reset then the IDT Standard mode,
along with EF and FF are selected. EF will go LOW and FF will go HIGH. If
FWFT/SIisHIGH,thentheFirstWordFallThroughmode(FWFT),alongwith
IR and OR, are selected. OR will go HIGH and IR will go LOW.
AllcontrolsettingssuchasOW,IW,BM,BE,RM,PFMandIParedefined
duringtheMasterResetcycle.
FIRST WORD FALL THROUGH/SERIAL IN (FWFT/SI)
This is a dualpurpose pin. DuringMasterReset, the state ofthe FWFT/
SIinputdetermineswhetherthedevicewilloperateinIDTStandardmodeor
First Word Fall Through (FWFT) mode.
DuringaMasterReset,theoutputregisterisinitializedtoallzeroes.AMaster
Resetisrequiredafterpowerup,beforeawriteoperationcantakeplace.MRS
isasynchronous.
If,atthetimeofMasterReset,FWFT/SIisLOW,thenIDTStandardmode
willbeselected. This modeuses theEmptyFlag(EF)toindicatewhetheror
notthereareanywordspresentintheFIFOmemory. ItalsousestheFullFlag
function(FF)toindicatewhetherornottheFIFOmemoryhasanyfreespace
forwriting. InIDTStandardmode,everywordreadfromtheFIFO,including
the first, mustbe requestedusingthe ReadEnable (REN)andRCLK.
If,atthetimeofMasterReset,FWFT/SIisHIGH,thenFWFTmodewillbe
selected. ThismodeusesOutputReady(OR)toindicatewhetherornotthere
isvaliddataatthedataoutputs(Qn). ItalsousesInputReady(IR)toindicate
whetherornottheFIFOmemoryhasanyfreespaceforwriting. IntheFWFT
mode,thefirstwordwrittentoanemptyFIFOgoesdirectlytoQnafterthreeRCLK
rising edges, REN = LOW is not necessary. Subsequent words must be
accessed using the Read Enable (REN) and RCLK.
See Figure 5, Master Reset Timing, forthe relevanttimingdiagram.
PARTIAL RESET ( PRS )
APartialResetisaccomplishedwheneverthePRS inputistakentoaLOW
state.AsinthecaseoftheMasterReset,theinternalreadandwritepointers
aresettothefirstlocationoftheRAMarray,PAEgoesLOW, PAFgoesHIGH,
and HF goes HIGH.
WhichevermodeisactiveatthetimeofPartialReset,IDTStandardmode
orFirstWordFallThrough,thatmodewillremainselected. IftheIDTStandard
modeisactive,thenFFwillgoHIGHandEFwillgoLOW. IftheFirstWordFall
Through mode is active, then OR will go HIGH, and IR will go LOW.
Following Partial Reset, all values held in the offset registers remain
unchanged. Theprogrammingmethod(parallelorserial)currentlyactiveat
thetimeofPartialResetisalsoretained. Theoutputregisterisinitializedtoall
zeroes. PRS is asynchronous.
AfterMasterReset,FWFT/SIactsasaserialinputforloadingPAEandPAF
offsetsintotheprogrammableregisters. Theserialinputfunctioncanonlybe
usedwhentheserialloadingmethodhasbeenselectedduringMasterReset.
SerialprogrammingusingtheFWFT/SIpinfunctionsthesamewayinbothIDT
StandardandFWFTmodes.
A Partial Reset is useful for resetting the device during the course of
operation,whenreprogrammingprogrammableflagoffsetsettingsmaynotbe
convenient.
WRITE CLOCK (WCLK)
See Figure 6, PartialResetTiming, forthe relevanttimingdiagram.
AwritecycleisinitiatedontherisingedgeoftheWCLKinput.Datasetup
andholdtimesmustbemetwithrespecttotheLOW-to-HIGHtransitionofthe
WCLK.ItispermissibletostoptheWCLK. NotethatwhileWCLKisidle,theFF/
IR,PAFandHFflagswillnotbeupdated. (NotethatWCLKisonlycapableof
updating HF flag to LOW.) The Write and Read Clocks can either be
independentorcoincident.
RETRANSMIT ( RT )
The Retransmit operation allows data that has already been read to be
accessedagain. Thereare2modesofRetransmitoperation,normallatency
andzerolatency. TherearetwostagestoRetransmit:first,asetupprocedure
that resets the read pointer to the first location of memory, then the actual
retransmit,whichconsistsofreadingoutthememorycontents,startingatthe
beginningofthememory.
RetransmitsetupisinitiatedbyholdingRTLOWduringarising RCLKedge.
RENandWENmustbeHIGHbeforebringingRTLOW. Whenzerolatencyis
utilized, RENdoesnotneedtobeHIGHbeforebringingRT LOW.
IfIDTStandardmodeisselected,theFIFOwillmarkthebeginningofthe
RetransmitsetupbysettingEFLOW. Thechangeinlevelwillonlybenoticeable
ifEF was HIGHbefore setup. Duringthis period, the internalreadpointeris
initializedtothefirstlocationoftheRAMarray.
WRITE ENABLE ( WEN )
WhentheWENinput isLOW,datamaybeloadedintotheFIFORAMarray
ontherisingedgeofeveryWCLKcycleifthedeviceisnotfull. Dataisstored
in the RAM array sequentially and independently of any ongoing read
operation.
WhenWENisHIGH,nonewdataiswrittenintheRAMarrayoneachWCLK
cycle.
To prevent data overflow in the IDT Standard mode, FF will go LOW,
inhibitingfurtherwriteoperations. Uponthecompletionofavalidreadcycle,
FF will go HIGH allowing a write to occur. The FF is updated by two WCLK
cycles +tSKEW afterthe RCLKcycle.
WhenEFgoesHIGH,Retransmitsetupiscompleteandreadoperations
maybeginstartingwiththefirstlocationinmemory. SinceIDTStandardmode
17
TM
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
Topreventdataoverflow intheFWFTmode, IR willgoHIGH,inhibiting
AfterMasterReset,theLDpinisusedtoactivatetheprogrammingprocess
furtherwriteoperations. Uponthecompletionofavalidreadcycle,IRwillgo oftheflagoffsetvaluesPAEandPAF.PullingLDLOWwillbeginaserialloading
LOWallowingawritetooccur. TheIRflagis updatedbytwoWCLKcycles + orparallelloadorreadofthese offsetvalues.
tSKEW afterthe validRCLKcycle.
WENisignoredwhentheFIFOisfullineitherFWFTorIDTStandardmode. BUS-MATCHING (BM, IW, OW)
ThepinsBM,IWandOWareusedtodefinetheinputandoutputbuswidths.
READ CLOCK (RCLK)
DuringMasterReset,thestateofthesepinsisusedtoconfigurethedevicebus
AreadcycleisinitiatedontherisingedgeoftheRCLKinput. Datacanbe sizes. SeeTable1forcontrolsettings. Allflagswilloperateontheword/byte
readontheoutputs,ontherisingedgeoftheRCLKinput. Itispermissibleto sizeboundaryasdefinedbytheselectionofbuswidth.SeeFigure4forBus-
stoptheRCLK. NotethatwhileRCLKisidle,theEF/OR,PAEandHFflagswill MatchingByteArrangement.
not be updated. (Note that RCLK is only capable of updating the HF flag to
HIGH.) The Write and Read Clocks can be independent or coincident.
BIG-ENDIAN/LITTLE-ENDIAN ( BE )
During Master Reset, a LOW on BE will select Big-Endian operation. A
HIGHonBEduringMasterResetwillselectLittle-Endianformat.Thisfunction
READ ENABLE ( REN )
WhenReadEnableisLOW,dataisloadedfromtheRAMarrayintotheoutput isusefulwhenthefollowinginputtooutputbuswidthsareimplemented:x36to
register on the rising edge of every RCLK cycle if the device is not empty. x18,x36tox9,x18tox36andx9tox36.IfBig-Endianmodeisselected,then
WhentheRENinputisHIGH,theoutputregisterholdsthepreviousdata themostsignificantbyte(word)ofthelongwordwrittenintotheFIFOwillberead
andnonewdata is loadedintothe outputregister. The data outputs Q0-Qn outoftheFIFOfirst,followedbytheleastsignificantbyte.IfLittle-Endianformat
maintainthepreviousdatavalue.
isselected,thentheleastsignificantbyteofthelongwordwrittenintotheFIFO
IntheIDTStandardmode,everywordaccessedatQn,includingthefirst willbereadoutfirst,followedbythemostsignificantbyte.Themodedesiredis
wordwrittentoanemptyFIFO,mustberequestedusingREN. Whenthelast configured during master reset by the state of the Big-Endian (BE) pin. See
wordhasbeenreadfromtheFIFO,theEmptyFlag(EF)willgoLOW,inhibiting Figure 4 for Bus-Matching Byte Arrangement.
furtherreadoperations. RENisignoredwhentheFIFOisempty.Onceawrite
isperformed,EFwillgoHIGHallowingareadtooccur. TheEFflagisupdated PROGRAMMABLEFLAGMODE(PFM)
by two RCLK cycles + tSKEW after the valid WCLK cycle.
DuringMasterReset,aLOWonPFMwillselectAsynchronousProgram-
IntheFWFTmode,thefirstwordwrittentoanemptyFIFOautomaticallygoes mableflagtimingmode.AHIGHonPFMwillselectSynchronousProgrammable
totheoutputsQn,onthethirdvalidLOW-to-HIGHtransitionofRCLK+tSKEW flagtimingmode.IfasynchronousPAF/PAEconfigurationisselected(PFM,
afterthefirstwrite. RENdoesnotneedtobeassertedLOW. Inordertoaccess LOWduringMRS),thePAEisassertedLOWontheLOW-to-HIGHtransition
allotherwords,areadmustbeexecutedusingREN. TheRCLKLOW-to-HIGH of RCLK. PAE is reset to HIGH on the LOW-to-HIGH transition of WCLK.
transitionafterthelastword hasbeenreadfromtheFIFO,OutputReady(OR) Similarly,thePAFisassertedLOWontheLOW-to-HIGHtransitionofWCLKand
willgoHIGHwithatrueread(RCLKwithREN=LOW),inhibitingfurtherread PAFisresettoHIGHontheLOW-to-HIGHtransitionofRCLK.
operations. REN is ignored when the FIFO is empty.
If synchronous PAE/PAF configuration is selected (PFM, HIGH during
MRS),thePAEisassertedandupdatedontherisingedgeofRCLKonlyand
notWCLK.Similarly,PAFisassertedandupdatedontherisingedgeofWCLK
SERIAL ENABLE ( SEN )
TheSENinput isanenableusedonlyforserialprogrammingoftheoffset onlyandnotRCLK.Themodedesiredisconfiguredduringmasterresetbythe
registers. The serial programming method must be selected during Master stateoftheProgrammableFlagMode(PFM)pin.
Reset. SENisalwaysusedinconjunctionwithLD. Whentheselinesareboth
LOW,dataattheSIinputcanbeloadedintotheprogramregisteronebitforeach INTERSPERSED PARITY (IP)
LOW-to-HIGHtransitionofWCLK.
DuringMasterReset,aLOWonIPwillselectNon-InterspersedParitymode.
When SEN is HIGH, the programmable registers retains the previous A HIGHwillselectInterspersedParitymode.TheIPbitfunctionallowstheuser
settings andnooffsets areloaded. SEN functions thesamewayinbothIDT to select the parity bit in the word loaded into the parallel port (D0-Dn) when
StandardandFWFTmodes.
programmingtheflagoffsets.IfInterspersedParitymodeisselected,thenthe
FIFOwillassumethattheparitybitsarelocatedinbitpositionD8,D17,D26and
D35 duringthe parallelprogrammingofthe flagoffsets. IfNon-Interspersed
OUTPUT ENABLE ( OE )
WhenOutputEnableisenabled(LOW),theparalleloutputbuffersreceive Paritymodeisselected,thenD8,D17andD28 areisassumedtobevalidbits
datafromtheoutputregister. WhenOEisHIGH,theoutputdatabus(Qn)goes and D32, D33, D34 and D35 are ignored. IP mode is selected during Master
intoahighimpedancestate.
ResetbythestateoftheIPinputpin.InterspersedParitycontrolonlyhas an
effectduringparallelprogrammingoftheoffsetregisters.Itdoesnoteffectthedata
writtentoandreadfromthe FIFO.
LOAD ( LD )
Thisisadualpurposepin. DuringMasterReset,thestateoftheLDinput,
alongwithFSEL0andFSEL1,determinesoneofeightdefaultoffsetvaluesfor
thePAEandPAFflags,alongwiththemethodbywhichtheseoffsetregisters
canbeprogrammed,parallelorserial(seeTable2). AfterMasterReset, LD
enableswriteoperationstoandreadoperationsfromtheoffsetregisters.Only
theoffsetloadingmethodcurrentlyselectedcanbeusedtowritetotheregisters.
Offsetregisters canbereadonlyinparallel.
OUTPUTS:
FULL FLAG ( FF/IR )
Thisisadualpurposepin. InIDTStandardmode,theFullFlag (FF) function
is selected. When the FIFO is full, FF will go LOW, inhibiting further write
operations. WhenFF isHIGH,theFIFOisnotfull. Ifnoreadsareperformed
18
TM
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
after a reset (eitherMRS orPRS), FF willgoLOWafterDwrites tothe FIFO IDT72V3660and(8,193-m)writesfortheIDT72V3670,(16,385-m)writesfor
(D = 1,024 for the IDT72V3640, 2,048 for the IDT72V3650, 4,096 for the theIDT72V3680,(32,769-m)writesfortheIDT72V3690,(65,537-m)writesfor
IDT72V3660,8,192fortheIDT72V3670,16,384fortheIDT72V3680,32,768 theIDT72V36100and(131,073-m)writes fortheIDT72V36110,wheremis
for the IDT72V3690, 65,536 for the IDT72V36100 and 131,072 for the thefulloffsetvalue.Thedefaultsettingforthisvalueisstatedin Table2.
IDT72V36110).SeeFigure7,WriteCycleandFullFlagTiming(IDTStandard
Mode),fortherelevanttiminginformation.
SeeFigure18,SynchronousProgrammableAlmost-FullFlagTiming(IDT
StandardandFWFTMode),fortherelevanttiminginformation.
InFWFTmode, the InputReady(IR)functionis selected. IR goes LOW
IfasynchronousPAFconfigurationisselected,the PAFisassertedLOW
whenmemoryspaceis availableforwritingindata. Whenthereis nolonger ontheLOW-to-HIGHtransitionoftheWriteClock(WCLK). PAFisresettoHIGH
anyfreespaceleft,IRgoesHIGH,inhibitingfurtherwriteoperations. Ifnoreads ontheLOW-to-HIGHtransitionoftheReadClock(RCLK). IfsynchronousPAF
areperformedafterareset(eitherMRSorPRS),IRwillgoHIGHafterDwrites configurationisselected,thePAFisupdatedontherisingedgeofWCLK. See
totheFIFO(D=1,025fortheIDT72V3640,2,049fortheIDT72V3650,4,097 Figure20,AsynchronousAlmost-FullFlagTiming(IDTStandardandFWFT
fortheIDT72V3660,8,193fortheIDT72V3670,16,385fortheIDT72V3680, Mode).
32,769fortheIDT72V3690,65,537fortheIDT72V36100and131,073forthe
IDT72V36110). See Figure 9, Write Timing (FWFT Mode), for the relevant PROGRAMMABLEALMOST-EMPTYFLAG(PAE)
timinginformation.
TheProgrammableAlmost-Emptyflag(PAE)willgoLOWwhentheFIFO
TheIRstatusnotonlymeasuresthecontentsoftheFIFOmemory,butalso reachesthealmost-emptycondition.InIDTStandardmode,PAEwillgoLOW
countsthepresenceofawordintheoutputregister. Thus,inFWFTmode,the whenthere are nwords orless inthe FIFO. The offset“n”is the emptyoffset
totalnumberofwritesnecessarytodeassertIRisonegreaterthanneededto value.ThedefaultsettingforthisvalueisstatedinthefootnoteofTable1.
assert FF in IDT Standard mode.
In FWFT mode, the PAE will go LOW when there are n+1 words or less
FF/IRissynchronousandupdatedontherisingedgeofWCLK.FF/IRare intheFIFO.Thedefaultsettingforthis valueis statedinTable2.
doubleregister-bufferedoutputs.
See Figure 19, Synchronous Programmable Almost-EmptyFlagTiming
(IDTStandardandFWFTMode), forthe relevanttiminginformation.
IfasynchronousPAEconfigurationisselected,thePAEisassertedLOW
EMPTY FLAG ( EF/OR )
Thisisadualpurposepin. IntheIDTStandardmode,theEmptyFlag(EF) ontheLOW-to-HIGHtransitionoftheReadClock(RCLK). PAEisresettoHIGH
functionisselected. WhentheFIFOisempty,EFwillgoLOW,inhibitingfurther ontheLOW-to-HIGHtransitionoftheWriteClock(WCLK). IfsynchronousPAE
readoperations. WhenEFisHIGH,theFIFOisnotempty.SeeFigure8,Read configurationisselected,thePAEisupdatedontherisingedgeofRCLK. See
Cycle, EmptyFlagandFirstWordLatencyTiming(IDTStandardMode),for Figure 21, Asynchronous Programmable Almost-Empty Flag Timing (IDT
therelevanttiminginformation.
Standard and FWFT Mode).
InFWFTmode,theOutputReady(OR)functionisselected.ORgoesLOW
atthesametimethatthefirstwordwrittentoanemptyFIFOappearsvalidon HALF-FULL FLAG ( HF )
theoutputs. ORstaysLOWaftertheRCLKLOWtoHIGHtransitionthatshifts
Thisoutputindicatesahalf-fullFIFO.TherisingWCLKedgethatfillstheFIFO
thelastwordfromtheFIFOmemorytotheoutputs. ORgoesHIGHonlywith beyondhalf-fullsetsHFLOW.TheflagremainsLOWuntilthedifferencebetween
atrueread(RCLKwithREN=LOW). Thepreviousdatastaysattheoutputs, thewriteandreadpointersbecomeslessthanorequaltohalfofthetotaldepth
indicatingthelastwordwasread. FurtherdatareadsareinhibiteduntilORgoes ofthedevice;therisingRCLKedgethataccomplishesthisconditionsetsHF
LOWagain.SeeFigure10,ReadTiming(FWFTMode),fortherelevanttiming HIGH.
information.
EF/OR is synchronous and updated on the rising edge of RCLK.
InIDTStandardmode,ifnoreadsareperformedafterreset(MRSorPRS),
HF will go LOW after (D/2 + 1) writes to the FIFO, where D = 1,024 for the
InIDTStandardmode,EFis a double register-bufferedoutput. InFWFT IDT72V3640, 2,048 for the IDT72V3650, 4,096 for the IDT72V3660, 8,192
mode,ORisatripleregister-bufferedoutput.
fortheIDT72V3670,16,384fortheIDT72V3680,32,768fortheIDT72V3690,
65,536 for the IDT72V36100 and 131,072 for the IDT72V36110.
In FWFT mode, if no reads are performed after reset (MRS orPRS), HF
PROGRAMMABLE ALMOST-FULL FLAG (PAF)
The Programmable Almost-Full flag (PAF) will go LOW when the FIFO will go LOW after (D-1/2 + 2) writes to the FIFO, where D = 1,025 for the
reaches the almost-full condition. In IDT Standard mode, if no reads are IDT72V3640,2,049fortheIDT72V3650,4,097fortheIDT72V3660,8,193for
performedafterreset(MRS),PAFwillgoLOWafter(D-m)wordsarewritten the IDT72V3670, 16,385 for the IDT72V3680, 32,769 for the IDT72V3690,
totheFIFO.ThePAFwillgoLOWafter(1,024-m)writesfortheIDT72V3640, 65,537 for the IDT72V36100 and 131,073 for the IDT72V36110.
(2,048-m)writesfortheIDT72V3650,(4,096-m)writesfortheIDT72V3660,
See Figure 22, Half-Full Flag Timing (IDT Standard and FWFT Modes),
(8,192-m)writesfortheIDT72V3670,(16,384-m)writesfortheIDT72V3680, fortherelevanttiminginformation.BecauseHFisupdatedbybothRCLKand
(32,768-m)writesfortheIDT72V3690,(65,536-m)writesfortheIDT72V36100 WCLK,itisconsideredasynchronous.
and(131,072-m)writes fortheIDT72V36110.Theoffset“m”is thefulloffset
value.ThedefaultsettingforthisvalueisstatedinthefootnoteofTable1.
DATAOUTPUTS(Q0-Qn)
In FWFT mode, the PAF will go LOW after (1,025-m) writes for the
(Q0-Q35)aredataoutputsfor36-bitwidedata,(Q0-Q17)aredataoutputs
IDT72V3640,(2,049-m)writesfortheIDT72V3650,(4,097-m)writesforthe for 18-bit wide data or (Q0-Q8) are data outputs for 9-bit wide data.
19
TM
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
D35-D27
D26-D18
D17-D9
D8-D0
BYTE ORDER ON INPUT PORT:
Write to FIFO
A
B
C
D
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
BYTE ORDER ON OUTPUT PORT:
BE BM IW
OW
L
A
B
C
D
Read from FIFO
X
L
L
(a) x36 INPUT to x36 OUTPUT
Q35-Q27
Q35-Q27
Q26-Q18
Q26-Q18
Q17-Q9
Q8-Q0
BE BM IW
OW
L
1st: Read from FIFO
2nd: Read from FIFO
A
B
L
H
L
Q17-Q9
Q8-Q0
C
D
(b) x36 INPUT to x18 OUTPUT - BIG-ENDIAN
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
BE BM IW
OW
L
1st: Read from FIFO
2nd: Read from FIFO
C
D
H
H
L
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
A
B
(c) x36 INPUT to x18 OUTPUT - LITTLE-ENDIAN
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
BE BM IW
OW
H
A
1st: Read from FIFO
2nd: Read from FIFO
L
H
L
Q35-Q27
Q35-Q27
Q26-Q18
Q26-Q18
Q17-Q9
Q17-Q9
Q8-Q0
B
Q8-Q0
C
3rd: Read from FIFO
4th: Read from FIFO
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
D
(d) x36 INPUT to x9 OUTPUT - BIG-ENDIAN
Q35-Q27
Q35-Q27
Q35-Q27
Q35-Q27
Q26-Q18
Q26-Q18
Q26-Q18
Q26-Q18
Q17-Q9
Q17-Q9
Q17-Q9
Q17-Q9
Q8-Q0
BE BM IW
OW
H
D
1st: Read from FIFO
H
H
L
Q8-Q0
2nd: Read from FIFO
3rd: Read from FIFO
C
Q8-Q0
B
Q8-Q0
A
4th: Read from FIFO
4667 drw 08
(e) x36 INPUT to x9 OUTPUT - LITTLE-ENDIAN
Figure 4. Bus-Matching Byte Arrangement
20
TM
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
D35-D27
D26-D18
D17-D9
D8-D0
BYTE ORDER ON INPUT PORT:
1st: Write to FIFO
2nd: Write to FIFO
A
B
D35-D27
D26-D18
D17-D9
D8-D0
C
D
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
BYTE ORDER ON OUTPUT PORT:
BE BM IW
OW
L
B
D
Read from FIFO
Read from FIFO
A
C
L
H
H
(a) x18 INPUT to x36 OUTPUT - BIG-ENDIAN
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
BE BM IW
OW
L
D
B
C
A
H
H
H
(b) x18 INPUT to x36 OUTPUT - LITTLE-ENDIAN
BYTE ORDER ON INPUT PORT:
D35-D27
D35-D27
D35-D27
D35-D27
D26-D18
D26-D18
D26-D18
D26-D18
D17-D9
D17-D9
D17-D9
D17-D9
D8-D0
A
1st: Write to FIFO
2nd: Write to FIFO
D8-D0
B
D8-D0
3rd: Write to FIFO
4th: Write to FIFO
C
D8-D0
D
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
BYTE ORDER ON OUTPUT PORT:
BE BM IW
OW
H
A
B
C
D
Read from FIFO
L
H
H
(a) x9 INPUT to x36 OUTPUT - BIG-ENDIAN
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
BE BM IW
OW
H
C
A
Read from FIFO
4667 drw 09
D
B
H
H
H
(b) x9 INPUT to x36 OUTPUT - LITTLE-ENDIAN
Figure 4. Bus-Matching Byte Arrangement (Continued)
21
TM
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
tRS
MRS
REN
t
RSS
RSS
t
RSR
RSR
t
t
WEN
tRSR
tRSS
FWFT/SI
tRSS
tRSR
LD
tRSS
FSEL0,
FSEL1
tRSS
tRSS
tRSS
tRSS
BM,
OW, IW
BE
RM
PFM
tRSS
IP
RT
t
RSS
RSS
t
SEN
t
RSF
If FWFT = HIGH, OR = HIGH
If FWFT = LOW, EF = LOW
EF/OR
t
RSF
If FWFT = LOW, FF = HIGH
If FWFT = HIGH, IR = LOW
FF/IR
PAE
t
RSF
t
RSF
PAF, HF
t
RSF
OE = HIGH
OE = LOW
Q0 - Qn
4667 drw 10
Figure 5. Master Reset Timing
22
TM
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
tRS
PRS
REN
tRSS
tRSR
tRSS
tRSR
WEN
RT
tRSS
tRSS
SEN
If FWFT = HIGH, OR = HIGH
If FWFT = LOW, EF = LOW
If FWFT = LOW, FF = HIGH
If FWFT = HIGH, IR = LOW
t
RSF
EF/OR
t
RSF
FF/IR
PAE
t
RSF
t
RSF
PAF, HF
t
RSF
OE = HIGH
OE = LOW
Q0 - Qn
4667 drw 11
Figure 6. Partial Reset Timing
23
TM
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
t
CLK
t
CLKH
NO WRITE
NO WRITE
tCLKL
2
1
WCLK
1
2
(1)
SKEW1
t
SKEW1(1)
t
t
DS
tDH
t
DS
tDH
D
X
DX+1
D0 - Dn
t
WFF
t
WFF
t
WFF
t
WFF
FF
WEN
RCLK
t
ENS
tENH
t
ENS
tENH
REN
t
A
tA
Q0 - Qn
DATA READ
DATA IN OUTPUT REGISTER
NEXT DATA READ
4667 drw 12
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH (after one WCLK cycle pus tWFF). If the time between
the rising edge of the RCLK and the rising edge of the WCLK is less than tSKEW1, then the FF deassertion may be delayed one extra WCLK cycle.
2. LD = HIGH, OE = LOW, EF = HIGH
Figure 7. Write Cycle and Full Flag Timing (IDT Standard Mode)
tCLK
tCLKH
tCLKL
1
2
RCLK
REN
tENH
tENS
tENS
tENH
tENH
tENS
NO OPERATION
NO OPERATION
tREF
tREF
tREF
EF
tA
tA
tA
D0
LAST WORD
D1
LAST WORD
Q0 - Qn
tOLZ
t
OLZ
tOHZ
tOE
OE
WCLK
WEN
t
SKEW1(1)
tENH
tENH
tENS
tENS
tDS
tDH
tDH
tDS
D0
D1
D0 - Dn
4667 drw 13
NOTES:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus tREF). If the time between the rising edge
of WCLK and the rising edge of RCLK is less than tSKEW1, then EF deassertion may be delayed one extra RCLK cycle.
2. LD = HIGH.
3. First data word latency = tSKEW1 + 1*TRCLK + tREF.
Figure 8. Read Cycle, Empty Flag and First Data Word Latency Timing (IDT Standard Mode)
24
1
WCLK
tENS
WEN
tDS
tDS
tDS
tDS
tDH
tENH
D-1
D-1
D-1
WD
W3
W[n+4]
W[D-m-2]
W1
W
2
W4
W[n +2]
W
[n+3]
[
]
[
]
[
W
]
W[D-m-1]
W[D-m]
W[D-m+1]
W[D-m+2]
W[D-1]
W
W
D0 - D17
(2)
tSKEW2
t
SKEW1(1)
2
1
3
1
2
RCLK
REN
tA
DATA IN OUTPUT REGISTER
W1
Q0
- Q17
t
REF
OR
t
PAES
PAE
tHF
HF
t
PAFS
PAF
IR
t
WFF
4667 drw 14
NOTES:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that OR will go LOW after two RCLK cycles plus tREF. If the time between the rising edge of WCLK and the rising edge of RCLK is less than
tSKEW1, then OR assertion may be delayed one extra RCLK cycle.
2. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH after one RCLK cycle plus tPAES. If the time between the rising edge of WCLK and the rising edge of RCLK is less than
tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.
3. LD = HIGH, OE = LOW
4. n = PAE offset, m = PAF offset and D = maximum FIFO depth.
5. D = 1,025 for IDT72V3640, 2,049 for IDT72V3650, 4,097 for IDT72V3660, 8,193 for IDT72V3670, 16,385 for the IDT72V3680, 32,769 for the IDT72V3690, 65,537 for the IDT72V36100 and 131,073 for the IDT72V36110.
6. First data word latency = tSKEW1 + 2*TRCLK + tREF.
Figure 9. Write Timing (First Word Fall Through Mode)
WCLK
1
t
2
(2)
(1)
SKEW1
tSKEW2
tENS
tENH
WEN
tDS
tDH
WD
D0
- D17
1
RCLK
tENS
tENS
REN
OE
tOHZ
tOE
tA
tA
tA
tA
tA
tA
D-1
D-1
Wm+2
W
[
]
W
[
]
W[D-n-1]
W[D-n]
WD
W1
W1
W2
W3
W[m+3]
W[m+4]
W[D-n+1]
W[D-n+2]
W[D-1]
Q0
- Q17
t
REF
OR
t
PAES
PAE
HF
tHF
t
PAFS
PAF
IR
t
WFF
t
WFF
4667 drw 15
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that IR will go LOW after one WCLK cycle plus tWFF. If the time between the rising edge of RCLK and the rising edge of WCLK is less than
tSKEW1, then the IR assertion may be delayed one extra WCLK cycle.
2. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH after one WCLK cycle plus tPAFS. If the time between the rising edge of RCLK and the rising edge of WCLK is less than
tSKEW2, then the PAF deassertion may be delayed one extra WCLK cycle.
3. LD = HIGH
4. n = PAE Offset, m = PAF offset and D = maximum FIFO depth.
5. D = 1,025 for IDT72V3640, 2,049 for IDT72V3650, 4,097 for IDT72V3660, 8,193 for IDT72V3670, 16,385 for the IDT72V3680, 32,769 for the IDT72V3690, 65,537 for the IDT72V36100 and 131,073 for the IDT72V36110.
Figure 10. Read Timing (First Word Fall Through Mode)
TM
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
1
2
RCLK
t
ENS
t
ENH
t
ENS
tENH
tRTS
REN
t
A
t
A
t
A
(3)
(3)
Q0 - Qn
Wx
Wx+1
W
1
W
2
t
SKEW2
1
2
WCLK
WEN
RT
tRTS
t
ENS
tENH
tREF
tREF
EF
PAE
HF
t
PAES
tHF
t
PAFS
PAF
4667 drw 16
NOTES:
1. Retransmit setup is complete after EF returns HIGH, only then can a read operation begin.
2. OE = LOW.
3. W1 = first word written to the FIFO after Master Reset, W2 = second word written to the FIFO after Master Reset.
4. No more than D - 2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure.
D = 1,024 for IDT72V3640, 2,048 for IDT72V3650, 4,096 for IDT72V3660, 8,192 for IDT72V3670, 16,384 for the IDT72V3680, 32,768 for the IDT72V3690, 65,536 for the IDT72V36100
and 131,072 for the IDT72V36110.
5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.
6. RM is set HIGH during MRS.
Figure 11. Retransmit Timing (IDT Standard Mode)
27
TM
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
3
1
2
4
RCLK
t
ENH
t
ENH
t
ENS
t
ENS
tRTS
REN
t
A
t
A
tA
t
A
(4)
(4)
(4)
Q0 - Qn
Wx
Wx+1
W
2
W4
W
1
W3
t
SKEW2
1
2
WCLK
tRTS
WEN
t
ENS
tENH
RT
OR
tREF
tREF
t
PAES
PAE
tHF
HF
t
PAFS
PAF
4667 drw 17
NOTES:
1. Retransmit setup is complete after OR returns LOW.
2. No more than D - 2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup procedure.
D = 1,025 for the IDT72V3640, 2,049 for the IDT72V3650, 4,097 for the IDT72V3660, 8,193 for the IDT72V3670, 16,385 for the IDT72V3680, 32,769 for the IDT72V3690, 65,537
for the IDT72V36100 and 131,073 for the IDT72V36110.
3. OE = LOW.
4. W1, W2, W3 = first, second and third words written to the FIFO after Master Reset.
5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.
6. RM is set HIGH during MRS.
Figure 12. Retransmit Timing (FWFT Mode)
28
TM
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
1
2
3
RCLK
t
ENS
tENH
REN
t
A
tA
t
A
t
A
t
A
(3)
2
(3)
1
Q0 - Qn
W
3
W
Wx
W0
W
Wx+1
t
SKEW2
1
2
WCLK
tRTS
WEN
t
ENS
tENH
RT
EF
t
PAES
PAE
tHF
HF
t
PAFS
PAF
4667 drw 18
NOTES:
1. If the part is empty at the point of Retransmit, the empty flag (EF) will be updated based on RCLK (Retransmit clock cycle), valid data will also appear on the output.
2. OE = LOW.
3. W1 = first word written to the FIFO after Master Reset, W2 = second word written to the FIFO after Master Reset.
4. No more than D - 2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure.
D = 1,024 for IDT72V3640, 2,048 for IDT72V3650, 4,096 for IDT72V3660, 8,192 for IDT72V3670, 16,384 for the IDT72V3680, 32,768 for the IDT72V3690, 65,536 for the IDT72V36100
and 131,072 for the IDT72V36110.
5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.
6. RM is set LOW during MRS.
Figure 13. Zero Latency Retransmit Timing (IDT Standard Mode)
29
TM
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
4
1
2
5
3
RCLK
t
ENH
t
ENS
REN
t
A
t
A
t
A
tA
t
A
(4)
(4)
(4)
Q0 - Qn
Wx
Wx+1
W3
W1
W
2
W
4
W5
t
SKEW2
1
2
WCLK
tRTS
WEN
t
ENS
tENH
RT
OR
t
PAES
PAE
HF
tHF
t
PAFS
PAF
4667 drw 19
NOTES:
1. If the part is empty at the point of Retransmit, the output ready flag (OR) will be updated based on RCLK (Retransmit clock cycle), valid data will also appear on the output.
2. No more than D - 2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup procedure.
D = 1,025 for the IDT72V3640, 2,049 for the IDT72V3650, 4,097 for the IDT72V3660, 8,193 for the IDT72V3670, 16,385 for the IDT72V3680, 32,769 for the IDT72V3690, 65,537
for the IDT72V36100 and 131,073 for the IDT72V36110.
3. OE = LOW.
4. W1, W2, W3 = first, second and third words written to the FIFO after Master Reset.
5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.
6. RM is set LOW during MRS.
Figure 14. Zero Latency Retransmit Timing (FWFT Mode)
WCLK
t
ENH
LDH
t
t
ENS
LDS
tENH
SEN
LD
t
tLDH
tDH
t
DS
(1)
(1)
BIT 0
BIT 0
BIT X
BIT X
SI
4667 drw 20
EMPTY OFFSET
FULL OFFSET
NOTE:
1. X = 9 for the IDT72V3640, X = 10 for the IDT72V3650, X = 11 for the IDT72V3660, X = 12 for the IDT72V3670, X = 13 for the IDT72V3680, X = 14 for the IDT72V3690, X = 15 for
the IDT72V36100 and X = 16 for the IDT72V36110.
Figure 15. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
30
TM
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
t
CLK
t
CLKH
t
CLKL
WCLK
LD
t
LDH
t
LDS
t
LDH
ENH
t
t
ENH
t
ENS
WEN
t
DS
tDH
t
DH
PAF
OFFSET
PAE
OFFSET
D0
- Dn
4667 drw 21
NOTE:
1. This timing diagram illustrates programming with an input bus width of 36 bits.
Figure 16. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
t
CLK
t
CLKH
tCLKL
RCLK
t
LDS
t
LDH
t
LDH
ENH
LD
t
ENS
tENH
t
REN
t
A
t
A
DATA IN OUTPUT REGISTER
PAE OFFSET
PAF OFFSET
Q0 - Qn
4667 drw 22
NOTES:
1. OE = LOW.
2. The timing diagram illustrates reading of offset registers with an output bus width of 36 bits.
Figure 17. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes)
tCLKL
tCLKL
1
2
WCLK
WEN
PAF
2
1
tENS
tENH
t
PAFS
t
PAFS
D - (m+1) words in FIFO(2)
D - m words in FIFO(2)
D-(m+1) words
in FIFO(2)
t
SKEW2(3)
RCLK
tENS
tENH
4667 drw 23
REN
NOTES:
1. m = PAF offset.
2. D = maximum FIFO depth.
In IDT Standard mode: D = 1,024 for the IDT72V3640, 2,048 for the IDT72V3650, 4,096 for the IDT72V3660 and 8,192 for the IDT72V3670, 16,384 for the IDT72V3680, 32,768
for the IDT72V3690, 65,536 for the IDT72V36100 and 131,072 for the IDT72V36110.
In FWFT mode: D = 1,025 for the IDT72V3640, 2,049 for the IDT72V3650, 4,097 for the IDT72V3660, 8,193 for the IDT72V3670, 16,3 85 for the IDT72V3680, 32,769 for the IDT72V3690,
65,537 for the IDT72V36100 and 131,073 for the IDT72V36110.
3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus tPAFS). If the time between the
rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then the PAF deassertion time may be delayed one extra WCLK cycle.
4. PAF is asserted and updated on the rising edge of WCLK only.
5. Select this mode by setting PFM HIGH during Master Reset.
Figure 18. Synchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
31
TM
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
tCLKH
tCLKL
WCLK
tENS
tENH
WEN
PAE
n words in FIFO (2)
n+1 words in FIFO (3)
,
n words in FIFO (2)
n+1 words in FIFO (3)
,
n+1 words in FIFO (2)
n+2 words in FIFO (3)
,
SKEW2(4)
t
t
PAES
PAES
t
1
2
1
2
RCLK
tENS
tENH
4667 drw 24
REN
NOTES:
1. n = PAE offset.
2. For IDT Standard mode
3. For FWFT mode.
4. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH (after one RCLK cycle plus tPAES). If the time between the rising edge of
WCLK and the rising edge of RCLK is less than tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.
5. PAE is asserted and updated on the rising edge of WCLK only.
6. Select this mode by setting PFM HIGH during Master Reset.
Figure 19. Synchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
tCLKH
tCLKL
WCLK
tENS
tENH
WEN
PAF
tPAFA
D - m words
in FIFO
D - (m + 1) words
in FIFO
D - (m + 1) words in FIFO
tPAFA
RCLK
tENS
REN
4667 drw25
NOTES:
1. m = PAF offset.
2. D = maximum FIFO Depth.
In IDT Standard Mode: D = 1,024 for the IDT72V3640, 2,048 for the IDT72V3650, 4,096 for the IDT72V3660, 8,192 for the IDT72V3670, 16,384 for the IDT72V3680, 32,768 for the
IDT72V3690, 65,536 for the IDT72V36100 and 131,072 for the IDT72V36110.
In FWFT Mode: D = 1,025 for the IDT72V3640, 2,049 for the IDT72V3650, 4,097 for the IDT72V3660, 8,193 for the IDT72V3670, 16,385 for the IDT72V3680, 32,769 for the IDT72V3690,
65,537 for the IDT72V36100 and 131,073 for the IDT72V36110.
3. PAF is asserted to LOW on WCLK transition and reset to HIGH on RCLK transition.
4. Select this mode by setting PFM LOW during Master Reset.
Figure 20. Asynchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
32
TM
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
tCLKH
tCLKL
WCLK
tENS
tENH
WEN
(2)
(2)
tPAEA
n words in FIFO
,
n words in FIFO
,
(2)
n+1wordsinFIFO
,
(3)
(3)
PAE
RCLK
REN
n + 1 words in FIFO
n + 1 words in FIFO
(3)
n+2wordsinFIFO
tPAEA
tENS
4667 drw 26
NOTES:
1. n = PAE offset.
2. For IDT Standard Mode.
3. For FWFT Mode.
4. PAE is asserted LOW on RCLK transition and reset to HIGH on WCLK transition.
5. Select this mode by setting PFM LOW during Master Reset.
Figure 21. Asynchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
tCLKH
tCLKL
WCLK
tENH
tENS
WEN
HF
tHF
D/2 + 1 words in FIFO(1),
D/2 words in FIFO(1)
,
D/2 words in FIFO(1)
,
D-1
[
+ 2]
words in FIFO(2)
D-1
2
D-1
[
+ 1
]
words in FIFO(2)
[
+ 1
]
words in FIFO(2)
2
2
tHF
RCLK
tENS
REN
4667 drw 27
NOTES:
1. In IDT Standard mode: D = maximum FIFO depth. D = 1,024 for the IDT72V3640, 2,048 for the IDT72V3650, 4,096 for the IDT72V3660, 8,192 for the IDT72V3670, 16,384 for the
IDT72V3680, 32,768 for the IDT72V3690, 65,536 for the IDT72V36100 and 131,072 for the IDT72V36110.
2. In FWFT mode: D = maximum FIFO depth. D = 1,025 for the IDT72V3640, 2,049 for the IDT72V3650, 4,097 for the IDT72V3660, 8,193 for the IDT72V3670, 16,385 for the IDT72V3680,
32,769 for the IDT72V3690, 65,537 for the IDT72V36100 and 131,073 for the IDT72V36110.
Figure 22. Half-Full Flag Timing (IDT Standard and FWFT Modes)
33
TM
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
avoided by creating composite flags, that is, ANDingEF of every FIFO, and
separatelyANDingFFofeveryFIFO. InFWFTmode,compositeflagscanbe
createdbyORingORofeveryFIFO,andseparatelyORingIRofeveryFIFO.
Figure 22 demonstrates a width expansion using two IDT72V3640/
72V3650/72V3660/72V3670/72V3680/72V3690/72V36100/72V36110de-
vices. D0-D35fromeachdeviceforma72-bitwideinputbusandQ0-Q35from
eachdeviceforma72-bitwideoutputbus.Anywordwidthcanbeattainedby
adding additional IDT72V3640/72V3650/72V3660/72V3670/72V3680/
72V3690/72V36100/72V36110devices.
OPTIONALCONFIGURATIONS
WIDTH EXPANSION CONFIGURATION
Wordwidthmaybe increasedsimplybyconnectingtogetherthe control
signalsofmultipledevices. Statusflagscanbedetectedfromanyonedevice.
TheexceptionsaretheEFandFFfunctionsinIDTStandardmodeandtheIR
andORfunctionsinFWFTmode. BecauseofvariationsinskewbetweenRCLK
andWCLK, itis possible forEF/FF deassertionandIR/OR assertiontovary
byonecyclebetweenFIFOs. InIDTStandardmode,suchproblems canbe
PARTIAL RESET (PRS)
MASTER RESET (MRS)
FIRST WORD FALL THROUGH/
SERIAL INPUT (FWFT/SI)
RETRANSMIT (RT)
Dm+1 - Dn
m + n
m
n
D0 - Dm
DATA IN
READ CLOCK (RCLK)
IDT
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
LOAD (LD)
IDT
READ ENABLE (REN)
72V3640
72V3640
72V3650
72V3660
72V3670
72V3680
72V3690
72V36100
72V36110
72V3650
72V3660
OUTPUT ENABLE (OE)
72V3670
72V3680
PROGRAMMABLE (PAE)
FULL FLAG/INPUT READY (FF/IR)
72V3690
72V36100
72V36110
#1
(1)
EMPTY FLAG/OUTPUT READY (EF/OR) #1
EMPTY FLAG/OUTPUT READY (EF/OR) #2
(1)
GATE
FULL FLAG/INPUT READY (FF/IR) #2
GATE
PROGRAMMABLE (PAF)
HALF-FULL FLAG (HF)
FIFO
#1
FIFO
#2
m + n
n
Qm+1 - Qn
DATA OUT
m
4667 drw 28
Q0
- Qm
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
Figure23. BlockDiagramof1,024x72,2,048x72,4,096x72,8,192x72,16,384x72,32,768x72,65,536x72and131,072x72WidthExpansion
DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY)
23 shows a depth expansion using two IDT72V3640/72V3650/72V3660/
72V3670/72V3680/72V3690/72V36100/72V36110devices.
The IDT72V3640 can easily be adapted to applications requiring depths
greater than 1,024, 2,048 for the IDT72V3650, 4,096 for the IDT72V3660,
8,192 for the IDT72V3670, 16,384 for the IDT72V3680, 32,768 for the
IDT72V3690,65,536fortheIDT72V36100and131,072fortheIDT72V36110
withan18-bitbuswidth.InFWFTmode,theFIFOscanbeconnectedinseries
(thedataoutputsofoneFIFOconnectedtothedatainputsofthenext)withno
externallogicnecessary. The resultingconfigurationprovides a totaldepth
equivalenttothesumofthedepthsassociatedwitheachsingleFIFO. Figure
CareshouldbetakentoselectFWFTmodeduringMasterResetforallFIFOs
in the depth expansion configuration. The first word written to an empty
configurationwillpassfromoneFIFOtothenext("rippledown")untilitfinally
appears at the outputs of the last FIFO in the chain – no read operation is
necessarybuttheRCLKofeachFIFOmustbefree-running. Eachtimethedata
word appears at the outputs of one FIFO, that device's OR line goes LOW,
enabling a write to the next FIFO in line.
34
TM
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC II 36-BIT FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
FWFT/SI
TRANSFER CLOCK
FWFT/SI
FWFT/SI
READ CLOCK
RCLK
WRITE CLOCK
WCLK
WEN
IR
RCLK
WCLK
IDT
IDT
72V3640
72V3650
72V3660
72V3670
72V3680
72V3690
72V36100
72V36110
72V3640
72V3650
72V3660
72V3670
72V3680
72V3690
72V36100
72V36110
READ ENABLE
WRITE ENABLE
INPUT READY
OR
WEN
REN
OUTPUT READY
REN
OR
IR
OUTPUT ENABLE
OE
OE
GND
n
DATA OUT
n
n
DATA IN
Dn
Qn
Qn
Dn
4667 drw 29
Figure24. BlockDiagramof2,048x36,4,096x36,8,192x36,16,384x36,32,768x36,65,536x36,131,072x36and262,144x36DepthExpansion
FIFOofthechain,thatFIFO'sIRlinegoesLOW,enablingtheprecedingFIFO
towrite a wordtofillit.
Forafullexpansionconfiguration,theamountoftimeittakesforIRofthefirst
FIFOinthechaintogoLOWafterawordhasbeenreadfromthelastFIFO is
the sumofthe delays foreachindividualFIFO:
Foranemptyexpansionconfiguration,theamountoftimeittakesforORof
thelastFIFOinthechaintogoLOW(i.e.validdatatoappearonthelastFIFO's
outputs)afterawordhasbeenwrittentothefirstFIFOisthesumofthedelays
for each individual FIFO:
(N – 1)*(4*transfer clock) + 3*TRCLK
(N – 1)*(3*transfer clock) + 2 TWCLK
whereNisthenumberofFIFOsintheexpansionandTRCLKistheRCLKperiod.
Note that extra cycles should be added for the possibility that the tSKEW1
specificationisnotmetbetweenWCLKandtransferclock,orRCLKandtransfer
clock,fortheORflag.
The"rippledown"delayisonlynoticeableforthefirstwordwrittentoanempty
depthexpansionconfiguration. Therewillbenodelayevidentforsubsequent
wordswrittentotheconfiguration.
The first free location created by reading from a full depth expansion
configurationwill"bubbleup"fromthelastFIFOtothepreviousoneuntilitfinally
movesintothefirstFIFOofthechain. Eachtimeafreelocationiscreatedinone
where N is the number of FIFOs in the expansion and TWCLK is the WCLK
period. NotethatextracyclesshouldbeaddedforthepossibilitythatthetSKEW1
specificationisnotmetbetweenRCLKandtransferclock,orWCLKandtransfer
clock,fortheIRflag.
TheTransferClocklineshouldbetiedtoeitherWCLKorRCLK,whichever
isfaster. Boththeseactionsresultindatamoving,asquicklyaspossible,tothe
endofthechainandfreelocations tothebeginningofthechain.
35
ORDERINGINFORMATION
IDT
XXXXX
X
XX
X
X
Process /
Temperature
Range
Device Type
Power
Speed
Package
BLANK
I(1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
PF
Thin Plastic Quad Flatpack (TQFP, PK128-1)
Commercial Only
7.5
10
15
Clock Cycle Time (tCLK
)
Commercial Only
Com’l & Ind’l
Speed in Nanoseconds
L
Low Power
72V3640
72V3650
72V3660
72V3670
72V3680
72V3690
72V36100
72V36110
1,024 x 36
2,048 x 36
4,096 x 36
8,192 x 36
16,384 x 36
32,768 x 36
65,536 x 36
131,072 x 36
3.3V SuperSync II FIFO
3.3V SuperSync II FIFO
3.3V SuperSync II FIFO
3.3V SuperSync II FIFO
3.3V SuperSync II FIFO
3.3V SuperSync II FIFO
3.3V SuperSync II FIFO
3.3V SuperSync II FIFO
4667 drw 30
NOTE:
1. Industrial temperature range is available by special order for speed grades faster than 15ns.
DATASHEETDOCUMENTHISTORY
05/25/2000
07/28/2000
12/14/2000
03/27/2001
04/06/2001
pgs.1, 6, 7, 8, 34 and 35.
pgs. 13, 14 and 34.
pgs. 6, 7 and 8.
pg. 7.
pgs. 4, 5 and 18.
CORPORATE HEADQUARTERS
2975StenderWay
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
for Tech Support:
408-330-1753
email:FIFOhelp@idt.com
www.idt.com*
PFPkg: www.idt.com/docs/PSC4045.pdf
*To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2.
The SuperSync ll FIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
36
相关型号：
IDT72V3680L39268BBGI
FIFO, 16KX36, 5ns, Synchronous, CMOS, PBGA144, 13 X 13 MM, 1 MM PITCH, GREEN, PLASTIC, BGA-144
IDT
IDT72V3680L7-5BB
FIFO, 16KX36, 5ns, Synchronous, CMOS, PBGA144, 13 X 13 MM, 1 MM PITCH, PLASTIC, BGA-144
IDT
©2020 ICPDF网 联系我们和版权申明