IDT72V281 [IDT]
3.3 VOLT CMOS SuperSync FIFOTM; 3.3伏的CMOS SuperSync FIFOTM
| 型号： | IDT72V281 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 3.3 VOLT CMOS SuperSync FIFOTM |
| 文件： | 总26页 (文件大小：242K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3 VOLT CMOS SuperSync FIFO™
65,536 x 9
131,072 x 9
IDT72V281
IDT72V291
• Independent Read and Write clocks (permit reading and writing
simultaneously)
• Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64-pin
Slim Thin Quad Flat Pack (STQFP)
• High-performance submicron CMOS technology
• Industrial Temperature Range (-40°C to + 85°C) is available
ꢀEATURES:
• Choose among the following memory organizations:
IDT72V281
IDT72V291
65,536 x 9
131,072 x 9
• Pin-compatible with the IDT72V261/72V271 SuperSync FIFOs
• 10ns read/write cycle time (6.5ns access time)
• Fixed, low first word data latency time
DESCRIPTION:
• Auto power down minimizes standby power consumption
• Master Reset clears entire FIFO
• Partial Reset clears data, but retains programmable
settings
• Retransmit operation with fixed, low first word data
latency time
• Empty, Full and Half-Full flags signal FIFO status
• Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of two preselected offsets
The IDT72V281/72V291 are exceptionally deep, high speed, CMOS
First-In-First-Out (FIFO) memories with clocked read and write controls.
These FIFOs offer numerous improvements over previous SuperSync
FIFOs,includingthefollowing:
• Thelimitationofthefrequencyofoneclockinputwithrespecttotheotherhas
been removed. The Frequency Select pin (FS) has been removed, thus
it is no longer necessary to select which of the two clock inputs, RCLK or
WCLK, is runningatthe higherfrequency.
• Program partial flags by either serial or parallel means
• The period required by the retransmit operation is now fixed and short.
• Select IDT Standard timing (using EF and FF flags) or First Word • Thefirstworddatalatencyperiod,fromthetimethefirstwordiswrittentoan
Fall Through timing (using OR and IR flags)
• Output enable puts data outputs into high impedance state
• Easily expandable in depth and width
emptyFIFOtothetimeitcanberead,isnowfixedandshort. (Thevariable
clock cycle counting delay associated with the latency period found on
previousSuperSyncdeviceshasbeeneliminatedonthisSuperSyncfamily.)
ꢀUNCTIONAL BLOCK DIAGRAM
WEN
D0-D8
WCLK
LD
SEN
OFFSET REGISTER
INPUT REGISTER
FF/IR
PAF
EF/OR
PAE
FLAG
LOGIC
WRITE CONTROL
LOGIC
HF
FWFT/SI
RAM ARRAY
65,536 x 9
131,072 x 9
WRITE POINTER
READ POINTER
READ
CONTROL
LOGIC
RT
OUTPUT REGISTER
MRS
PRS
RESET
LOGIC
RCLK
REN
Q0-Q8
4513 drw 01
OE
SuperSyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
APRIL 2001
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE
1
2001 Integrated Device Technology, Inc.
DSC-4513/1
IDT72V281/72V291
COCOMMCOMMERCIALANDINDUSTRIALTEMPERATURERANGE
ThefrequenciesofboththeRCLKandtheWCLKsignalsmayvaryfrom0
tofMAXwithcompleteindependence. Therearenorestrictionsonthefrequency
oftheoneclockinputwithrespecttotheother.
There are two possible timing modes of operation with these devices:
IDT Standard mode and First Word Fall Through (FWFT) mode.
In IDT Standard mode, the first word written to an empty FIFO will not
appear on the data output lines unless a specific read operation is
performed. A read operation, which consists of activating REN and
enabling a rising RCLK edge, will shift the word from internal memory to the
data output lines.
DESCRIPTION (Continued)
SuperSyncFIFOsareparticularlyappropriatefornetwork,video,telecommu-
nications,datacommunicationsandotherapplicationsthatneedtobufferlarge
amountsofdata.
The input port is controlled by a Write Clock (WCLK) input and a Write
Enable (WEN) input. Data is written into the FIFO on every rising edge of
WCLK when WEN is asserted. The output port is controlled by a Read
Clock (RCLK) input and Read Enable (REN) input. Data is read from the
FIFO on every rising edge of RCLK when REN is asserted. An Output
Enable (OE) input is provided for three-state control of the outputs.
PIN CONꢀIGURATIONS
PIN 1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
DNC(3)
DNC(3)
GND
DNC(3)
DNC(3)
WEN
SEN
DC(1)
2
3
VCC
4
VCC
5
GND(2)
GND(2)
GND(2)
GND(2)
GND(2)
GND(2)
GND(2)
GND(2)
GND(2)
D8
6
VCC
DNC(3)
DNC(3)
DNC(3)
GND
DNC(3)
DNC(3)
Q8
7
8
9
10
11
12
13
14
15
16
Q7
Q6
GND
D7
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
4513 drw 02
TQFP (PN64-1, order code: PF)
STQFP (PP64-1, order code: TF)
TOP VIEW
NOTES:
1. DC = Don’t Care. Must be tied to GND or VCC, cannot be left open.
2. This pin may either be tied to ground or left open.
3. DNC = Do Not Connect.
2
IDT72V281/72V291
COMMERCIALANDINDUSTRIALTEMPERATURERANGE
WCLK,areusedtoloadtheoffsetregistersviaDn. RENtogetherwithLDon
eachrisingedge ofRCLKcanbe usedtoreadthe offsets inparallelfromQn
regardlessofwhetherserialorparalleloffsetloadinghasbeenselected.
During Master Reset (MRS) the following events occur: The read and
write pointers are settothe firstlocationofthe FIFO. The FWFTpinselects
IDTStandardmode orFWFTmode. The LDpinselects eithera partialflag
default setting of 127 with parallel programming or a partial flag default
setting of 1,023 with serial programming. The flags are updated according
to the timing mode and default offsets selected.
ThePartialReset(PRS)alsosets thereadandwritepointers tothefirst
location of the memory. However, the timing mode, partial flag program-
ming method, and default or programmed offset settings existing before
Partial Reset remain unchanged. The flags are updated according to the
timing mode and offsets in effect. PRS is useful for resetting a device in
mid-operation, when reprogramming partial flags would be undesirable.
The Retransmit function allows data to be reread from the FIFO more
than once. A LOW on the RT input during a rising RCLK edge initiates a
retransmit operation by setting the read pointer to the first location of the
memory array.
DESCRIPTION (Continued)
InFWFTmode,thefirstwordwrittentoanemptyFIFOisclockeddirectly
to the data output lines after three transitions of the RCLK signal. A REN
does not have to be asserted for accessing the first word. However,
subsequent words written to the FIFO do require a LOW on REN for
access. ThestateoftheFWFT/SIinputduringMasterResetdeterminesthe
timing mode in use.
ForapplicationsrequiringmoredatastoragecapacitythanasingleFIFO
can provide, the FWFT timing mode permits depth expansion by chaining
FIFOs in series (i.e. the data outputs of one FIFO are connected to the
corresponding data inputs of the next). No external logic is required.
These FIFOs have five flag pins, EF/OR (Empty Flag or Output
Ready), FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE
(Programmable Almost-Empty flag) and PAF (Programmable Almost-Full
flag). The EF and FF functions are selected in IDT Standard mode. The
IRandORfunctionsareselectedinFWFTmode. HF,PAEandPAFare
always available for use, irrespective of timing mode.
PAE and PAF can be programmed independently to switch at any
point in memory. (See Table 1 and Table 2.) Programmable offsets
determine the flag switching threshold and can be loaded by two methods:
parallelorserial. Twodefaultoffsetsettings arealsoprovided,sothatPAE
can be set to switch at 127 or 1,023 locations from the empty boundary and
the PAF threshold can be set at 127 or 1,023 locations from the full
boundary. These choices are made with the LD pin during Master Reset.
For serial programming, SEN together with LD on each rising edge
of WCLK, are used to load the offset registers via the Serial Input (SI). For
parallel programming, WEN together with LD on each rising edge of
If, at any time, the FIFO is not actively performing an operation, the chip
will automatically power down. Once in the power down state, the standby
supply current consumption is minimized. Initiating any operation (by
activating control inputs) will immediately take the device out of the power
down state.
The IDT72V281/72V291 are fabricated using IDT’s high speed submi-
cron CMOS technology.
PARTIAL RESET (PRS) MASTER RESET (MRS)
READ CLOCK (RCLK)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
LOAD (LD)
DATA IN (D0 - Dn)
DATA OUT (Q0 - Qn)
IDT
72V281
72V291
RETRANSMIT (RT)
SERIAL ENABLE(SEN)
FIRST WORD FALL THROUGH/SERIAL INPUT
(FWFT/SI)
EMPTY FLAG/OUTPUT READY (EF/OR)
PROGRAMMABLE ALMOST-EMPTY (PAE)
FULL FLAG/INPUT READY (FF/IR)
HALF-FULL FLAG (HF)
PROGRAMMABLE ALMOST-FULL (PAF)
4513 drw 03
Figure 1. Block Diagram of Single 65,536 x 9 and 131,072 x 9 Synchronous FIFO
3
IDT72V281/72V291
COCOMMCOMMERCIALANDINDUSTRIALTEMPERATURERANGE
PIN DESCRIPTION
Symbol
D0–D8
MRS
Name
Data Inputs
Master Reset
I/O
I
Description
Data inputs for a 9-bit bus.
I
MRS initializes the read and write pointers to zero and sets the output register to
all zeroes. During Master Reset, the FIFO is configured for either FWFT or IDT
Standard mode, one of two programmable flag default settings, and serial or
parallel programming of the offset settings.
PRS
RT
Partial Reset
Retransmit
I
I
PRS initializes the read and write pointers to zero and sets the output register to
all zeroes. During Partial Reset, the existing mode (IDT or FWFT), programming
method (serial or parallel), and programmable flag settings are all retained.
RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets
the EF flag to LOW (OR to HIGH in FWFT mode) temporarily and does not disturb
the write pointer, programming method, existing timing mode or programmable flag
settings. RT is useful to reread data from the first physical location of the FIFO.
FWFT/SI
WCLK
First Word Fall
Through/Serial In
I
I
During Master Reset, selects First Word Fall Through or IDT Standard mode.
After Master Reset, this pin functions as a serial input for loading offset registers
Write Clock
When enabled by WEN, the rising edge of WCLK writes data into the FIFO and
offsets into the programmable registers for parallel programming, and when
enabled by SEN, the rising edge of WCLK writes one bit of data into the
programmable register for serial programming.
WEN
Write Enable
Read Clock
I
I
WEN enables WCLK for writing data into the FIFO memory and offset registers.
RCLK
When enabled by REN, the rising edge of RCLK reads data from the FIFO
memory and offsets from the programmable registers.
REN
OE
Read Enable
Output Enable
Serial Enable
Load
I
I
I
I
REN enables RCLK for reading data from the FIFO memory and offset registers.
OE controls the output impedance of Qn.
SEN
LD
SEN enables serial loading of programmable flag offsets.
During Master Reset, LD selects one of two partial flag default offsets (127 or 1,023
and determines the flag offset programming method, serial or parallel. After
Master Reset, this pin enables writing to and reading from the offset registers.
DC
Don't Care
I
This pin must be tied to either VCC or GND and must not toggle after Master
Reset.
FF/IR
Full Flag/
Input Ready
O
In the IDT Standard mode, the FF function is selected. FF indicates whether or
not the FIFO memory is full. In the FWFT mode, the IR function is selected. IR
indicates whether or not there is space available for writing to the FIFO memory.
EF/OR
PAF
Empty Flag/
Output Ready
O
O
O
In the IDT Standard mode, the EF function is selected. EF indicates whether or
not the FIFO memory is empty. In FWFT mode, the OR function is selected.
OR indicates whether or not there is valid data available at the outputs.
Programmable
Almost-Full Flag
PAF goes LOW if the number of words in the FIFO memory is more than
total word capacity of the FIFO minus the full offset value m, which is stored in the
Full Offset register. There are two possible default values for m: 127 or 1,023.
PAE
Programmable
Almost-Empty Flag
PAE goes LOW if the number of words in the FIFO memory is less than offset n,
which is stored in the Empty Offset register. There are two possible default values
for n: 127 or 1,023. Other values for n can be programmed into the device.
HF
Half-Full Flag
Data Outputs
Power
O
O
HF indicates whether the FIFO memory is more or less than half-full.
Data outputs for a 9-bus.
Q0–Q8
VCC
+3.3 Volt power supply pins.
GND
Ground
Ground pins.
4
IDT72V281/72V291
COMMERCIALANDINDUSTRIALTEMPERATURERANGE
RECOMMENDEDDCOPERATING
CONDITIONS
ABSOLUTEMAXIMUMRATINGS
Symbol
Rating
Commercial
Unit
Symbol
Parameter
Min.
Typ.
Max.
Unit
VTERM
TerminalVoltage
–0.5to+4.6
V
with respect to GND
VCC
SupplyVoltage(Com’l&Ind’’l) 3.0
3.3
3.6
V
TSTG
Storage
Temperature
–55to+125
–50 to +50
° C
GND
VIH
SupplyVoltage(Com’l&Ind’l)
0
0
0
V
InputHighVoltage
(Com’l & Ind’l)
IOUT
DC Output Current
mA
2.0
—
VCC + 0.5
V
(1)
VIL
InputLowVoltage
(Com’l & Ind’l)
NOTE:
—
0
—
—
0.8
70
V
OC
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
TA
TA
OperatingTemperature
Commercial
OperatingTemperature
Industrial
-40
85
°C
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 3.3V ± 0.3V, TA = 0oC to +70oC; Industrial: VCC = 3.3V ± 0.3V, TA= -40°C to +85°C)
IDT72V281L
IDT72V291L
Com’l & Ind’l (1)
tCLK = 10, 15, 20 ns
Symbol
Parameter
Min.
Max.
Unit
(2)
ILI
InputLeakageCurrent
OutputLeakageCurrent
–1
–10
2.4
—
1
µ A
µA
V
(3)
ILO
10
—
0.4
VOH
VOL
Output Logic “1” Voltage, IOH = –2 mA
Output Logic “0” Voltage, IOL = 8 mA
V
(4,5,6)
ICC1
Active Power Supply Current
StandbyCurrent
—
—
55
20
mA
mA
(4,7)
ICC2
NOTES:
1. Industrial temperature range product for the 15ns speed grade is available as a standard device.
2. Measurements with 0.4 ≤ VIN ≤ VCC.
3. OE ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
4. Tested with outputs open (IOUT = 0).
5. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.
6. Typical ICC1 = 11 + 1.65*fS + 0.02*CL*fS (in mA) with VCC = 3.3V, tA = 25oC, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2, CL
= capacitive load (in pF).
7. All Inputs = VCC - 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
CAPACITANCE(TA = +25oC, f = 1.0MHz)
Symbol
Parameter(1)
Conditions
Max.
Unit
(2)
CIN
Input
VIN = 0V
10
pF
Capacitance
(1,2)
COUT
Output
VOUT = 0V
10
pF
Capacitance
NOTES:
1. With output deselected, (OE ≥ VIH).
2. Characterized values, not currently tested.
5
IDT72V281/72V291
COCOMMCOMMERCIALANDINDUSTRIALTEMPERATURERANGE
AC ELECTRICAL CHARACTERISTICS(1)
(Commercial: VCC = 3.3V ± 0.3V, TA = 0oC to +70oC; Industrial: VCC = 3.3V ± 3.3V, TA = -40°C to +85°C)
Commercial
IDT72V281L10
Com’l & Ind’l (2)
IDT72V281L15
Commercial
IDT72V281L20
IDT72V291L10
IDT72V291L15
IDT72V291L20
Symbol
fS
Parameter
Clock Cycle Frequency
Min.
Max.
Min.
Max.
Min.
Max.
50
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
2
100
6.5
—
—
—
—
—
—
—
—
—
—
—
—
10
—
2
66.7
10
—
—
—
—
—
—
—
—
—
—
—
—
15
—
—
—
8
—
2
tA
DataAccessTime
Clock Cycle Time
Clock High Time
12
tCLK
tCLKH
tCLKL
tDS
10
4.5
4.5
3
15
6
20
8
—
—
—
—
—
—
—
—
—
—
—
—
20
Clock Low Time
6
8
DataSetupTime
4
5
tDH
DataHoldTime
0.5
3
1
1
tENS
tENH
tLDS
EnableSetupTime
EnableHoldTime
LoadSetupTime
4
5
0.5
3
1
1
4
5
tLDH
tRS
LoadHoldTime
0.5
10
10
10
—
0
1
1
ResetPulseWidth(3)
ResetSetupTime
ResetRecoveryTime
ResettoFlagandOutputTime
ModeSelectTime
RetransmitSetupTime
15
15
15
—
0
20
20
20
—
0
tRSS
tRSR
tRSF
tFWFT
tRTS
tOLZ
tOE
—
—
—
6
—
—
—
10
3
4
5
(4)
OutputEnabletoOutputinLowZ
OutputEnabletoOutputValid
0
0
0
2
3
3
(4)
tOHZ
tWFF
tREF
tPAF
tPAE
tHF
OutputEnabletoOutputinHighZ
Write Clock to FFor IR
Read Clock to EF or OR
Write Clock to PAF
2
6
3
8
3
10
—
—
—
—
—
5
6.5
6.5
6.5
6.5
16
—
—
—
—
—
6
10
10
10
10
20
—
—
—
—
—
—
10
12
12
12
Read Clock to PAE
12
Clock to HF
22
tSKEW1
Skew time between RCLK and WCLK
—
—
forFF/IR
tSKEW2
tSKEW3
Skew time between RCLK and WCLK
for PAEand PAF
12
60
—
—
15
60
—
—
20
60
—
—
ns
ns
Skew time between RCLK and WCLK
forEF/OR
NOTES:
1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.
2. Industrial temperature range product for the 15ns speed grade is available as a standard device.
3. Pulse widths less than minimum values are not allowed.
3.3V
4. Values guarenteed by design, not currently tested.
330Ω
D.U.T.
510Ω
AC TEST CONDITIONS
30pF*
Input Pulse Levels
GND to 3.0V
3ns
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
4513 drw 04
1.5V
1.5V
Figure 2. Output Load
* Includes jig and scope capacitances.
See Figure 2
6
IDT72V281/72V291
COMMERCIALANDINDUSTRIALTEMPERATURERANGE
When configured in IDT Standard mode, the EF and FF outputs are
double register-buffered outputs.
ꢀUNCTIONAL DESCRIPTION
Relevanttimingdiagrams forIDTStandardmodecanbefoundinFigure
7, 8 and 11.
TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH
(FWFT) MODE
The IDT72V281/72V291 support two different timing modes of opera-
tion: IDT Standard mode or First Word Fall Through (FWFT) mode. The
selection of which mode will operate is determined during Master Reset,
FIRST WORD FALL THROUGH MODE (FWFT)
In this mode, the status flags, IR, PAF, HF, PAE, and OR operate in
the manner outlined in Table 2. To write data into to the FIFO, WEN must
be LOW. Data presented to the DATA IN lines will be clocked into the FIFO
on subsequent transitions of WCLK. After the first write is performed, the
Output Ready (OR) flag will go LOW. Subsequent writes will continue to fill
upthe FIFO. PAEwillgoHIGHaftern + 2words have beenloadedintothe
FIFO, where n is the empty offset value. The default setting for this value
is stated in the footnote of Table 2. This parameter is also user program-
mable. See section on Programmable Flag Offset Loading.
If one continued to write data into the FIFO, and we assumed no read
operations were taking place, the HF would toggle to LOW once the
32,770th word for the IDT72V281 and 65,538th word for the IDT72V291,
respectively was written into the FIFO. Continuing to write data into the
FIFO will cause the PAF to go LOW. Again, if no reads are performed, the
PAFwillgoLOWafter(65,537-m)writesfortheIDT72V281 and(131,073-m)
writesfortheIDT72V291,wheremisthefulloffsetvalue. Thedefaultsetting
for this value is stated in the footnote of Table 2.
When the FIFO is full, the Input Ready (IR) flag will go HIGH, inhibiting
further write operations. If no reads are performed after a reset, IR will go
HIGH after D writes to the FIFO. D = 65,537 writes for the IDT72V281 and
131,073 writes for the IDT72V291, respectively. Note that the additional
word in FWFT mode is due to the capacity of the memory plus output
register.
IftheFIFOisfull,thefirstreadoperationwillcausetheIRflagtogoLOW.
Subsequent read operations will cause the PAFand HFto go HIGH at the
conditions described in Table 2. If further read operations occur, without
write operations, the PAE will go LOW when there are n + 1 words in the
FIFO, where n is the empty offset value. Continuing read operations will
cause the FIFO to become empty. When the last word has been read from
the FIFO, OR will go HIGH inhibiting further read operations. REN is
ignored when the FIFO is empty.
by the state of the FWFT/SI input.
If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard
mode will be selected. This mode uses the Empty Flag (EF) to indicate
whether or not there are any words present in the FIFO. It also uses the Full
Flag function (FF) to indicate whether or not the FIFO has any free space
forwriting. InIDTStandardmode,everywordreadfromtheFIFO,including
the first, must be requested using the Read Enable (REN) and RCLK.
If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will
beselected. This modeuses OutputReady(OR)toindicatewhetherornot
there is valid data at the data outputs (Qn). It also uses Input Ready (IR)
to indicate whether or not the FIFO has any free space for writing. In the
FWFTmode,thefirstwordwrittentoanemptyFIFOgoesdirectlytoQnafter
three RCLK rising edges, REN = LOW is not necessary. Subsequent
words must be accessed using the Read Enable (REN) and RCLK.
Various signals, both input and output signals operate differently de-
pending on which timing mode is in effect.
IDT STANDARD MODE
In this mode, the status flags, FF, PAF, HF, PAE, and EF operate in
the manner outlined in Table 1. To write data into to the FIFO, Write Enable
(WEN) must be LOW. Data presented to the DATA IN lines will be clocked
intotheFIFOonsubsequenttransitionsoftheWriteClock(WCLK).Afterthe
first write is performed, the Empty Flag (EF) will go HIGH. Subsequent
writes will continue to fill up the FIFO. The Programmable Almost-Empty
flag (PAE) will go HIGH after n + 1 words have been loaded into the FIFO,
where n is the empty offset value. The default setting for this value is stated
in the footnote of Table 1. This parameter is also user programmable. See
section on Programmable Flag Offset Loading.
If one continued to write data into the FIFO, and we assumed no read
operations were taking place, the Half-Full flag (HF) would toggle to LOW
once the 32,769th word for IDT72V281 and 65,537th word for IDT72V291
respectively was written into the FIFO. Continuing to write data into the
FIFO will cause the Programmable Almost-Full flag (PAF) to go LOW.
Again, if no reads are performed, the PAF will go LOW after (65,536-m)
writes for the IDT72V281 and (131,072-m) writes for the IDT72V291. The
offset “m” is the full offset value. The default setting for this value is stated
in the footnote of Table 1. This parameter is also user programmable. See
section on Programmable Flag Offset Loading.
When the FIFO is full, the Full Flag (FF) will go LOW, inhibiting further
write operations. If no reads are performed after a reset, FF will go LOW
after D writes to the FIFO. D = 65,536 writes for the IDT72V281 and
131,072 for the IDT72V291, respectively.
If the FIFO is full, the first read operation will cause FF to go HIGH.
Subsequent read operations will cause PAF and HF to go HIGH at the
conditions described in Table 1. If further read operations occur, without
write operations, PAE will go LOW when there are n words in the FIFO,
where nis the emptyoffsetvalue. Continuingreadoperations willcause the
FIFO to become empty. When the last word has been read from the FIFO,
theEFwillgoLOWinhibitingfurtherreadoperations.RENisignoredwhen
the FIFO is empty.
When configured in FWFT mode, the OR flag output is triple register-
buffered, and the IR flag output is double register-buffered.
Relevant timing diagrams for FWFT mode can be found in Figure 9, 10
and 12.
PROGRAMMING FLAG OFFSETS
Full and Empty Flag offset values are user programmable. The
IDT72V281/72V291hasinternalregistersfortheseoffsets.Defaultsettings
are stated in the footnotes of Table 1 and Table 2. Offset values can be
programmed into the FIFO in one of two ways; serial or parallel loading
method. The selection of the loading method is done using the LD (Load)
pin. During Master Reset, the state of the LD input determines whether
serial or parallel flag offset programming is enabled. A HIGH on LDduring
Master Reset selects serial loading of offset values and in addition, sets a
default PAEoffset value of 3FFH (a threshold 1,023 words from the empty
boundary), and a default PAF offset value of 3FFH (a threshold 1,023
words from the full boundary). A LOW on LD during Master Reset selects
parallel loading of offset values, and in addition, sets a default PAE offset
value of 07FH (a threshold 127 words from the empty boundary), and a
default PAF offset value of 07FH (a threshold 127 words from the full
boundary). See Figure 3, Offset Register Location and Default Values.
7
IDT72V281/72V291
COCOMMCOMMERCIALANDINDUSTRIALTEMPERATURERANGE
Inadditiontoloadingoffsetvalues intotheFIFO,italsopossibletoreadthe
The offsetregisters maybe programmed(andreprogrammed)anytime
current offset values. It is only possible to read offset values via parallel read. after Master Reset, regardless of whether serial or parallel programming
Figure 4, Programmable Flag Offset Programming Sequence, summa- has been selected.
rizesthecontrolpinsandsequenceforbothserialandparallelprogramming
modes. For a more detailed description, see discussion that follows.
TABLE 1 STATUS ꢀLAGS ꢀOR IDT STANDARD MODE
72V281
0
72V291
0
FF PAF HF PAE EF
H
H
H
H
H
L
H
H
H
H
L
H
H
H
L
L
L
L
H
H
H
H
H
1 to n (1)
1 to n (1)
Number of
Words in
FIFO
H
H
H
H
(n+1) to 32,768
32,769 to (65,536-(m+1))
(65,536-m)(2) to 65,535
65,536
(n+1) to 65,536
65,537 to (131,072-(m+1))
(131,072-m) (2) to 131,071
131,072
L
L
L
NOTES:
1. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n = 1,023 when serial offset loading is selected.
2. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or m = 1,023 when serial offset loading is selected.
TABLE 2 STATUS ꢀLAGS ꢀOR ꢀWꢀT MODE
72V281
72V291
0
IR PAF HF PAE OR
0
L
L
L
L
L
H
H
H
H
H
L
H
H
H
L
L
L
H
L
L
L
L
L
1 to n+1(1)
(n+2) to 65,537
1 to n+1(1)
Number of
Words in
FIFO
H
H
H
H
(n+2) to 32,769
32,770 to (65,537-(m+1)) (2)
(2)
65,538 to (131,073-(m+1))
L
(131,073-m)
(65,537-m)
to 131,072
131,073
to 65,536
L
L
65,537
NOTES:
4513 drw 05
1. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n = 1,023 when serial offset loading is selected.
2. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or m = 1,023 when serial offset loading is selected.
8
IDT72V281/72V291
COMMERCIALANDINDUSTRIALTEMPERATURERANGE
72V281 (65,536 x 9›BIT)
72V291 (131,072 x 9›BIT)
8
7
7
0
0
0
8
8
7
7
0
0
EMPTY OFFSET (LSB) REGISTER
EMPTY OFFSET (LSB) REGISTER
DEFAULT VALUE
DEFAULT VALUE
7FH if LD is LOW at Master Reset
FFH if LD is HIGH at Master Reset
7FH if LD is LOW at Master Reset
FFH if LD is HIGH at Master Reset
8
8
EMPTY OFFSET (MSB) REGISTER
EMPTY OFFSET (MID-BYTE) REGISTER
DEFAULT VALUE
DEFAULT VALUE
00H if LD is LOW at Master Reset
03H if LD is HIGH at Master Reset
00H if LD is LOW at Master Reset
03H if LD is HIGH at Master Reset
7
8
1
0
EMPTY OFFSET
(MSB) REGISTER
FULL OFFSET (LSB) REGISTER
DEFAULT
0H
DEFAULT VALUE
7FH if LD is LOW at Master Reset
FFH if LD is HIGH at Master Reset
8
8
7
7
0
FULL OFFSET (LSB) REGISTER
8
7
0
FULL OFFSET (MSB) REGISTER
DEFAULT VALUE
7FH if LD is LOW at Master Reset
FFH if LD is HIGH at Master Reset
DEFAULT VALUE
00H if LD is LOW at Master Reset
03H if LD is HIGH at Master Reset
0
FULL OFFSET (MID-BYTE) REGISTER
DEFAULT VALUE
00H if LD is LOW at Master Reset
03H if LD is HIGH at Master Reset
8
1
0
FULL OFFSET
(MSB) REGISTER
DEFAULT
0H
4513 drw 06
Figure 3. Offset Register Location and Default Values
LD WEN REN SEN
WCLK
RCLK
X
72V281
72V291
Parallel write to registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Parallel write to registers:
Empty Offset (LSB)
Empty Offset (Mid-Byte)
Empty Offset (MSB)
Full Offset (LSB)
0
0
0
0
1
1
1
0
1
1
1
0
Full Offset (MSB)
Full Offset (Mid-Byte)
Full Offset (MSB)
Parallel read from registers:
Empty Offset (LSB)
Empty Offset (Mid-Byte)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (Mid-Byte)
Full Offset (MSB)
Parallel read from registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
X
Serial shift into registers:
Serial shift into registers:
34 bits for the 72V291
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
X
32 bits for the 72V281
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
X
X
X
No Operation
No Operation
X
1
1
0
1
1
X
X
Write Memory
Write Memory
X
X
1
1
X
1
0
1
X
X
Read Memory
No Operation
Read Memory
X
No Operation
4513 drw 07
NOTES:
1. The programming method can only be selected at Master Reset.
2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
3. The programming sequence applies to both IDT Standard and FWFT modes.
Figure 4. Programmable Flag Offset Programming Sequence
9
IDT72V281/72V291
COCOMMCOMMERCIALANDINDUSTRIALTEMPERATURERANGE
SERIAL PROGRAMMING MODE
Upon the sixth LOW-to-HIGH transition of WCLK, data are written into the
If Serial Programming mode has been selected, as described above, Full Offset MSB Register. The seventh transition of WCLK writes, once
then programming of PAE and PAF values can be achieved by using a again, into the Empty Offset LSB Register. See Figure 15, Parallel Loading
combinationoftheLD,SEN,WCLKandSIinputpins.ProgrammingPAE of Programmable Flag Registers for the IDT72V291, for the timing diagram
and PAF proceeds as follows: when LD and SEN are set LOW, data on for this mode.
the SIinputare written, one bitforeachWCLKrisingedge, startingwiththe
The act of writing offsets in parallel employs a dedicated write offset
Empty Offset LSB and ending with the Full Offset MSB. A total of 32 bits register pointer. The act of reading offsets employs a dedicated read offset
for the IDT72V281 and 34 bits for the IDT72V291. See Figure 13, Serial register pointer. The two pointers operate independently; however, a read
Loading of Programmable Flag Registers, for the timing diagram for this and a write should not be performed simultaneously to the offset registers.
mode.
Using the serial method, individual registers cannot be programmed A Partial Reset has no effect on the position of these pointers.
selectively. PAEandPAFcanshowavalidstatus onlyafterthecomplete Write operations to the FIFO are allowed before and during the parallel
A Master Reset initializes both pointers to the Empty Offset (LSB) register.
set of bits (for all offset registers) has been entered. The registers can be programmingsequence.Inthiscase,theprogrammingofalloffsetregisters
reprogrammed as long as the complete set of new offset bits is entered. does not have to occur at one time. One, two or more offset registers can
When LD is LOW and SEN is HIGH, no serial write to the registers can be written and then by bringing LD HIGH, write operations can be
occur.
redirected to the FIFO memory. When LD is set LOW again, and WEN is
Write operations to the FIFO are allowed before and during the serial LOW, the next offset register in sequence is written to. As an alternative to
programming sequence. In this case, the programming of all offset bits holding WEN LOW and toggling LD, parallel programming can also be
does not have to occur at once. A select number of bits can be written to interrupted by setting LD LOW and toggling WEN.
the SI input and then, by bringing LD and SEN HIGH, data can be written
Note that the status of a partial flag (PAE or PAF) output is invalid
to FIFO memory via Dn by toggling WEN. When WEN is brought HIGH during the programming process. From the time parallel programming has
with LD and SEN restored to a LOW, the next offset bit in sequence is begun, a partial flag output will not be valid until the appropriate offset word
written to the registers via SI. If an interruption of serial programming is hasbeenwrittentotheregister(s)pertainingtothatflag.Measuringfromthe
desired, it is sufficient either to set LD LOW and deactivate SEN or to set rising WCLK edge that achieves the above criteria; PAF will be valid after
SEN LOW and deactivate LD. Once LD and SEN are both restored to two more rising WCLK edges plus tPAF, PAEwill be valid after the next two
a LOW level, serial offset programming continues.
rising RCLK edges plus tPAE plus tSKEW2.
From the time serial programming has begun, neither partial flag will be
The act of reading the offset registers employs a dedicated read offset
valid until the full set of bits required to fill all the offset registers has been register pointer. The contents of the offset registers can be read on the Q0-
written. Measuring from the rising WCLK edge that achieves the above Qn pins when LD is set LOW and REN is set LOW. For the IDT72V281,
criteria; PAF will be valid after two more rising WCLK edges plus tPAF, data are read via Qn from the Empty Offset LSB Register on the first LOW-
PAE will be valid after the next two rising RCLK edges plus tPAE plus to-HIGH transition of RCLK. Upon the second LOW-to-HIGH transition of
tSKEW2.
RCLK, data are read from the Empty Offset MSB Register. Upon the third
LOW-to-HIGH transition of RCLK, data are read from the Full Offset LSB
Register. Upon the fourth LOW-to-HIGH transition of RCLK, data are read
from the Full Offset MSB Register. The fifth transition of RCLK reads, once
It is not possible to read the flag offset values in a serial mode.
PARALLEL MODE
If Parallel Programming mode has been selected, as described above, again, from the Empty Offset LSB Register. See Figure 16, Parallel Read
then programming of PAE and PAF values can be achieved by using a of Programmable Flag Registers for the IDT72V281, for the timing diagram
combination of the LD, WCLK , WEN and Dn input pins. For the for this mode.
IDT72V281, programming PAEand PAFproceeds as follows: when LD
For the IDT72V291, data is read via Qn from the Empty Offset LSB
and WEN are set LOW, data on the inputs Dn are written into the Empty Register on the first LOW-to-HIGH transition of RCLK. Upon the second
OffsetLSBRegisteronthefirstLOW-to-HIGHtransitionofWCLK.Uponthe LOW-to-HIGHtransitionofRCLK, dataarereadfromtheEmptyOffsetMid-
second LOW-to-HIGH transition of WCLK, data are written into the Empty Byte Register. Upon the third LOW-to-HIGH transition of RCLK, data are
Offset MSB Register. Upon the third LOW-to-HIGH transition of WCLK, read from the Empty Offset MSB Register. Upon the fourth LOW-to-HIGH
data are written into the Full Offset LSB Register. Upon the fourth LOW- transition of RCLK, data are read from the Full Offset LSB Register. Upon
to-HIGH transition of WCLK, data are written into the Full Offset MSB thefifthLOW-to-HIGHtransitionofRCLK,dataarereadfromtheFullOffset
Register. The fifth transition of WCLK writes, once again, to the Empty Mid-Byte Register. Upon the sixth LOW-to-HIGH transition of RCLK, data
Offset LSB Register. See Figure 14, Parallel Loading of Programmable arereadfromtheFullOffsetMSBRegister. TheseventhtransitionofRCLK
reads, once again, from the Empty Offset LSB Register. See Figure 17,
Parallel Read of Programmable Flag Registers for the IDT72V291, for the
timing diagram for this mode.
Itis permissible tointerruptthe offsetregisterreadsequence withreads
or writes to the FIFO. The interruption is accomplished by deasserting
REN, LD, or both together. When REN and LD are restored to a LOW
level, reading of the offset registers continues where it left off. It should be
noted, and care should be taken from the fact that when a parallel read of
the flag offsets is performed, the data word that was present on the output
lines Qn will be overwritten.
Flag Registers for the IDT72V281, for the timing diagram for this mode.
For the IDT72V291, programming PAE and PAF proceeds as
follows: whenLDandWENaresetLOW,dataontheinputsDn arewritten
into the Empty Offset LSB Register on the first LOW-to-HIGH transition of
WCLK. Upon the second LOW-to-HIGH transition of WCLK, data are
written into the Empty Offset Mid-Byte Register. Upon the third LOW-to-
HIGH transition of WCLK, data are written into the Empty Offset MSB
Register. Upon the fourth LOW-to-HIGH transition of WCLK, data are
written into the Full Offset LSB Register. Upon the fifth LOW-to-HIGH
transition of WCLK, data are written into the Full Offset Mid-Byte Register.
10
IDT72V281/72V291
COMMERCIALANDINDUSTRIALTEMPERATURERANGE
Parallelreadingofthe offsetregisters is always permittedregardless of Standard mode is selected, every word read including the first word
which timing mode (IDT Standard or FWFT modes) has been selected.
following Retransmit setup requires a LOW on REN to enable the rising
edge ofRCLK. See Figure 11, RetransmitTiming(IDTStandardMode), for
the relevant timing diagram.
RETRANSMIT OPERATION
The Retransmit operation allows data that has already been read to be
If FWFT mode is selected, the FIFO will mark the beginning of the
accessed again. There are two stages: first, a setup procedure that resets Retransmit setup by setting ORHIGH. During this period, the internal read
the read pointer to the first location of memory, then the actual retransmit, pointer is set to the first location of the RAM array.
whichconsistsofreadingoutthememorycontents,startingatthebeginning
of memory.
When OR goes LOW, Retransmit setup is complete; at the same time,
the contents of the first location appear on the outputs. Since FWFT mode
Retransmit setup is initiated by holding RT LOW during a rising RCLK is selected, the first word appears on the outputs, no LOW on REN is
edge. REN and WEN must be HIGH before bringing RT LOW. At least necessary. Reading all subsequent words requires a LOW on REN to
one word, but no more than D - 2 words should have been written into the enable the rising edge of RCLK. See Figure 12, Retransmit Timing (FWFT
FIFO between Reset (Master or Partial) and the time of Retransmit setup. Mode), for the relevant timing diagram.
D = 65,536 for the IDT72V281 and D = 131,072 for the IDT72V291 in IDT
Standard mode. In FWFT mode, D = 65,537 for the IDT72V281 and HF and PAF flags begin with the rising edge of RCLK that RT is setup.
D = 131,073 for the IDT72V291. PAE is synchronized to RCLK, thus on the second rising edge of RCLK
For either IDT Standard mode or FWFT mode, updating of the PAE,
If IDT Standard mode is selected, the FIFO will mark the beginning of after RTis setup, the PAEflagwillbe updated. HFis asynchronous, thus
the Retransmit setup by setting EF LOW. The change in level will only be the rising edge of RCLK that RT is setup will update HF. PAF is
noticeable if EF was HIGH before setup. During this period, the internal synchronized to WCLK, thus the second rising edge of WCLK that occurs
read pointer is initialized to the first location of the RAM array.
tSKEW after the rising edge of RCLK that RT is setup will update PAF. RT
When EF goes HIGH, Retransmit setup is complete and read opera- is synchronized to RCLK.
tions may begin starting with the first location in memory. Since IDT
11
IDT72V281/72V291
COCOMMCOMMERCIALANDINDUSTRIALTEMPERATURERANGE
Retransmit setup is initiated by holding RT LOW during a rising RCLK
edge. REN and WEN must be HIGH before bringing RT LOW.
If IDT Standard mode is selected, the FIFO will mark the beginning of
the Retransmit setup by setting EF LOW. The change in level will only be
noticeable if EF was HIGH before setup. During this period, the internal
read pointer is initialized to the first location of the RAM array.
When EF goes HIGH, Retransmit setup is complete and read opera-
tions may begin starting with the first location in memory. Since IDT
Standard mode is selected, every word read including the first word
following Retransmit setup requires a LOW on REN to enable the rising
edge ofRCLK. See Figure 11, RetransmitTiming(IDTStandardMode), for
the relevant timing diagram.
IfFWFTmodeisselected,theFIFOwillmarkthebeginningoftheRetransmit
setup by setting OR HIGH. During this period, the internal read pointer is set to
the first location of the RAM array.
When OR goes LOW, Retransmit setup is complete; at the same time,
the contents of the first location appear on the outputs. Since FWFT mode
is selected, the first word appears on the outputs, no LOW on REN is
necessary. Reading all subsequent words requires a LOW on REN to
enable the rising edge of RCLK. See Figure 12, Retransmit Timing (FWFT
SIGNAL DESCRIPTION
INPUTS:
DATA IN (D0 - D8)
Data inputs for 9-bit wide data.
CONTROLS:
MASTER RESET (MRS)
A Master Reset is accomplished whenever the MRS input is taken to
a LOW state. This operation sets the internal read and write pointers to the
first location of the RAM array. PAE will go LOW, PAF will go HIGH, and
HF will go HIGH.
If FWFT is LOW during Master Reset then the IDT Standard mode,
along with EF and FF are selected. EF will go LOW and FFwill go HIGH.
IfFWFTisHIGH,thentheFirstWordFallThroughmode(FWFT),alongwith
IR and OR, are selected. OR will go HIGH and IR will go LOW.
If LD is LOW during Master Reset, then PAE is assigned a threshold
127 words from the empty boundary and PAF is assigned a threshold 127
words from the full boundary; 127 words corresponds to an offset value of Mode), for the relevant timing diagram.
07FH. Following Master Reset, parallel loading of the offsets is permitted,
but not serial loading.
FIRST WORD FALL THROUGH/SERIAL IN (FWFT/SI)
This is a dual purpose pin. During Master Reset, the state of the FWFT/SI
If LD is HIGH during Master Reset, then PAE is assigned a threshold
1,023 words from the empty boundary and PAF is assigned a threshold input determines whether the device will operate in IDT Standard mode or First
1,023 words from the full boundary; 1,023 words corresponds to an offset Word Fall Through (FWFT) mode.
value of 3FFH. Following Master Reset, serial loading of the offsets is
permitted, but not parallel loading.
If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard
mode will be selected. This mode uses the Empty Flag (EF) to indicate
Parallel reading of the registers is always permitted. (See section whetherornotthereareanywordspresentintheFIFOmemory. Italsouses
describing the LD pin for further details.)
the Full Flag function (FF) to indicate whether or not the FIFO memory has
During a Master Reset, the output register is initialized to all zeroes. A anyfree space forwriting. InIDTStandardmode, everywordreadfromthe
Master Reset is required after power up, before a write operation can take FIFO, including the first, must be requested using the Read Enable (REN)
place. MRS is asynchronous.
and RCLK.
If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will
See Figure 5, Master Reset Timing, for the relevant timing diagram.
beselected. This modeuses OutputReady(OR)toindicatewhetherornot
there is valid data at the data outputs (Qn). It also uses Input Ready (IR)
to indicate whether or not the FIFO memory has any free space for writing.
In the FWFT mode, the first word written to an empty FIFO goes directly to
Qn after three RCLK rising edges, REN = LOW is not necessary. Subse-
quent words must be accessed using the Read Enable (REN) and RCLK.
AfterMasterReset, FWFT/SIacts as a serialinputforloadingPAEand
PAFoffsets intothe programmable registers. The serialinputfunctioncan
only be used when the serial loading method has been selected during
Master Reset. Serial programming using the FWFT/SI pin functions the
same way in both IDT Standard and FWFT modes.
PARTIAL RESET (PRS)
A Partial Reset is accomplished whenever the PRS input is taken to a LOW
state. As in the case of the Master Reset, the internal read and write pointers are
set to the first location of the RAM array, PAEgoes LOW, PAFgoes HIGH, and
HF goes HIGH.
Whichever mode is active at the time of Partial Reset, IDT Standard mode
orFirstWordFallThrough,thatmodewillremainselected. IftheIDTStandard
mode is active, then FF will go HIGH and EF will go LOW. If the First Word
Fall Through mode is active, then OR will go HIGH, and IR will go LOW.
Following Partial Reset, all values held in the offset registers remain
unchanged. The programming method (parallel or serial) currently active
at the time of Partial Reset is also retained. The output register is initialized
to all zeroes. PRS is asynchronous.
WRITE CLOCK (WCLK)
AwritecycleisinitiatedontherisingedgeoftheWCLKinput.Datasetup
and hold times must be met with respect to the LOW-to-HIGH transition of
theWCLK.Itis permissibletostoptheWCLK. NotethatwhileWCLKis idle,
theFF/IR,PAFandHFflags willnotbeupdated. (NotethatWCLKis only
capable of updating HF flag to LOW.) The Write and Read Clocks can
either be independent or coincident.
A Partial Reset is useful for resetting the device during the course of
operation, when reprogramming partial flag offset settings may not be
convenient.
See Figure 6, Partial Reset Timing, for the relevant timing diagram.
RETRANSMIT (RT)
WRITE ENABLE (WEN)
The Retransmit operation allows data that has already been read to be
accessed again. There are two stages: first, a setup procedure that resets the
read pointer to the first location of memory, then the actual retransmit, which
consists of reading out the memory contents, starting at the beginning of the
memory.
When the WEN input is LOW, data may be loaded into the FIFO RAM
array on the rising edge of every WCLK cycle if the device is not full. Data
is stored in the RAM array sequentially and independently of any ongoing
read operation.
12
IDT72V281/72V291
When WEN is HIGH, no new data is written in the RAM array on each PAF flags, along with the method by which these offset registers can be
COMMERCIALANDINDUSTRIALTEMPERATURERANGE
WCLK cycle.
programmed, parallel or serial. After Master Reset, LD enables write
To prevent data overflow in the IDT Standard mode, FF will go LOW, operations to and read operations from the offset registers. Only the offset
inhibitingfurtherwriteoperations. Uponthecompletionofavalidreadcycle, loading method currently selected can be used to write to the registers.
FFwillgoHIGHallowinga write tooccur. The FFis updatedbytwoWCLK Offset registers can be read only in parallel. A LOW on LD during Master
cycles + tSKEW after the RCLK cycle.
Reset selects a default PAE offset value of 07FH (a threshold 127 words
Topreventdataoverflow intheFWFTmode, IR willgoHIGH,inhibiting from the empty boundary), a default PAFoffset value of 07FH (a threshold
further write operations. Upon the completion of a valid read cycle, IR will 127 words from the full boundary), and parallel loading of other offset
go LOW allowing a write to occur. The IR flag is updated by two WCLK values. A HIGH on LD during Master Reset selects a default PAE offset
cycles + tSKEW after the valid RCLK cycle.
valueof3FFH(athreshold1,023wordsfromtheemptyboundary),adefault
WEN is ignored when the FIFO is full in either FWFT or IDT Standard PAFoffsetvalue of3FFH(a threshold1,023words fromthe fullboundary),
mode.
READ CLOCK (RCLK)
and serial loading of other offset values.
After Master Reset, the LD pin is used to activate the programming
process oftheflagoffsetvalues PAEandPAF.PullingLDLOWwillbegin
A read cycle is initiated on the rising edge of the RCLK input. Data can be a serial loading or parallel load or read of these offset values. See Figure 4,
read on the outputs, on the rising edge of the RCLK input. It is permissible to Programmable Flag Offset Programming Sequence.
stopthe RCLK. Note thatwhile RCLKis idle, the EF/OR, PAEandHFflags
will not be updated. (Note that RCLK is only capable of updating the HF flag
to HIGH.) The Write and Read Clocks can be independent or coincident.
OUTPUTS:
FULL FLAG (FF/IR)
This is a dual purpose pin. In IDT Standard mode, the Full Flag (FF)
functionisselected.WhentheFIFOisfull,FFwillgoLOW,inhibitingfurther
write operations. When FF is HIGH, the FIFO is not full. If no reads are
performed after a reset (either MRS or PRS), FF will go LOW after D
writes to the FIFO (D = 65,536 for the IDT72V281 and 131,072 for the
IDT72V291). See Figure 7, Write Cycle and Full Flag Timing (IDT Standard
Mode), for the relevant timing information.
READ ENABLE (REN)
When Read Enable is LOW, data is loaded from the RAM array into the
outputregisterontherisingedgeofeveryRCLKcycleifthedeviceisnotempty.
When the RENinput is HIGH, the output register holds the previous data
and no new data is loaded into the output register. The data outputs Q
maintain the previous data value.
0-Qn
IntheIDTStandardmode,everywordaccessedatQn,includingthefirst
word written to an empty FIFO, must be requested using REN. When the
last word has been read from the FIFO, the Empty Flag (EF) will go LOW,
inhibitingfurtherreadoperations. RENis ignoredwhentheFIFOis empty.
Once a write is performed, EF will go HIGH allowing a read to occur. The
EFflagis updatedbytwoRCLKcycles +tSKEW afterthevalidWCLKcycle.
In the FWFT mode, the first word written to an empty FIFO automatically
In FWFT mode, the Input Ready (IR) function is selected. IR goes
LOW when memory space is available for writing in data. When there is no
longeranyfreespaceleft,IRgoesHIGH,inhibitingfurtherwriteoperations.
If no reads are performed after a reset (either MRS or PRS), IR will go
HIGH after D writes to the FIFO (D = 65,537 for the IDT72V281 and
131,073 for the IDT72V291) See Figure 9, Write Timing (FWFT Mode), for
the relevant timing information.
The IRstatus not only measures the contents of the FIFO memory, but
also counts the presence of a word in the output register. Thus, in FWFT
mode, the total number of writes necessary to deassert IR is one greater
than needed to assert FF in IDT Standard mode.
goestotheoutputsQn,onthethirdvalidLOWtoHIGHtransitionofRCLK+ tSKEW
afterthefirstwrite. RENdoesnotneedtobeassertedLOW. Inordertoaccess
allotherwords,areadmustbeexecutedusingREN. TheRCLKLOWtoHIGH
transitionafterthelastword hasbeenreadfromtheFIFO,OutputReady(OR)
will go HIGH with a true read (RCLK with REN=LOW), inhibitingfurtherread
operations. REN is ignored when the FIFO is empty.
FF/IRis synchronous andupdatedontherisingedgeofWCLK. FF/IR
are double register-buffered outputs.
SERIAL ENABLE (SEN)
EMPTY FLAG (EF/OR)
The SEN input is an enable used only for serial programming of the
offset registers. The serial programming method must be selected during
Master Reset. SEN is always used in conjunction with LD. When these
lines are both LOW, data at the SI input can be loaded into the program
register one bit for each LOW-to-HIGH transition of WCLK. (See Figure 4.)
When SEN is HIGH, the programmable registers retains the previous
settings and no offsets are loaded. SEN functions the same way in both
IDT Standard and FWFT modes.
This is a dual purpose pin. In the IDT Standard mode, the Empty Flag
(EF) function is selected. When the FIFO is empty, EF will go LOW,
inhibitingfurtherreadoperations. WhenEFisHIGH,theFIFOisnotempty.
See Figure 8, Read Cycle, Empty Flag and First Word Latency Timing (IDT
Standard Mode), for the relevant timing information.
In FWFT mode, the Output Ready (OR) function is selected. OR goes
LOW at the same time that the first word written to an empty FIFO appears
valid on the outputs. OR stays LOW after the RCLK LOW to HIGH
transitionthatshiftsthelastwordfromtheFIFOmemorytotheoutputs. OR
goes HIGH only with a true read (RCLK with REN = LOW). The previous
data stays at the outputs, indicating the last word was read. Further data
reads are inhibited until ORgoes LOW again. See Figure 10, Read Timing
(FWFT Mode), for the relevant timing information.
OUTPUT ENABLE (OE)
When Output Enable is enabled (LOW), the parallel output buffers receive
datafromtheoutputregister. WhenOEisHIGH,theoutputdatabus(Qn)goes
into a high impedance state.
EF/OR is synchronous and updated on the rising edge of RCLK.
InIDTStandardmode,EFisadoubleregister-bufferedoutput.InFWFT
mode, OR is a triple register-buffered output.
LOAD (LD)
This is a dual purpose pin. During Master Reset, the state of the LD input
determines one of two default offset values (127 or 1,023) for the PAE and
13
IDT72V281/72V291
COCOMMCOMMERCIALANDINDUSTRIALTEMPERATURERANGE
PROGRAMMABLE ALMOST-FULL FLAG (PAF)
See Figure 19, Programmable Almost-Empty Flag Timing (IDT Stan-
The Programmable Almost-Full flag (PAF) will go LOW when the FIFO dard and FWFT Mode), for the relevant timing information.
reaches the almost-full condition. In IDT Standard mode, if no reads are
PAE is synchronous and updated on the rising edge of RCLK.
performed after reset (MRS), PAF will go LOW after (D - m) words are
written to the FIFO. The PAF will go LOW after (65,536-m) writes for the HALF-FULL FLAG (HF)
IDT72V281and (131,072-m)writesfortheIDT72V291.Theoffset“m”isthe
This outputindicates ahalf-fullFIFO.TherisingWCLKedgethatfills the
full offset value. The default setting for this value is stated in the footnote of FIFO beyond half-full sets HF LOW. The flag remains LOW until the
Table 1.
difference between the write and read pointers becomes less than or equal
In FWFT mode, the PAF will go LOW after (65,537-m) writes for the to half of the total depth of the device; the rising RCLK edge that accom-
IDT72V281 and (131,073-m) writes for the IDT72V291, where m is the full plishes this condition sets HF HIGH.
offset value. The default setting for this value is stated in the footnote of
In IDT Standard mode, if no reads are performed after reset (MRS or
PRS), HFwillgoLOWafter(D/2 + 1)writes totheFIFO,whereD=65,536
for the IDT72V281 and 131,072 for the IDT72V291.
In FWFT mode, if no reads are performed after reset (MRS or PRS),
HF will go LOW after (D-1/2 + 2) writes to the FIFO, where D = 65,537 for
the IDT72V281 and 131,073 for the IDT72V291.
Table 2.
See Figure 18, Programmable Almost-Full Flag Timing (IDT Standard
and FWFT Mode), for the relevant timing information.
PAF is synchronous and updated on the rising edge of WCLK.
See Figure 20, Half-Full Flag Timing (IDT Standard and FWFT Modes),
for the relevant timing information. Because HF is updated by both RCLK
and WCLK, it is considered asynchronous.
PROGRAMMABLE ALMOST-EMPTY FLAG (PAE)
The Programmable Almost-Empty flag (PAE) will go LOW when the
FIFO reaches the almost-empty condition. In IDT Standard mode, PAE will
go LOW when there are n words or less in the FIFO. The offset “n” is the
emptyoffsetvalue. The defaultsettingforthis value is statedinthe footnote
of Table 1.
DATA OUTPUTS (Q0-Q8)
(Q0 - Q8) are data outputs for 9-bit wide data.
InFWFTmode, the PAEwillgoLOWwhenthere are n+1words orless in
the FIFO. The default setting for this value is stated in the footnote of Table 2.
14
IDT72V281/72V291
COMMERCIALANDINDUSTRIALTEMPERATURERANGE
tRS
MRS
REN
tRSS
tRSR
tRSR
tRSS
WEN
FWFT/SI
LD
t
RSR
t
FWFT
tRSS
tRSR
tRSS
RT
tRSS
SEN
t
RSF
If FWFT = HIGH, OR = HIGH
If FWFT = LOW, EF = LOW
If FWFT = LOW, FF = HIGH
If FWFT = HIGH, IR = LOW
EF/OR
FF/IR
t
RSF
t
RSF
PAE
t
RSF
PAF, HF
t
RSF
OE = HIGH
OE = LOW
Q0 - Qn
4513 drw 08
Figure 5. Master Reset Timing
15
IDT72V281/72V291
COCOMMCOMMERCIALANDINDUSTRIALTEMPERATURERANGE
tRS
PRS
REN
tRSS
tRSR
tRSS
tRSR
WEN
RT
t
RSS
RSS
t
SEN
If FWFT = HIGH, OR = HIGH
If FWFT = LOW, EF = LOW
If FWFT = LOW, FF = HIGH
If FWFT = HIGH, IR = LOW
t
RSF
EF/OR
t
RSF
FF/IR
PAE
t
RSF
t
RSF
PAF, HF
t
RSF
OE = HIGH
OE = LOW
Q0 - Qn
4513 drw 09
Figure 6. Partial Reset Timing
16
IDT72V281/72V291
COMMERCIALANDINDUSTRIALTEMPERATURERANGE
t
CLK
t
CLKH
NO WRITE
NO WRITE
tCLKL
2
1
WCLK
1
2
(1)
SKEW1
t
SKEW1(1)
t
t
DS
tDH
t
DS
tDH
D
X
DX+1
D0 - Dn
t
WFF
t
WFF
t
WFF
t
WFF
FF
WEN
RCLK
t
ENS
tENH
t
ENS
tENH
REN
t
A
tA
Q0 - Qn
DATA IN OUTPUT REGISTER
DATA READ
NEXT DATA READ
4513 drw 10
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go high (after one WCLK cycle pus tWFF). If the time between the rising
edge of the RCLK and the rising edge of the WCLK is less than tSKEW1, then the FF deassertion may be delayed one extra WCLK cycle.
2. LD = HIGH, OE = LOW, EF = HIGH
Figure 7. Write Cycle and Full Flag Timing (IDT Standard Mode)
tCLK
tCLKH
tCLKL
1
2
RCLK
REN
EF
tENH
tENS
tENS
tENH
t
ENH
tENS
NO OPERATION
NO OPERATION
tREF
tREF
tREF
tA
tA
tA
D0
Q0
- Qn
LAST WORD
D1
LAST WORD
tOLZ
t
OLZ
tOHZ
tOE
OE
t
SKEW3(1)
WCLK
tENH
tENH
tENS
tENS
WEN
tDS
tDH
tDHS
tDS
D0
- Dn
D0
D1
4513 drw 11
NOTES:
1. tSKEW3 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus tREF). If the time between the rising edge
of WCLK and the rising edge of RCLK is less than tSKEW3, then EF deassertion may be delayed one extra RCLK cycle.
2. LD = HIGH.
3. First data word latency: 60ns + tREF + 1*TRCLK.
Figure 8. Read Cycle, Empty Flag and First Data Word Latency Timing (IDT Standard Mode)
17
WCLK
1
tENS
WEN
tDS
tDS
tDS
tDS
tDH
tENH
D-1
D-1
D-1
D0 - D8
WD
W3
W[n+4]
W[D-m-2]
W1
W
2
W4
W[n +2]
W
[n+3]
[
]
[
]
[
W
]
W[D-m-1]
W[D-m]
W[D-m+1]
W[D-m+2]
W[D-1]
W
W
(2)
tSKEW2
t
SKEW3(1)
2
1
3
1
2
RCLK
REN
tA
DATA IN OUTPUT REGISTER
Q0 - Q8
W1
t
REF
OR
t
PAE
PAE
tHF
HF
t
PAF
PAF
IR
t
WFF
4513 drw 12
NOTES:
1. tSKEW3 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that OR will go LOW after two RCLK cycles plus tREF. If the time between the rising edge of WCLK and the rising edge of RCLK is less than
tSKEW3, then OR assertion may be delayed one extra RCLK cycle.
2. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH after one RCLK cycle plus tPAE. If the time between the rising edge of WCLK and the rising edge of RCLK is less than
tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.
3. LD = HIGH, OE = LOW
4. n = PAE offset, m = PAF offset and D = maximum FIFO depth.
5. D = 65,537 for the IDT72V281 and 131,073 for the IDT72V291.
6. First data word latency: 60ns + tREF + 2*TRCLK.
Figure 9. Write Timing (First Word Fall Through Mode)
WCLK
1
t
2
(2)
(1)
SKEW1
tSKEW2
tENS
tENH
WEN
tDS
tDH
D0 - D8
WD
RCLK
1
tENS
tENS
REN
OE
tOHZ
tOE
tA
tA
tA
tA
tA
tA
D-1
D-1
Q0 - Q8
Wm+2
W
[
]
W
[
]
W[D-n-1]
W[D-n]
WD
W1
W1
W2
W3
W[m+3]
W[m+4]
W[D-n+1]
W[D-n+2]
W[D-1]
t
REF
OR
t
PAE
PAE
tHF
HF
t
PAF
PAF
IR
t
WFF
t
WFF
4513 drw 13
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that IR will go LOW after one WCLK cycle plus tWFF. If the time between the rising edge of RCLK and the rising edge of WCLK is less than
tSKEW1, then the IR assertion may be delayed one extra WCLK cycle.
2. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH after one WCLK cycle plus tPAF. If the time between the rising edge of RCLK and the rising edge of WCLK is less than
tSKEW2, then the PAF deassertion may be delayed one extra WCLK cycle.
3. LD = HIGH
4. n = PAE Offset, m = PAF offset and D = maximum FIFO depth.
5. D = 65,537 for the IDT72V281 and 131,073 for the IDT72V291.
Figure 10. Read Timing (First Word Fall Through Mode)
IDT72V281/72V291
COCOMMCOMMERCIALANDINDUSTRIALTEMPERATURERANGE
1
2
RCLK
t
ENS
t
ENH
t
ENS
tENH
tRTS
REN
t
A
t
A
t
A
(3)
(3)
Q0 - Qn
Wx
Wx+1
W
1
W
2
t
SKEW2
1
2
WCLK
WEN
RT
tRTS
t
ENS
tENH
(5)
tREF
tREF
EF
PAE
HF
t
PAE
tHF
t
PAF
PAF
4513 drw 14
NOTES:
1. Retransmit setup is complete after EF returns HIGH, only then can a read operation begin.
2. OE = LOW.
3. W1 = first word written to the FIFO after Master Reset, W2 = second word written to the FIFO after Master Reset.
4. No more than D - 2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FFwill be HIGH throughout the Retransmit setup procedure. D = 65,536
for the IDT72V281 and 131,072 for the IDT72V291.
5. EF goes HIGH at 60ns + 1 RCLK cycle + tREF.
Figure 11. Retransmit Timing (IDT Standard Mode)
20
IDT72V281/72V291
COMMERCIALANDINDUSTRIALTEMPERATURERANGE
3
1
2
4
RCLK
t
ENH
t
ENH
t
ENS
t
ENH
tRTS
REN
- Q
t
A
t
A
(4)
Q0
n
Wx
Wx+1
W2
W
1
W3
t
SKEW2
1
2
WCLK
tRTS
WEN
t
ENS
tENH
RT
OR
(5)
tREF
tREF
t
PAE
PAE
tHF
HF
PAF
t
PAF
4513 drw 15
NOTES:
1. Retransmit setup is complete after OR returns LOW.
2. No more than D - 2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup procedure.
D = 65,537 for the IDT72V281 and 131,073 for the IDT72V291.
3. OE = LOW
4. W1, W2, W3 = first, second and third words written to the FIFO after Master Reset.
5. OR goes LOW at 60ns + 2 RCLK cycles + tREF.
Figure 12. Retransmit Timing (FWFT Mode)
WCLK
t
ENH
LDH
t
ENS
t
ENH
SEN
LD
t
t
LDS
tLDH
t
DS
tDH
(1)
BIT X(1)
BIT 0
BIT 0
BIT X
SI
4513 drw 16
EMPTY OFFSET
FULL OFFSET
NOTE:
1. X = 15 for the IDT72V281 and X = 16 for the IDT72V291.
Figure 13. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
21
IDT72V281/72V291
COCOMMCOMMERCIALANDINDUSTRIALTEMPERATURERANGE
t
CLK
t
CLKH
t
CLKL
WCLK
LD
t
LDS
t
LDH
t
LDH
t
ENS
t
t
ENH
DH
t
ENH
WEN
t
DH
t
DS
D0 - D7
PAE OFFSET
(LSB)
PAE OFFSET
(MSB)
PAF OFFSET
(LSB)
PAF OFFSET
(MSB)
4513 drw 17
Figure 14. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes) for the IDT72V281
t
CLK
t
CLKH
t
CLKL
WCLK
LD
t
LDS
t
LDH
t
LDH
t
ENS
t
t
ENH
DH
t
ENH
WEN
t
DH
t
DS
D0 - D7
PAF OFFSET
(MSB)
PAE OFFSET
(LSB)
PAE OFFSET
(MID-BYTE)
PAE OFFSET
(MSB)
PAF OFFSET
(LSB)
PAF OFFSET
(MID-BYTE)
4513 drw 18
Figure 15. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes) for the IDT72V291
t
CLK
t
CLKH
tCLKL
RCLK
t
LDS
t
LDH
t
t
LDH
ENH
LD
t
ENS
tENH
REN
t
A
t
A
PAE OFFSET
(MSB)
PAE OFFSET
(LSB)
PAF OFFSET
(LSB)
PAF OFFSET
(MSB)
4513 drw 19
DATA IN OUTPUT REGISTER
Q0
- Q7
NOTE:
1. OE = LOW
Figure 16. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes) for the IDT72V281
t
CLK
t
CLKH
t
CLKL
RCLK
t
t
LDS
tLDH
t
LDH
LD
t
ENH
ENS
tENH
REN
t
A
t
A
PAE OFFSET
(LSB)
PAE OFFSET
(MID-BYTE)
PAE OFFSET
(MSB)
PAF OFFSET
(LSB)
PAF OFFSET
(MID-BYTE)
PAF OFFSET
(MSB)
DATA IN OUTPUT REGISTER
Q0 - Q7
4513 drw 20
NOTE:
1. OE = LOW
Figure 17. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes) for the IDT72V291
22
IDT72V281/72V291
COMMERCIALANDINDUSTRIALTEMPERATURERANGE
t
CLKH
t
CLKL
1
2
WCLK
WEN
PAF
2
1
t
ENS
tENH
t
PAF
tPAF
D - (m+1) words in FIFO(2)
D - m words in FIFO(2)
D-(m+1) words
in FIFO(2)
(3)
t
SKEW2
RCLK
t
ENH
t
ENS
4513 drw 21
REN
NOTES:
1. m = PAF offset .
2. D = maximum FIFO depth.
In IDT Standard mode: D = 65,536 for the IDT72V281 and 131,072 for the IDT72V291.
In FWFT mode: D = 65,537 for the IDT72V281 and 131,073 for the IDT72V291.
3.
t
SKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus tPAF). If the time between the rising edge of
RCLK and the rising edge of WCLK is less than tSKEW2, then the PAF deassertion time may be delayed one extra WCLK cycle.
4. PAF is asserted and updated on the rising edge of WCLK only.
Figure 18. Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
t
CLKH
t
CLKL
WCLK
t
ENH
t
ENS
WEN
PAE
n words in FIFO (2)
n+1 words in FIFO (3)
,
n words in FIFO (2)
n+1 words in FIFO (3)
,
n+1 words in FIFO (2)
n+2 words in FIFO (3)
,
(4)
SKEW2
t
PAE
t
PAE
t
1
2
1
2
RCLK
t
ENS
tENH
4513 drw 22
REN
NOTES:
1. n = PAE offset.
2. For IDT Standard mode
3. For FWFT mode.
4. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH (after one RCLK cycle plus tPAE). If the time between the rising edge of
WCLK and the rising edge of RCLK is less than tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.
5. PAE is asserted and updated on the rising edge of WCLK only.
Figure 19. Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
tCLKH
tCLKL
WCLK
tENH
tENS
WEN
HF
tHF
D/2 + 1 words in FIFO(1),
D/2 words in FIFO(1)
,
D/2 words in FIFO(1)
,
D-1
2
[
+ 2]
words in FIFO(2)
D-1
2
D-1
2
[
+ 1
]
words in FIFO(2)
[
+ 1
words in FIFO(2)
]
tHF
RCLK
tENS
REN
4513 drw 23
NOTES:
1. For IDT Standard mode: D = maximum FIFO depth. D = 65,536 for the IDT72V281 and 131,072 for the IDT72V291.
2. For FWFT mode: D = maximum FIFO depth. D = 65,537 for the IDT72V281 and 131,073 for the IDT72V291.
Figure 20. Half-Full Flag Timing (IDT Standard and FWFT Modes)
23
IDT72V281/72V291
COCOMMCOMMERCIALANDINDUSTRIALTEMPERATURERANGE
such problems can be avoided by creating composite flags, that is, ANDing
EF of every FIFO, and separately ANDing FF of every FIFO. In FWFT
mode, composite flags can be created by ORing OR of every FIFO, and
separately ORing IR of every FIFO.
Figure 21 demonstrates a width expansion using two IDT72V281/
72V291 devices. D0 - D8 from each device form a 18-bit wide input bus and
Q0-Q8 from each device form a 18-bit wide output bus. Any word width can
be attained by adding additional IDT72V281/72V291 devices.
OPTIONAL CONꢀIGURATIONS
WIDTH EXPANSION CONFIGURATION
Wordwidthmaybe increasedsimplybyconnectingtogetherthe control
signals of multiple devices. Status flags can be detected from any one
device. TheexceptionsaretheEFandFFfunctionsinIDTStandardmode
andtheIRandORfunctionsinFWFTmode. Becauseofvariationsinskew
between RCLK and WCLK, it is possible for EF/FF deassertion and IR/
OR assertion to vary by one cycle between FIFOs. In IDT Standard mode,
PARTIAL RESET (PRS)
MASTER RESET (MRS)
FIRST WORD FALL THROUGH/
SERIAL INPUT (FWFT/SI)
RETRANSMIT (RT)
Dm+1 - Dn
m + n
m
n
D0 - Dm
DATA IN
READ CLOCK (RCLK)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
LOAD (LD)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
PROGRAMMABLE (PAE)
IDT
72V281
72V291
IDT
72V281
72V291
FULL FLAG/INPUT READY (FF/IR)
#1
(1)
EMPTY FLAG/OUTPUT READY (EF/OR) #1
EMPTY FLAG/OUTPUT READY (EF/OR) #2
(1)
GATE
FULL FLAG/INPUT READY (FF/IR) #2
GATE
PROGRAMMABLE (PAF)
HALF-FULL FLAG (HF)
m + n
n
Qm+1 - Qn
FIFO
#1
FIFO
#2
DATA OUT
m
4513 drw 24
Q0 - Qm
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
Figure 21. Block Diagram of 65,536 x 18 and 131,072 x 18 Width Expansion
FIFO'soutputs)afterawordhasbeenwrittentothefirstFIFOisthesumofthe
delays for each individual FIFO:
DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY)
The IDT72V281 can easily be adapted to applications requiring depths
greater than 65,536 and 131,072 for the IDT72V291 with a 9-bit bus width.
In FWFT mode, the FIFOs can be connected in series (the data outputs of
one FIFO connected to the data inputs of the next) with no external logic
necessary. The resulting configuration provides a total depth equivalent to
the sum of the depths associated with each single FIFO. Figure 22 shows
a depth expansion using two IDT72V281/72V291 devices.
(N – 1)*(4*transfer clock) + 3*TRCLK
whereNisthenumberofFIFOsintheexpansionandTRCLKistheRCLKperiod.
Note that extra cycles should be added for the possibility that the tSKEW3
specificationisnotmetbetweenWCLKandtransferclock,orRCLKandtransfer
clock,fortheORflag.
The "ripple down" delay is only noticeable for the first word written to an
empty depth expansion configuration. There will be no delay evident for
subsequent words written to the configuration.
The first free location created by reading from a full depth expansion
configuration will "bubble up" from the last FIFO to the previous one until it
finally moves into the first FIFO of the chain. Each time a free location is
created in one FIFO of the chain, that FIFO's IR line goes LOW, enabling
the preceding FIFO to write a word to fill it.
Care should be taken to select FWFT mode during Master Reset for all
FIFOs in the depth expansion configuration. The first word written to an
emptyconfigurationwillpass fromone FIFOtothe next("ripple down")until
it finally appears at the outputs of the last FIFO in the chain–no read
operation is necessary but the RCLK of each FIFO must be free-running.
Each time the data word appears at the outputs of one FIFO, that device's
OR line goes LOW, enabling a write to the next FIFO in line.
Foranemptyexpansionconfiguration,theamountoftimeittakesforOR
of the last FIFO in the chain to go LOW (i.e. valid data to appear on the last
24
IDT72V281/72V291
COMMERCIALANDINDUSTRIALTEMPERATURERANGE
FWFT/SI
TRANSFER CLOCK
FWFT/SI
FWFT/SI
READ CLOCK
READ ENABLE
WRITE CLOCK
WRITE ENABLE
WCLK
WEN
IR
RCLK
WCLK
RCLK
OR
WEN
REN
IDT
72V281
72V291
IDT
72V281
72V291
INPUT READY
OUTPUT READY
OUTPUT ENABLE
REN
OR
OE
Qn
IR
OE
GND
n
DATA OUT
n
n
DATA IN
Dn
Qn
Dn
4513 drw 25
Figure 22. Block Diagram of 131,072 x 9 and 262,144 x 9 Depth Expansion
Forafullexpansionconfiguration,theamountoftimeittakesforIRofthefirst tSKEW1specificationisnotmetbetweenRCLKandtransferclock,orWCLKand
FIFOinthechaintogoLOWafterawordhasbeenreadfromthelastFIFO is transferclock,fortheIRflag.
the sumofthe delays foreachindividualFIFO:
The Transfer Clock line should be tied to either WCLK or RCLK,
whichever is faster. Both these actions result in data moving, as quickly as
possible, to the end of the chain and free locations to the beginning of the
chain.
(N – 1)*(3*transfer clock) + 2 TWCLK
where N is the number of FIFOs in the expansion and TWCLK is the WCLK
period. Note that extra cycles should be added for the possibility that the
25
ORDERINGINꢀORMATION
IDT
XXXXX
X
XX
X
X
Process /
Temperature
Range
Device Type
Power
Speed
Package
BLANK
I(1)
Commercial (0 C to +70 C)
Industrial (-40 C to +85 C)
PF
TF
Thin Plastic Quad Flatpack (TQFP, PN64-1)
Slim Thin Quad Flatpack (STQFP, PP64-1)
Commercial Only
10
15
20
Clock Cycle Time (tCLK
Speed in Nanoseconds
)
Com’l & Ind’l
Commercial Only
Low Power
L
65,536 x 9 3.3V SuperSyncFIFO
131,072 x 9 3.3V SuperSyncFIFO
72V281
72V291
4513 drw 26
NOTE:
1. Industrial temperature range product for the 15ns speed grade is available as a standard device.
DATASHEET DOCUMENT HISTORY
pgs. 1, 5, 6 and 26.
04/24/2001
2975 Stender Way
Santa Clara, CA 95054
800-345-7015
fax: 408-492-8674
www.idt.com
SuperSyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
26
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