IDT72V223L10BCI [IDT]
3.3 VOLT HIGH-DENSITY SUPERSYNC NARROW BUS FIFO; 3.3伏高密度SUPERSYNC窄总线FIFO
| 型号： | IDT72V223L10BCI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 3.3 VOLT HIGH-DENSITY SUPERSYNC NARROW BUS FIFO |
| 文件： | 总45页 (文件大小：429K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3VOLTHIGH-DENSITYSUPERSYNCII™
NARROWBUSFIFO
512 x 18/1,024 x 9, 1,024 x 18/2,048 x 9
2,048 x 18/4,096 x 9, 4,096 x 18/8,192 x 9
8,192 x 18/16,384 x 9, 16,384 x 18/32,768 x 9
32,768 x 18/65,536 x 9, 65,536 x 18/131,072 x 9
IDT72V223,IDT72V233
IDT72V243,IDT72V253
IDT72V263,IDT72V273
IDT72V283,IDT72V293
• Fixed, low first word latency
• Zero latency retransmit
• Auto power down minimizes standby power consumption
• Master Reset clears entire FIFO
• Partial Reset clears data, but retains programmable settings
• Empty, Full and Half-Full flags signal FIFO status
• Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of eight preselected offsets
• Selectable synchronous/asynchronous timing modes for Almost-
Empty and Almost-Full flags
FEATURES:
• Choose among the following memory organizations:
IDT72V223
IDT72V233
IDT72V243
IDT72V253
IDT72V263
IDT72V273
IDT72V283
IDT72V293
512 x 18/1,024 x 9
1,024 x 18/2,048 x 9
2,048 x 18/4,096 x 9
4,096 x 18/8,192 x 9
8,192 x 18/16,384 x 9
16,384 x 18/32,768 x 9
32,768 x 18/65,536 x 9
65,536 x 18/131,072 x 9
• Functionally compatible with the IDT72V255LA/72V265LA and
IDT72V275/72V285 SuperSync FIFOs
• Up to 166 MHz Operation of the Clocks
• User selectable Asynchronous read and/or write ports (BGA Only)
• User selectable input and output port bus-sizing
- x9 in to x9 out
• Program programmable flags by either serial or parallel means
• Select IDT Standard timing (using EF and FF flags) or First Word
Fall Through timing (using OR and IR flags)
• Output enable puts data outputs into high impedance state
• Easily expandable in depth and width
• JTAG port, provided for Boundary Scan function (BGA Only)
• Independent Read and Write Clocks (permit reading and writing
simultaneously)
- x9 in to x18 out
- x18 in to x9 out
- x18 in to x18 out
• Available in a 80-pin Thin Quad Flat Pack (TQFP) or a 100-pin Ball
Grid Array (BGA) (with additional features)
• High-performance submicron CMOS technology
• Industrial temperature range (–40°C to +85°C) is available
• Pin to Pin compatible to the higher density of IDT72V2103/72V2113
• Big-Endian/Little-Endian user selectable byte representation
• 5V tolerant inputs
FUNCTIONAL BLOCK DIAGRAM
*Available on the
BGA package only.
D0 -Dn (x9 or x18)
LD SEN
WEN
WCLK/WR
*
INPUT REGISTER
OFFSET REGISTER
FF/IR
PAF
EF/OR
PAE
FLAG
LOGIC
WRITE CONTROL
LOGIC
ASYW
RAM ARRAY
HF
*
512 x 18 or 1,024 x 9
FWFT/SI
PFM
1,024 x 18 or 2,048 x 9
2,048 x 18 or 4,096 x 9
4,096 x 18 or 8,192 x 9
8,192 x 18 or 16,384 x 9
16,384 x 18 or 32,768 x 9
32,768 x 18 or 65,536 x 9
65,536 x 18 or 131,072 x 9
FSEL0
FSEL1
WRITE POINTER
READ POINTER
BE
CONTROL
LOGIC
IP
RT
READ
CONTROL
LOGIC
RM
ASYR
OUTPUT REGISTER
IW
OW
BUS
*
CONFIGURATION
MRS
PRS
RESET
LOGIC
RCLK/RD
*
REN
TCK
*
*
TRST
*
JTAG CONTROL
(BOUNDARY SCAN)
TMS
4666 drw01
*
TDI
Q0 -Qn (x9 or x18)
OE
*
TDO
*
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT and the IDT logo are a registered trademarks of Integrated Device Technology, Inc. The SuperSync II FIFO is a trademark of Integrated Device Technology, Inc.
SEPTEMBER 2003
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-4666/12
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
• The period required by the retransmit operation is now fixed and short.
• Thefirstworddatalatencyperiod,fromthetimethefirstwordiswrittentoan
emptyFIFOtothetimeitcanberead,isnowfixedandshort.(Thevariable
clock cycle counting delay associated with the latency period found on
previousSuperSyncdeviceshasbeeneliminatedonthisSuperSyncfamily.)
• Asynchronous/Synchronous translationonthereadorwriteports
• Highdensityofferingsupto1Mbit
Bus-MatchingSuperSyncFIFOsareparticularlyappropriatefornetwork,
video,telecommunications,datacommunicationsandotherapplicationsthat
needtobufferlargeamountsofdataandmatchbussesofunequalsizes.
DESCRIPTION:
The IDT72V223/72V233/72V243/72V253/72V263/72V273/72V283/
72V293areexceptionallydeep,highspeed,CMOSFirst-In-First-Out(FIFO)
memorieswithclockedreadandwritecontrolsandaflexibleBus-Matchingx9/
x18 data flow. These FIFOs offer numerous improvements over previous
SuperSyncFIFOs,includingthefollowing:
• Flexible x9/x18 Bus-Matching on both read and write ports
• The limitationofthe frequencyofone clockinputwithrespecttothe other
has been removed. The Frequency Select pin (FS) has been removed,
thus it is no longer necessary to select which of the two clock inputs,
RCLK or WCLK, is running at the higher frequency.
PIN CONFIGURATIONS
INDEX
1
2
3
4
5
6
7
8
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
RT
OE
WEN
SEN
DNC(1)
VCC
VCC
Q17
Q16
GND
GND
Q15
DNC(1)
IW
GND
D17
VCC
9
Q14
D16
D15
D14
D13
GND
D12
D11
D10
D9
10
11
12
13
14
15
16
17
18
19
20
VCC
Q13
Q12
GND
Q11
GND
Q10
VCC
Q9
Q8
Q7
D8
VCC
4666 drw02
TQFP (PN80-1, order code: PF)
TOP VIEW
NOTE:
1. DNC = Do Not Connect.
2
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
DuringAsynchronousoperationonlytheRDinputisusedtoreaddatafromthe
FIFO.Datais readonarisingedgeofRD,theRENinputshouldbetiedtoits
activestate,LOW.WhenAsynchronousoperationisselectedontheoutputport
theFIFOmustbeconfiguredforStandardIDTmode,andtheOEinputused
toprovidethree-statecontroloftheoutputs,Qn.
ThefrequenciesofboththeRCLKandtheWCLKsignalsmayvaryfrom0
tofMAXwithcompleteindependence.Therearenorestrictionsonthefrequency
oftheoneclockinputwithrespecttotheother.
Therearetwopossibletimingmodesofoperationwiththesedevices:IDT
Standard mode and First Word Fall Through (FWFT) mode.
InIDTStandardmode,thefirstwordwrittentoanemptyFIFOwillnotappear
onthedataoutputlinesunlessaspecificreadoperationisperformed.Aread
operation,whichconsistsofactivatingRENandenablingarisingRCLKedge,
willshiftthewordfrominternalmemorytothedataoutputlines.
DESCRIPTION(CONTINUED)
EachFIFOhas a data inputport(Dn)anda data outputport(Qn), bothof
whichcanassumeeitheran18-bitora9-bitwidthasdeterminedbythestate
ofexternalcontrolpinsInputWidth(IW)andOutputWidth(OW)duringtheMaster
Resetcycle.
TheinputportcanbeselectedaseitheraSynchronous(clocked)interface,
or Asynchronous interface. During Synchronous operation the input port is
controlledbyaWriteClock(WCLK)inputandaWriteEnable(WEN)input. Data
presentontheDndatainputs is writtenintotheFIFOoneveryrisingedgeof
WCLKwhenWENisasserted.DuringAsynchronousoperationonlytheWR
inputisusedtowritedataintotheFIFO.DataiswrittenonarisingedgeofWR,
theWENinputshouldbetiedtoitsactivestate,(LOW).
TheoutputportcanbeselectedaseitheraSynchronous(clocked)interface,
orAsynchronousinterface.DuringSynchronousoperationtheoutputportis
controlledbyaReadClock(RCLK)inputandReadEnable(REN)input. Data
is read from the FIFO on every rising edge of RCLK when REN is asserted.
InFWFTmode,thefirstwordwrittentoanemptyFIFOisclockeddirectly
tothedataoutputlinesafterthreetransitionsoftheRCLKsignal.ARENdoes
PINCONFIGURATIONS(CONTINUED)
A1 BALL PAD CORNER
A
PRS
MRS
SEN
LD
PAF
BE
ASYR
REN
RCLK
OE
WCLK
WEN
FSEL0
PFM
RM
EF/OR
RT
B
C
D
E
HF
PAE
FWFT/SI OW
FSEL1
IP
ASYW
FF/IR
VCC
VCC
VCC
VCC
VCC
D17
D16
IW
VCC
GND
GND
GND
GND
GND
GND
GND
GND
V
CC
CC
Q16
Q14
Q17
Q15
D15
VCC
V
F
Q12
Q10
Q8
D14
D12
D9
V
CC
GND
GND
GND
GND
GND
GND
GND
GND
V
CC
Q13
Q11
Q9
D13
D11
D8
G
V
CC
VCC
H
J
D10
D2
VCC
VCC
VCC
VCC
Q1
Q2
TCK
D6
D7
D0
TMS
TDO
Q4
Q7
K
D5
D4
D3
D1
TDI
Q0
Q3
Q5
Q6
TRST
1
2
3
4
5
6
7
8
9
10
4666 drw02b
BGA: 1mm pitch, 11mm x 11mm (BC100-1, order code: BC)
TOP VIEW
3
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
Forserialprogramming,SENtogetherwithLDoneachrisingedgeofWCLK,
are used to load the offset registers via the Serial Input (SI). For parallel
programming,WENtogetherwithLDoneachrisingedgeofWCLK,areused
toloadthe offsetregisters via Dn.REN togetherwithLD oneachrisingedge
ofRCLKcanbeusedtoreadtheoffsetsinparallelfromQnregardlessofwhether
serialorparalleloffsetloadinghasbeenselected.
During Master Reset (MRS) the following events occur: the read and
write pointers are set to the first location of the FIFO. The FWFT pin selects
IDT Standard mode or FWFT mode.
The Partial Reset (PRS) also sets the read and write pointers to the first
location of the memory. However, the timing mode, programmable flag
programming method, and default or programmed offset settings existing
beforePartialResetremainunchanged.Theflagsareupdatedaccordingtothe
timingmodeandoffsets ineffect.PRS is usefulforresettingadeviceinmid-
operation,whenreprogrammingprogrammableflagswouldbeundesirable.
ItisalsopossibletoselectthetimingmodeofthePAE(ProgrammableAlmost-
Empty flag) and PAF (Programmable Almost-Full flag) outputs. The timing
modescanbesettobeeitherasynchronousorsynchronousforthePAEand
PAFflags.
DESCRIPTION(CONTINUED)
not have to be asserted for accessing the first word. However, subsequent
words writtentotheFIFOdorequireaLOWonREN foraccess.Thestateof
theFWFT/SIinputduringMasterResetdeterminesthetimingmodeinuse.
ForapplicationsrequiringmoredatastoragecapacitythanasingleFIFO
canprovide,theFWFTtimingmodepermitsdepthexpansionbychainingFIFOs
inseries(i.e.thedataoutputsofoneFIFOareconnectedtothecorresponding
data inputs ofthe next). Noexternallogicis required.
These FIFOs have five flagpins, EF/OR (EmptyFlagorOutputReady),
FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable
Almost-Emptyflag)andPAF (Programmable Almost-Fullflag). The EF and
FFfunctionsareselectedinIDTStandardmode.TheIRandORfunctionsare
selected in FWFT mode. HF, PAE and PAF are always available for use,
irrespectiveoftimingmode.
PAEandPAFcanbeprogrammedindependentlytoswitchatanypointin
memory.Programmableoffsetsdeterminetheflagswitchingthresholdandcan
beloadedbytwomethods:parallelorserial.Eightdefaultoffsetsettingsarealso
provided,sothatPAEcanbesettoswitchatapredefinednumberoflocations
from the empty boundary and the PAF threshold can also be set at similar
predefinedvaluesfromthefullboundary.Thedefaultoffsetvaluesaresetduring
MasterResetbythe state ofthe FSEL0, FSEL1, and LD pins.
Ifasynchronous PAE/PAFconfigurationisselected,thePAEisasserted
LOWontheLOW-to-HIGHtransitionofRCLK.PAEisresettoHIGHontheLOW-
PARTIAL RESET (PRS) MASTER RESET (MRS)
WRITE CLOCK (WCLK/WR*)
READ CLOCK (RCLK/RD*)
WRITE ENABLE (WEN)
LOAD (LD)
READ ENABLE (REN)
IDT
OUTPUT ENABLE (OE)
72V223
72V233
72V243
72V253
72V263
72V273
72V283
72V293
(x9 or x18) DATA IN (D0 - Dn)
(x9 or x18) DATA OUT (Q0 - Qn)
SERIAL CLOCK (SCLK)
RETRANSMIT (RT)
EMPTY FLAG/OUTPUT READY (EF/OR)
SERIAL ENABLE(SEN)
PROGRAMMABLE ALMOST-EMPTY (PAE)
HALF-FULL FLAG (HF)
FIRST WORD FALL THROUGH/
SERIAL INPUT (FWFT/SI)
BIG-ENDIAN/LITTLE-ENDIAN (BE)
INTERSPERSED/
NON-INTERSPERSED PARITY (IP)
FULL FLAG/INPUT READY (FF/IR)
PROGRAMMABLE ALMOST-FULL (PAF)
4666 drw03
OUTPUT WIDTH (OW)
INPUT WIDTH (IW)
BUS-
MATCHING
(BM)
Figure 1. Single Device Configuration Signal Flow Diagram
4
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
outoftheFIFOfirst,followedbytheleastsignificantbyte.IfLittle-Endianformat
isselected,thentheleastsignificantbyteofthelongwordwrittenintotheFIFO
willbereadoutfirst,followedbythemostsignificantbyte.Themodedesiredis
configuredduringmasterresetbythestateoftheBig-Endian(BE)pin.
TheInterspersed/Non-InterspersedParity(IP)bitfunctionallowstheuser
to select the parity bit in the word loaded into the parallel port (D0-Dn) when
programmingtheflagoffsets.IfInterspersedParitymodeisselected,thenthe
FIFOwillassumethattheparitybitislocatedinbitpositionD8duringtheparallel
programmingoftheflagoffsets.IfNon-InterspersedParitymodeisselected,then
D8isassumedtobeavalidbitandD16andD17areignored.IPmodeisselected
duringMasterResetbythestateoftheIPinputpin.Thismodeisrelevantonly
whentheinputwidthis settox18mode.InterspersedParitycontrolonlyhas
aneffectduringparallelprogrammingoftheoffsetregisters.Itdoesnoteffectthe
data writtentoandreadfromthe FIFO.
AJTAGtestportisprovided,heretheFIFOhasfullyfunctionalBoundary
Scan feature, compliant with IEEE 1149.1 Standard Test Access Port and
BoundaryScanArchitecture.
If,atanytime,theFIFOisnotactivelyperforminganoperation,thechipwill
automaticallypowerdown.Onceinthepowerdownstate,thestandbysupply
currentconsumptionisminimized.Initiatinganyoperation(byactivatingcontrol
inputs)willimmediatelytakethedeviceoutofthepowerdownstate.
The IDT72V223/72V233/72V243/72V253/72V263/72V273/72V283/
72V293arefabricatedusingIDT’shighspeedsubmicronCMOStechnology.
to-HIGHtransitionofWCLK.Similarly,thePAFisassertedLOWontheLOW-
to-HIGHtransitionofWCLKandPAF is resettoHIGHonthe LOW-to-HIGH
transitionofRCLK.
If synchronous PAE/PAF configuration is selected , the PAE is asserted
andupdatedonthe risingedge ofRCLKonlyandnotWCLK. Similarly, PAF
isassertedandupdatedontherisingedgeofWCLKonlyandnotRCLK.The
modedesiredisconfiguredduringmasterresetbythestateoftheProgrammable
Flag Mode (PFM) pin.
The Retransmit function allows data to be reread from the FIFO more
than once. A LOW on the RT input during a rising RCLK edge initiates a
retransmitoperationbysettingthereadpointertothefirstlocationofthememory
array. A zero-latency retransmit timing mode can be selected using the
RetransmittimingModepin(RM).DuringMasterReset,aLOWonRMwillselect
zero-latencyretransmit.AHIGHonRMduringMasterResetwillselectnormal
latency.
If zero-latency retransmit operation is selected the first data word to be
retransmitted will be placed on the output register with respect to the same
RCLK edge that initiated the retransmit based on RT being LOW.
RefertoFigure11and12forRetransmitTimingwithnormallatency.Refer
to Figure 13 and 14 for Retransmit Timing with zero-latency.
ABig-Endian/Little-Endiandatawordformatis provided.This functionis
useful when data is written into the FIFO in long word format (x18) and read
outoftheFIFOinsmallword(x9)format.IfBig-Endianmodeisselected,then
themostsignificantbyte(word)ofthelongwordwrittenintotheFIFOwillberead
TABLE 1 — BUS-MATCHING CONFIGURATION MODES
IW
OW
Write Port Width
Read Port Width
L
L
L
H
L
x18
x18
x9
x18
x9
H
H
x18
x9
H
x9
5
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
PIN DESCRIPTION (TQFP & BGA PACKAGES)
Symbol
Name
I/O
Description
(1)
BE
*Big-Endian/
Little-Endian
I
DuringMasterReset, a LOWonBE willselectBig-Endianoperation. AHIGHonBE duringMasterResetwill
selectLittle-Endianformat.
D0–D17 DataInputs
I
Data inputs for a 18- or 9-bit bus. When in 18-bit mode, D0–D17 are used. When in 9-bit mode, D0–D8 are used
andthe unusedinputs, D9–D17, shouldbe tiedLOW.
EF/OR EmptyFlag/
O
O
IntheIDTStandardmode, the EF functionis selected.EF indicates whetherornotthe FIFOmemoryis empty.In
FWFTmode,theOR functionisselected.ORindicateswhetherornotthereisvaliddataavailableattheoutputs.
Inthe IDTStandardmode, the FF functionis selected. FF indicates whetherornotthe FIFOmemoryis full. Inthe
FWFTmode,theIRfunctionisselected. IRindicateswhetherornotthereisspaceavailableforwritingtotheFIFO
memory.
OutputReady
FF/IR
Full Flag/
Input Ready
FSEL0(1) FlagSelectBit0
FSEL1(1) FlagSelectBit1
I
I
I
DuringMasterReset,thisinputalongwithFSEL1andtheLDpin,willselectthedefaultoffsetvaluesforthe
programmableflagsPAEandPAF.Thereareuptoeightpossiblesettings available.
DuringMasterReset,thisinputalongwithFSEL0andtheLDpinwillselectthedefaultoffsetvaluesforthe
programmableflags PAEandPAF.Thereareuptoeightpossiblesettings available.
DuringMasterReset,selectsFirstWordFallThroughorIDTStandardmode.AfterMasterReset,thispinfunctions
asaserialinputforloadingoffsetregisters.
FWFT/SI FirstWordFall
Through/Serial In
HF
IP(1)
Half-FullFlag
O
I
HFindicates whethertheFIFOmemoryis moreorless thanhalf-full.
InterspersedParity
DuringMasterReset,aLOWonIPwillselectNon-InterspersedParitymode.AHIGHwillselectInterspersed
Paritymode. InterspersedParitycontrolonlyhasaneffectduringparallelprogrammingoftheoffsetregisters.It
doesnoteffectthedatawrittentoandreadfromtheFIFO.
(1)
IW
InputWidth
Load
I
I
This pinselects the bus widthofthe write port. DuringMasterReset, whenIWis LOW, the write portwillbe
configured with a x18 bus width. If IW is HIGH, the write port will be a x9 bus width.
LD
Thisisadualpurposepin.DuringMasterReset,thestateoftheLDinput,alongwithFSEL0andFSEL1,determines
oneofeightdefaultoffsetvaluesforthePAEandPAFflags,alongwiththemethodbywhichtheseoffsetregisterscan
beprogrammed,parallelorserial(seeTable2).AfterMasterReset,thispinenableswritingtoandreadingfromthe
offsetregisters.
MRS
OE
MasterReset
I
MRSinitializesthereadandwritepointerstozeroandsetstheoutputregistertoallzeroes.DuringMasterReset,the
FIFOisconfiguredforeitherFWFTorIDTStandardmode,Bus-Matchingconfigurations,oneofeightprogrammable
flagdefaultsettings,serialorparallelprogrammingoftheoffsetsettings,Big-Endian/Little-Endianformat,zerolatency
timingmode,interspersedparity,andsynchronousversusasynchronousprogrammableflagtimingmodes.
OutputEnable
OutputWidth
I
I
OEcontrolstheoutputimpedanceofQn.
This pinselects the bus widthofthe readport. DuringMasterReset, whenOWis LOW, the readportwillbeconfig-
ured with a x18 bus width. If OW is HIGH, the read port will be a x9 bus width.
(1)
OW
PAE
PAF
Programmable
Almost-EmptyFlag
O
O
I
PAEgoesLOWifthenumberofwordsintheFIFOmemoryislessthanoffsetn,whichisstoredintheEmptyOffset
register. PAE goes HIGHifthe numberofwords inthe FIFOmemoryis greaterthanorequaltooffsetn.
PAF goes HIGHifthenumberoffreelocations intheFIFOmemoryis morethanoffsetm,whichis storedinthe
FullOffsetregister.PAFgoes LOWifthenumberoffreelocations intheFIFOmemoryis less thanorequaltom.
DuringMasterReset,aLOWonPFMwillselectAsynchronous Programmableflagtimingmode.AHIGHonPFM
willselectSynchronousProgrammableflagtimingmode.
Programmable
Almost-FullFlag
(1)
PFM
Programmable
Flag Mode
PRS
PartialReset
I
PRSinitializesthereadandwritepointerstozeroandsetstheoutputregistertoallzeroes.DuringPartialReset,
theexistingmode(IDTorFWFT),programmingmethod(serialorparallel),andprogrammableflagsettings are
allretained.
Q0–Q17 DataOutputs
O
Data outputs for a 18- or 9-bit bus. When in 18-bit mode, Q0–Q17 are used and when in 9-bit mode, Q0–Q8 are
used,andtheunusedoutputs,Q9-Q17shouldnotbeconnected.Outputsarenot5Vtolerantregardlessofthe
stateofOE.
REN
ReadEnable
I
I
RENenables RCLKforreadingdatafromtheFIFOmemoryandoffsetregisters.
RCLK/ ReadClock/
RD
If Synchronous operation of the read port has been selected, when enabled byREN, the rising edge of RCLK
readsdatafromtheFIFOmemoryandoffsetsfromtheprogrammableregisters.IfLDisLOW,thevaluesloaded
intothe offsetregisters is outputona risingedge ofRCLK. IfAsynchronous operationofthe readporthas been
selected, a rising edge on RD reads data from the FIFO in an Asynchronous manner. REN should be tied LOW.
Asynchronous operationofthe RCLK/RDinputis onlyavailable inthe BGApackage.
ReadStrobe
NOTE:
1. Inputs should not change state after Master Reset.
6
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
PIN DESCRIPTION-CONTINUED (TQFP & BGA PACKAGES)
Symbol
Name
I/O
Description
(1)
RM
RetransmitTiming
Mode
I
DuringMasterReset,aLOWonRMwillselectzerolatencyRetransmittimingMode.AHIGHonRMwillselect
normallatencymode.
RT
Retransmit
I
RT assertedonthe risingedge ofRCLKinitializes the READpointertozero, sets the EFflagtoLOW(OR toHIGH
inFWFTmode)anddoesnotdisturbthewritepointer,programmingmethod,existingtimingmodeorprogrammable
flagsettings.RTisusefultorereaddatafromthefirstphysicallocationoftheFIFO.
SEN
WCLK/
WR
SerialEnable
I
I
SENenablesserialloadingofprogrammableflagoffsets.
WriteClock/
WriteStrobe
If Synchronous operation of the write port has been selected, when enabled byWEN, the risingedge ofWCLK
writesdataintotheFIFO.IfAsynchronousoperationofthewriteporthasbeenselected,WRwritesdataintothe
FIFOonarisingedgeinanAsynchronousmanner,(WENshouldbetiedtoitsactivestate).Asynchronousoperation
oftheWCLK/WRinputisonlyavailableintheBGApackage.
WEN
VCC
WriteEnable
I
I
WENenablesWCLKforwritingdataintotheFIFOmemoryandoffsetregisters.
These are VCC supply inputs and must be connected to the 3.3V supply rail.
+3.3VSupply
NOTE:
1. Inputs should not change state after Master Reset.
PIN DESCRIPTION (BGA PACKAGE ONLY)
Symbol
Name
I/O
Description
(1)
ASYR
Asynchronous
ReadPort
I
AHIGHonthis inputduringMasterResetwillselectSynchronous readoperationfortheoutputport.ALOW
willselectAsynchronousoperation.IfAsynchronousisselectedtheFIFOmustoperateinIDTStandardmode.
(1)
ASYW
Asynchronous
WritePort
I
I
AHIGHonthis inputduringMasterResetwillselectSynchronous writeoperationfortheinputport.ALOW
willselectAsynchronousoperation.
(2)
TCK
JTAGClock
ClockinputforJTAGfunction.OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.Testoperationsofthe
devicearesynchronoustoTCK.DatafromTMSandTDIaresampledontherisingedgeofTCKandoutputschange
onthefallingedgeofTCK.IftheJTAGfunctionis notusedthis signalneeds tobetiedtoGND.
(2)
TDI
JTAGTestData
Input
I
OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.DuringtheJTAGboundaryscanoperation,testdata
seriallyloadedviatheTDIontherisingedgeofTCKtoeithertheInstructionRegister,IDRegisterandBypassRegister.
Aninternalpull-upresistorforcesTDIHIGHifleftunconnected.
(2)
TDO
JTAGTestData
Output
O
OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.DuringtheJTAGboundaryscanoperation,testdata
seriallyloadedoutputviatheTDOonthefallingedgeofTCKfromeithertheInstructionRegister,IDRegisterandBypass
Register.This outputis highimpedanceexceptwhenshifting,whileinSHIFT-DRandSHIFT-IRcontrollerstates.
TMS(2)
JTAGModeSelect
JTAGReset
I
I
TMSisaserialinputpin.OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.TMSdirectsthedevicethrough
itsTAPcontrollerstates.Aninternalpull-upresistorforcesTMSHIGHifleftunconnected.
(2)
TRST
TRSTisanasynchronousresetpinfortheJTAGcontroller.TheJTAGTAPcontrollerdoesnotautomaticallyreset
upon power-up, thus it must be reset by either this signal or by setting TMS= HIGH for five TCK cycles. If the TAP
controllerisnotproperlyresetthentheFIFOoutputswillalwaysbeinhigh-impedance.IftheJTAGfunctionisused
butthe userdoes notwanttouse TRST, thenTRST canbe tiedwithMRS toensure properFIFOoperation. Ifthe
JTAGfunctionisnotusedthenthissignalneedstobetiedtoGND.
NOTES:
1. Inputs should not change state after Master Reset.
2. These pins are for the JTAG port. Please refer to pages 41-44 and Figures 31-33.
7
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
Rating
Com'l & Ind'l
Unit
(2)
Symbol
Parameter
Supply Voltage (Com'l & Ind'l)
Min.
3.15
0
Typ. Max. Unit
VTERM
TerminalVoltage
with respect to GND
–0.5to+4.5
V
(1)
VCC
3.3
0
3.45
0
V
V
TSTG
IOUT
StorageTemperature
–55to+125
–50 to +50
° C
GND Supply Voltage (Com'l & Ind'l)
(2)
VIH
Input High Voltage (Com'l & Ind'l)
Input Low Voltage (Com'l & Ind'l)
OperatingTemperatureCommercial
OperatingTemperatureIndustrial
2.0
—
0
—
—
—
—
5.5
0.8
+70
+85
V
DC Output Current
mA
(3)
VIL
TA
V
NOTE:
° C
° C
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
TA
-40
NOTES:
1. VCC=3.3V ± 0.15V, JEDEC JESD8-A compliant.
2. Outputs are not 5V tolerant.
2. VCC terminal only.
3. 1.5V undershoots are allowed for 10ns once per cycle.
DCELECTRICALCHARACTERISTICS
(Commercial: VCC = 3.3V ± 0.15V, TA = 0°C to +70°C; Industrial: VCC = 3.3V ± 0.15V, TA = -40°C to +85°C; JEDEC JESD8-A compliant)
IDT72V223L
IDT72V233L
IDT72V243L
IDT72V253L
IDT72V263L
IDT72V273L
IDT72V283L
IDT72V293L
Commercial and Industrial(1)
tCLK = 6, 7.5, 10, 15 ns
Symbol
Parameter
Min.
Max.
Unit
(2)
ILI
InputLeakageCurrent
OutputLeakageCurrent
–1
–10
2.4
—
—
—
—
1
µA
µA
V
(3)
ILO
10
—
0.4
30
35
15
VOH
Output Logic “1” Voltage, IOH = –2 mA
Output Logic “0” Voltage, IOL = 8 mA
Active Power Supply Current (x9 Input to x9 Output)
Active Power Supply Current (x18 Input to x18 Output)
StandbyCurrent
VOL
V
ICC1(4,5,6)
ICC1(4,5,6)
ICC2(4,7)
mA
mA
mA
NOTES:
1. Industrial temperature range product for the 10ns speed grade is available as a standard device.
2. Measurements with 0.4 ≤ VIN ≤ VCC.
3. OE ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
4. Tested with outputs open (IOUT = 0).
5. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.
6. For x 18 bus widths, typical ICC1 = 5 + fS + 0.002*CL*fS (in mA);
for x 9 bus widths, typical ICC1 = 5 + 0.775*fS + 0.002*CL*fS (in mA).
These equations are valid under the following conditions:
VCC = 3.3V, tA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2, CL = capacitive load (in pF).
7. All Inputs = VCC - 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
CAPACITANCE(TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Input
Conditions
Max.
Unit
(2)
CIN
VIN = 0V
10
pF
Capacitance
Output
(1,2)
COUT
VOUT = 0V
10
pF
Capacitance
NOTES:
1. With output deselected, (OE ≥ VIH).
2. Characterized values, not currently tested.
8
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
ACELECTRICALCHARACTERISTICS(1)
(Commercial: VCC = 3.3V ± 0.15V, TA = 0°C to +70°C; Industrial: VCC = 3.3V ± 0.15V, TA = -40°C to +85°C; JEDEC JESD8-A compliant)
Commercial
BGA & TQFP
Commercial
BGA & TQFP
Com’l & Ind’l(2)
TQFP Only
Commercial
TQFP Only
IDT72V223L6
IDT72V233L6
IDT72V243L6
IDT72V253L6
IDT72V263L6
IDT72V273L6
IDT72V283L6
IDT72V293L6
IDT72V223L7-5
IDT72V233L7-5
IDT72V243L7-5
IDT72V253L7-5
IDT72V263L7-5
IDT72V273L7-5
IDT72V283L7-5
IDT72V293L7-5
IDT72V263L10
IDT72V273L10
IDT72V283L10
IDT72V293L10
IDT72V263L15
IDT72V273L15
IDT72V283L15
IDT72V293L15
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
fS
Clock Cycle Frequency
DataAccessTime(5)
Clock Cycle Time
Clock High Time
Clock Low Time
—
166
—
133.3
—
100
—
66.7
MHz
(5)
(5)
tA
1
6
4
1(5)
7.5
3.5
3.5
2.5
0.5
2.5
0.5
3.5
0.5
10
5
—
—
—
—
—
—
—
—
—
—
—
—
15
—
—
6
1
6.5
—
—
—
—
—
—
—
—
—
—
—
—
15
1
10
—
—
—
—
—
—
—
—
—
—
—
—
15
—
—
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCLK
tCLKH
tCLKL
tDS
—
—
—
—
—
—
—
—
—
—
—
—
15
—
—
4
10
4.5
4.5
3.5
0.5
3.5
0.5
3.5
0.5
10
15
6
2.7
2.7
2
6
DataSetupTime
4
tDH
DataHoldTime
0.5
2
1
tENS
EnableSetupTime
EnableHoldTime
LoadSetupTime
4
tENH
tLDS
0.5
3
1
4
tLDH
LoadHoldTime
0.5
10
15
10
—
3
1
tRS
ResetPulseWidth(3)
ResetSetupTime
ResetRecoveryTime
15
15
15
—
4
tRSS
15
15
tRSR
tRSF
tRTS
10
10
ResettoFlagandOutputTime
RetransmitSetupTime
—
3.5
0
—
3.5
0
—
—
6
(4)
tOLZ
tOE
OutputEnabletoOutputinLowZ
OutputEnabletoOutputValid(5)
0
0
(5)
(5)
1
1(5)
1(5)
—
—
—
—
—
—
—
5
1
1
(4,5)
(5)
(5)
tOHZ
tWFF
tREF
tPAFA
tPAFS
tPAEA
tPAES
tHF
OutputEnabletoOutputinHighZ
1
4
6
1
6
1
8
Write Clock to FF or IR
Read Clock to EF or OR
—
—
—
—
—
—
—
4
4
5
—
—
—
—
—
—
—
7
6.5
6.5
16
—
—
—
—
—
—
—
9
10
10
20
10
20
10
20
—
—
4
5
ClocktoAsynchronousProgrammableAlmost-FullFlag
WriteClocktoSynchronousProgrammableAlmost-FullFlag
ClocktoAsynchronousProgrammableAlmost-EmptyFlag
ReadClocktoSynchronousProgrammableAlmost-EmptyFlag
Clock to HF
10
4
12.5
5
6.5
16
10
4
12.5
5
6.5
16
10
—
—
12.5
—
—
tSKEW1
tSKEW2
NOTES:
Skew time between RCLK and WCLK for EF/OR and FF/IR
Skew time between RCLK and WCLK for PAE and PAF
—
—
5
7
10
14
1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.
2. Industrial temperature range product for the 10ns is available as a standard device. All other speed grades are available by special order.
3. Pulse widths less than minimum values are not allowed.
4. Values guaranteed by design, not currently tested.
5. TQFP package only: for speed grades 7.5ns, 10ns and 15ns the minimum for tA, tOE, and tOHZ is 2ns.
6. The IDT72V223/72V233/72V243/72V253 are only available in 6ns and 7.5ns speed grades.
9
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
ACELECTRICALCHARACTERISTICS(1)—ASYNCHRONOUSTIMING
(Commercial: VCC = 3.3V ± 0.15V, TA = 0°C to +70°C;Industrial: VCC = 3.3V ± 0.15V, TA = -40°C to +85°C; JEDEC JESD8-A compliant)
Commercial
IDT72V223L6
IDT72V233L6
IDT72V243L6
IDT72V253L6
IDT72V263L6
IDT72V273L6
IDT72V283L6
IDT72V293L6
IDT72V223L7-5
IDT72V233L7-5
IDT72V243L7-5
IDT72V253L7-5
IDT72V263L7-5
IDT72V273L7-5
IDT72V283L7-5
IDT72V293L7-5
Symbol
Parameter
Cycle Frequency (Asynchronous mode)
DataAccessTime
Min.
—
0.6
10
Max.
Min.
—
0.6
12
Max.
83
Unit
MHz
ns
(4)
fA
100
8
(4)
tAA
10
(4)
tCYC
Cycle Time
—
—
—
—
8
—
—
—
—
10
ns
(4)
tCYH
Cycle HIGH Time
4.5
4.5
8
5
ns
(4)
tCYL
Cycle LOW Time
5
ns
(4)
tRPE
Read Pulse after EF HIGH
Clock to Asynchronous FF
Clock to Asynchronous EF
ClocktoAsynchronousProgrammableAlmost-FullFlag
10
ns
(4)
tFFA
—
—
—
—
—
—
—
—
ns
(4)
tEFA
8
10
ns
(4)
tPAFA
8
10
ns
(4)
tPAEA
ClocktoAsynchronousProgrammableAlmost-EmptyFlag
8
10
ns
NOTES:
1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.
2. Pulse widths less than minimum values are not allowed.
3. Values guaranteed by design, not currently tested.
4. Parameters apply to the BGA package only.
10
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
ACTESTCONDITIONS
InputPulseLevels
ACTESTLOADS-6ns,7.5nsSpeedGrade
GND to 3.0V
3ns(1)
1.5V
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
1.5V
50
Ω
1.5V
Output Load for tCLK = 10ns, 15 ns
OutputLoadfortCLK =6ns,7.5ns
See Figure 2a
See Figure 2b & 2c
Z0 = 50Ω
I/O
4666 drw04a
NOTE:
Figure 2b. AC Test Load
1. For 166Mhz and 133MHz operation input rise/fall times are 1.5ns.
ACTESTLOADS-10ns,15nsSpeedGrades
6
5
4
3
2
1
3.3V
330Ω
D.U.T.
20 30 50 80 100
Capacitance (pF)
200
30pF*
510Ω
4666 drw04b
4666 drw04
Figure 2c. Lumped Capacitive Load, Typical Derating
Figure 2a. Output Load
* Includes jig and scope capacitances.
OUTPUT ENABLE & DISABLE TIMING
Output
Enable
Output
Disable
VIH
OE
VIL
tOE &
tOLZ
tOHZ
V
2
CC
Output
Normally
LOW
V
2
CC
100mV
100mV
100mV
V
OL
V
OH
Output
Normally
HIGH
VCC
100mV
VCC
2
2
4666 drw04c
NOTE:
1. REN is HIGH.
11
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
writesfortheIDT72V293.Theoffset“m”isthefulloffsetvalue.Thedefaultsetting
forthesevaluesarestatedinthefootnoteofTable2.Thisparameterisalsouser
programmable.SeesectiononProgrammableFlagOffsetLoading.
WhentheFIFOisfull,theFullFlag(FF)willgoLOW,inhibitingfurtherwrite
operations.Ifnoreadsareperformedafterareset,FFwillgoLOWafterDwrites
totheFIFO.Ifthex18Inputorx18OutputbusWidthisselected,D=512writes
for the IDT72V223, 1,024 writes for the IDT72V233, 2,048 writes for the
IDT72V243,4,096writesfortheIDT72V253,8,192writesfortheIDT72V263,
16,384writesfortheIDT72V273,32,768writesfortheIDT72V283and65,536
writesfortheIDT72V293.Ifbothx9Inputandx9OutputbusWidthsareselected,
D = 1024 writes for the IDT72V223, 2,048 writes for the IDT72V233, 4,096
writes fortheIDT72V243,8,192writes fortheIDT72V253,16,384writes for
the IDT72V263, 32,768 writes for the IDT72V273, 65,536 writes for the
IDT72V283 and 131,072 writes for the IDT72V293, respectively.
If the FIFO is full, the first read operation will cause FF to go HIGH.
SubsequentreadoperationswillcausePAFandHFtogoHIGHattheconditions
describedinTable3.Iffurtherreadoperationsoccur,withoutwriteoperations,
PAE will go LOW when there are n words in the FIFO, where n is the empty
offsetvalue.ContinuingreadoperationswillcausetheFIFOtobecomeempty.
WhenthelastwordhasbeenreadfromtheFIFO,theEFwillgoLOWinhibiting
further read operations. REN is ignored when the FIFO is empty.
WhenconfiguredinIDTStandardmode,theEFandFFoutputsaredouble
register-bufferedoutputs.
FUNCTIONALDESCRIPTION
TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH
(FWFT) MODE
The IDT72V223/72V233/72V243/72V253/72V263/72V273/72V283/
72V293supporttwodifferenttimingmodesofoperation:IDTStandardmode
orFirstWordFallThrough(FWFT)mode.The selectionofwhichmode will
operateisdeterminedduringMasterReset,bythestateoftheFWFT/SIinput.
If,atthetimeofMasterReset,FWFT/SIisLOW,thenIDTStandardmode
willbe selected. This mode uses the EmptyFlag(EF)toindicate whetheror
notthereareanywordspresentintheFIFO.ItalsousestheFullFlagfunction
(FF)toindicatewhetherornottheFIFOhasanyfreespaceforwriting.InIDT
Standardmode, everywordreadfromthe FIFO, includingthe first, mustbe
requested using the Read Enable (REN) and RCLK.
If,atthetimeofMasterReset,FWFT/SIisHIGH,thenFWFTmodewillbe
selected.ThismodeusesOutputReady(OR)toindicatewhetherornotthere
isvaliddataatthedataoutputs(Qn).ItalsousesInputReady(IR)toindicate
whether or not the FIFO has any free space for writing. In the FWFT mode,
thefirstwordwrittentoanemptyFIFOgoesdirectlytoQnafterthreeRCLKrising
edges,REN=LOWisnotnecessary.Subsequentwordsmustbeaccessed
using the Read Enable (REN) and RCLK.
Varioussignals,bothinputandoutputsignalsoperatedifferentlydepending
onwhichtimingmodeisineffect.
Relevanttimingdiagrams forIDTStandardmodecanbefoundinFigure
7, 8 and 11.
IDT STANDARD MODE
In this mode, the status flags, FF, PAF, HF, PAE, and EF operate in the
manneroutlinedinTable3.TowritedataintototheFIFO,WriteEnable(WEN)
mustbeLOW.DatapresentedtotheDATAINlineswillbeclockedintotheFIFO
on subsequent transitions of the Write Clock (WCLK). After the first write is
performed,theEmptyFlag(EF)willgoHIGH.Subsequentwriteswillcontinue
tofilluptheFIFO.TheProgrammableAlmost-Emptyflag(PAE)willgoHIGH
aftern + 1wordshavebeenloadedintotheFIFO,wherenistheemptyoffset
value.ThedefaultsettingforthesevaluesarestatedinthefootnoteofTable2.
Thisparameterisalsouserprogrammable.SeesectiononProgrammableFlag
OffsetLoading.
If one continued to write data into the FIFO, and we assumed no read
operationsweretakingplace,theHalf-Fullflag(HF)wouldtoggletoLOWonce
(D/2+1)wordswerewrittenintotheFIFO.Ifx18Inputorx18OutputbusWidth
is selected, (D/2 + 1) = the 257th word for the IDT72V223, 513rd word for
IDT72V233,1,025thwordfortheIDT72V243,2,049thwordfortheIDT72V253,
4,097thwordfortheIDT72V263,8,193thwordforIDT72V273,16,385thword
fortheIDT72V283and32,769thwordfortheIDT72V293.Ifbothx9Inputand
x9 Output bus Widths are selected, (D/2 + 1) = the 513rd word for the
IDT72V223,1,025thwordforIDT72V233,2,049thwordfortheIDT72V243,
4,097thwordfortheIDT72V253,8,193rdwordfortheIDT72V263,16,385th
word for IDT72V273, 32,769th word for the IDT72V283 and 65,537th word
for the IDT72V293. Continuing to write data into the FIFO will cause the
Programmable Almost-Full flag (PAF) to go LOW. Again, if no reads are
performed,thePAFwillgoLOWafter(D-m)writestotheFIFO.Ifx18Inputor
x18OutputbusWidthisselected,(D-m) = (512-m)writesfortheIDT72V223,
(1,024-m)writesfortheIDT72V233,(2,048-m)writesfortheIDT72V243and
(4,096-m) writes for the IDT72V253, (8,192-m) writes for the IDT72V263,
(16,384-m)writes forthe IDT72V273, (32,768-m)writes forthe IDT72V283
and(65,536-m)writesfortheIDT72V293.Ifbothx9Inputandx9Outputbus
Widthsareselected,(D-m) = (1,024-m)writesfortheIDT72V223,(2,048-m)
writes for the IDT72V233, (4,096-m) writes for the IDT72V243, (8,192-m)
writesfortheIDT72V253,(16,384-m)writesfortheIDT72V263,(32,768-m)
writesfortheIDT72V273,(65,536-m)writesfortheIDT72V283and(131,072-m)
FIRST WORD FALL THROUGH MODE (FWFT)
In this mode, the status flags, IR, PAF, HF, PAE, and OR operate in the
manneroutlinedinTable4.TowritedataintotheFIFO,WENmustbeLOW.
DatapresentedtotheDATAINlineswillbeclockedintotheFIFOonsubsequent
transitionsofWCLK.Afterthefirstwriteisperformed,theOutputReady(OR)
flagwillgoLOW.SubsequentwriteswillcontinuetofilluptheFIFO.PAEwillgo
HIGHaftern+2words havebeenloadedintotheFIFO,wherenis theempty
offsetvalue.ThedefaultsettingforthesevaluesarestatedinthefootnoteofTable
2.Thisparameterisalsouserprogrammable.SeesectiononProgrammable
FlagOffsetLoading.
If one continued to write data into the FIFO, and we assumed no read
operationsweretakingplace,theHFwouldtoggletoLOWoncethe(D/2+2)
wordswerewrittenintotheFIFO.Ifx18Inputorx18OutputbusWidthisselected,
(D/2 + 2) = the 258th word for the IDT72V223, 514th word for IDT72V233,
1,026th word for the IDT72V243, 2,050th word for the IDT72V253, 4,098th
wordfortheIDT72V263,8,194thwordforIDT72V273,16,386thwordforthe
IDT72V283 and 32,770th word for the IDT72V293. If both x9 Input and x9
OutputbusWidthsareselected,(D/2 + 2) = the514thwordfortheIDT72V223,
1,026thwordforIDT72V233,2,050thwordfortheIDT72V243,4,098thword
for the IDT72V253, 8,194th word for the IDT72V263, 16,386th word for
IDT72V273, 32,770th word for the IDT72V283 and 65,538th word for the
IDT72V293.ContinuingtowritedataintotheFIFOwillcausethePAFtogoLOW.
Again,ifnoreadsareperformed,thePAFwillgoLOWafter(D-m)writestothe
FIFO.Ifx18Inputorx18OutputbusWidthisselected,(D-m) = (513-m)writes
fortheIDT72V223,(1,025-m)writesfortheIDT72V233,(2,049-m)writesfor
theIDT72V243,(4,097-m)writesfortheIDT72V253,(8,193-m)writesforthe
IDT72V263,(16,385-m)writesfortheIDT72V273,(32,769-m)writesforthe
IDT72V283and(65,537-m)writesfortheIDT72V293.Ifbothx9Inputandx9
OutputbusWidthsareselected,(D-m)=(1,025-m)writesfortheIDT72V223,
(2,049-m) writes for the IDT72V233, (4,097-m) writes for the IDT72V243,
(8,193-m) writes for the IDT72V253, (16,385-m) writes for the IDT72V263,
12
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
(32,769-m) writes for the IDT72V273, (65,537-m) writes for the IDT72V283 be programmed into the FIFO in one of two ways; serial or parallel loading
and(131,073-m)writesfortheIDT72V293.Theoffsetmisthefulloffsetvalue. method.TheselectionoftheloadingmethodisdoneusingtheLD(Load)pin.
ThedefaultsettingforthesevaluesarestatedinthefootnoteofTable2.
During Master Reset, the state of the LD input determines whether serial or
WhentheFIFOisfull,theInputReady(IR)flagwillgoHIGH,inhibitingfurther parallelflagoffsetprogrammingisenabled.AHIGHonLDduringMasterReset
writeoperations.Ifnoreadsareperformedafterareset,IRwillgoHIGHafter selectsserialloadingofoffsetvalues.ALOWonLDduringMasterResetselects
DwritestotheFIFO.Ifx18Inputorx18OutputbusWidthisselected,D = 513 parallelloadingofoffsetvalues.
writesfortheIDT72V223,1,025writesfortheIDT72V233,2,049writesforthe
InadditiontoloadingoffsetvaluesintotheFIFO,itisalsopossibletoread
IDT72V243,4,097writesfortheIDT72V253,8,193writesfortheIDT72V263, thecurrentoffsetvalues.Offsetvaluescanbereadviatheparalleloutputport
16,385writesfortheIDT72V273,32,769writesfortheIDT72V283and65,537 Q0-Qn,regardlessoftheprogrammingmodeselected(serialorparallel).Itis
writesfortheIDT72V293.Ifbothx9Inputandx9OutputbusWidthsareselected, notpossibletoreadtheoffsetvaluesinserialfashion.
D = 1,025 writes for the IDT72V223, 2,049 writes for the IDT72V233, 4,097
Figure3,ProgrammableFlagOffsetProgrammingSequence,summaries
writes fortheIDT72V243,8,193writes fortheIDT72V253,16,385writes for thecontrolpinsandsequenceforbothserialandparallelprogrammingmodes.
the IDT72V263, 32,769 writes for the IDT72V273, 65,537 writes for the Foramoredetaileddescription,seediscussionthatfollows.
IDT72V283and131,073writesfortheIDT72V293,respectively.Notethatthe
additionalwordinFWFTmodeisduetothecapacityofthememoryplusoutput MasterReset,regardlessofwhetherserialorparallelprogramminghasbeen
register. selected.Validprogrammingranges arefrom0toD-1.
IftheFIFOisfull,thefirstreadoperationwillcausetheIRflagtogoLOW.
Theoffsetregistersmaybeprogrammed(andreprogrammed)anytimeafter
Subsequent read operations will cause the PAF and HF to go HIGH at the SYNCHRONOUS vs ASYNCHRONOUS PROGRAMMABLE FLAG
conditionsdescribedinTable4.Iffurtherreadoperationsoccur,withoutwrite TIMING SELECTION
operations,thePAEwillgoLOWwhentherearen+1wordsintheFIFO,where
The IDT72V223/72V233/72V243/72V253/72V263/72V273/72V283/
nistheemptyoffsetvalue.ContinuingreadoperationswillcausetheFIFOto 72V293canbeconfiguredduringtheMasterResetcyclewitheithersynchro-
becomeempty.WhenthelastwordhasbeenreadfromtheFIFO,OR willgo nous or asynchronous timing for PAF and PAE flags by use of the PFM pin.
HIGHinhibitingfurtherreadoperations.RENisignoredwhentheFIFOisempty.
If synchronous PAF/PAE configuration is selected (PFM, HIGH during
When configured in FWFT mode, the OR flag output is triple register- MRS),thePAFisassertedandupdatedontherisingedgeofWCLKonlyand
buffered,andtheIRflagoutputisdoubleregister-buffered. notRCLK.Similarly,PAEisassertedandupdatedontherisingedgeofRCLK
RelevanttimingdiagramsforFWFTmodecanbefoundinFigure9,10and onlyandnotWCLK.Fordetailtimingdiagrams,seeFigure18forsynchronous
PAF timingandFigure19forsynchronous PAEtiming.
12.
If asynchronous PAF/PAE configuration is selected (PFM, LOW during
PROGRAMMING FLAG OFFSETS
MRS),thePAFisassertedLOWontheLOW-to-HIGHtransitionofWCLKand
FullandEmptyFlagoffsetvaluesareuserprogrammable.TheIDT72V223/ PAFisresettoHIGHontheLOW-to-HIGHtransitionofRCLK.Similarly,PAE
72V233/72V243/72V253/72V263/72V273/72V283/72V293hasinternalreg- isassertedLOWontheLOW-to-HIGHtransitionofRCLK.PAEisresettoHIGH
istersfortheseoffsets.Thereareeightdefaultoffsetvaluesselectableduring ontheLOW-to-HIGHtransitionofWCLK.Fordetailtimingdiagrams,seeFigure
MasterReset.TheseoffsetvaluesareshowninTable2.Offsetvaluescanalso 20forasynchronousPAFtimingandFigure21forasynchronousPAEtiming.
TABLE 2 DEFAULT PROGRAMMABLE FLAG OFFSETS
IDT72V253
IDT72V223
IDT72V233
IDT72V263
IDT72V273
IDT72V243
IDT72V283
IDT72V293
Offsets n,m
Offsets n,m
Offsets n,m
Offsets n,m
Offsets n,m
All Other x9 to x9
All Other x9 to x9
LD
L
L
FSEL0 FSEL1
All Modes
Modes
511
255
63
15
31
7
3
127
Mode
511
255
63
31
1,023
15
All Modes
511
Modes
511
255
63
31
1,023
15
Mode
16,383
8,191
4,095
2,047
1,023
511
All Modes
16,383
8,191
4,095
2,047
1,023
511
L
H
H
L
H
L
H
H
L
511
255
63
15
31
7
255
63
31
1,023
15
7
L
H
H
H
H
L
L
H
H
L
L
H
L
3
127
7
127
7
127
255
127
255
127
127
H
L
X
X
X
X
Serial Programming Mode(3)
Parallel Programming Mode(4)
NOTES:
1. n = empty offset for PAE.
2. m = full offset for PAF.
3. As well as selecting serial programming mode, one of the default values will also be loaded depending on the state of FSEL0 & FSEL1.
4. As well as selecting parallel programming mode, one of the default values will also be loaded depending on the state of FSEL0 & FSEL1.
13
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
TABLE 3 STATUS FLAGS FOR IDT STANDARD MODE
IDT72V243
IDT72V253
IW = OW = x9
IDT72V223
IDT72V233
IW OW or
≠
IDT72V223
PAE
IDT72V233
IDT72V243
FF PAF
HF
EF
IW = OW = x18
0
L
0
1 to n
0
1 to n
0
H
H
H
H
H
H
H
H
H
H
H
L
L
1 to n
L
H
H
H
1 to n
Number of
Words in
(n+1) to 1,024
H
H
(n+1) to 256
257 to (512-(m+1))
(512-m) to 511
512
(n+1) to 512
(n+1) to 2,048
2,049 to (4,096-(m+1))
(4,096-m) to 4,095
4,096
(2)
513 to (1,024-(m+1))
(1,024-m) to 1,023
1,025 to (2,048-(m+1))
(2,048-m) to 2,047
2,048
FIFO
H
L
L
L
L
L
H
H
H
H
1,024
IDT72V253
IDT72V263
IDT72V263
IDT72V273
IW = OW = x9
IDT72V273
IDT72V283
IDT72V283
IDT72V293
IDT72V293
IW
≠ OW or
PAE
FF PAF
HF
EF
IW = OW = x18
0
0
0
L
0
0
H
H
H
H
H
H
H
H
H
H
H
L
L
1 to n
1 to n
L
H
H
H
1 to n
1 to n
1 to n
Number of
Words in
(n+1) to 4,096
4,097 to (8,192-(m+1))
(8,192-m) to 8,191
8,192
(n+1) to 32,768
H
H
(n+1) to 8,192
8,193 to (16,384-(m+1))
(16,384-m) to 16,383
16,384
(n+1) to 16,384
(n+1) to 65,536
(2)
16,385 to (32,768-(m+1))
(32,768-m) to 32,767
32,769 to (65,536-(m+1))
(65,536-m) to 65,535
65,536
65,537 to (131,072-(m+1))
(131,072-m) to 131,071
131,072
FIFO
H
L
L
L
L
L
H
H
H
H
32,768
NOTE:
1. See Table 2 for values for n, m.
TABLE 4 STATUS FLAGS FOR FWFT MODE
IDT72V243
IDT72V253
IW = OW = x9
IDT72V223
IDT72V233
IDT72V243
IW OW or
≠
IDT72V223
PAE
IDT72V233
IR PAF
HF
OR
IW = OW = x18
0
H
L
0
1 to n+1
0
0
L
L
L
L
H
H
H
H
H
H
H
L
L
1 to n+1
L
1 to n+1
1 to n+1
Number of
Words in
(n+2) to 1,025
H
H
L
(n+2) to 257
258 to (513-(m+1))
(513-m) to 512
513
(n+2) to 513
(n+2) to 2,049
2,050 to (4,097-(m+1))
(4,097-m) to 4,096
4,097
L
(2)
514 to (1,025-(m+1))
(1,025-m) to 1,024
1,026 to (2,049-(m+1))
(2,049-m) to 2,048
2,049
FIFO
L
L
L
L
L
H
H
L
L
1,025
H
IDT72V253
IDT72V263
IDT72V263
IDT72V273
IW = OW = x9
IDT72V273
IDT72V283
IDT72V283
IDT72V293
IDT72V293
IW
≠ OW or
PAE
IR PAF
HF
OR
IW = OW = x18
0
0
0
H
L
0
0
L
L
L
L
H
H
H
H
H
H
H
L
L
1 to n+1
1 to n+1
L
1 to n+1
1 to n+1
1 to n+1
Number of
Words in
(n+2) to 4,097
4,098 to (8,193-(m+1))
(8,193-m) to 8,192
8,193
(n+2) to 32,769
H
H
L
(n+2) to 8,193
8,194 to (16,385-(m+1))
(16,385-m) to 16,384
16,385
(n+2) to 16,385
(n+2) to 65,537
L
(2)
16,386 to (32,769-(m+1))
(32,769-m) to 32,768
32,770 to (65,537-(m+1))
(65,537-m) to 65,536
65,537
65,538 to (131,073-(m+1))
(131,073-m) to 131,072
131,073
FIFO
L
L
L
L
L
H
H
L
L
32,769
H
4666 drw05
NOTE:
1. See Table 2 for values for n, m.
2. Number of Words in FIFO = FIFO Depth + Output Register
14
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
1st Parallel Offset Write/Read Cycle
D/Q8
1st Parallel Offset Write/Read Cycle
D/Q8
D/Q0
D/Q0
EMPTY OFFSET REGISTER
EMPTY OFFSET REGISTER
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
2nd Parallel Offset Write/Read Cycle
D/Q8
D/Q0
EMPTY OFFSET REGISTER
15 14 13 12
2nd Parallel Offset Write/Read Cycle
D/Q8
D/Q0
16
11
19
10
18
9
EMPTY OFFSET REGISTER
3rd Parallel Offset Write/Read Cycle
D/Q8
16
15
14
13
12
11
10
9
D/Q0
EMPTY OFFSET REGISTER
17
3rd Parallel Offset Write/Read Cycle
D/Q8
D/Q0
4th Parallel Offset Write/Read Cycle
D/Q8
FULL OFFSET REGISTER
D/Q0
FULL OFFSET REGISTER
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
5th Parallel Offset Write/Read Cycle
D/Q8
4th Parallel Offset Write/Read Cycle
D/Q8
D/Q0
D/Q0
FULL OFFSET REGISTER
15 14 13 12
FULL OFFSET REGISTER
16
11
10
9
16
1
5
14
13
12
11
10
9
6th Parallel Offset Write/Read Cycle
D/Q8
D/Q0
IDT72V223/72V233/72V243/72V253/72V263/
FULL OFFSET REGISTER
72V273/72V283/72V293(2) x9 Bus Width
17
1st Parallel Offset Write/Read Cycle
D/Q17
IDT72V293(2) x9 Bus Width
Data Inputs/Outputs
D/Q16
D/Q0
EMPTY OFFSET REGISTER
Non-Interspersed
Parity
16
15 14 13 12 11 10
9
8
8
7
7
6
6
5
5
4
4
3
2
2
1
1
16 15 14 13 12 11 10
9
3
Interspersed
Parity
x9 to x9 Mode
# of Bits Used:
All Other Modes
# of Bits Used:
D/Q8
# of Bits Used
10 bits for the IDT72V223
11 bits for the IDT72V233
12 bits for the IDT72V243
13 bits for the IDT72V253
14 bits for the IDT72V263
15 bits for the IDT72V273
16 bits for the IDT72V283
17 bits for the IDT72V293
9 bits for the IDT72V223
10 bits for the IDT72V233
11 bits for the IDT72V243
12 bits for the IDT72V253
13 bits for the IDT72V263
14 bits for the IDT72V273
15 bits for the IDT72V283
16 bits for the IDT72V293
2nd Parallel Offset Write/Read Cycle
D/Q17
Data Inputs/Outputs
FULL OFFSET REGISTER
D/Q0
D/Q16
16 15 14 13 12 11 10 9
16 15 14 13 12 11 10
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
9
D/Q8
Note: All unused bits of the
LSB & MSB are don't care
Note: All unused bits of the
LSB & MSB are don't care
IDT72V223/72V233/72V243/72V253/72V263/72V273/
72V283/72V293
x18 Bus Width
4666 drw06
NOTES:
1. When programming the IDT72V293 with an input bus width of x9 and output bus width of x18, 4 write cycles will be required. When Reading the IDT72V293 with an output bus
width of x9 and input bus width of x18, 4 read cycles will be required.
2. A total of 6 program/ read cycles will be required for x9 bus width if both the input and output bus widths are set to x9.
Figure 3. Programmable Flag Offset Programming Sequence
15
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
IDT72V223, IDT72V233
IDT72V243, IDT72V253
IDT72V263, IDT72V273
WCLK
RCLK
X
LD WEN REN SEN
IDT72V283, IDT72V293
Parallel write to registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
0
0
1
1
Full Offset (MSB)
Parallel read from registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
X
0
1
0
1
Full Offset (MSB)
x9 to x9 Mode
All Other Modes
Serial shift into registers:
Serial shift into registers:
20 bits for the IDT72V223
22 bits for the IDT72V233
24 bits for the IDT72V243
26 bits for the IDT72V253
28 bits for the IDT72V263
30 bits for the IDT72V273
32 bits for the IDT72V283
34 bits for the IDT72V293
0
1
1
0
X
18 bits for the IDT72V223
20 bits for the IDT72V233
22 bits for the IDT72V243
24 bits for the IDT72V253
26 bits for the IDT72V263
28 bits for the IDT72V273
30 bits for the IDT72V283
32 bits for the IDT72V293
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
X
X
X
X
1
1
1
No Operation
1
1
0
X
1
X
0
1
X
X
X
Write Memory
X
X
Read Memory
No Operation
X
1
4666 drw06a
NOTES:
1. The programming method can only be selected at Master Reset.
2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
3. The programming sequence applies to both IDT Standard and FWFT modes.
Figure 3. Programmable Flag Offset Programming Sequence (Continued)
16
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
SERIAL PROGRAMMING MODE
LOW-to-HIGHtransitionofWCLK.UponthesecondLOW-to-HIGHtransition
IfSerialProgrammingmodehasbeenselected,asdescribedabove,then ofWCLK,dataarewrittenintotheMSBoftheEmptyOffsetRegister.Onthethird
programmingofPAEandPAFvaluescanbeachievedbyusingacombination LOW-to-HIGHtransitionofWCLK,dataarewrittenintotheLSBoftheFullOffset
oftheLD,SEN,WCLKandSIinputpins.ProgrammingPAEandPAFproceeds Register.OnthefourthLOW-to-HIGHtransitionofWCLK,dataarewritteninto
as follows:whenLD andSEN are setLOW, data onthe SIinputare written, theMSBoftheFullOffsetRegister.ThefifthLOW-to-HIGHtransitionofWCLK,
onebitforeachWCLKrisingedge,startingwiththeEmptyOffsetLSBandending dataarewritten,onceagaintotheEmptyOffsetRegister.Notethatforx9bus
withtheFullOffsetMSB.Ifx9tox9modeis selected,atotalof20bits forthe width,oneextraWritecycleisrequiredforboththeEmptyOffsetRegisterand
IDT72V223,22bitsfortheIDT72V233,24bitsfortheIDT72V243,26bitsfor FullOffsetRegister.SeeFigure16,ParallelLoadingofProgrammableFlag
theIDT72V253,28bitsfortheIDT72V263,30bitsfortheIDT72V273,32bits Registers,forthetimingdiagramforthismode.
for the IDT72V283 and 34 bits for the IDT72V293. For any other mode of
Theactofwritingoffsetsinparallelemploysadedicatedwriteoffsetregister
operation(thatincludesx18buswidthoneithertheInputorOutput),minus2 pointer. The act of reading offsets employs a dedicated read offset register
bitsfromthevaluesabove.So,atotalof18bitsfortheIDT72V223,20bitsfor pointer.Thetwopointersoperateindependently;however,areadandawrite
theIDT72V233,22bitsfortheIDT72V243,24bitsfortheIDT72V253,26bits shouldnotbeperformedsimultaneouslytotheoffsetregisters.AMasterReset
fortheIDT72V263,28bitsfortheIDT72V273,30bitsfortheIDT72V283and initializesbothpointerstotheEmptyOffset(LSB)register.APartialResethas
32bits forthe IDT72V293. See Figure 15, SerialLoadingofProgrammable noeffectonthepositionofthesepointers.RefertoFigure3,Programmable
FlagRegisters,forthetimingdiagramforthismode.
FlagOffsetProgrammingSequence,foradetaileddiagramofthedatainput
Using the serial method, individual registers cannot be programmed lines D0-Dnusedduringparallelprogramming.
selectively.PAEandPAFcanshowavalidstatusonlyafterthecompleteset
Write operations to the FIFO are allowed before and during the parallel
of bits (for all offset registers) has been entered. The registers can be programmingsequence.Inthiscase,theprogrammingofalloffsetregisters
reprogrammedaslongasthecompletesetofnewoffsetbitsisentered.When does nothavetooccuratonetime.One,twoormoreoffsetregisters canbe
LD is LOW and SEN is HIGH, no serial write to the registers can occur.
writtenandthenbybringingLDHIGH,writeoperations canberedirectedto
Write operations to the FIFO are allowed before and during the serial theFIFOmemory.WhenLDissetLOWagain,andWENisLOW,thenextoffset
programmingsequence.Inthiscase,theprogrammingofalloffsetbitsdoesnot registerinsequenceiswrittento.AsanalternativetoholdingWENLOWand
havetooccuratonce.AselectnumberofbitscanbewrittentotheSIinputand togglingLD,parallelprogrammingcanalsobeinterruptedbysettingLDLOW
then,bybringingLDandSENHIGH,datacanbewrittentoFIFOmemoryvia andtogglingWEN.
DnbytogglingWEN.WhenWENisbroughtHIGHwithLDandSENrestored
Notethatthestatusofaprogrammableflag(PAEorPAF)outputisinvalid
toaLOW,thenextoffsetbitinsequenceiswrittentotheregistersviaSI.Ifan during the programming process. From the time parallel programming has
interruptionofserialprogrammingisdesired,itissufficienteithertosetLDLOW begun,aprogrammableflagoutputwillnotbevaliduntiltheappropriateoffset
anddeactivateSENortosetSENLOWanddeactivateLD.OnceLDandSEN wordhasbeenwrittentotheregister(s)pertainingtothatflag.Measuringfrom
arebothrestoredtoaLOWlevel,serialoffsetprogrammingcontinues.
Fromthetimeserialprogramminghasbegun,neitherprogrammableflag twomorerisingWCLKedgesplustPAF,PAEwillbevalidafterthenexttworising
willbevaliduntilthefullsetofbitsrequiredtofillalltheoffsetregistershasbeen RCLK edges plus tPAE plus tSKEW2.
therisingWCLKedgethatachievestheabovecriteria;PAFwillbevalidafter
written.MeasuringfromtherisingWCLKedgethatachievestheabovecriteria;
The act of reading the offset registers employs a dedicated read offset
PAFwillbevalidaftertwomorerisingWCLKedgesplustPAF,PAEwillbevalid registerpointer.ThecontentsoftheoffsetregisterscanbereadontheQ0-Qn
afterthe nexttworisingRCLKedges plus tPAE plus tSKEW2.
Itis notpossibletoreadtheflagoffsetvalues inaserialmode.
pinswhenLDissetLOWandRENissetLOW.IftheFIFOisconfiguredforan
inputbuswidthandoutputbuswidthbothsettox9,thenthetotalnumberofread
operationsrequiredtoreadtheoffsetregistersis4fortheIDT72V223/72V233/
72V243/72V253/72V263/72V273/72V283or6fortheIDT72V293.Referto
PARALLELPROGRAMMINGMODE
IfParallelProgrammingmodehasbeenselected,asdescribedabove,then Figure3,ProgrammableFlagOffsetProgrammingSequence,foradetailed
programmingofPAEandPAFvaluescanbeachievedbyusingacombination diagramofthedatainputlinesD0-Dnusedduringparallelprogramming.Ifthe
oftheLD,WCLK,WENandDninputpins.IftheFIFOisconfiguredforaninput FIFO is configured for an input to output bus width of x9 to x18, x18 to x9 or
bus widthandoutputbus widthbothsettox9, thenthe totalnumberofwrite x18tox18,thenthefollowingnumberofreadoperationsarerequired:foran
operations required to program the offset registers is 4 for the IDT72V223/ outputbuswidthofx18atotalof2readoperationswillberequiredtoreadthe
72V233/72V243/72V253/72V263/72V273/72V283or6fortheIDT72V293. offsetregistersfortheIDT72V223/72V233/72V243/72V253/72V263/72V273/
RefertoFigure3,ProgrammableFlagOffsetProgrammingSequence,fora 72V283/72V293.Foranoutputbuswidthofx9atotalof4readoperationswill
detaileddiagramofthedatainputlinesD0-Dnusedduringparallelprogram- berequiredtoreadtheoffsetregistersfortheIDT72V223/72V233/72V243/
ming.IftheFIFOisconfiguredforaninputtooutputbuswidthofx9tox18,x18 72V253/72V263/72V273/72V283/72V293. Refer to Figure 3, Program-
tox9orx18tox18,thenthefollowingnumberofwriteoperationsarerequired. mable Flag Offset Programming Sequence, for a detailed diagram. For
For an input bus width of x18 a total of 2 write operations will be required to example, reading PAE and PAF on the IDT72V293 configured for x18 bus
program the offset registers for the IDT72V223/72V233/72V243/72V253/ widthproceedsasfollows:dataarereadviaQnfromtheEmptyOffsetRegister
72V263/72V273/72V283/72V293.Foraninputbuswidthofx9atotalof4write onthefirstandsecondLOW-to-HIGHtransitionofRCLK.Uponthethirdand
operationswillberequiredtoprogramtheoffsetregistersfortheIDT72V223/ fourth LOW-to-HIGH transition of RCLK, data are read from the Full Offset
72V233/72V243/72V253/72V263/72V273/72V283/72V293.RefertoFigure Register. The fifth and sixth transition of RCLK reads, once again, from the
3,ProgrammableFlagOffsetProgrammingSequence,foradetaileddiagram. EmptyOffsetRegister. Note thatfora x9bus width, one extra Readcycle is
Forexample,programmingPAEandPAFontheIDT72V293configured requiredforboththeEmptyOffsetRegisterandFullOffsetRegister.SeeFigure
forx18buswidthproceedsasfollows:whenLDandWENaresetLOW,data 17,ParallelReadofProgrammableFlagRegisters,forthetimingdiagramfor
ontheinputsDnarewrittenintotheLSBoftheEmptyOffsetRegisteronthefirst thismode.
17
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
Itispermissibletointerrupttheoffsetregisterreadsequencewithreadsor IDT72V253,16,385fortheIDT72V263,32,769fortheIDT72V273,65,537for
writestotheFIFO.TheinterruptionisaccomplishedbydeassertingREN,LD, the IDT72V283 and 131,073 for the IDT72V293.
orbothtogether. WhenREN andLD are restoredtoa LOWlevel, readingof
IfIDTStandardmodeisselected,theFIFOwillmarkthebeginningofthe
theoffsetregisterscontinueswhereitleftoff.Itshouldbenoted,andcareshould RetransmitsetupbysettingEFLOW.Thechangeinlevelwillonlybenoticeable
betakenfromthefactthatwhenaparallelreadoftheflagoffsetsisperformed, if EF was HIGH before setup. During this period, the internal read pointer is
the data wordthatwas presentonthe outputlines Qnwillbe overwritten.
Parallelreadingofthe offsetregisters is always permittedregardless of
whichtimingmode (IDTStandardorFWFTmodes)has beenselected.
initializedtothefirstlocationoftheRAMarray.
WhenEFgoesHIGH,Retransmitsetupiscompleteandreadoperations
maybeginstartingwiththefirstlocationinmemory.SinceIDTStandardmode
isselected,everywordreadincludingthefirstwordfollowingRetransmitsetup
requires a LOW on REN to enable the rising edge of RCLK. See Figure 11,
RETRANSMITOPERATION
The Retransmit operation allows data that has already been read to be Retransmit Timing (IDT Standard Mode), forthe relevanttimingdiagram.
accessedagain.Thereare2modesofRetransmitoperation,normallatency IfFWFTmodeisselected,theFIFOwillmarkthebeginningoftheRetransmit
andzerolatency.TherearetwostagestoRetransmit:first,asetupprocedure setupbysettingOR HIGH.Duringthis period,theinternalreadpointeris set
that resets the read pointer to the first location of memory, then the actual tothefirstlocationoftheRAMarray.
retransmit,whichconsistsofreadingoutthememorycontents,startingatthe
beginningofmemory.
WhenORgoesLOW,Retransmitsetupiscomplete;atthesametime,the
contentsofthefirstlocationappearontheoutputs.SinceFWFTmodeisselected,
RetransmitsetupisinitiatedbyholdingRTLOWduringarisingRCLKedge. thefirstwordappearsontheoutputs,noLOWonRENisnecessary.Reading
RENandWENmustbeHIGHbeforebringingRTLOW.Whenzerolatencyis all subsequent words requires a LOW on REN to enable the rising edge of
utilized,RENdoesnotneedtobeHIGHbeforebringingRTLOW.Atleasttwo RCLK.SeeFigure12,RetransmitTiming(FWFTMode),fortherelevanttiming
words, butnomorethanD-2 words should have been written into the FIFO, diagram.
and read from the FIFO, between Reset (Master or Partial) and the time of
ForeitherIDTStandardmodeorFWFTmode,updatingofthePAE,HFand
Retransmitsetup.Ifx18Inputorx18OutputbusWidthisselected,D=512for PAF flags beginwiththe risingedge ofRCLKthatthe RT is setupon. PAEis
theIDT72V223,1,024fortheIDT72V233,2,048fortheIDT72V243,4,096for synchronizedtoRCLK,thusonthesecondrisingedgeofRCLKafterRTissetup,
theIDT72V253,8,192fortheIDT72V263,16,384fortheIDT72V273,32,768 thePAEflagwillbeupdated.HFisasynchronous,thustherisingedgeofRCLK
fortheIDT72V283and65,536fortheIDT72V293.Ifbothx9Inputandx9Output thatRTissetupwillupdateHF.PAFissynchronizedtoWCLK,thusthesecond
bus Widths are selected, D = 1,024 for the IDT72V223, 2,048 for the risingedgeofWCLKthatoccurstSKEW aftertherisingedgeofRCLKthatRT
IDT72V233, 4,096 for the IDT72V243, 8,192 for the IDT72V253, 16,384 for is setup will update PAF. RT is synchronized to RCLK.
the IDT72V263, 32,768 for the IDT72V273, 65,536 for the IDT72V283 and
TheRetransmitfunctionhastheoptionof2modesofoperation,either"normal
131,072fortheIDT72V293.InFWFTmode,ifx18Inputorx18OutputbusWidth latency" or "zero latency". Figure 11 and Figure 12 mentioned previously,
is selected, D = 513 for the IDT72V223, 1,025 for the IDT72V233, 2,049 for relate to "normal latency". Figure 13 and Figure 14 show "zero latency"
theIDT72V243,4,097fortheIDT72V253,8,193fortheIDT72V263,16,385 retransmitoperation.Zerolatencybasicallymeansthatthefirstdatawordtobe
fortheIDT72V273,32,769fortheIDT72V283and65,537fortheIDT72V293. retransmitted,isplacedontotheoutputregisterwithrespecttotheRCLKpulse
If both x9 Input and x9 Output bus Widths are selected, D = 1,025 for the thatinitiatedtheretransmit.
IDT72V223,2,049fortheIDT72V233,4,097fortheIDT72V243,8,193forthe
18
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
SIGNALDESCRIPTION
INPUTS:
Asynchronousoperationofthereadportwillbeselected.DuringAsynchronous
operation of the read port the RCLK input becomes RD input, this is the
Asynchronousreadstrobeinput.ArisingedgeonRDwillreaddatafromthe
FIFO via the output register and Qn port. (REN must be tied LOW during
Asynchronous operationofthe readport).
DATA IN (D0 - Dn)
Datainputsfor18-bitwidedata(D0-D17)ordatainputsfor9-bitwidedata
(D0-D8).
The OE input provides three-state control of the Qn output bus, in an
asynchronousmanner.
CONTROLS:
WhenthereadportisconfiguredforAsynchronousoperationthedevice
mustbeoperatingonIDTstandardmode,FWFTmodeisnotpermissibleifthe
readportisAsynchronous.TheEmptyFlag(EF)operatesinanAsynchronous
manner,thatis,theemptyflagwillbeupdatedbasedonbothareadoperation
andawriteoperation.Refertofigures25,26,27and28forrelevanttimingand
operationalwaveforms.
MASTER RESET (MRS)
AMasterResetisaccomplishedwhenevertheMRSinputistakentoaLOW
state.Thisoperationsetstheinternalreadandwritepointerstothefirstlocation
oftheRAMarray.PAEwillgoLOW,PAFwillgoHIGH,andHF willgoHIGH.
IfFWFT/SIisLOWduringMasterResetthentheIDTStandardmode,along
withEF andFF are selected. EFwillgoLOWandFF willgoHIGH. IfFWFT/
SIisHIGH,thentheFirstWordFallThroughmode(FWFT),alongwithIRand
OR, are selected. OR will go HIGH and IR will go LOW.
AllcontrolsettingssuchasOW,IW,BE,RM,PFMandIParedefinedduring
theMasterResetcycle.
RETRANSMIT (RT)
The Retransmit operation allows data that has already been read to be
accessedagain.Thereare2modesofRetransmitoperation,normallatency
andzerolatency.TherearetwostagestoRetransmit:first,asetupprocedure
that resets the read pointer to the first location of memory, then the actual
retransmit,whichconsistsofreadingoutthememorycontents,startingatthe
beginningofthememory.
DuringaMasterReset,theoutputregisterisinitializedtoallzeroes.AMaster
Resetisrequiredafterpowerup,beforeawriteoperationcantakeplace.MRS
isasynchronous.
See Figure 5, Master Reset Timing, forthe relevanttimingdiagram.
RetransmitsetupisinitiatedbyholdingRTLOWduringarisingRCLKedge.
REN and WEN must be HIGH before bringing RT LOW. Whenzerolatency
is utilized, REN does not need to be HIGH before bringing RT LOW.
IfIDTStandardmodeisselected,theFIFOwillmarkthebeginningofthe
RetransmitsetupbysettingEFLOW.Thechangeinlevelwillonlybenoticeable
if EF was HIGH before setup. During this period, the internal read pointer is
initializedtothefirstlocationoftheRAMarray.
PARTIAL RESET (PRS)
APartialResetisaccomplishedwheneverthePRSinputistakentoaLOW
state.AsinthecaseoftheMasterReset,theinternalreadandwritepointers
aresettothefirstlocationoftheRAMarray,PAEgoesLOW,PAFgoesHIGH,
and HF goes HIGH.
WhichevermodeisactiveatthetimeofPartialReset,IDTStandardmode
orFirstWordFallThrough,thatmodewillremainselected.IftheIDTStandard
modeisactive,thenFFwillgoHIGHandEFwillgoLOW.IftheFirstWordFall
Through mode is active, then OR will go HIGH, and IR will go LOW.
Following Partial Reset, all values held in the offset registers remain
unchanged.Theprogrammingmethod(parallelorserial)currentlyactiveat
thetimeofPartialResetisalsoretained.Theoutputregisterisinitializedtoall
zeroes.PRS is asynchronous.
WhenEFgoesHIGH,Retransmitsetupiscompleteandreadoperations
maybeginstartingwiththefirstlocationinmemory.SinceIDTStandardmode
isselected,everywordreadincludingthefirstwordfollowingRetransmitsetup
requires a LOW on REN to enable the rising edge of RCLK. See Figure 11,
Retransmit Timing (IDT Standard Mode), forthe relevanttimingdiagram.
IfFWFTmodeisselected,theFIFOwillmarkthebeginningoftheRetransmit
setupbysettingORHIGH.Duringthisperiod,theinternalreadpointerisset
tothefirstlocationoftheRAMarray.
WhenORgoesLOW,Retransmitsetupiscomplete;atthesametime,the
contentsofthefirstlocationappearontheoutputs.SinceFWFTmodeisselected,
thefirstwordappearsontheoutputs,noLOWonRENisnecessary.Reading
all subsequent words requires a LOW on REN to enable the rising edge of
RCLK.SeeFigure12,RetransmitTiming(FWFTMode),fortherelevanttiming
diagram.
A Partial Reset is useful for resetting the device during the course of
operation,whenreprogrammingprogrammableflagoffsetsettingsmaynotbe
convenient.
See Figure 6, PartialResetTiming, forthe relevanttimingdiagram.
ASYNCHRONOUS WRITE (ASYW)
ThewriteportcanbeconfiguredforeitherSynchronousorAsynchronous
mode of operation. If during Master Reset the ASYW input is LOW, then
Asynchronousoperationofthewriteportwillbeselected.DuringAsynchro-
nousoperationofthewriteporttheWCLKinputbecomesWRinput,thisisthe
Asynchronouswritestrobeinput.ArisingedgeonWRwillwritedatapresent
ontheDninputsintotheFIFO.(WENmustbetiedLOWwhenusingthewrite
portinAsynchronous mode).
WhenthewriteportisconfiguredforAsynchronousoperationthefullflag
(FF)operatesinanasynchronousmanner,thatis,thefullflagwillbeupdated
based in both a write operation and read operation. Note, if Asynchronous
modeis selected,FWFTis notpermissable.RefertoFigures 23,24,27and
28forrelevanttimingandoperationalwaveforms.
In Retransmit operation, zero-latency mode can be selected using the
RetransmitMode(RM)pinduringaMasterReset.Thiscanbeappliedtoboth
IDT Standard mode and FWFT mode.
RETRANSMIT LATENCY MODE (RM)
Azero-latencyretransmittimingmodecanbeselectedusingtheRetransmit
timing Mode pin (RM). During Master Reset, a LOW on RM will select zero-
latency retransmit. A HIGH on RM during Master Reset will select normal
latency.
If zero-latency retransmit operation is selected the first data word to be
retransmittedwillbeplacedontheoutputregisterwithrespecttothesameRCLK
edgethatinitiatedtheretransmitbasedonRTbeingLOW.
RefertoFigure13forRetransmitTimingwithzerolatency(IDTStandard
Mode). Refer to Figure 14 for Retransmit Timing with zero latency (FWFT
Mode).
ASYNCHRONOUS READ (ASYR)
ThereadportcanbeconfiguredforeitherSynchronousorAsynchronous
mode of operation. If during a Master Reset the ASYR input is LOW, then
19
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
FIRST WORD FALL THROUGH/SERIAL IN (FWFT/SI)
ItispermissibletostoptheRCLK. NotethatwhileRCLKisidle,theEF/OR,PAE
This is a dualpurpose pin. DuringMasterReset, the state ofthe FWFT/ andHFflagswillnotbeupdated.(NotethatRCLKisonlycapableofupdating
SIinputdetermineswhetherthedevicewilloperateinIDTStandardmodeor the HF flag to HIGH). The Write and Read Clocks can be independent or
First Word Fall Through (FWFT) mode.
coincident.
If Asynchronous operation has been selected this input is RD (Read
If,atthetimeofMasterReset,FWFT/SIisLOW,thenIDTStandardmode
willbeselected.ThismodeusestheEmptyFlag(EF)toindicatewhetherornot Strobe) . Data is Asynchronously read from the FIFO via the output register
there are any words present in the FIFO memory. It also uses the Full Flag whenever there is a rising edge on RD. In this mode the REN input must be
function(FF)toindicatewhetherornottheFIFOmemoryhasanyfreespace tiedLOW.TheOEinputisusedtoprovideAsynchronouscontrolofthethree-
forwriting. InIDTStandardmode, everywordreadfromthe FIFO, including stateQnoutputs.
the first, mustbe requestedusingthe ReadEnable (REN)andRCLK.
If,atthetimeofMasterReset,FWFT/SIisHIGH,thenFWFTmodewillbe READ ENABLE (REN)
selected.ThismodeusesOutputReady(OR)toindicatewhetherornotthere
isvaliddataatthedataoutputs(Qn).ItalsousesInputReady(IR)toindicate register on the rising edge of every RCLK cycle if the device is not empty.
whetherornottheFIFOmemoryhasanyfreespaceforwriting.IntheFWFT
WhenReadEnableisLOW,dataisloadedfromtheRAMarrayintotheoutput
WhentheRENinputisHIGH,theoutputregisterholdsthepreviousdata
mode,thefirstwordwrittentoanemptyFIFOgoesdirectlytoQnafterthreeRCLK and no new data is loaded into the output register. The data outputs Q0-Qn
rising edges, REN = LOW is not necessary. Subsequent words must be maintainthepreviousdatavalue.
accessed using the Read Enable (REN) and RCLK.
IntheIDTStandardmode,everywordaccessedatQn,includingthefirst
AfterMasterReset,FWFT/SIactsasaserialinputforloadingPAEandPAF wordwrittentoanemptyFIFO,mustberequestedusingREN.Whenthelast
offsetsintotheprogrammableregisters.Theserialinputfunctioncanonlybe wordhasbeenreadfromtheFIFO,theEmptyFlag(EF)willgoLOW,inhibiting
usedwhentheserialloadingmethodhasbeenselectedduringMasterReset. furtherreadoperations.RENisignoredwhentheFIFOisempty.Onceawrite
SerialprogrammingusingtheFWFT/SIpinfunctionsthesamewayinbothIDT isperformed,EFwillgoHIGHallowingareadtooccur.TheEFflagisupdated
StandardandFWFTmodes.
by two RCLK cycles + tSKEW after the valid WCLK cycle.
IntheFWFTmode,thefirstwordwrittentoanemptyFIFOautomaticallygoes
totheoutputsQn,onthethirdvalidLOWtoHIGHtransitionofRCLK+tSKEW
WRITE STROBE & WRITE CLOCK (WR/WCLK)
IfSynchronousoperationofthewriteporthasbeenselectedviaASYW,this afterthefirstwrite.RENdoesnotneedtobeassertedLOW.Inordertoaccess
inputbehavesasWCLK. allotherwords,areadmustbeexecutedusingREN.TheRCLKLOWtoHIGH
AwritecycleisinitiatedontherisingedgeoftheWCLKinput.Datasetup transitionafterthelastwordhasbeenreadfromtheFIFO,OutputReady(OR)
andholdtimesmustbemetwithrespecttotheLOW-to-HIGHtransitionofthe willgoHIGHwithatrueread(RCLKwithREN=LOW),inhibitingfurtherread
WCLK.ItispermissibletostoptheWCLK. NotethatwhileWCLKisidle,theFF/ operations. REN is ignored when the FIFO is empty.
IR,PAFandHFflagswillnotbeupdated. (NotethatWCLKisonlycapableof
IfAsynchronousoperationoftheReadporthasbeenselected,thenREN
updating HF flag to LOW). The Write and Read Clocks can either be mustbeheldactive,(tiedLOW).
independentorcoincident.
IfAsynchronousoperationhasbeenselectedthisinputisWR(writestrobe). SERIAL ENABLE (SEN)
DataisAsynchronouslywrittenintotheFIFOviatheDninputswheneverthere
is arisingedgeonWR.Inthis modetheWENinputmustbetiedLOW.
TheSENinputisanenableusedonlyforserialprogrammingoftheoffset
registers. The serial programming method must be selected during Master
Reset.SENisalwaysusedinconjunctionwithLD.Whentheselinesareboth
LOW,dataattheSIinputcanbeloadedintotheprogramregisteronebitforeach
WRITE ENABLE (WEN)
WhentheWENinputisLOW,datamaybeloadedintotheFIFORAMarray LOW-to-HIGHtransitionofWCLK.
ontherisingedgeofeveryWCLKcycleifthedeviceis notfull.Datais stored
in the RAM array sequentially and independently of any ongoing read settings andnooffsets are loaded. SEN functions the same wayinbothIDT
operation.
WhenWENisHIGH,nonewdataiswrittenintheRAMarrayoneachWCLK
cycle.
To prevent data overflow in the IDT Standard mode, FF will go LOW,
When SEN is HIGH, the programmable registers retains the previous
StandardandFWFTmodes.
OUTPUTENABLE(OE)
WhenOutputEnableisenabled(LOW),theparalleloutputbuffersreceive
inhibitingfurtherwriteoperations.Uponthecompletionofavalidreadcycle,FF datafromtheoutputregister.WhenOEisHIGH,theoutputdatabus(Qn)goes
willgoHIGHallowingawritetooccur.TheFFisupdatedbytwoWCLKcycles intoahighimpedancestate.
+tSKEW afterthe RCLKcycle.
To prevent data overflow in the FWFT mode, IR will go HIGH, inhibiting LOAD (LD)
furtherwriteoperations.Uponthecompletionofavalidreadcycle,IRwillgo
Thisisadualpurposepin.DuringMasterReset,thestateoftheLDinput,
LOWallowinga write tooccur. The IR flagis updatedbytwoWCLKcycles + alongwithFSEL0andFSEL1,determinesoneofeightdefaultoffsetvaluesfor
tSKEW afterthe validRCLKcycle. thePAEandPAFflags,alongwiththemethodbywhichtheseoffsetregisters
WENisignoredwhentheFIFOisfullineitherFWFTorIDTStandardmode. canbe programmed, parallelorserial(see Table 2). AfterMasterReset, LD
IfAsynchronousoperationoftheReadporthasbeenselected,thenWEN enableswriteoperationstoandreadoperationsfromtheoffsetregisters.Only
mustbeheldactive,(tiedLOW).
theoffsetloadingmethodcurrentlyselectedcanbeusedtowritetotheregisters.
Offsetregisters canbereadonlyinparallel.
READ STROBE & READ CLOCK (RD/RCLK)
AfterMasterReset,theLDpinisusedtoactivatetheprogrammingprocess
IfSynchronousoperationofthereadporthasbeenselectedviaASYR,this oftheflagoffsetvaluesPAEandPAF.PullingLDLOWwillbeginaserialloading
inputbehavesasRCLK.A readcycleisinitiatedontherisingedgeoftheRCLK orparallelloadorreadofthese offsetvalues.
input. Datacanbereadontheoutputs,ontherisingedgeoftheRCLKinput.
20
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
BUS-MATCHING (IW, OW)
1,024fortheIDT72V233,2,048fortheIDT72V243,4,096fortheIDT72V253,
The pins IWandOWare usedtodefine the inputandoutputbus widths. 8,192fortheIDT72V263,16,384fortheIDT72V273,32,768fortheIDT72V283
DuringMasterReset,thestateofthesepinsisusedtoconfigurethedevicebus and65,536fortheIDT72V293.Ifbothx9Inputandx9OutputbusWidthsare
sizes.SeeTable1forcontrolsettings.Allflagswilloperatebasedontheword/ selected,D = 1,024fortheIDT72V223,2,048fortheIDT72V233,4,096forthe
bytesizeboundaryasdefinedbytheselectionofthewidestinputoroutputbus IDT72V243,8,192fortheIDT72V253,16,384fortheIDT72V263,32,768for
width.
theIDT72V273,65,536fortheIDT72V283and131,072fortheIDT72V293.
SeeFigure7,WriteCycleandFullFlagTiming(IDTStandardMode),forthe
relevanttiminginformation.
BIG-ENDIAN/LITTLE-ENDIAN (BE)
DuringMasterReset,aLOWonBEwillselectBig-Endianoperation.AHIGH
In FWFT mode, the Input Ready (IR) function is selected. IR goes LOW
onBEduringMasterResetwillselectLittle-Endianformat.Thisfunctionisuseful whenmemoryspace is available forwritingindata. Whenthere is nolonger
whendataiswrittenintotheFIFOinwordformat(x18)andreadoutoftheFIFO anyfreespaceleft,IRgoesHIGH,inhibitingfurtherwriteoperations.Ifnoreads
inwordformat(x18)orbyteformat(x9).IfBig-Endianmodeisselected,then areperformedafterareset(eitherMRSorPRS),IRwillgoHIGHafterD writes
themostsignificantbyteofthewordwrittenintotheFIFOwillbereadoutofthe totheFIFO.Ifx18Inputorx18Outputbus Widthis selected,D = 513forthe
FIFOfirst,followedbytheleastsignificantbyte.IfLittle-Endianformatisselected, IDT72V223,1,025fortheIDT72V233,2,049fortheIDT72V243,4,097forthe
thentheleastsignificantbyteofthewordwrittenintotheFIFOwillbereadout IDT72V253,8,193fortheIDT72V263,16,385fortheIDT72V273,32,769for
first,followedbythemostsignificantbyte.Themodedesiredisconfiguredduring theIDT72V283and65,537fortheIDT72V293.Ifbothx9Inputandx9Output
masterresetbythe state ofthe Big-Endian(BE)pin. RefertoFigure 4, Bus- bus Widths are selected, D = 1,025 for the IDT72V223, 2,049 for the
MatchingByte Arrangement, fora diagramshowingthe byte arrangement. IDT72V233, 4,097 for the IDT72V243, 8,193 for the IDT72V253, 16,385 for
the IDT72V263, 32,769 for the IDT72V273, 65,537 for the IDT72V283 and
PROGRAMMABLEFLAGMODE(PFM)
131,073 for the IDT72V293. See Figure 9, Write Timing (FWFT Mode), for
During Master Reset During Master Reset, a LOW on PFM will select therelevanttiminginformation.
Asynchronous Programmable flag timing mode. A HIGH on PFM will select
TheIRstatusnotonlymeasuresthecontentsoftheFIFOmemory,butalso
Synchronous Programmable flag timing mode. If asynchronous PAF/PAE countsthepresenceofawordintheoutputregister.Thus,inFWFTmode,the
configurationisselected(PFM,LOWduringMRS),thePAEisassertedLOW totalnumberofwritesnecessarytodeassertIRisonegreaterthanneededto
ontheLOW-to-HIGHtransitionofRCLK.PAEisresettoHIGHontheLOW-to- assert FF in IDT Standard mode.
HIGHtransitionofWCLK.Similarly,thePAFisassertedLOWontheLOW-to-
FF/IRissynchronousandupdatedontherisingedgeofWCLK.FF/IRare
HIGH transition of WCLK and PAF is reset to HIGH on the LOW-to-HIGH doubleregister-bufferedoutputs.
transitionofRCLK.
If synchronous PAE/PAF configuration is selected (PFM, HIGH during EMPTYFLAG(EF/OR)
MRS),thePAEisassertedandupdatedontherisingedgeofRCLKonlyand
Thisisadualpurposepin.IntheIDTStandardmode,theEmptyFlag(EF)
notWCLK.Similarly,PAFisassertedandupdatedontherisingedgeofWCLK functionisselected.WhentheFIFOisempty,EFwillgoLOW,inhibitingfurther
onlyandnotRCLK.Themodedesiredisconfiguredduringmasterresetbythe readoperations.WhenEFisHIGH,theFIFOisnotempty.SeeFigure8,Read
stateoftheProgrammableFlagMode(PFM)pin.
Cycle, EmptyFlagandFirstWordLatencyTiming(IDTStandardMode),for
therelevanttiminginformation.
INTERSPERSED PARITY (IP)
InFWFTmode,theOutputReady(OR)functionisselected.ORgoesLOW
DuringMasterReset,aLOWonIPwillselectNon-InterspersedParitymode. atthesametimethatthefirstwordwrittentoanemptyFIFOappearsvalidon
AHIGHwillselectInterspersedParitymode.TheIPbitfunctionallowstheuser theoutputs.ORstaysLOWaftertheRCLKLOWtoHIGHtransitionthatshiftsthe
to select the parity bit in the word loaded into the parallel port (D0-Dn) when lastwordfromtheFIFOmemorytotheoutputs.ORgoesHIGHonlywithatrue
programmingtheflagoffsets.IfInterspersedParitymodeisselected,thenthe read(RCLKwithREN=LOW).Thepreviousdatastaysattheoutputs,indicating
FIFOwillassumethattheparitybitislocatedinbitpositionD8andD17during the last word was read. Further data reads are inhibited untilOR goes LOW
theparallelprogrammingoftheflagoffsets,andwillthereforeignoreD8when again. See Figure 10, Read Timing (FWFT Mode), for the relevant timing
loadingthe offsetregisterinparallelmode. This is alsoappliedtothe output information.
registerwhenreadingthevalueoftheoffsetregister.IfInterspersedParityis
selected then output Q8 will be invalid. If Non-Interspersed Parity mode is
EF/OR is synchronous and updated on the rising edge of RCLK.
InIDTStandardmode, EFis a double register-bufferedoutput. InFWFT
selected,thenD16andD17aretheparitybitsandareignoredduringparallel mode,ORisatripleregister-bufferedoutput.
programmingoftheoffsets.(D8becomesavalidbit).Additionally,outputQ8will
become a valid bit when performing a read of the offset register. IP mode is PROGRAMMABLE ALMOST-FULL FLAG (PAF)
selectedduringMasterResetbythestateoftheIPinputpin. InterspersedParity
controlonlyhasaneffectduringparallelprogrammingoftheoffsetregisters.It reaches the almost-full condition. In IDT Standard mode, if no reads are
The Programmable Almost-Full flag (PAF) will go LOW when the FIFO
doesnoteffectthedatawrittentoandreadfromtheFIFO.
performedafterreset(MRS),PAFwillgoLOWafter(D-m)wordsarewritten
totheFIFO.Ifx18Inputorx18OutputbusWidthisselected,(D-m) = (512-m)
writes for the IDT72V223, (1,024-m) writes for the IDT72V233, (2,048-m)
writes for the IDT72V243, (4,096-m) writes for the IDT72V253, (8,192-m)
writesfortheIDT72V263,(16,384-m)writesfortheIDT72V273,(32,768-m)
writesfortheIDT72V283and(65,536-m)writesfortheIDT72V293.Ifbothx9
Inputandx9OutputbusWidthsareselected,(D-m)=(1,024-m)writesforthe
IDT72V223, (2,048-m) writes for the IDT72V233, (4,096-m) writes for the
IDT72V243, (8,192-m) writes for the IDT72V253, (16,384-m) writes for the
OUTPUTS:
FULL FLAG (FF/IR)
Thisisadualpurposepin.InIDTStandardmode,theFullFlag(FF)function
is selected. When the FIFO is full, FF will go LOW, inhibiting further write
operations. WhenFF is HIGH, the FIFOis notfull. Ifnoreads are performed
afterareset(eitherMRS orPRS), FF willgoLOWafterDwrites totheFIFO.
Ifx18Inputorx18Outputbus Widthis selected, D=512forthe IDT72V223,
21
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
configurationisselected,thePAEisupdatedontherisingedgeofRCLK.See
Figure 21, Asynchronous Programmable Almost-Empty Flag Timing (IDT
StandardandFWFTMode),fortherelevanttiminginformation.
IDT72V263,(32,768-m)writesfortheIDT72V273,(65,536-m)writesforthe
IDT72V283and(131,072-m)writesfortheIDT72V293.Theoffset“m”isthe
fulloffsetvalue.ThedefaultsettingforthisvalueisstatedinTable2.
InFWFTmode,ifx18Inputorx18Outputbus Widthis selected,thePAF
willgoLOWafter(513-m)writesfortheIDT72V223,(1,025-m)writesforthe
IDT72V233, (2,049-m) writes for the IDT72V243, (4,097-m) writes for the
IDT72V253, (8,193-m) writes for the IDT72V263, (16,385-m) writes for the
IDT72V273,(32,769-m)writesfortheIDT72V283and(65,537-m)writesfor
theIDT72V293.Ifbothx9Inputandx9OutputbusWidthsareselected,thePAF
willgoLOWafter(1,025-m)writesfortheIDT72V223,(2,049-m)writesforthe
IDT72V233, (4,097-m) writes for the IDT72V243, (8,193-m) writes for the
IDT72V253,(16,385-m)writesfortheIDT72V263,(32,769-m)writesforthe
IDT72V273,(65,537-m)writesfortheIDT72V283and(131,073-m)writesfor
theIDT72V293.Theoffsetmisthefulloffsetvalue.Thedefaultsettingforthis
value is stated in Table 2.
HALF-FULL FLAG (HF)
Thisoutputindicatesahalf-fullFIFO.TherisingWCLKedgethatfillstheFIFO
beyondhalf-fullsetsHFLOW.TheflagremainsLOWuntilthedifferencebetween
thewriteandreadpointersbecomeslessthanorequaltohalfofthetotaldepth
ofthedevice;therisingRCLKedgethataccomplishesthisconditionsetsHF
HIGH.
InIDTStandardmode,ifnoreadsareperformedafterreset(MRSorPRS),
HF will go LOW after (D/2 + 1) writes to the FIFO. If x18 Input or x18 Output
busWidthisselected,D = 512fortheIDT72V223,1,024fortheIDT72V233,
2,048fortheIDT72V243,4,096fortheIDT72V253,8,192fortheIDT72V263,
16,384 for the IDT72V273, 32,768 for the IDT72V283 and 65,536 for the
IDT72V293.Ifbothx9Inputandx9OutputbusWidthsareselected,D=1,024
fortheIDT72V223,2,048fortheIDT72V233,4,096fortheIDT72V243,8,192
for the IDT72V253, 16,384 for the IDT72V263, 32,768 for the IDT72V273,
65,536 for the IDT72V283 and 131,072 for the IDT72V293.
In FWFT mode, if no reads are performed after reset (MRS or PRS), HF
willgoLOWafter(D-1/2 + 2)writestotheFIFO.Ifx18Inputorx18Outputbus
Widthisselected,D=513fortheIDT72V223,1,025fortheIDT72V233,2,049
fortheIDT72V243,4,097fortheIDT72V253,8,193fortheIDT72V263,16,385
fortheIDT72V273,32,769fortheIDT72V283and65,537fortheIDT72V293.
If both x9 Input and x9 Output bus Widths are selected, D = 1,025 for the
IDT72V223,2,049fortheIDT72V233,4,097fortheIDT72V243,8,193forthe
IDT72V253,16,385fortheIDT72V263,32,769fortheIDT72V273,65,537for
the IDT72V283 and 131,073 for the IDT72V293.
SeeFigure18,SynchronousProgrammableAlmost-FullFlagTiming(IDT
StandardandFWFTMode),fortherelevanttiminginformation.
IfasynchronousPAFconfigurationisselected,thePAFisassertedLOW
ontheLOW-to-HIGHtransitionoftheWriteClock(WCLK).PAFisresettoHIGH
ontheLOW-to-HIGHtransitionoftheReadClock(RCLK).IfsynchronousPAF
configurationisselected,thePAFisupdatedontherisingedgeofWCLK.See
Figure 20 for Asynchronous Programmable Almost-Full Flag Timing (IDT
Standard and FWFT Mode).
PROGRAMMABLEALMOST-EMPTYFLAG(PAE)
TheProgrammableAlmost-Emptyflag(PAE)willgoLOWwhentheFIFO
reachesthealmost-emptycondition.InIDTStandardmode,PAEwillgoLOW
whenthere are nwords orless inthe FIFO. The offset“n”is the emptyoffset
value.Thedefaultsettingforthis valueis statedinTable2.
In FWFT mode, the PAE will go LOW when there are n+1 words or less
intheFIFO.Thedefaultsettingforthis valueis statedinTable2.
See Figure 19, Synchronous ProgrammableAlmost-EmptyFlagTiming
(IDTStandardandFWFTMode), forthe relevanttiminginformation.
IfasynchronousPAEconfigurationisselected,thePAEisassertedLOW
ontheLOW-to-HIGHtransitionoftheReadClock(RCLK).PAEisresettoHIGH
ontheLOW-to-HIGHtransitionoftheWriteClock(WCLK).IfsynchronousPAE
See Figure 22, Half-Full Flag Timing (IDT Standard and FWFT Mode),
fortherelevanttiminginformation.BecauseHFisupdatedbybothRCLKand
WCLK,itisconsideredasynchronous.
DATAOUTPUTS(Q0-Qn)
(Q0 -Q17)dataoutputsfor18-bitwidedataor(Q0-Q8)dataoutputsfor9-
bitwidedata.
22
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
D17-D9
D8-D0
BYTE ORDER ON INPUT PORT:
B
A
Write to FIFO
Q17-Q9
Q8-Q0
BYTE ORDER ON OUTPUT PORT:
BE
IW
L
OW
L
A
B
Read from FIFO
L
(a) x18 INPUT to x18 OUTPUT - BIG ENDIAN
Q17-Q9
Q8-Q0
BE
IW
L
OW
L
B
A
Read from FIFO
H
(b) x18 INPUT to x18 OUTPUT - LITTLE ENDIAN
Q8-Q0
Q17-Q9
Q17-Q9
BE
IW
L
OW
H
A
1st: Read from FIFO
2nd: Read from FIFO
L
Q8-Q0
B
(c) x18 INPUT to x9 OUTPUT - BIG ENDIAN
Q17-Q9
Q8-Q0
BE
IW
L
OW
H
B
1st: Read from FIFO
H
Q17-Q9
Q8-Q0
A
2nd: Read from FIFO
(d) x18 INPUT to x9 OUTPUT - LITTLE ENDIAN
D17-D9
D8-D0
BYTE ORDER ON INPUT PORT:
A
1st: Write to FIFO
2nd: Write to FIFO
D17-Q9
D8-Q0
B
BYTE ORDER ON OUTPUT PORT:
Q17-Q9
Q8-Q0
BE
IW OW
A
B
Read from FIFO
L
H
L
(a) x9 INPUT to x18 OUTPUT - BIG ENDIAN
Q17-Q9
Q8-Q0
BE
IW
H
OW
L
A
B
Read from FIFO
H
(a) x9 INPUT to x18 OUTPUT - LITTLE ENDIAN
4666 drw07
Figure 4. Bus-Matching Byte Arrangement
23
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
tRS
MRS
REN
t
RSR
RSR
tRSS
t
tRSS
WEN
tRSR
tRSS
FWFT/SI
tRSR
tRSS
tRSS
tRSS
LD
ASYW,
ASYR
FSEL0,
FSEL1
tRSS
tRSS
tRSS
tRSS
OW, IW
BE
RM
PFM
tRSS
IP
RT
tRSS
tRSS
SEN
t
t
RSF
If FWFT = HIGH, OR = HIGH
If FWFT = LOW, EF = LOW
If FWFT = LOW, FF = HIGH
If FWFT = HIGH, IR = LOW
EF/OR
t
RSF
FF/IR
PAE
RSF
t
RSF
PAF, HF
t
RSF
OE = HIGH
OE = LOW
Q0 - Qn
4666 drw 08
Figure 5. Master Reset Timing
24
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
tRS
PRS
REN
tRSS
tRSR
tRSS
tRSR
WEN
RT
tRSS
tRSS
SEN
t
RSF
If FWFT = HIGH, OR = HIGH
If FWFT = LOW, EF = LOW
If FWFT = LOW, FF = HIGH
If FWFT = HIGH, IR = LOW
EF/OR
tRSF
FF/IR
PAE
tRSF
tRSF
PAF, HF
tRSF
OE = HIGH
OE = LOW
Q0 - Qn
4666 drw09
Figure 6. Partial Reset Timing
25
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
tCLK
tCLKH
tCLKL
NO WRITE
NO WRITE
2
1
WCLK
1
2
t
SKEW1(1)
tDS
t
DH
t
SKEW1(1)
t
DH
tDS
DX
DX+1
WFF
D0 - Dn
t
tWFF
tWFF
tWFF
FF
WEN
RCLK
tENS
tENS
tENH
tENH
REN
tA
tA
Q0
- Qn
NEXT DATA READ
4666 drw10
DATA IN OUTPUT REGISTER
DATA READ
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go high (after one WCLK cycle pus tWFF). If the time between the rising edge
of the RCLK and the rising edge of the WCLK is less than tSKEW1, then the FF deassertion may be delayed one extra WCLK cycle.
2. LD = HIGH, EF = HIGH
Figure 7. Write Cycle and Full Flag Timing (IDT Standard Mode)
tCLK
tCLKH
tCLKL
1
2
RCLK
REN
EF
tENS
tENS
tENH
tENS
tENH
t
ENH
NO OPERATION
NO OPERATION
tREF
tREF
tREF
tA
tA
tA
D0
Q0
- Qn
LAST WORD
D1
LAST WORD
tOLZ
tOLZ
tOHZ
tOE
OE
t
SKEW1(1)
WCLK
tENH
tENH
tENS
tENS
WEN
tDS
tDH
tDHS
tDS
D0
- Dn
D0
D1
4666 drw11
NOTES:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus tREF). If the time between the rising edge
of WCLK and the rising edge of RCLK is less than tSKEW1, then EF deassertion may be delayed one extra RCLK cycle.
2. LD = HIGH.
3. First data word latency: tSKEW1 + 1*TRCLK + tREF.
Figure 8. Read Cycle, Empty Flag and First Data Word Latency Timing (IDT Standard Mode)
26
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
27
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
28
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
1
2
RCLK
tENS
tENH
tENS
tENH
tRTS
REN
tA
tA
tA
1(3)
W
2(3)
Q0 - Qn
Wx
Wx+1
W
tSKEW2
1
2
WCLK
WEN
RT
t
RTS
t
ENS
t
ENH
tREF
t
REF
EF
PAE
HF
tPAES
tHF
tPAFS
PAF
4666 drw14
NOTES:
1. Retransmit setup is complete after EF returns HIGH, only then can a read operation begin.
2. OE = LOW.
3. W1 = first word written to the FIFO after Master Reset, W2 = second word written to the FIFO after Master Reset.
4. No more than D - 2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure.
If x18 Input or x18 Output bus Width is selected, D = 512 for the IDT72V223, 1,024 for the IDT72V233, 2,048 for the IDT72V243, 4,096 for the IDT72V253, 8,192 for the IDT72V263,
16,384 for the IDT72V273, 32,768 for the IDT72V283 and 65,536 for the IDT72V293.
If both x9 Input and x9 Output bus Widths are selected, D = 1,024 for the IDT72V223, 2,048 for the IDT72V233, 4,096 for the IDT72V243, 8,192 for the IDT72V253, 16,384
for the IDT72V263, 32,768 for the IDT72V273, 65,536 for the IDT72V283 and 131,072 for the IDT72V293.
5. There must be at least two words written to and two words read from the FIFO before a Retransmit operation can be invoked.
6. RM is set HIGH during MRS.
Figure 11. Retransmit Timing (IDT Standard Mode)
29
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
3
1
2
4
RCLK
tENH
tENH
tENS
tENS
tRTS
REN
tA
tA
tA
tA
W (4)
1
W
2(4)
W
3(4)
Q0 - Qn
Wx+1
Wx
W4
tSKEW2
1
2
WCLK
tRTS
WEN
tENS
tENH
RT
OR
tREF
tREF
tPAES
PAE
tHF
HF
tPAFS
PAF
4666 drw15
NOTES:
1. Retransmit setup is complete after OR returns LOW.
2. No more than D - 2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup procedure.
If x18 Input or x18 Output bus Width is selected, D = 513 for the IDT72V223, 1,025 for the IDT72V233, 2,049 for the IDT72V243, 4,097 for the IDT72V253, 8,193 for the IDT72V263,
16,385 for the IDT72V273, 32,769 for the IDT72V283 and 65,537 for the IDT72V293.
If both x9 Input and x9 Output bus Widths are selected, D = 1,025 for the IDT72V223, 2,049 for the IDT72V233, 4,097 for the IDT72V243, 8,193 for the IDT72V253, 16,385
for the IDT72V263, 32,769 for the IDT72V273, 65,537 for the IDT72V283 and 131,073 for the IDT72V293.
3. OE = LOW
4. W1, W2, W3 = first, second and third words written to the FIFO after Master Reset.
5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.
6. RM is set HIGH during MRS.
Figure 12. Retransmit Timing (FWFT Mode)
30
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
2
3
1
RCLK
tENH
tENS
REN
tA
tA
tA
tA
tA
(3)
(3)
(3)
Q0 - Qn
Wx
Wx+1
W4
W1
W2
W3
tSKEW2
1
2
WCLK
tRTS
WEN
tENH
tENS
RT
EF(1)
PAE
tPAES
tHF
HF
tPAFS
PAF
4666 drw16
NOTES:
1. If the part is empty at the point of Retransmit, the Empty Flag (EF) will be updated based on RCLK (Retransmit clock cycle). Valid data will also appear on the output.
2. OE = LOW: enables data to be read on outputs Q0-Qn.
3. W1 = first word written to the FIFO after Master Reset, W2 = second word written to the FIFO after Master Reset.
4. No more than D - 2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure.
If x18 Input or x18 Output bus Width is selected, D = 512 for the IDT72V223, 1,024 for the IDT72V233, 2,048 for the IDT72V243, 4,096 for the IDT72V253, 8,192 for the IDT72V263,
16,384 for the IDT72V273, 32,768 for the IDT72V283 and 65,536 for the IDT72V293.
If both x9 Input and x9 Output bus Widths are selected, D = 1,024 for the IDT72V223, 2,048 for the IDT72V233, 4,096 for the IDT72V243, 8,192 for the IDT72V253, 16,384
for the IDT72V263, 32,768 for the IDT72V273, 65,536 for the IDT72V283 and 131,072 for the IDT72V293.
5. There must be at least two words written to and read from the FIFO before a Retransmit operation can be invoked.
6. RM is set LOW during MRS.
Figure 13. Zero Latency Retransmit Timing (IDT Standard Mode)
31
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
4
1
2
5
3
RCLK
tENH
tENS
REN
tA
tA
tA
tA
tA
W
3(3)
2 (3)
W
4(3)
W5
Q0 - Qn
Wx
Wx+1
W1
W
tSKEW2
1
2
WCLK
tRTS
WEN
tENS
tENH
RT
OR
tPAES
PAE
tHF
HF
PAF
tPAFS
4666 drw17
NOTES:
1. If the part is empty at the point of Retransmit, the output ready flag (OR), will be updated based on RCLK (Retransmit clock cycle), valid data will also appear on the output.
2. No more than D - 2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup procedure.
If x18 Input or x18 Output bus Width is selected, D = 513 for the IDT72V223, 1,025 for the IDT72V233, 2,049 for the IDT72V243, 4,097 for the IDT72V253, 8,193 for the IDT72V263,
16,385 for the IDT72V273, 32,769 for the IDT72V283 and 65,537 for the IDT72V293.
If both x9 Input and x9 Output bus Widths are selected, D = 1,025 for the IDT72V223, 2,049 for the IDT72V233, 4,097 for the IDT72V243, 8,193 for the IDT72V253, 16,385
for the IDT72V263, 32,769 for the IDT72V273, 65,537 for the IDT72V283 and 131,073 for the IDT72V293.
3. OE = LOW
4. W1, W2, W3 = first, second and third words written to the FIFO after Master Reset.
5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.
6. RM is set LOW during MRS.
Figure 14. Zero Latency Retransmit Timing (FWFT Mode)
WCLK
tENH
tENS
tENH
SEN
LD
t
LDH
tLDS
t
LDH
tDS
t
DH
BIT X(1)
BIT 0
BIT X(1)
BIT 0
SI
4666 drw18
FULL OFFSET
EMPTY OFFSET
NOTES:
1. x9 to x9 mode: X = 9 for the IDT72V223, X = 10 for the IDT72V233, X = 11 for the IDT72V243, X = 12 for the IDT72V253, X = 13 for the IDT72V263, X = 14 for the IDT72V273,
X = 15 for the IDT72V283 and X = 16 for the IDT72V293.
2. All other modes: X = 8 for the IDT72V223, X = 9 for the IDT72V233, X = 10 for the IDT72V243, X = 11 for the IDT72V253, X = 12 for the IDT72V263, X = 13 for the IDT72V273,
X = 14 for the IDT72V283 and X = 15 for the IDT72V293.
Figure 15. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
32
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
tCLK
tCLKH
tCLKL
WCLK
LD
tLDS
t
LDH
tLDH
t
ENS
tENH
t
ENH
DH
WEN
tDS
tDS
tDS
tDS
t
t
DH
t
DH
tDH
D0
- D16
4666 drw19
PAE OFFSET (LSB)
PAE OFFSET (MSB)
PAF OFFSET (LSB)
PAF OFFSET (MSB)
NOTE:
1. This diagram is based on programming the IDT72V293 x18 bus width. Add one extra cycle to both the PAE offset and PAF offset for x9 bus width.
Figure 16. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
tCLK
tCLKH
tCLKL
RCLK
tLDS
tENS
tLDH
tLDH
tENH
LD
tENH
REN
tA
tA
tA
PAE OFFSET
tA
PAE OFFSET
(MSB)
PAF OFFSET
(LSB)
PAF OFFSET
(MSB)
DATA IN OUTPUT
REGISTER
Q0
- Q16
(LSB)
4666 drw20
NOTES:
1. OE = LOW.
2. This diagram is based on programming the IDT72V293 x18 bus width. Add one extra cycle to both the PAE offset and PAF offset for x9 bus width.
Figure 17. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes)
tCLKH
tCLKL
WCLK
WEN
PAF
1
2
2
1
tENS
tENH
tPAFS
tPAFS
2)
D-(m+1) words in FIFO(
D - m words in FIFO(2)
D-(m+1) words
2)
in FIFO(
t
SKEW2(3)
RCLK
tENH
tENS
4666 drw21
REN
NOTES:
1. m = PAF offset .
2. D = maximum FIFO depth.
In IDT Standard mode: if x18 Input or x18 Output bus Width is selected, D = 512 for the IDT72V223, 1,024 for the IDT72V233, 2,048 for the IDT72V243, 4,096 for the IDT72V253,
8,192 for the IDT72V263, 16,384 for the IDT72V273, 32,768 for the IDT72V283 and 65,536 for the IDT72V293. If both x9 Input and x9 Output bus Widths are selected, D = 1,024
for the IDT72V223, 2,048 for the IDT72V233, 4,096 for the IDT72V243, 8,192 for the IDT72V253, 16,384 for the IDT72V263, 32,768 for the IDT72V273, 65,536 for the IDT72V283
and 131,072 for the IDT72V293.
In FWFT mode: if x18 Input or x18 Output bus Width is selected, D = 513 for the IDT72V223, 1,025 for the IDT72V233, 2,049 for the IDT72V243, 4,097 for the IDT72V253, 8,193
for the IDT72V263, 16,385 for the IDT72V273, 32,769 for the IDT72V283 and 65,537 for the IDT72V293. If both x9 Input and x9 Output bus Widths are selected, D = 1,025 for the
IDT72V223, 2,049 for the IDT72V233, 4,097 for the IDT72V243, 8,193 for the IDT72V253, 16,385 for the IDT72V263, 32,769 for the IDT72V273, 65,537 for the IDT72V283 and 131,073
for the IDT72V293.
3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus tPAFS). If the time between the
rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then the PAF deassertion time may be delayed one extra WCLK cycle.
4. PAF is asserted and updated on the rising edge of WCLK only.
5. Select this mode by setting PFM HIGH during Master Reset.
Figure 18. Synchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
33
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
tCLKH
tCLKL
WCLK
tENS
tENH
WEN
PAE
n words in FIFO (2)
n+1 words in FIFO (3)
,
n words in FIFO (2)
,
n+1 words in FIFO (2)
n+2 words in FIFO (3)
,
n+1 words in FIFO(3)
SKEW2(4)
tPAES
t
tPAES
1
2
1
2
RCLK
tENH
tENS
4666 drw22
REN
NOTES:
1. n = PAE offset.
2. For IDT Standard mode
3. For FWFT mode.
4. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH (after one RCLK cycle plus tPAES). If the time between the rising
edge of WCLK and the rising edge of RCLK is less than tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.
5. PAE is asserted and updated on the rising edge of WCLK only.
6. Select this mode by setting PFM HIGH during Master Reset.
Figure 19. Synchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
tCLKL
tCLKH
WCLK
tENS
tENH
WEN
PAF
tPAFA
D m words
D (m + 1)
words in FIFO
D (m + 1) words in FIFO
in FIFO
tPAFA
RCLK
tENS
REN
4666 drw23
NOTES:
1. m = PAF offset.
2. D = maximum FIFO Depth.
In IDT Standard mode: if x18 Input or x18 Output bus Width is selected, D = 512 for the IDT72V223, 1,024 for the IDT72V233, 2,048 for the IDT72V243, 4,096 for the IDT72V253,
8,192 for the IDT72V263, 16,384 for the IDT72V273, 32,768 for the IDT72V283 and 65,536 for the IDT72V293. If both x9 Input and x9 Output bus Widths are selected, D = 1,024
for the IDT72V223, 2,048 for the IDT72V233, 4,096 for the IDT72V243, 8,192 for the IDT72V253, 16,384 for the IDT72V263, 32,768 for the IDT72V273, 65,536 for the IDT72V283
and 131,072 for the IDT72V293.
In FWFT mode: if x18 Input or x18 Output bus Width is selected, D = 513 for the IDT72V223, 1,025 for the IDT72V233, 2,049 for the IDT72V243, 4,097 for the IDT72V253, 8,193
for the IDT72V263, 16,385 for the IDT72V273, 32,769 for the IDT72V283 and 65,537 for the IDT72V293. If both x9 Input and x9 Output bus Widths are selected, D = 1,025 for the
IDT72V223, 2,049 for the IDT72V233, 4,097 for the IDT72V243, 8,193 for the IDT72V253, 16,385 for the IDT72V263, 32,769 for the IDT72V273, 65,537 for the IDT72V283 and 131,073
for the IDT72V293.
3. PAF is asserted to LOW on WCLK transition and reset to HIGH on RCLK transition.
4. Select this mode by setting PFM LOW during Master Reset.
Figure 20. Asynchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
34
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
tCLKH
tCLKL
WCLK
tENS
tENH
WEN
tPAEA
(2)
(2)
n words in FIFO
,
n words in FIFO
,
(2)
n+1wordsinFIFO
,
(3)
(3)
PAE
RCLK
REN
n + 1 words in FIFO
n + 1 words in FIFO
(3)
n+2wordsinFIFO
tPAEA
tENS
4666 drw24
NOTES:
1. n = PAE offset.
2. For IDT Standard Mode.
3. For FWFT Mode.
4. PAE is asserted LOW on RCLK transition and reset to HIGH on WCLK transition.
5. Select this mode by setting PFM LOW during Master Reset.
Figure 21. Asynchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
tCLKH
tCLKL
WCLK
tENH
tENS
WEN
HF
D
2
D + 1
2
tHF
[
+ 1
]
words in FIFO(1)
+ 1 words in FIFO(2)
,
D/2 words in FIFO(1)
,
D/2 words in FIFO(1)
,
[
]
D + 1
2
D + 1
2
[
]
words in FIFO(2)
[
]
words in FIFO(2)
tHF
RCLK
tENS
REN
4666 drw25
NOTES:
1. In IDT Standard mode: D = maximum FIFO depth. If x18 Input or x18 Output bus Width is selected, D = 512 for the IDT72V223, 1,024 for the IDT72V233, 2,048 for the IDT72V243,
4,096 for the IDT72V253, 8,192 for the IDT72V263, 16,384 for the IDT72V273, 32,768 for the IDT72V283 and 65,536 for the IDT72V293. If both x9 Input and x9 Output bus Widths
are selected, D = 1,024 for the IDT72V223, 2,048 for the IDT72V233, 4,096 for the IDT72V243, 8,192 for the IDT72V253, 16,384 for the IDT72V263, 32,768 for the IDT72V273,
65,536 for the IDT72V283 and 131,072 for the IDT72V293.
2. In FWFT mode: D = maximum FIFO depth. If x18 Input or x18 Output bus Width is selected, D = 513 for the IDT72V223, 1,025 for the IDT72V233, 2,049 for the IDT72V243, 4,097
for the IDT72V253, 8,193 for the IDT72V263, 16,385 for the IDT72V273, 32,769 for the IDT72V283 and 65,537 for the IDT72V293. If both x9 Input and x9 Output bus Widths are
selected, D = 1,025 for the IDT72V223, 2,049 for the IDT72V233, 4,097 for the IDT72V243, 8,193 for the IDT72V253, 16,385 for the IDT72V263, 32,769 for the IDT72V273, 65,537
for the IDT72V283 and 131,073 for the IDT72V293.
Figure 22. Half-Full Flag Timing (IDT Standard and FWFT Modes)
35
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
RCLK
tENS
tENH
tA
REN
Qn
W0
W1
tFFA
FF
tFFA
tFFA
tCYC
WR
tCYH
tDS
tDH
WD
Dn
WD+1
4666 drw26
NOTE:
1. OE = LOW and WEN = LOW.
Figure 23. Asynchronous Write, Synchronous Read, Full Flag Operation (IDT Standard Mode)
1
2
RCLK
tENS
tENH
REN
tA
tA
Last Word
W1
W0
Qn
tREF
tREF
EF
tCYL
tSKEW
WR
tCYH
tCYC
tDH
tDH
tDS
tDS
W0
W1
Dn
4666 drw27
NOTE:
1. OE = LOW and WEN = LOW.
Figure 24. Asynchronous Write, Synchronous Read, Empty Flag Operation (IDT Standard Mode)
36
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
No Write
1
WCLK
WEN
Dn
2
DF+1
DF
tWFF
tWFF
FF
tCYC
tSKEW
tCYL
tCYH
RD
Qn
tAA
t
AA
Last Word
WX
WX+1
4666 drw28
NOTE:
1. OE = LOW and REN = LOW.
2. Asynchronous Read is available in IDT Standard Mode only.
Figure 25. Synchronous Write, Asynchronous Read, Full Flag Operation (IDT Standard Mode)
WCLK
WEN
Dn
t
ENS
t
ENH
t
DS
t
DH
W0
tEFA
EF
tEFA
tRPE
RD
Qn
tCYH
tAA
Last Word in Output Register
W0
4666 drw29
NOTE:
1. OE = LOW and REN = LOW.
2. Asynchronous Read is available in IDT Standard Mode only.
Figure 26. Synchronous Write, Asynchronous Read, Empty Flag Operation (IDT Standard Mode)
37
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
tCYC
tCYH
tCYL
WR
Dn
tDH
tDH
tDS
W0
W1
RD
Qn
tAA
tAA
W1
W0
Last Word in O/P Register
tRPE
tEFA
tEFA
EF
4666 drw30
NOTES:
1. OE = LOW, WEN = LOW, and REN = LOW.
2. Asynchronous Read is available in IDT Standard Mode only.
Figure 27. Asynchronous Write, Asynchronous Read, Empty Flag Operation (IDT Standard Mode)
tCYC
tCYH
tCYL
WR
Dn
tDH
tDH
tDS
tDS
W
y+1
Wy
tCYC
tCYH
tCYL
RD
Qn
tAA
tAA
Wx
Wx+1
Wx+2
tFFA
tFFA
FF
4666 drw31
NOTES:
1. OE = LOW, WEN = LOW, and REN = LOW.
2. Asynchronous Read is available in IDT Standard Mode only.
Figure 28. Asynchronous Write, Asynchronous Read, Full Flag Operation (IDT Standard Mode)
38
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
compositeflags canbecreatedbyORingOR ofeveryFIFO,andseparately
ORing IR of every FIFO.
OPTIONAL CONFIGURATIONS
WIDTH EXPANSION CONFIGURATION
Figure29demonstratesawidthexpansionusingtwoIDT72V223/72V233/
72V243/72V253/72V263/72V273/72V283/72V293 devices. If x18 Input or
x18OutputbusWidthisselected,D0-D17 fromeachdeviceforma36-bitwide
inputbusandQ0-Q17 fromeachdeviceforma36-bitwideoutputbus.Ifboth
x9Inputandx9OutputbusWidthsareselected,D0-D8fromeachdeviceform
an18-bitwideinputbusandQ0-Q8fromeachdeviceforman18-bitwideoutput
bus.AnywordwidthcanbeattainedbyaddingadditionalIDT72V223/72V233/
72V243/72V253/72V263/72V273/72V283/72V293devices.
Wordwidthmaybe increasedsimplybyconnectingtogetherthe control
signals of multiple devices. Status flags can be detected from any one
device. The exceptions are the EF and FF functions in IDT Standard mode
and the IR and OR functions in FWFT mode. Because of variations in skew
between RCLK and WCLK, it is possible for EF/FF deassertion and IR/OR
assertiontovarybyone cycle betweenFIFOs. InIDTStandardmode, such
problems can be avoided by creating composite flags, that is, ANDing EF
of every FIFO, and separately ANDing FF of every FIFO. In FWFT mode,
PARTIAL RESET (PRS)
MASTER RESET (MRS)
FIRST WORD FALL THROUGH/
SERIAL INPUT (FWFT/SI)
RETRANSMIT (RT)
Dm+1 - Dn
m
D0 - Dm
m + n
n
DATA IN
READ CLOCK (RCLK)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
LOAD (LD)
READ ENABLE (REN)
IDT
IDT
72V223
72V233
72V243
72V253
72V263
72V273
72V283
72V293
72V223
OUTPUT ENABLE (OE)
72V233
72V243
PROGRAMMABLE (PAE)
72V253
FULL FLAG/INPUT READY (FF/IR) #1
FULL FLAG/INPUT READY (FF/IR) #2
72V263
EMPTY FLAG/OUTPUT READY (EF/OR) #1
(1)
GATE
72V273
(1)
72V283
GATE
EMPTY FLAG/OUTPUT READY (EF/OR) #2
72V293
PROGRAMMABLE (PAF)
HALF-FULL FLAG (HF)
n
m + n
Qm+1 - Qn
DATA OUT
m
FIFO
#1
FIFO
#2
4666 drw32
Q0 - Qm
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
Figure 29. Block Diagram of Width Expansion
For the x18 Input or x18 Output bus Width: 512 x 36, 1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36 and 65,536 x 36
For both x9 Input and x9 Output bus Widths: 1,024 x 18, 2,048 x 18, 4,096 x 18, 8,192 x 18, 16,284 x 18, 32,768 x 18, 65,536 x 18 and 131,072 x 18
39
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
FWFT/SI
TRANSFER CLOCK
FWFT/SI
FWFT/SI
READ CLOCK
RCLK
WRITE CLOCK
WCLK
WEN
IR
RCLK
WCLK
IDT
IDT
READ ENABLE
WRITE ENABLE
INPUT READY
OR
WEN
REN
72V223
72V233
72V243
72V253
72V263
72V273
72V283
72V293
72V223
72V233
72V243
72V253
72V263
72V273
72V283
72V293
OUTPUT READY
REN
OR
IR
OUTPUT ENABLE
OE
OE
GND
n
DATA OUT
n
n
DATA IN
Dn
Qn
Qn
Dn
4666 drw33
Figure 30. Block Diagram of Depth Expansion
For the x18 Input or x18 Output bus Width: 1,024 x 18, 2,048 x 18, 4,096 x 18, 8,192 x 18, 16,384 x 18, 32,768 x 18, 65,536 x 18 and 131,072 x 18
For both x9 Input and x9 Output bus Widths: 2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9, 65,536 x 9, 131,072 x 9 and 262,144 x 9
DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY)
Note that extra cycles should be added for the possibility that the tSKEW1
The IDT72V223 can easily be adapted to applications requiring depths specificationisnotmetbetweenWCLKandtransferclock,orRCLKandtransfer
greaterthan512whenthex18Inputorx18OutputbusWidthisselected,1,024 clock,fortheORflag.
fortheIDT72V233,2,048fortheIDT72V243,4,096fortheIDT72V253,8,192
The"rippledown"delayisonlynoticeableforthefirstwordwrittentoanempty
fortheIDT72V263,16,384fortheIDT72V273,32,768fortheIDT72V283and depthexpansionconfiguration.Therewillbenodelayevidentforsubsequent
65,536fortheIDT72V293.Whenbothx9Inputandx9OutputbusWidthsare wordswrittentotheconfiguration.
selected,depthsgreaterthan1,024canbeadaptedfortheIDT72V223,2,048
The first free location created by reading from a full depth expansion
fortheIDT72V233,4,096fortheIDT72V243,8,192fortheIDT72V253,16,384 configuration will "bubble up" from the last FIFO to the previous one until it
fortheIDT72V263,32,768fortheIDT72V273,65,536fortheIDT72V283and finally moves into the first FIFO of the chain. Each time a free location is
131,072fortheIDT72V293.InFWFTmode,theFIFOs canbeconnectedin createdinoneFIFOofthechain,thatFIFO'sIRlinegoesLOW,enablingthe
series(thedataoutputsofoneFIFOconnectedtothedatainputsofthenext) preceding FIFO to write a word to fill it.
withnoexternallogicnecessary.Theresultingconfigurationprovidesatotal
Forafullexpansionconfiguration,theamountoftimeittakesforIRofthefirst
depthequivalenttothesumofthedepths associatedwitheachsingleFIFO. FIFOinthechaintogoLOWafterawordhasbeenreadfromthelastFIFOis
Figure30showsadepthexpansionusingtwoIDT72V223/72V233/72V243/ the sumofthe delays foreachindividualFIFO:
72V253/72V263/72V273/72V283/72V293devices.
CareshouldbetakentoselectFWFTmodeduringMasterResetforallFIFOs
in the depth expansion configuration. The first word written to an empty
(N – 1)*(3*transfer clock) + 2 TWCLK
configurationwillpassfromoneFIFOtothenext("rippledown")untilitfinally where N is the number of FIFOs in the expansion and TWCLK is the WCLK
appears at the outputs of the last FIFO in the chain–no read operation is period.NotethatextracyclesshouldbeaddedforthepossibilitythatthetSKEW1
necessarybuttheRCLKofeachFIFOmustbefree-running.Eachtimethedata specificationisnotmetbetweenRCLKandtransferclock,orWCLKandtransfer
word appears at the outputs of one FIFO, that device's OR line goes LOW, clock,fortheIRflag.
enabling a write to the next FIFO in line.
TheTransferClocklineshouldbetiedtoeitherWCLKorRCLK,whichever
Foranemptyexpansionconfiguration,theamountoftimeittakesforORof isfaster.Boththeseactionsresultindatamoving,asquicklyaspossible,tothe
thelastFIFOinthechaintogoLOW(i.e.validdatatoappearonthelastFIFO's endofthechainandfreelocations tothebeginningofthechain.
outputs)afterawordhasbeenwrittentothefirstFIFOisthesumofthedelays
for each individual FIFO:
(N – 1)*(4*transfer clock) + 3*TRCLK
whereNisthenumberofFIFOsintheexpansionandTRCLKistheRCLKperiod.
40
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
tTCK
t
4
t
3
t
1
t
2
TCK
TDI/
TMS
tDS
tDH
TDO
TDO
t
6
tDO
4666 drw34
TRST
Notes to diagram:
t1 = tTCKLOW
t2 = tTCKHIGH
t
5
t3 = tTCKFALL
t4 = tTCKRise
t5 = tRST (reset pulse width)
t6 = tRSR (reset recovery)
Figure 31. Standard JTAG Timing
JTAGACELECTRICAL
CHARACTERISTICS
SYSTEMINTERFACEPARAMETERS
(VCC = 3.3V ± 5%; Tcase = 0°C to +85°C)
IDT72V223
IDT72V233
IDT72V243
IDT72V253
IDT72V263
IDT72V273
IDT72V283
IDT72V293
Parameter
Symbol
Test
Conditions Min. Max. Units
JTAGClockInputPeriod tTCK
-
-
-
-
-
-
-
100
40
40
-
-
-
ns
ns
ns
ns
ns
ns
ns
JTAGClockHIGH
JTAGClockLow
tTCKHIGH
tTCKLOW
tTCKRise
tTCKFall
tRST
-
JTAGClockRiseTime
JTAGClockFallTime
JTAGReset
5(1)
5(1)
-
Parameter
Symbol Test Conditions Min. Max. Units
DataOutput
tDO = Max
-
20
-
ns
ns
ns
-
(1)
DataOutputHold tDOH
0
50
50
DataInput
tDS
tDH
trise=3ns
tfall=3ns
10
10
-
-
JTAG Reset Recovery
tRSR
-
NOTE:
1. Guaranteed by design.
NOTE:
1. 50pf loading on external output signals.
41
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
TheStandardJTAGinterfaceconsistsoffourbasicelements:
JTAGINTERFACE
•
•
•
•
Test Access Port (TAP)
TAPcontroller
Instruction Register (IR)
Data Register Port (DR)
Five additional pins (TDI, TDO, TMS, TCK and TRST) are provided to
supporttheJTAGboundaryscaninterface.TheIDT72V223/72V233/72V243/
72V253/72V263/72V273/72V283/72V293 incorporates the necessary tap
controllerandmodifiedpadcellstoimplementtheJTAG facility.
NotethatIDTprovidesappropriateBoundaryScanDescriptionLanguage
programfilesforthesedevices.
Thefollowingsectionsprovideabriefdescriptionofeachelement. Fora
completedescriptionrefertotheIEEEStandardTestAccessPortSpecification
(IEEEStd. 1149.1-1990).
The Figure belowshows the standardBoundary-ScanArchitecture
DeviceID Reg.
Mux
Boundary Scan Reg.
Bypass Reg.
TDO
TDI
T
A
clkDR, ShiftDR
UpdateDR
P
TMS
TAP
TCLK
Cont-
roller
TRST
Instruction Decode
clklR, ShiftlR
UpdatelR
Instruction Register
Control Signals
4666 drw35
Figure 32. Boundary Scan Architecture
THETAPCONTROLLER
TEST ACCESS PORT (TAP)
TheTapcontrollerisasynchronousfinitestatemachinethatrespondsto
TMSandTCLKsignalstogenerateclockandcontrolsignalstotheInstruction
andDataRegisters forcaptureandupdateofdata.
The Tap interface is a general-purpose port that provides access to the
internaloftheprocessor. Itconsistsoffourinputports(TCLK,TMS,TDI,TRST)
and one output port (TDO).
42
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
1
Test-Logic
Reset
0
1
Select-
IR-Scan
0
1
1
Run-Test/
Idle
Select-
DR-Scan
0
0
1
1
Capture-DR
Capture-IR
0
0
0
0
Shift-DR
Shift-IR
1
1
1
1
Input = TMS
Exit1-IR
EXit1-DR
0
0
0
0
Pause-DR
Pause-IR
1
1
Exit2-IR
Exit2-DR
0
0
1
1
Update-DR
Update-IR
1
0
1
0
4666 drw36
NOTES:
1. Five consecutive TCK cycles with TMS = 1 will reset the TAP.
2. TAP controller does not automatically reset upon power-up. The user must provide a reset to the TAP controller (either by TRST or TMS).
3. TAP controller must be reset before normal FIFO operations can begin.
Figure 33. TAP Controller State Diagram
UPDATE-DR
The shifting process has been completed. The data is latched into their
Refer to the IEEE Standard Test Access Port Specification (IEEE Std.
1149.1)forthefullstatediagram
paralleloutputsinthisstatetobeaccessedthroughtheinternalbus.
AllstatetransitionswithintheTAPcontrolleroccurattherisingedgeofthe
TCLKpulse. TheTMSsignallevel(0or1)determinesthestateprogression
thatoccursoneachTCLKrisingedge. TheTAPcontrollertakesprecedence
overtheFIFOmemoryandmustberesetafterpowerupofthedevice. See
TRSTdescriptionformoredetailsonTAPcontrollerreset.
EXIT1-DR / EXIT2-DR
Thisisatemporarycontrollerstate.IfTMSisheldhigh,arisingedgeapplied
toTCKwhileinthisstatecausesthecontrollertoentertheUpdate-DRstate.This
terminatesthescanningprocess.Alltestdataregistersselectedbythecurrent
instructionretaintheirpreviousstateunchanged.
CAPTURE-DR
Data is loaded from the parallel input pins or core outputs into the Data
Register.
PAUSE-DR
Thiscontrollerstateallowsshiftingofthetestdataregisterintheserialpath
betweenTDIandTDOtobetemporarilyhalted.Alltestdataregistersselected
bythecurrentinstructionretaintheirpreviousstateunchanged.
SHIFT-DR
Thepreviouslycaptureddataisshiftedinserially,LSBfirstattherisingedge
ofTCLKintheTDI/TDOpathandshiftedoutserially,LSBfirstatthefallingedge
ofTCLKtowardstheoutput.
Capture-IR, Shift-IR and Update-IR, Exit-IR and Pause-IR are
similartoDataregisters.Theseinstructionsoperateontheinstructionregisters.
43
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
THE INSTRUCTION REGISTER
31(MSB)
Version (4 bits) Part Number (16-bit) Manufacturer ID (11-bit)
0X0 0X33
28 27
12 11
1 0(LSB)
TheInstructionregisterallowsaninstructiontobeshiftedinseriallyintothe
processor at the rising edge of TCLK.
1
TheInstructionis usedtoselectthetesttobeperformed,orthetestdata
registertobeaccessed,orboth. Theinstructionshiftedintotheregisterislatched
atthecompletionoftheshiftingprocesswhentheTAPcontrollerisatUpdate-
IRstate.
Theinstructionregistermustcontain4bitinstructionregister-basedcells
whichcanholdinstructiondata. Thesemandatorycellsarelocatednearestthe
serialoutputstheyaretheleastsignificantbits.
IDT72V223/233/243/253/263/273/283/293JTAGDeviceIdentificationRegister
JTAG INSTRUCTION REGISTER
TheInstructionregisterallowsinstructiontobeseriallyinputintothedevice
whentheTAPcontrollerisintheShift-IRstate. Theinstructionisdecodedto
performthefollowing:
•
Selecttestdataregistersthatmayoperatewhiletheinstructionis
current. Theothertestdataregistersshouldnotinterferewithchip
operationandtheselecteddataregister.
Definetheserialtestdataregisterpaththatisusedtoshiftdatabetween
TDI and TDO during data register scanning.
TESTDATAREGISTER
•
TheTestDataregistercontainsthreetestdataregisters:theBypass,the
Boundary Scan register and Device ID register.
Theseregistersareconnectedinparallelbetweenacommonserialinput
andacommonserialdataoutput.
The Instruction Register is a 4 bit field (i.e. IR3, IR2, IR1, IR0) to decode
16differentpossibleinstructions. Instructionsaredecodedasfollows.
Thefollowingsectionsprovideabriefdescriptionofeachelement. Fora
completedescription,refertotheIEEEStandardTestAccessPortSpecification
(IEEEStd. 1149.1-1990).
Hex
Value
0x00
0x02
0x01
0x03
0x0F
Instruction
Function
EXTEST
IDCODE
SelectBoundaryScanRegister
SelectChipIdentificationdataregister
SAMPLE/PRELOAD SelectBoundaryScanRegister
HI-Z
BYPASS
TEST BYPASS REGISTER
JTAG
SelectBypassRegister
TheregisterisusedtoallowtestdatatoflowthroughthedevicefromTDI
toTDO. Itcontainsasinglestageshiftregisterforaminimumlengthinserialpath.
Whenthebypassregisterisselectedbyaninstruction,theshiftregisterstage
is settoa logiczeroonthe risingedge ofTCLKwhenthe TAPcontrolleris in
theCapture-DRstate.
Table 6. JTAG Instruction Register Decoding
Thefollowingsectionsprovideabriefdescriptionofeachinstruction. For
acompletedescriptionrefertotheIEEEStandardTestAccessPortSpecification
(IEEEStd. 1149.1-1990).
The operation of the bypass register should not have any effect on the
operationofthedeviceinresponsetotheBYPASSinstruction.
THE BOUNDARY-SCAN REGISTER
EXTEST
TheBoundaryScanRegisterallowsserialdataTDIbeloadedintoorread
outoftheprocessorinput/outputports. TheBoundaryScanRegisterisapart
oftheIEEE1149.1-1990StandardJTAGImplementation.
The mandatoryEXTESTinstructionis providedforexternalcircuityand
boardlevelinterconnectioncheck.
IDCODE
THE DEVICE IDENTIFICATION REGISTER
ThisinstructionisprovidedtoselectDeviceIdentificationRegistertoread
outmanufacture’sidentity,partnumberandversionnumber.
The Device IdentificationRegisteris a ReadOnly32-bitregisterusedto
specify the manufacturer, part number and version of the processor to be
determinedthroughtheTAPinresponsetotheIDCODEinstruction.
IDT JEDEC ID number is 0xB3. This translates to 0x33 when the parity
is droppedinthe11-bitManufacturerIDfield.
SAMPLE/PRELOAD
ThemandatorySAMPLE/PRELOADinstructionallowsdatavaluestobe
loadedontothelatchedparalleloutputsoftheboundary-scanshiftregisterprior
toselectionofthe boundary-scantestinstruction. The SAMPLEinstruction
allowsasnapshotofdataflowingfromthesystempinstotheon-chiplogicorvice
versa.
FortheIDT72V223/72V233/72V243/72V253/72V263/72V273/72V283/
72V293,thePartNumberfieldcontainsthefollowingvalues:
Device
Part# Field
04EF
04EE
04ED
04EC
04EB
04EA
04E9
IDT72V223
IDT72V233
IDT72V243
IDT72V253
IDT72V263
IDT72V273
IDT72V283
IDT72V293
HIGH-Z
Thisinstructionplacesalltheoutputpinsonthedeviceintoahighimpedance
state.
BYPASS
TheBypassinstructioncontainsasingleshift-registerstageandissetto
provideaminimum-lengthserialpathbetweentheTDIandtheTDOpinsofthe
device whennotestoperationofthe device is required.
04E8
44
ORDERINGINFORMATION
IDT
XXXXX
X
XX
X
X
Process /
Temperature
Range
Device Type
Power
Speed
Package
BLANK
I(1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
PF
BC
Thin Plastic Quad Flatpack (TQFP, PN80-1)
Ball Grid Array (BGA, BC100-1)
Commercial, BGA & TQFP Only
6
Clock Cycle Time (tCLK
Speed in Nanoseconds
)
Commercial, BGA & TQFP Only
Com’l & Ind’l, TQFP Only
Commercial, TQFP Only
7-5
10
15
L
Low Power
72V223(2)
72V233(2)
72V243(2)
72V253(2)
72V263
72V273
72V283
72V293
512 x 18/1,024 x 9 3.3V SuperSync II FIFO
1,024 x 18/2,048 x 9 3.3V SuperSync II FIFO
2,048 x 18/4,096 x 9 3.3V SuperSync II FIFO
4,096 x 18/8,192 x 9 3.3V SuperSync II FIFO
8,192 x 18/16,384 x 9 3.3V SuperSync II FIFO
16,384 x 18/32,768 x 9 3.3V SuperSync II FIFO
32,768 x 18/65,536 x 9 3.3V SuperSync II FIFO
65,536 x 18/131,072 x 9 3.3V SuperSync II FIFO
4666 drw37
NOTE:
1. Industrial temperature range product for the 10ns is available as a standard device. All other speed grades are available by special order.
2. The IDT72V223/72V233/72V243/72V253 are only available in 6ns and 7.5ns speed grades.
DATASHEETDOCUMENTHISTORY
12/18/2000
03/27/2001
04/06/2001
12/14/2001
12/20/2001
02/01/2002
03/25/2002
05/24/2002
01/20/2003
02/11/2003
07/15/2003
09/29/2003
pgs.7, 8, 9, and 37.
pgs.9, and 37.
pgs.4, 5, and 21.
pgs.1-45.
pg. 9.
pgs.9, and 45.
pgs.2, and 41.
pgs.3, and 11.
pgs.1, 7, 9, 10, and 15.
pgs.7, and 43.
pgs.3, 19, and 36-38.
pg. 8.
CORPORATE HEADQUARTERS
2975 Stender Way
Santa Clara, CA 95054
for SALES:
for Tech Support:
408-330-1753
email: FIFOhelp@idt.com
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
45
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