IDT71V433S12PFG [IDT]
Cache SRAM, 32KX32, 12ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100;
| 型号： | IDT71V433S12PFG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Cache SRAM, 32KX32, 12ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100 静态存储器 内存集成电路 |
| 文件： | 总19页 (文件大小：625K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT71V433
32K x 32
3.3V Synchronous SRAM
Flow-Through Outputs
Features
◆
32K x 32 memory configuration
The IDT71V433 SRAM contains write, data-input, address and
controlregisters.There are noregisters inthe data outputpath(flow-
througharchitecture). Internallogicallows the SRAMtogenerate a
self-timed write based upon a decision which can be left until the
extreme end of the write cycle.
The burstmode feature offers the highestlevelofperformance to
thesystemdesigner,astheIDT71V433canprovidefourcyclesofdata
forasingleaddresspresentedtotheSRAM. Aninternalburstaddress
counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe
access sequence.Thefirstcycleofoutputdatawillflow-throughfrom
the arrayaftera clock-to-data access time delayfromthe risingclock
edgeofthesamecycle. Ifburstmodeoperationisselected(ADV=LOW),
the subsequent three cycles of output data will be available to the
user on the next three rising clock edges. The order of these three
addresses willbe definedbythe internalburstcounterandthe LBO
inputpin.
◆
Supports high performance system speed:
CommercialandIndustrial:
— 11 11ns Clock-to-DataAccess (50MHz)
— 12 12ns Clock-to-DataAccess (50MHz)
LBO input selects interleaved or linear burst mode
◆
◆
Self-timed write cycle with global write control (GW), byte
write enable (BWE), and byte writes (BWx)
Power down controlled by ZZ input
Single 3.3V power supply (+10/-5%)
Packaged in a JEDEC Standard 100-pin rectangular plastic
◆
◆
◆
thin quad flatpack (TQFP).
Description
The IDT71V433 is a 3.3V high-speed 1,048,576-bit SRAM orga-
nized as 32K x 32 with full support of various processor interfaces
includingthePentium™andPowerPC™.Theflow-throughburstarchi-
tectureprovidescost-effective2-1-1-1performanceforprocessorsupto
50MHz.
The IDT71V433 SRAM utilizes IDT's high-performance 3.3V
CMOSprocess,andispackagedinaJEDECStandard14mmx20mm
100-pinthinplasticquadflatpack(TQFP).
PinDescription
A0–A14
Address Inputs
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Synchronous
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Chip Enable
CE
CS
0
, CS
1
Chips Selects
Output Enable
OE
GW
Global Write Enable
Byte Write Enable
BWE
BW –BW
Individual Byte Write Selects
Clock Input
1
4
CLK
Burst Address Advance
Address Status (Cache Controller)
Address Status (Processor)
Linear / Interleaved Burst Order
Sleep Mode
Synchronous
Synchronous
Synchronous
DC
ADV
ADSC
ADSP
LBO
ZZ
Asynchronous
Synchronous
N/A
I/O
0
–I/O31
DD, VDDQ
SS, VSSQ
Data Input/Output
V
Core and I/O Power Supply (3.3V)
Array Ground, I/O Ground
Power
Power
V
N/A
3729 tbl 01
PentiumisatrademarkofIntelCorp.
PowerPCisatrademarkofInternationalBusinessMachines,Inc.
AUGUST 2001
1
DSC-3729/04
©2000IntegratedDeviceTechnology,Inc.
IDT71V433
32K x 32, 3.3V Synchronous SRAM with Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Pin Definitions(1)
Symbol
Pin Function
I/O
Active
Description
Address Inputs
I
N/A
Synchronous Address inputs. The address register is triggered by a combination
of the rising edge of CLK and ADSC Low or ADSP Low and CE Low.
A0–A14
Address Status
(Cache Controller)
I
LOW
Synchronous Address Status from Cache Controller. ADSC is an active LOW input
thatis used to load the address registers with newaddresses. ADSC is NOT gated
by CE.
ADSC
Address Status (Processor)
Burst Address Advance
I
I
LOW
LOW
Synchronous Address Status from Processor. ADSP is an active LOW input that
is used to load the address registers with new addresses. ADSP is gated by CE.
ADSP
ADV
Synchronous Address Advance. ADV is an active LOW input that is used to
advance the internal burst counter, controlling burst access after the initial address
is loaded. When this input is HIGH the burst counter is not incremented; that is,
there is no address advance.
Byte Write Enable
I
I
LOW
LOW
Synchronous byte write enable gates the byte write inputs BW
LOW at the rising edge of CLK then BW inputs are passed to the next stage in
the circuit. A byte write can still be blocked if ADSP is LOW at the rising edge of
is LOW at the rising edge of CLK then data will
be written to the SRAM. If BWE is HIGH then the byte write inputs are blocked
and only GW can initiate a write cycle.
1
–BW
4
. If BWE is
BWE
X
CLK. If ADSP is HIGH and BW
X
Individual Byte Write
Enables
Synchronous byte write enables. BW
etc. Any active byte write causes all outputs to be disabled. ADSP LOW disables
all byte writes. BW –BW must meet specified setup and hold times with respect
to CLK.
1
controls I/O(7:0), BW2 controls I/O(15:8),
BW
1
–BW
4
1
4
Chip Enable
Clock
I
I
LOW
N/A
Synchronous chip enable. CE is used with CS
CE also gates ADSP.
0
and CS1 to enable the IDT71V433.
CE
CLK
This is the clock input. All timing references for the device are made with respect
to this input.
Chip Select 0
Chip Select 1
Global Write Enable
Data Input/Output
Linear Burst
I
HIGH
LOW
LOW
N/A
Synchronous active HIGH chip select. CS
chip.
0
is used with CE and CS
1
to enable the
CS
0
I
Synchronous active LOW chip select. CS
1
is used with CE and CS0 to enable the
CS
GW
I/O –I/O31
1
chip.
I
Synchronous global write enable. This input will write all four 8-bit data bytes when
LOW on the rising edge of CLK. GW supercedes individual byte write enables.
I/O
I
Synchronous data input/output (I/O) pins. Only the data input path is registered
and triggered by the rising edge of CLK. Outputs are Flow-Through.
0
LOW
When LBO is HIGH the Interleaved Order (Intel) burstsequence is selected. When
LBO is LOW the Linear (PowerPC)burst sequence is selected. LBO has an internal
pull-up resistor.
LBO
OE
Output Enable
I
LOW
Asynchronous output enable. When OE is HIGH the I/O pins are in a high-
impedence state. When OE is LOW the data output drivers are enabled ifthe chip
is also selected.
V
DD
DDQ
SS
SSQ
Power Supply
Power Supply
Ground
N/A
N/A
N/A
N/A
N/A
I
N/A
N/A
N/A
N/A
N/A
HIGH
3.3V core power supply inputs.
3.3V I/O power supply inputs.
Core ground pins.
V
V
V
Ground
I/O ground pins.
NC
ZZ
No Connect
Sleep Mode
NC pins are not electrically connected to the chip.
Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power
down the IDT71V433 to its lowest power consumption level. Data retention is
guaranteed in Sleep Mode. ZZ has an internal pull-down resistor.
3729 tbl 02
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
2
IDT71V433
32K x 32, 3.3V Synchronous SRAM with Flow-Through Outputs
Commercial and Industrial Temperature Ranges
FunctionalBlockDiagram
LBO
ADV
INTERNAL
ADDRESS
CE
CLK
2
Burst
Logic
32K x 32
BIT
MEMORY
ARRAY
15
Binary
Counter
ADSC
A0*
Q0
Q1
CLR
A1*
ADSP
2
CLK EN
A0, A1
A2–A14
ADDRESS
REGISTER
A
0
–A14
GW
BWE
32
32
15
Byte 1
Write Register
Byte 1
Write Driver
BW
1
8
8
Byte 2
Write Register
Byte 2
Write Driver
BW2
Byte 3
Write Register
Byte 3
Write Driver
BW
3
8
8
Byte 4
Write Register
Byte 4
Write Driver
BW4
CE
Q
D
CS
CS
0
Enable
DATA INPUT
REGISTER
1
Register
CLK EN
Powerdown
ZZ
OE
OUTPUT
BUFFER
OE
.
32
I/O0–I/O31
3729 drw 01
3
6.42
IDT71V433
32K x 32, 3.3V Synchronous SRAM with Flow-Through Outputs
Commercial and Industrial Temperature Ranges
AbsoluteMaximumDCRatings(1)
RecommendedOperating
TemperatureandSupplyVoltage
Symbol
Rating
Value
Unit
Grade
Temperature
0°C to +70°C
–40°C to +85°C
VSS
VDD
VDDQ
(2)
Terminal Voltage with
Respect to GND
–0.5 to +4.6
V
V
TERM
Commercial
Industrial
0V
0V
3.3V+10/-5% 3.3V+10/-5%
(3)
TERM
Terminal Voltage with
Respect to GND
–0.5 to VDD+0.5
V
V
3.3V+10/-5% 3.3V+10/-5%
3729 tbl 03
T
A
Operating Temperature
Temperature Under Bias
Storage Temperature
Power Dissipation
0 to +70
–55 to +125
–55 to +125
1.2
oC
oC
oC
W
T
BIAS
STG
T
RecommendedDCOperating
Conditions
P
T
I
OUT
DC Output Current
50
mA
Symbol
Parameter
Core Supply Voltage
I/O Supply Voltage
Min. Typ.
3.135 3.3
3.135 3.3
Max.
3.63
3.63
0
Unit
V
3729 tbl 05
V
DD
DDQ
SS,
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD, VDDQ and input terminals only.
V
V
V
V
SSQ Ground
0
0
V
____
V
IH
Input High Voltage
Input Low Voltage
2.0(1)
–0.5(3)
V
DDQ+0.3(2)
V
____
VIL
0.8
V
3. I/O terminals.
3729 tbl 04
NOTES:
1. VIH and VIL as indicated is for both input and I/O pins.
2. VIH (max) = 6.0V for pulse width less than tCYC/2, once per cycle.
3. VIL (min) = –1.0V for pulse width less than tCYC/2, once per cycle.
Capacitance
(TA = +25°C, f = 1.0MHz, TQFP package)
Symbol
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
IN = 3dV
OUT = 3dV
Max. Unit
CIN
V
4
8
pF
CI/O
V
pF
3729 tbl 06
NOTE:
1. This parameter is guaranteed by device characterization, but not production
tested.
4
IDT71V433
32K x 32, 3.3V Synchronous SRAM with Flow-Through Outputs
Commercial and Industrial Temperature Ranges
PinConfiguration
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
79
78
77
NC
I/O15
I/O14
NC
2
I/O16
I/O17
3
4
V
DDQ
VDDQ
5
VSSQ
76
75
74
73
VSSQ
6
I/O18
I/O19
I/O20
I/O21
I/O13
I/O12
I/O11
I/O10
7
8
9
72
71
70
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VSSQ
VSSQ
V
DDQ
VDDQ
69
68
67
66
I/O22
I/O23
I/O9
I/O8
(1)
VSS
V
SS
V
NC
DD
PK100-1
65
64
NC
V
DD
ZZ(2)
VSS
63
62
61
60
59
I/O24
I/O25
I/O
I/O
7
6
V
DDQ
VDDQ
VSSQ
VSSQ
I/O26
I/O27
I/O28
I/O29
I/O
I/O
I/O
I/O
5
58
57
56
55
4
3
2
VSSQ
VSSQ
V
DDQ
54
53
VDDQ
I/O30
I/O31
NC
I/O
I/O
1
0
52
51
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
3729 drw 02
.
Top View TQFP
NOTES
1. Pin 14 does not have to be directly connected to VSS as long as the input voltage is ≤ VIL.
2. Pin 64 can be left unconnected and the device will always remain in active mode.
5
6.42
IDT71V433
32K x 32, 3.3V Synchronous SRAM with Flow-Through Outputs
Commercial and Industrial Temperature Ranges
SynchronousTruthTable(1,2)
Address
Used
OE(3)
X
X
X
X
X
L
Operation
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Read Cycle, Begin Burst
CS
X
X
L
0
CLK
I/O
CE
H
L
CS
1
ADSP ADSC ADV
GW
X
X
X
X
X
X
X
H
H
H
H
L
BWE BWX
None
X
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
H
L
X
X
X
X
X
X
X
X
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
None
H
X
H
X
L
None
L
L
None
L
X
L
X
X
L
None
L
L
External
External
External
External
External
External
External
Next
L
H
H
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
DOUT
Read Cycle, Begin Burst
L
L
L
H
L
Hi-Z
Read Cycle, Begin Burst
L
L
H
H
H
H
H
H
H
H
H
X
X
X
X
H
H
X
X
H
H
H
H
X
X
X
X
H
H
X
X
DOUT
Read Cycle, Begin Burst
L
L
L
H
H
L
L
DOUT
Read Cycle, Begin Burst
L
L
L
L
H
X
X
L
Hi-Z
Write Cycle, Begin Burst
L
L
L
L
D
IN
IN
OUT
Write Cycle, Begin Burst
L
L
L
X
H
H
X
X
H
H
X
X
L
X
X
X
H
H
X
X
H
H
L
D
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
X
X
X
X
H
H
H
H
X
X
H
H
X
X
X
X
H
H
H
H
X
X
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
D
Next
L
H
L
Hi-Z
Next
L
DOUT
Next
L
H
L
Hi-Z
Next
L
DOUT
Next
L
H
L
Hi-Z
Next
L
DOUT
Next
L
H
X
X
X
X
L
Hi-Z
Next
L
D
IN
IN
IN
IN
OUT
Next
L
X
L
X
L
D
Next
L
H
L
D
Next
L
X
H
H
X
X
H
H
X
X
L
X
X
X
H
H
X
X
H
H
L
D
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
D
H
L
Hi-Z
DOUT
H
L
Hi-Z
DOUT
H
L
Hi-Z
DOUT
H
X
X
X
X
Hi-Z
D
IN
IN
IN
IN
3729 tbl 07
X
L
X
L
D
H
L
D
X
X
D
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. ZZ = LOW for this table.
3. OE is an asynchronous input.
6
IDT71V433
32K x 32, 3.3V Synchronous SRAM with Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Synchronous Write Function Truth Table(1)
Operation
GW
H
H
L
BWE
H
L
BW1
BW
2
BW
3
BW4
Read
X
H
X
L
X
H
X
L
X
H
X
L
X
H
X
L
Read
Write all Bytes
Write all Bytes
Write Byte 1(2)
Write Byte 2(2)
Write Byte 3(2)
Write Byte 4(2)
NOTES:
X
L
H
H
H
H
H
L
L
H
L
H
H
L
H
H
H
L
L
H
H
H
L
H
H
L
H
3729 tbl 08
1. L = VIL, H = VIH, X = Don’t Care.
2. Multiple bytes may be selected during the same cycle.
AsynchronousTruthTable(1)
Operation
OE
ZZ
I/O Status
Power
Read
L
L
Data Out (I/O
0
–I/O31
)
Active
Active
Active
Standby
Sleep
Read
H
X
X
X
L
High-Z
Write
L
High-Z — Data In (I/O
0–I/O31)
Deselected
Sleep Mode
L
High-Z
H
High-Z
3729 tbl 09
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Synchronous function pins must be biased appropriately to satisfy operation requirements.
InterleavedBurstSequenceTable(LBO=VDD)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
0
A0
0
A1
0
A0
1
A1
1
A0
0
A1
1
A0
1
First Address
Second Address
Third Address
Fourth Address(1)
NOTE:
0
1
0
0
1
1
1
0
1
0
1
1
0
0
0
1
1
1
1
0
0
1
0
0
3729 tbl 10
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
LinearBurstSequenceTable(LBO=VSS)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
0
A0
0
A1
0
A0
1
A1
1
A0
0
A1
1
A0
1
First Address
Second Address
Third Address
Fourth Address(1)
0
1
1
0
1
1
0
0
1
0
1
1
0
0
0
1
1
1
0
0
0
1
1
0
3729 tbl 11
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
7
6.42
IDT71V433
32K x 32, 3.3V Synchronous SRAM with Flow-Through Outputs
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics Over the Operating Temperature and
Supply Voltage Range(VDD = 3.3V +10/-5%, Commercial and Industrial Temperature Ranges)
Unit
µA
µ A
µA
V
Symbol
Parameter
Test Conditions
DD = Max., VIN = 0V to VDD
DD = Max., VIN = 0V to VDD
Min.
Max.
___
|ILI|
Input Leakage Current
V
5
ZZ & LBO Input Leakage Current(1)
Output Leakage Current
Output Low Voltage
V
30
5
___
___
___
|ILI|
|ILO
|
CE > VIH or OE > VIH, VOUT = 0V to VDD, VDD = Max.
OL = 5mA, VDD = Min.
OH = –5mA, VDD = Min.
VOL
I
0.4
___
VOH
Output High Voltage
I
2.4
V
3729 tbl 12
NOTE:
1. The LBO pin will be internally pulled to VDD if it is not actively driven in the application and the ZZ pin will be internally pulled to VSS if not actively driven.
DC Electrical Characteristics Over the Operating Temperature and
Supply Voltage Range(1) (VHD = VDDQ–0.2V, VLD = 0.2V)
IDT71V433S11
IDT71V433S12
Unit
Symbol
Parameter
Test Conditions
Com'l.
Ind.
Com'l.
Ind.
Operating Core Power
Supply Current
Device Selected, Outputs Open, VDD = Max.,
220
220
210
210
mA
IDD
(2)
VDDQ = Max., VIN > VIH or < VIL, f = fMAX
Standby Core Power
Supply Current
Device Deselected, Outputs Open, VDD = Max.,
45
45
15
15
40
40
15
15
mA
mA
ISB
ISB1
IZZ
(2)
VDDQ = Max., VIN > VIH or < VIL, f = fMAX
Full Standby Core Power Device Deselected, Outputs Open, VDD = Max.,
Supply Current
15
15
VDDQ = Max., VIN > VHD or < VLD, f = 0(2)
ZZ > VHD, VDD = Max.
Full Sleep Mode Core
Power Supply Current
15
15
mA
3729 tbl 13
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC while ADSC = LOW; f=0 means no input lines are changing.
AC Test Loads
+3.3V
VDDQ/2
317Ω
50Ω
DATA
OUT
DATA OUT
Z0 = 50Ω
5pF*
351Ω
3729 drw 03
Figure 1. AC Test Load
3729 drw 04
* Including scope and jig capacitance.
6
5
4
3
Figure 2. High-Impedence Test Load
(for tOHZ, tCHZ, tOLZ, and tDC1)
∆tCD
(Typical, ns)
AC Test Conditions
2
1
Input Pulse Levels
0 to 3.0V
2ns
Input Rise/Fall Times
Input Timing Reference Levels
Output Timing Reference Levels
AC Test Load
1.5V
20 30 50
80 100
Capacitance (pF)
200
1.5V
3729 drw 05
See Figures 1 and 2
3729 tbl 14
Figure 3. Lumped Capacitive Load, Typical Derating
8
IDT71V433
32K x 32, 3.3V Synchronous SRAM with Flow-Through Outputs
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = 3.3V +10/-5%, Commercial and Industrial Temperature Ranges)
71V433S11
71V433S12
Min.
Max.
Min.
Max.
Symbol
Clock Parameters
tCYC
Parameter
Unit
____
____
____
____
____
____
Clock Cycle Time
20
6
20
6
ns
ns
ns
(1)
tCH
Clock High Pulse Width
Clock Low Pulse Width
(1)
tCL
6
6
Output Parameters
____
____
tCD
Clock High to Valid Data
11
12
ns
ns
ns
ns
ns
ns
ns
____
____
tCDC
Clock High to Data Change
Clock High to Output Active
Clock High to Data High-Z
Output Enable Access Time
3
0
3
0
(2)
____
____
tCLZ
(2)
tCHZ
tOE
3
6
3
6
____
____
4
4
(2)
____
____
tOLZ
Output Enable Low to Data Active
Output Enable High to Data High-Z
0
0
(2)
____
____
tOHZ
Setup Times
tSA
6
6
____
____
____
____
____
____
____
____
____
____
____
____
Address Setup Time
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
ns
ns
ns
ns
ns
ns
tSS
Address Status Setup Time
Data in Setup Time
tSD
tSW
Write Setup Time
tSAV
Address Advance Setup Time
Chip Enable/Select Setup Time
tSC
Hold Times
tHA
____
____
____
____
____
____
____
____
____
____
____
____
Address Hold Time
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
tHS
Address Status Hold Time
Data In Hold Time
tHD
tHW
Write Hold Time
tHAV
tHC
Address Advance Hold Time
Chip Enable/Select Hold Time
Sleep Mode and Configuration Parameters
____
____
____
____
____
____
tZZPW
ZZ Pulse Width
100
100
80
100
100
80
ns
ns
(3)
tZZR
ZZ Recovery Time
Configuration Set-up Time
(4)
tCFG
ns
3729 tbl 15
NOTES:
1. Measured as HIGH above 2.0V and LOW below 0.8V.
2. Transition is measured ±200mV from steady-state.
3. Device must be deselected when powered-up from sleep mode.
4. tCFG is the minimum time required to configure the device based on the LBO input. LBO is a static input and must not change during normal operation.
9
6.42
IDT71V433
32K x 32, 3.3V Synchronous SRAM with Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle(1,2)
.
10
IDT71V433
32K x 32, 3.3V Synchronous SRAM with Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of Combined Read and Write Cycles(1,2,3)
.
11
6.42
IDT71V433
32K x 32, 3.3V Synchronous SRAM with Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 1 — GW Controlled(1,2,3)
.
12
IDT71V433
32K x 32, 3.3V Synchronous SRAM with Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 2 — Byte Controlled(1,2,3)
.
13
6.42
IDT71V433
32K x 32, 3.3V Synchronous SRAM with Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of Sleep (ZZ) and Power-Down Modes(1,2,3)
.
14
IDT71V433
32K x 32, 3.3V Synchronous SRAM with Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Non-Burst Read Cycle Timing Waveform
CLK
ADSP
ADSC
Av
Aw
Ax
Ay
Az
ADDRESS
GW, BWE, BWx
CE, CS
1
CS0
OE
(Av)
(Aw)
(Ax)
(Ay)
DATAOUT
.
3729 drw 11
NOTES:
ZZ input is LOW, ADV is HIGH, and LBO is Don’t Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. For read cycles, ADSP and ADSC function identically and are therefore interchangeable.
1
15
6.42
IDT71V433
32K x 32, 3.3V Synchronous SRAM with Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Non-Burst Write Cycle Timing Waveform
CLK
ADSP
ADSC
Av
Aw
Ax
Ay
Az
ADDRESS
GW
CE, CS
1
CS0
(Av)
(Aw)
(Ax)
(Ay)
(Az)
DATAIN
.
3729 drw 12
NOTES:
1. ZZ input is LOW, ADV and OE are HIGH, and LBO is Don't Care for this cycle.
2. (Ax) represents the data for address Ax, etc.
3. Although only GW writes are shown, the functionality of BWE and BWx together is the same as GW.
4. For write cycles, ADSP and ADSC have different limitations.
16
IDT71V433
32K x 32, 3.3V Synchronous SRAM with Flow-Through Outputs
Commercial and Industrial Temperature Ranges
100-Pin Thin Quad Flatpack (TQFP) Package Diagram Outline
17
6.42
IDT71V433
32K x 32, 3.3V Synchronous SRAM with Flow-Through Outputs
Commercial and Industrial Temperature Ranges
OrderingInformation
X
S
X
PF
IDT 71V433
Device
Type
Power Speed
Package
Process/
Temperature
Range
Blank Commercial (0°C to +70°C)
I
Industrial (–40°C to +85°C)
Plastic Thin Quad Flatpack, 100 pin (PK100-1)
PF
.
11
12
t
CD in nanoseconds
PART NUMBER
SPEED IN MEGAHERTZ
CLOCK CYCLE TIME
t
CD PARAMETER
71V433S11PF
71V433S12PF
20 ns
20 ns
50 MHz
50 MHz
11 ns
12 ns
3729 drw 13
18
IDT71V433
32K x 32, 3.3V Synchronous SRAM with Flow-Through Outputs
Commercial and Industrial Temperature Ranges
DatasheetDocumentHistory
09/10/99
Updatedtonewformat
Pg. 1, 8, 9, 17
Pg. 3–5
Pg. 5
Pg. 11–14
Pg. 18
Revised speed offerings to 11 and 12 ns at 50 MHz
Adjustedpage layout, addedextra page
Addednotestopinconfiguration
Updatednotes
`
AddedDatasheetDocumentHistory
10/08/99
04/04/00
08/09/00
08/17/01
Pg. 1, 4, 8, 9, 17 AddedIndustrialtemperaturerangeofferings
Pg. 17
Added100pinTQFPPackageDiagramOutline
Notrecommendedfornewdesigns
Removed“Notrecommendedfornewdesigns”fromthebackgroundonthedatasheet
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
ipchelp@idt.com
800-345-7015
800-345-7015 or
408-284-8200
fax: 408-284-2775
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
19
6.42
相关型号：
©2020 ICPDF网 联系我们和版权申明