IDT71V3578S166BG8_技术文档

128K X 36, 256K X 18

Preliminary

IDT71V3576

IDT71V3578

3.3V Synchronous SRAMs

3.3V I/O, Pipelined Outputs

Burst Counter, Single Cycle Deselect

Features

Description

◆

128K x 36, 256K x 18 memory configurations

The IDT71V3576/78 are high-speed SRAMs organized as

128Kx36/256Kx18. TheIDT71V3576/78SRAMscontainwrite, data,

addressandcontrolregisters. InternallogicallowstheSRAMtogenerate

aself-timedwritebaseduponadecisionwhichcanbeleftuntiltheendof

thewritecycle.

◆

Supports high system speed:

200MHz 3.1ns clock access time

183MHz 3.3ns clock access time

166MHz 3.5ns clock access time

150MHz 3.8ns clock access time

133MHz 4.2ns clock access time

Theburstmodefeatureoffersthehighestlevelofperformancetothe

systemdesigner,astheIDT71V3576/78canprovidefourcyclesofdata

forasingleaddresspresentedtotheSRAM. Aninternalburstaddress

◆

LBO input selects interleaved or linear burst mode

Self-timedwritecyclewithglobalwritecontrol(GW),bytewrite counteracceptsthefirstcycleaddressfromtheprocessor,initiatingthe

◆

enable (BWE), and byte writes (BWx)

3.3V core power supply

Power down controlled by ZZ input

3.3V I/O

accesssequence.Thefirstcycleofoutputdatawillbepipelinedforone

cycle before it is available on the next rising clock edge. If burst mode

operationisselected(ADV=LOW),thesubsequentthreecyclesofoutput

datawillbeavailabletotheuseronthenextthreerisingclockedges. The

◆

Packaged in a JEDEC Standard 100-lead plastic thin quad orderofthesethreeaddressesaredefinedbytheinternalburstcounter

flatpack (TQFP) and 119-lead ball grid array (BGA)

and the LBOinput pin.

The IDT71V3576/78 SRAMs utilize IDTs latest high-performance

CMOSprocessandarepackagedinaJEDECstandard14mmx20mm

100-leadthinplasticquadflatpack(TQFP)aswellasa119-leadballgrid

array (BGA).

PinDescriptionSummary

0

17

A -A

Address Inputs

Input

I/O

Synchronous

Asynchronous

Synchronous

N/A

Chip Enable

CE

0

1

CS , CS

Chip Selects

Output Enable

OE

Global Write Enable

Byte Write Enable

Individual Byte Write Selects

Clock

GW

BWE

(1)

¹,

²,

³,

4

BW BW BW BW

CLK

ADV

ADSC

ADSP

LBO

ZZ

Burst Address Advance

Address Status (Cache Controller)

Address Status (Processor)

Linear / Interleaved Burst Order

Sleep Mode

Synchronous

DC

Asynchronous

Synchronous

N/A

0

31

P1

P4

I/O -I/O , I/O -I/O

Data Input / Output

Core Power, I/O Power

Ground

DD DDQ

V

, V

Supply

SS

N/A

5279 tbl 01

NOTE:

1. BW3 and BW4 are not applicable for the IDT71V3578.

SEPTEMBER1999

1

DSC-5279/3

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Preliminary

Commercial Temperature Ranges

PinDefinitions⁽¹⁾

Symbol

Pin Function

I/O

Active

Description

0

17

A -A

Address Inputs

I

N/A

Synchronous Address inputs. The address register is triggered by a combination of the

rising edge of CLK and ADSC Low or ADSP Low and CE Low.

Address Status

(Cache Controller)

I

LOW

Synchronous Address Status from Cache Controller. ADSC is an active LOW input that is

ADSC

ADSP

ADV

used to load the address registers with new addresses.

Address Status

(Processor)

Synchronous Address Status from Processor. ADSP is an active LOW input that is used to

load the address registers with new addresses. ADSP is gated by CE.

Burst Address

Advance

Synchronous Address Advance. ADV is an active LOW input that is used to advance the

internal burst counter, controlling burst access after the initial address is loaded. When the

input is HIGH the burst counter is not incremented; that is, there is no address advance.

1

4

Byte Write Enable

I

LOW

Synchronous byte write enable gates the byte write inputs BW -BW . If BWE is LOW at the

rising edge of CLK then BWx inputs are passed to the next stage in the circuit. If BWE is

HIGH then the byte write inputs are blocked and only GW can initiate a write cycle.

BWE

1

0-7

P1

2

8-15

P2

Individual Byte

Write Enables

I

LOW

N/A

Synchronous byte write enables. BW controls I/O , I/O , BW controls I/O , I/O , etc.

1

4

BW -BW

Any active byte write causes all outputs to be disabled.

0

1

Chip Enable

Synchronous chip enable. CE is used with CS and CS to enable the IDT71V3576/78. CE

CE

also gates ADSP.

CLK

Clock

This is the clock input. All timing references for the device are made with respect to this

input.

0

1

CS

Chip Select 0

Chip Select 1

I

HIGH

LOW

Synchronous active HIGH chip select. CS is used with CE and CS to enable the chip.

1

0

Synchronous active LOW chip select. CS is used with CE and CS to enable the chip.

1

CS

Global Write

Enable

Synchronous global write enable. This input will write all four 9-bit data bytes when LOW

on the rising edge of CLK. GW supersedes individual byte write enables.

GW

0

31

I/O -I/O

Data Input/Output

I/O

I

N/A

Synchronous data input/output (I/O) pins. Both the data input path and data output path are

registered and triggered by the rising edge of CLK.

P1

P4

I/O -I/O

Linear Burst Order

LOW

Asynchronous burst order selection input. When LBO is HIGH, the interleaved burst

sequence is selected. When LBO is LOW the Linear burst sequence is selected. LBO is a

static input and must not change state while the device is operating.

LBO

OE

Output Enable

I

LOW

Asynchronous output enable. When OE is LOW the data output drivers are enabled on the

I/O pins if the chip is also selected. When OE is HIGH the I/O pins are in a high-

impedance state.

DD

V

Power Supply

Ground

N/A

I

N/A

3.3V core power supply.

DDQ

V

3.3V I/O Supply.

SS

V

N/A

Ground.

NC

ZZ

No Connect

Sleep Mode

N/A

NC pins are not electrically connected to the device.

HIGH

Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the

IDT71V3576/78 to its lowest power consumption level. Data retention is guaranteed in

Sleep Mode.

5279 tbl 02

NOTE:

1. All synchronous inputs must meet specified setup and hold times with respect to CLK.

6.422

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Preliminary

Commercial Temperature Ranges

FunctionalBlockDiagram

LBO

ADV

INTERNAL

ADDRESS

Burst

Sequence

CEN

128K x 36/

256K x 18-

BIT

MEMORY

ARRAY

CLK

2

Burst

Logic

17/18

Binary

Counter

ADSC

A0*

A1*

Q0

Q1

CLR

ADSP

2

CLK EN

A0,A1

A2–A17

A0 - A16/17

GW

ADDRESS

REGISTER

36/18

17/18

Byte 1

Write Register

BWE

Byte 1

Write Driver

BW1

BW2

9

Byte 2

Write Register

Byte 2

Write Driver

9

Byte 3

Write Register

Byte 3

Write Driver

BW3

BW4

9

Byte 4

Write Register

Byte 4

Write Driver

9

OUTPUT

REGISTER

CE

CS⁰

CS1

Q

D

Enable

DATA INPUT

REGISTER

Register

CLK EN

ZZ

Powerdown

D

Q

Enable

Delay

Register

OE

OUTPUT

BUFFER

OE

,

36/18

I/O0 — I/O31

I/OP1 — I/OP4

5279 drw 01

6.42

3

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Preliminary

Commercial Temperature Ranges

AbsoluteMaximumRatings⁽¹⁾

RecommendedOperating

TemperatureandSupplyVoltage

Symbol

Rating

Commercial

Unit

(2)

Grade

Temperature

V^SS

V^DD

V^DDQ

TE RM

V

Terminal Voltage with

Respect to GND

-0.5 to +4.6

V

Commercial

0°C to +70°C

0V

3.3V±5%

(3,6)

(4,6)

(5,6)

TE RM

DD

-0.5 to V

5279 tbl 04

Terminal Voltage with

Respect to GND

V

DD

Terminal Voltage with

Respect to GND

-0.5 to V +0.5

V

DDQ

-0.5 to V

Terminal Voltage with

Respect to GND

+0.5

V

RecommendedDCOperating

Conditions

A

-0 to +70

-55 to +125

^oC

W

T

Operating Temperature

BIAS

T

Temperature

Under Bias

Symbol

Parameter

Core Supply Voltage

I/O Supply Voltage

Min.

3.135

0

Typ.

Max.

Unit

V

V^DD

3.3

3.465

STG

T

Storage

Temperature

DDQ

V

3.3

V

V^SSSupply Voltage

0

V

T

P

Power Dissipation

DC Output Current

2.0

50

____

V^IH

V^IL

Input High Voltage - Inputs

Input High Voltage - I/O

Input Low Voltage

2.0

V^DD+0.3

V^DDQ+0.3⁽¹⁾

0.8

V

OUT

I

mA

____

2.0

V

5279 tbl 03

NOTES:

-0.3⁽²⁾

V

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated

in the operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect reliability.

2. V^DDterminals only.

5279 tbl 06

NOTES:

1. VIH (max) = VDDQ + 1.0V for pulse width less than tCYC/2, once per cycle.

2. VIL (min) = -1.0V for pulse width less than tCYC/2, once per cycle.

3. VDDQ terminals only.

4. Input terminals only.

5. I/O terminals only.

6. This is a steady-state DC parameter that applies after the power supplies have

ramped up. Power supply sequencing is not necessary; however, the voltage

on any input or I/O pin cannot exceed V^DDQduring power supply ramp up.

Capacitance

(TA = +25°C, f = 1.0MHz)

Symbol

Parameter⁽¹⁾

Input Capacitance

I/O Capacitance

Conditions

VIN = 3dV

Max. Unit

CIN

5

7

pF

CI/O

VOUT = 3dV

pF

5279 tbl 07

NOTE:

1. This parameter is guaranteed by device characterization, but not production

tested.

6.442

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Preliminary

Commercial Temperature Ranges

Pin Configuration 128K x 36 TQFP

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

1

80

I/OP3

I/O16

I/O17

VDDQ

VSS

I/O18

I/O19

I/O20

I/O21

VSS

VDDQ

I/O22

I/OP2

I/O15

I/O14

VDDQ

VSS

I/O13

I/O12

I/O11

I/O10

VSS

2

79

78

77

3

4

5

76

75

74

73

6

7

8

9

72

71

10

11

70

69

68

67

66

VDDQ

12

I/O9

I/O8

VSS

NC

13

I/O23

VDD / NC⁽¹⁾

14

15

VDD

16

65

64

NC

VSS

I/O24

I/O25

VDDQ

VSS

I/O26

I/O27

I/O28

I/O29

VSS

VDDQ

I/O30

I/O31

I/OP4

VDD

ZZ⁽³⁾

I/O7

I/O6

VDDQ

VSS

I/O5

I/O4

I/O3

I/O2

VSS

17

18

63

62

19

20

61

60

59

58

57

56

55

54

53

52

51

21

22

23

24

25

26

27

VDDQ

I/O1

I/O0

28

,

29

30

I/OP1

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

5279 drw 02

Top View

NOTES:

1. Pin 14 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.

2. Pins 38 and 39 can be either NC or connected to VSS.

3. Pin 64 can be left unconnected and the device will always remain in active mode.

6.42

5

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Preliminary

Commercial Temperature Ranges

Pin Configuration 256K x 18 TQFP

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

1

80

79

78

77

NC

VDDQ

VSS

NC

I/O8

I/O9

VSS

VDDQ

I/O10

A10

NC

2

3

4

VDDQ

VSS

NC

I/OP1

I/O7

I/O6

VSS

VDDQ

I/O5

I/O4

VSS

NC

VDD

ZZ⁽³⁾

I/O3

I/O2

VDDQ

VSS

I/O1

I/O0

NC

5

76

75

74

73

6

7

8

9

72

71

70

10

11

12

69

68

67

66

65

64

63

62

61

60

59

13

I/O11

VDD / NC⁽¹⁾

14

15

VDD

NC

VSS

I/O12

I/O13

VDDQ

VSS

I/O14

I/O15

I/OP2

NC

VSS

VDDQ

NC

16

17

18

19

20

21

22

23

58

57

56

55

54

53

24

25

NC

VSS

VDDQ

NC

26

,

27

28

29

52

51

30

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

5279 drw 03

Top View

NOTES:

1. Pin 14 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.

2. Pins 38 and 39 can be either NC or connected to VSS.

3. Pin 64 can be left unconnected and the device will always remain in active mode.

6.462

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Preliminary

Commercial Temperature Ranges

Pin Configuration 128K x 36 BGA^(1,2,3)

1

2

3

4

5

6

7

DDQ

6

4

8

16

DDQ

V

A

B

C

D

E

F

ADSP

ADSC

0

3

2

9

NC

CS

NC

1

CS

7

A

DD

V

12

15

A

16

I/O

P3

I/O

SS

P2

I/O

15

I/O

V

NC

CE

V

17

I/O

18

I/O

13

I/O

14

I/O

DDQ

V

19

I/O

12

I/O

DDQ

V

OE

20

21

11

10

I/O

G

H

J

2

3

BW

ADV

GW

BW

22

I/O

23

I/O

SS

V

SS

V

9

I/O

8

I/O

DDQ

DD

V

DD

DDQ

V

NC

V

24

26

SS

4

SS

6

7

I/O

V

CLK

NC

V

I/O

K

L

25

I/O

27

I/O

4

I/O

5

I/O

1

BW

DDQ

28

SS

3

I/O

DDQ

V

I/O

V

M

N

P

R

T

BWE

29

I/O

30

I/O

1

0

2

I/O

1

I/O

A

31

P4

0

I/O

P1

I/O

NC

I/O

A

NC

5

DD

11

13

A

V

VDD / NC

LBO

10

A

14

A

NC

A

NC

ZZ

,

DDQ

V

DDQ

V

NC

U

5279 drw 04

Top View

Pin Configuration 256K x 18 BGA^(1,2,3)

1

2

3

4

5

6

7

DDQ

6

4

8

16

DDQ

V

A

B

C

D

E

F

ADSP

ADSC

3

2

9

NC

CS0

NC

1

CS

7

A

DD

V

13

17

A

8

SS

7

I/O

NC

V

NC

V

9

I/O

6

I/O

NC

CE

OE

DDQ

V

5

I/O

DDQ

V

NC

10

4

I/O

NC

I/O

NC

G

H

J

BW2

ADV

GW

11

I/O

SS

V

SS

3

I/O

V

NC

DDQ

V

DD

V

DD

DDQ

V

NC

V

12

SS

2

I/O

NC

I/O

NC

V

CLK

NC

V

NC

K

L

13

I/O

SS

1

V

I/O

NC

1

BW

DDQ

V

14

I/O

SS

V

DDQ

V

M

N

P

R

T

BWE

15

SS

1

0

SS

0

I/O

NC

A

V

I/O

NC

P2

SS

P1

I/O

A

5

DD

V

12

A

NC

DDQ

A

VDD / NC

14

NC

LBO

,

10

15

11

A

NC

A

ZZ

DDQ

V

NC

U

5279 drw 05

Top View

NOTES:

1. R5 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.

2. L4 and U4 can be either NC or connected to VSS.

3. T7 can be left unconnected and the device will always remain in active mode.

6.42

7

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Preliminary

Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range (VDD = 3.3V ± 5%)

Symbol

Parameter

Test Conditions

Min.

Max.

Unit

___

|I^LI|

Input Leakage Current

V^DD= Max., V^IN= 0V to V^DD

5

µA

ZZ and LBO Input Leakage Current⁽¹⁾

Output Leakage Current

Output Low Voltage

___

|I^LZZ|

|I^LO|

V^OL

V^OH

V^DD= Max., V^IN= 0V to V^DD

V^OUT= 0V to V^DDQ, Device Deselected

I^OL= +8mA, V^DD= Min.

30

5

µA

V

0.4

___

Output High Voltage

I^OH= -8mA, V^DD= Min.

2.4

V

5279 tbl 08

NOTE:

1. The LBO pin will be internally pulled to VDD if it is not actively driven in the application and the ZZ pin will be internally pulled to VSS if not actively driven.

DC Electrical Characteristics Over the Operating

TemperatureandSupplyVoltageRange⁽¹⁾

Symbol

Parameter

Test Conditions

200MHz 183MHz 166MHz 150MHz 133MHz

Unit

Operating Power Supply

Current

Device Selected, Outputs Open, V^DD= Max.,

V^DDQ= Max., V^IN> V^IHor < V^IL, f = f^MAX

360

30

340

320

295

250

mA

I^DD

(2)

I^SB1

I^SB2

I^ZZ

CMOS Standby Power

Supply Current

Device Deselected, Outputs Open, V^DD= Max.,

V^DDQ= Max., V^IN> V^HDor < V^LD, f = 0^(2,3)

30

mA

Clock Running Power

Supply Current

Device Deselected, Outputs Open, V^DD= Max.,

130

30

120

30

110

30

105

30

100

30

(2,3)

V^DDQ= Max., V^IN> V^HDor < V^LD, f = f^MAX

ZZ > V^HD,V^DD= Max.

Full Sleep Mode Supply

Current

mA

5279 tbl 09

NOTES:

1. All values are maximum guaranteed values.

2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC while ADSC = LOW; f=0 means no input lines are changing.

3. For I/Os VHD = VDDQ - 0.2V, VLD = 0.2V. For other inputs VHD = VDD - 0.2V, VLD = 0.2V.

AC Test Conditions

(VDDQ = 3.3V)

AC Test Load

V

DDQ/2

50

Ω

Input Pulse Levels

0 to 3V

2ns

I/O

Z0 = 50Ω

Input Rise/Fall Times

,

5279 drw 06

Input Timing Reference Levels

Output Timing Reference Levels

AC Test Load

1.5V

Figure 1. AC Test Load

6

5

4

3

1.5V

See Figure 1

5279 tbl 10

∆tCD

(Typical, ns)

2

1

20 30 50

80 100

Capacitance (pF)

200

5279 drw 07

,

Figure 2. Lumped Capacitive Load, Typical Derating

6.482

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Preliminary

Commercial Temperature Ranges

SynchronousTruthTable^(1,3)

CE

CS1

ADSP ADSC ADV

GW

BWE BW

x

OE

(2)

Operation

Address

Used

CS0

CLK

I/O

Deselected Cycle, Power Down

Read Cycle, Begin Burst

None

H

L

X

L

X

H

X

H

X

L

X

L

X

L

X

L

X

H

L

X

H

L

X

H

L

X

L

HI-Z

DOUT

HI-Z

DOUT

HI-Z

DIN

None

L

None

L

X

L

X

L

None

L

External

H

X

L

Read Cycle, Begin Burst

L

H

L

Read Cycle, Begin Burst

L

H

X

H

X

H

X

H

X

Read Cycle, Begin Burst

L

Read Cycle, Begin Burst

L

H

X

L

Write Cycle, Begin Burst

L

Write Cycle, Begin Burst

L

X

H

X

H

X

L

X

H

X

H

L

DIN

Read Cycle, Continue Burst

Write Cycle, Continue Burst

Read Cycle, Suspend Burst

Write Cycle, Suspend Burst

X

H

X

H

X

H

X

H

X

H

L

DOUT

HI-Z

DOUT

HI-Z

DOUT

HI-Z

DOUT

HI-Z

DIN

H

L

H

L

H

L

H

X

L

X

L

X

L

DIN

H

L

DIN

X

H

X

H

X

L

X

H

X

H

L

DIN

Current

H

L

DOUT

HI-Z

DOUT

HI-Z

DOUT

HI-Z

DOUT

HI-Z

DIN

H

L

H

L

H

L

H

X

L

X

L

DIN

H

L

DIN

X

DIN

5279 tbl 11

NOTES:

1. L = VIL, H = VIH, X = Dont Care.

2. OE is an asynchronous input.

3. ZZ = low for this table.

6.42

9

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Preliminary

Commercial Temperature Ranges

Synchronous Write Function Truth Table^{(1, 2)}

GW

BWE

BW1

BW2

X

BW3

X

BW4

X

Operation

Read

H

L

X

L

X

Read

H

Write all Bytes

Write Byte 1⁽³⁾

Write Byte 2⁽³⁾

Write Byte 3⁽³⁾

Write Byte 4⁽³⁾

L

X

H

L

H

L

H

L

H

L

H

L

5279 tbl 12

NOTES:

1. L = VIL, H = VIH, X = Dont Care.

2. BW3 and BW4 are not applicable for the IDT71V3578.

3. Multiple bytes may be selected during the same cycle.

AsynchronousTruthTable⁽¹⁾

Operation⁽²⁾

OE

ZZ

I/O Status

Power

Read

L

H

X

L

H

Data Out

High-Z

Active

Standby

Sleep

Write

High-Z Data In

High-Z

Deselected

Sleep Mode

High-Z

5279 tbl 13

NOTES:

1. L = V^IL, H = VIH, X = Dont Care.

2. Synchronous function pins must be biased appropriately to satisfy operation requirements.

InterleavedBurstSequenceTable(LBO=VDD)

Sequence 1

Sequence 2

Sequence 3

Sequence 4

A1

A0

0

A1

A0

1

A1

1

A0

A1

A0

First Address

0

1

0

1

0

1

0

1

0

1

Second Address

Third Address

1

0

1

0

1

0

1

Fourth Address⁽¹⁾

1

0

5279 tbl 14

NOTE:

1. Upon completion of the Burst sequence the counter wraps around to its initial state.

LinearBurstSequenceTable(LBO=VSS)

Sequence 1

Sequence 2

Sequence 3

Sequence 4

A1

0

A0

0

A1

0

A0

1

A1

1

A0

0

A1

1

A0

First Address

1

Second Address

Third Address

0

1

0

1

0

1

0

1

0

1

Fourth Address⁽¹⁾

1

0

1

0

5279 tbl 15

NOTE:

1. Upon completion of the Burst sequence the counter wraps around to its initial state.

6.1402

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Preliminary

Commercial Temperature Ranges

AC Electrical Characteristics

(VDD = 3.3V ±5%, TA = 0 to 70°C)

200MHz

183MHz

166MHz

150MHz

133MHz

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max. Unit

____

tCYC

Clock Cycle Time

5

2

5.5

2.2

6

6.7

2.6

7.5

3

ns

(1)

Clock High Pulse Width

Clock Low Pulse Width

2.4

tCH

____

(1)

3

tCL

Output Parameters

____

tCD

Clock High to Valid Data

3.1

3.3

3.5

3.8

4.2

ns

____

tCDC

Clock High to Data Change

1.0

0

1.0

0

1.0

0

1.5

0

1.5

0

____

(2)

Clock High to Output Active

Clock High to Data High-Z

tCLZ

(2)

1.5

3.1

1.5

3.3

1.5

3.5

1.5

3.8

1.5

4.2

ns

tCHZ

____

tOE

Output Enable Access Time

Output Enable Low to Output Active

Output Enable High to Output High-Z

3.1

3.3

3.5

3.8

4.2

____

(2)

0

tOLZ

____

3.1

3.3

3.5

3.8

4.2

tOHZ

Set Up Times

____

tSA

tSS

tSD

tSW

tSAV

tSC

Address Setup Time

1.2

1.5

ns

Address Status Setup Time

Data In Setup Time

Write Setup Time

Address Advance Setup Time

Chip Enable/Select Setup Time

Hold Times

____

tHA

tHS

tHD

tHW

tHAV

tHC

Address Hold Time

0.4

0.5

ns

Address Status Hold Time

Data In Hold Time

Write Hold Time

Address Advance Hold Time

Chip Enable/Select Hold Time

Sleep Mode and Configuration Parameters

____

tZZPW

ZZ Pulse Width

100

20

100

22

100

24

100

27

100

30

ns

(3)

ZZ Recovery Time

Configuration Set-up Time

tZZR

____

(4)

ns

tCFG

5279 tbl 16

NOTES:

1. Measured as HIGH above VIH and LOW below VIL.

2. Transition is measured ±200mV from steady-state.

3. Device must be deselected when powered-up from sleep mode.

4. tCFG is the minimum time required to configure the device based on the LBO input. LBO is a static input and must not change during normal operation.

6.42

11

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Preliminary

Commercial Temperature Ranges

Timing Waveform of Pipelined Read Cycle^(1,2)

,

6.1422

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Preliminary

Commercial Temperature Ranges

Timing Waveform of Combined Pipelined Read and Write Cycles^(1,2,3)

,

6.42

13

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Preliminary

Commercial Temperature Ranges

Timing Waveform of Write Cycle No. 1 - GW Controlled^(1,2,3)

,

6.1442

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Preliminary

Commercial Temperature Ranges

Timing Waveform of Write Cycle No. 2 - Byte Controlled^(1,2,3)

,

6.42

15

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Preliminary

Commercial Temperature Ranges

Timing Waveform of Sleep (ZZ) and Power-Down Modes^(1,2,3)

,

6.1462

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Preliminary

Commercial Temperature Ranges

Non-Burst Read Cycle Timing Waveform

CLK

ADSP

ADSC

Av

Aw

Ax

Ay

Az

ADDRESS

GW, BWE, BWx

CE, CS1

CS0

OE

(Av)

(Aw)

(Ax)

(Ay)

DATAOUT

,

5279 drw 14

NOTES:

1. ZZ input is LOW, ADV is HIGH and LBO is Don't Care for this cycle.

2. (Ax) represents the data for address Ax, etc.

3. For read cycles, ADSPandADSCfunction identically and are therefore interchangable.

Non-Burst Write Cycle Timing Waveform

CLK

ADSP

ADSC

Av

Aw

Ax

Ay

Az

ADDRESS

GW

CE, CS1

CS0

(Av)

(Aw)

(Ax)

(Ay)

(Az)

DATAIN

,

5279 drw 15

NOTES:

1. ZZ input is LOW, ADV and OE are HIGH, and LBO is Don't Care for this cycle.

2. (Ax) represents the data for address Ax, etc.

3. Although only GW writes are shown, the functionality of BWE and BWx together is the same as GW.

4. For write cycles, ADSP and ADSC have different limitations.

6.42

17

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Preliminary

Commercial Temperature Ranges

119-Lead Ball Grid Array (BGA) Package Diagram Outline

6.1482

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Preliminary

Commercial Temperature Ranges

OrderingInformation

IDT

XXX

S

X

XX

Device

Type

Power Speed

Package

PF

BG

100-lead Plastic Thin Quad Flatpack (TQFP)

119-lead Ball Grid Array (BGA)

200

183

166

150

133

Frequency in Megahertz

,

128K x 36 Pipelined Burst Synchronous SRAM with 3.3V I/O

256K x 18 Pipelined Burst Synchronous SRAM with 3.3V I/O

71V3576

71V3578

5279 drw 13

6.42

19

IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with

3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Preliminary

Commercial Temperature Ranges

Datasheet Document History

7/26/99

9/17/99

Updated to new format

Pg. 8

Revised ISB1 and IZZ for speeds 100200MHz

Revised tCDC (min.) at 166MHz

Added 119 BGA package diagram

Added Datasheet Document History

Pg. 11

Pg. 18

Pg. 20

CORPORATE HEADQUARTERS

2975StenderWay

Santa Clara, CA 95054

for SALES:

for Tech Support:

sramhelp@idt.com

800-544-7726, x4033

800-345-7015 or 408-727-6116

fax: 408-492-8674

www.idt.com

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

6.2402


型号：	IDT71V3578S166BG8
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Cache SRAM, 256KX18, 3.5ns, CMOS, PBGA119, BGA-119 静态存储器
文件：	总20页 (文件大小：363K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IDT71V3578S166BG8 [IDT]

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