IDT71V3556XS133PFGI [IDT]
ZBT SRAM, 128KX36, 4.2ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, PLASTIC, MO-136DJ, TQFP-100;
| 型号： | IDT71V3556XS133PFGI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | ZBT SRAM, 128KX36, 4.2ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, PLASTIC, MO-136DJ, TQFP-100 时钟 静态存储器 内存集成电路 |
| 文件： | 总28页 (文件大小：636K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT71V3556S/XS
IDT71V3558S/XS
IDT71V3556SA/XSA
IDT71V3558SA/XSA
128K x 36, 256K x 18
3.3VSynchronousZBTSRAMs
3.3V I/O, Burst Counter
PipelinedOutputs
Description
Features
◆
TheIDT71V3556/58are3.3Vhigh-speed4,718,592-bit(4.5Mega-
bit) synchronous SRAMS. They are designed to eliminate dead bus
cycles when turning the bus around between reads and writes, or
writes and reads. Thus, they have been given the name ZBTTM, or
Zero Bus Turnaround.
128K x 36, 256K x 18 memory configurations
◆
Supports high performance system speed - 200 MHz
(3.2 ns Clock-to-Data Access)
ZBTTM Feature - No dead cycles between write and read
◆
cycles
◆
Address and control signals are applied to the SRAM during one
clockcycle,andtwocycleslatertheassociateddatacycleoccurs,beit
read or write.
The IDT71V3556/58 contain data I/O, address and control signal
registers.Outputenableistheonlyasynchronoussignalandcanbeused
todisabletheoutputsatanygiventime.
A Clock Enable (CEN) pin allows operation of the IDT71V3556/58
to be suspended as long as necessary. All synchronous inputs are
ignored when (CEN) is high and the internal device registers will hold
their previous values.
Internally synchronized output buffer enable eliminates the
need to control OE
Single R/W (READ/WRITE) control pin
Positive clock-edge triggered address, data, and control
◆
◆
signal registers for fully pipelined applications
4-word burst capability (interleaved or linear)
Individual byte write (BW1 - BW4) control (May tie active)
Three chip enables for simple depth expansion
3.3V power supply (±5%), 3.3V I/O Supply (VDDQ)
Optional- Boundary Scan JTAG Interface (IEEE 1149.1
◆
◆
◆
◆
◆
Therearethreechipenablepins(CE1,CE2,CE2)thatallowtheuser
to deselect the device when desired. If any one of these three are not
asserted when ADV/LD is low, no new memory operation can be
initiated. However, any pending data transfers (reads or writes) will be
completed.Thedatabuswilltri-statetwocyclesafterchipisdeselected
orawriteisinitiated.
compliant)
◆
Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array (fBGA)
PinDescriptionSummary
A
0
-A17
Address Inputs
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
I/O
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Chip Enables
CE
1, CE
2
, CE
2
Output Enable
OE
R/W
Read/Write Signal
Clock Enable
CEN
Individual Byte Write Selects
Clock
BW
1, BW
2
, BW
3
, BW
4
CLK
ADV/LD
LBO
TMS
TDI
Advance burst address / Load new address
Linear / Interleaved Burst Order
Test Mode Select
Test Data Input
Synchronous
Static
Synchronous
Synchronous
N/A
TCK
Test Clock
TDO
TRST
ZZ
Test Data Output
Synchronous
Asynchronous
Synchronous
Synchronous
Static
JTAG Reset (Optional)
Sleep Mode
I/O
0-I/O31, I/OP1-I/OP4
Data Input / Output
Core Power, I/O Power
Ground
V
V
DD, VDDQ
SS
Supply
Supply
Static
5281 tbl 01
OCTOBER 2006
1
©2006IntegratedDeviceTechnology,Inc.
DSC-5281/09
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Descriptioncontinued
The IDT71V3556/58 has an on-chip burst counter. In the burst externaladdress(ADV/LD=LOW)orincrementtheinternalburstcounter
mode, the IDT71V3556/58 can provide four cycles of data for a single (ADV/LD = HIGH).
address presented to the SRAM. The order of the burst sequence is
The IDT71V3556/58 SRAMs utilize IDT's latest high-performance
defined by the LBO input pin. The LBO pin selects between linear and CMOSprocessandarepackagedinaJEDECstandard14mmx20mm
interleaved burst sequence. The ADV/LD signal is used to load a new 100-pinthinplasticquadflatpack(TQFP)aswellasa119ballgridarray
(BGA) and a 165 fine pitch ball grid array (fBGA).
Pin Definition(1)
Symbol
Pin Function
I/O
Active Description
Synchronous Address inputs. The address register is triggered by a combination of the rising edge of CLK,
ADV/LD low, CEN low, and true chip enables.
A
0-A17
Address Inputs
I
N/A
ADV/LD is a synchronous input that is used to load the internal registers with new address and control when it
is sampled low at the rising edge of clock with the chip selected. When ADV/LD is low with the chip
deselected, any burst in progress is terminated. When ADV/LD is sampled high then the internal burst counter
is advanced for any burst that was in progress. The external addresses are ignored when ADV/ LD is sampled
high.
ADV/LD
Advance / Load
I
N/A
R/W signal is a synchronous input that identifies whether the current load cycle initiated is a Read or Write
R/W
Read / Write
Clock Enable
I
I
N/A
access to the memory array. The data bus activity for the current cycle takes place two clock cycles later.
Synchronous Clock Enable Input. When CEN is sampled high, all other synchronous inputs, including clock are
ignored and outputs remain unchanged. The effect of CEN sampled high on the device outputs is as if the low
to high clock transition did not occur. For normal operation, CEN must be sampled low at rising edge of clock.
LOW
CEN
Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable. On load write cycles
(When R/W and ADV/LD are sampled low) the appropriate byte write signal (BW
write signal must also be valid on each cycle of a burst write. Byte Write signals are ignored when R/W is
sampled high. The appropriate byte(s) of data are written into the device two cycles later. BW -BW can all be
tied low if always doing write to the entire 36-bit word.
1
-BW4) must be valid. The byte
Individual Byte
Write Enables
I
I
LOW
LOW
BW
1
-BW
4
1
4
Synchronous active low chip enable. CE and CE are used with CE
1
2
2
to enable the IDT71V3556/58. (CE1 or
Chip Enables
CE sampled high or CE sampled low) and ADV/LD low at the rising edge of clock, initiates a deselect cycle.
2
2
CE1
, CE
2
The ZBTTM has a two cycle deselect, i.e., the data bus will tri-state two clock cycles after deselect is initiated.
Synchronous active high chip enable. CE is used with CE and CE to enable the chip. CE has inverted
2
1
2
2
CE
2
Chip Enable
Clock
I
I
HIGH
N/A
polarity but otherwise identical to CE and CE2.
1
This is the clock input to the IDT71V3556/58. Except for OE, all timing references for the device are made with
respect to the rising edge of CLK.
CLK
I/O -I/O31
0
Synchronous data input/output (I/O) pins. Both the data input path and data output path are registered and
triggered by the rising edge of CLK.
Data Input/Output
Linear Burst Order
I/O
I
N/A
I/OP1-I/OP4
Burst order selection input. When LBO is high the Interleaved burst sequence is selected. When LBO is low
the Linear burst sequence is selected. LBO is a static input and it must not change during device operation.
LOW
LBO
Asynchronous output enable. OE must be low to read data from the 71V3556/58. When OE is high the I/O pins
are in a high-impedance state. OE does not need to be actively controlled for read and write cycles. In normal
operation, OE can be tied low.
Output Enable
I
LOW
OE
TMS
TDI
Test Mode Select
Test Data Input
I
I
N/A
N/A
Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal pullup.
Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an internal
pullup.
Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of TCK,
while test outputs are driven from the falling edge of TCK. This pin has an internal pullup.
TCK
TDO
Test Clock
I
N/A
N/A
Serial output of registers placed between TDI and TDO. This output is active depending on the state of the TAP
controller.
Test Data Output
O
Optional Asynchronous JTAG reset. Can be used to reset the TAP controller, but not required. JTAG reset
occurs automatically at power up and also resets using TMS and TCK per IEEE 1149.1. If not used TRST can
be left floating. This pin has an internal pullup. Only available in BGA package.
JTAG Reset
(Optional)
I
I
LOW
TRST
Synchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the IDT71V3556/3558 to
HIGH its lowest power consumption level. Data retention is guaranteed in Sleep Mode. This pin has an internal
pulldown.
ZZ
Sleep Mode
V
DD
DDQ
SS
Power Supply
Power Supply
Ground
N/A
N/A
N/A
N/A
N/A
N/A
3.3V core power supply.
3.3V I/O Supply.
Ground.
V
V
5281 tbl 02
NOTE:
1. AllsynchronousinputsmustmeetspecifiedsetupandholdtimeswithrespecttoCLK.
6.42
2
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
FunctionalBlockDiagram
128Kx36 BIT
MEMORY ARRAY
LBO
Address A [0:16]
D
D
Q
Q
Address
CE1, CE2, CE2
R/W
CEN
Control
ADV/LD
BWx
DI
DO
D
Q
Control Logic
Clk
Mux
Sel
D
Output Register
Q
Clock
Gate
OE
5281 drw 01a
,
TMS
TDI
TCK
Data I/O [0:31],
I/O P[1:4]
JTAG
(SA Version)
TDO
TRST
(optional)
6.42
3
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
FunctionalBlockDiagram
256x18 BIT
MEMORY ARRAY
LBO
Address A [0:17]
D
D
Q
Q
Address
CE1, CE2, CE2
R/W
CEN
Control
ADV/LD
BWx
DI
DO
D
Q
Control Logic
Clk
Mux
Sel
D
Output Register
Q
Clock
Gate
OE
5281 drw 01b
,
TMS
TDI
TCK
Data I/O [0:15],
I/O P[1:2]
JTAG
(SA Version)
TDO
TRST
(optional)
RecommendedDCOperating
Conditions
Symbol
Parameter
Core Supply Voltage
I/O Supply Voltage
Supply Voltage
Min.
3.135
3.135
0
Typ.
Max.
3.465
3.465
0
Unit
V
V
DD
DDQ
SS
3.3
V
3.3
V
V
0
V
____
V
IH
IH
IL
Input High Voltage - Inputs
Input High Voltage - I/O
Input Low Voltage
2.0
V
DD +0.3
V
____
____
V
2.0
V
DDQ +0.3(2)
0.8
V
V
-0.3(1)
V
5281 tbl 04
NOTES:
1. VIL (min.) = –1.0V for pulse width less than tCYC/2, once per cycle.
2. VIH (max.) = +6.0V for pulse width less than tCYC/2, once per cycle.
6.42
4
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
RecommendedOperating
TemperatureandSupplyVoltage
Grade
Commercial
Industrial
Temperature(1)
0°C to +70°C
-40°C to +85°C
V
SS
V
DD
VDDQ
0V
0V
3.3V±5%
3.3V±5%
3.3V±5%
3.3V±5%
5281 tbl 05
NOTES:
1. TA is the "instant on" case temperature.
Pin Configuration - 128K x 36
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
79
78
77
I/OP3
I/O16
I/O17
I/OP2
I/O15
I/O14
2
3
4
VDDQ
VDDQ
5
VSS
76
75
74
73
VSS
6
I/O18
I/O19
I/O20
I/O21
I/O13
I/O12
I/O11
I/O10
7
8
9
72
71
70
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VSS
VSS
VDDQ
VDDQ
69
68
67
66
65
64
63
62
61
60
59
I/O22
I/O9
I/O8
I/O23
(1)
VDD
V
SS
(1)
V
DD
DD
V
V
V
DD
(1)
V
DD
SS/ZZ(3)
VSS
I/O24
I/O25
I/O7
I/O6
VDDQ
V
V
DDQ
SS
VSS
I/O26
I/O27
I/O28
I/O29
I/O
I/O
I/O
I/O
5
58
57
56
55
4
3
2
VSS
VSS
,
54
53
VDDQ
VDDQ
I/O30
I/O31
I/OP4
I/O
I/O
1
0
52
51
I/OP1
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
5281 drw 02
Top View
100TQFP
NOTES:
1. Pins 14, 16 and 66 do not have to be connected directly to VDD as long as the input voltage is ≥ VIH.
2. Pins 83 and 84 are reserved for future 8M and 16M respectively.
3. Pin 64 does not have to be connected directly to VSS as long as the input voltage is ≤ VIL; on the latest die revision this
pin supports ZZ (sleep mode).
6.42
5
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Pin Configuration - 256K x 18
Absolute Maximum Ratings (1)
Commercial &
Symbol
Rating
Unit
Industrial Values
(2)
V
V
V
V
TERM
Terminal Voltage with
Respect to GND
-0.5 to +4.6
V
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
NC
NC
NC
DDQ
A
NC
NC
10
(3,6)
2
79
78
77
TERM
Terminal Voltage with
Respect to GND
-0.5 to VDD
-0.5 to VDD +0.5
-0.5 to VDDQ +0.5
-0 to +70
V
3
4
V
VDDQ
5
VSS
76
75
74
73
VSS
(4,6)
TERM
Terminal Voltage with
Respect to GND
V
6
NC
NC
I/O8
NC
I/OP1
I/O
7
8
7
9
I/O9
72
71
70
I/O
6
(5,6)
TERM
Terminal Voltage with
Respect to GND
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VSS
VSS
V
DDQ
VDDQ
69
68
67
66
65
64
63
62
61
60
59
I/O10
I/O
I/O
5
oC
oC
oC
oC
W
I/O11
4
Commercial
Operating Temperature
(1)
V
DD
V
SS
(1)
A(7)
V
DD
DD
V
V
V
DD
T
(1)
V
DD
SS/ZZ(3)
Industrial
Operating Temperature
-40 to +85
VSS
I/O12
I/O13
I/O
I/O
3
2
V
DDQ
V
V
DDQ
SS
Te mp e rature
Under Bias
-55 to +125
TBIAS
VSS
I/O14
I/O15
I/OP2
NC
I/O
I/O
NC
NC
1
58
57
56
55
0
Storage
Te mp e rature
-55 to +125
TSTG
VSS
VSS
,
54
53
V
DDQ
NC
NC
NC
VDDQ
NC
NC
NC
P
T
Power Dissipation
DC Output Current
2.0
50
52
51
IOUT
mA
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
5281 drw 02a
5281 tbl 06
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD terminals only.
3. VDDQ terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supply has
reached its nominal operating value. Power sequencing is not necessary;
however, the voltage on any input or I/O pin cannot exceed VDDQ during power
supply ramp up.
Top View
100TQFP
NOTES:
1. Pins 14, 16 and 66 do not have to be connected directly to VDD as long as
the input voltage is ≥ VIH.
2. Pins 83 and 84 are reserved for future 8M and 16M respectively.
3. Pin 64 does not have to be connected directly to VSS as long as the input
voltage is ≤ VIL; on the latest die revision this pin supports ZZ (sleep
mode).
7. TA is the "instant on" case temperature.
100PinTQFPCapacitance(1)
119BGACapacitance(1)
(TA = +25° C, f = 1.0MHz)
(TA = +25° C, f = 1.0MHz)
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
IN = 3dV
OUT = 3dV
Max. Unit
Symbol
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
IN = 3dV
OUT = 3dV
Max. Unit
Symbol
CIN
V
5
7
pF
CIN
V
7
7
pF
CI/O
V
pF
CI/O
V
pF
5281 tbl 07
5281 tbl 07a
165fBGACapacitance(1)
(TA = +25° C, f = 1.0MHz)
Symbol
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
IN = 3dV
OUT = 3dV
Max. Unit
CIN
V
TBD
TBD
pF
CI/O
V
pF
5281 tbl 07b
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
6.42
6
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Pin Configuration - 128K x 36, 119 BGA
1
2
3
4
5
6
7
DDQ
6
4
8
16
DDQ
V
A
B
C
D
E
F
V
A
A
A
A
A
A
A
NC(2)
ADV/LD
2
3
2
9
NC
NC
16
CE
NC
NC
CE
2
7
A
DD
V
12
15
A
A
P3
I/O
SS
SS
SS
SS
SS
SS
P2
I/O
15
I/O
I/O
V
V
V
NC
V
V
V
17
I/O
18
I/O
13
I/O
14
I/O
1
CE
DDQ
20
19
I/O
12
I/O
DDQ
10
V
V
V
V
OE
21
I/O
11
I/O
G
H
J
I/O
NC(2)
I/O
2
BW
3
BW
22
I/O
23
I/O
SS
SS
V
9
I/O
8
I/O
V
V
V
R/W
DDQ
24
DD
DD
V
DD
DDQ
V
DD(1)
SS
DD(1)
V
V
V
26
I/O
SS
6
I/O
7
I/O
K
L
I/O
CLK
NC
V
25
I/O
27
I/O
4
I/O
5
I/O
4
BW
BW
1
DDQ
29
28
I/O
SS
V
SS
SS
SS
3
I/O
DDQ
V
M
N
P
R
T
V
V
V
CEN
30
I/O
SS
1
2
I/O
1
I/O
I/O
V
V
A
A
0
I/O
31
I/O
P4
I/O
SS
0
P1
I/O
,
5
A
DD
11
VDD(1)
13
A
NC
V
NC
LBO
(5)
10
A
14
NC
NC
A
A
NC
NC/ZZ
(3)
(3)
(3)
(3)
(3,4)
DDQ
DDQ
V
NC/TMS
NC/TDI
NC/TCK
NC/TDO
U
V
NC/TRST
5281 drw 13A
Top View
Pin Configuration - 256K x 18, 119 BGA
1
2
3
4
5
6
7
DDQ
6
4
8
16
DDQ
V
V
A
A
A
A
A
A
A
A
B
C
D
E
F
NC(2)
3
2
9
NC
NC
CE2
NC
NC
NC
2
CE
ADV/LD
7
A
DD
V
13
17
A
A
8
I/O
SS
SS
SS
SS
SS
SS
SS
P1
I/O
NC
V
V
V
NC
V
V
V
V
9
I/O
7
I/O
NC
DDQ
CE
1
NC
6
I/O
DDQ
V
V
NC
OE
10
5
I/O
G
H
J
NC
I/O
NC
NC(2)
NC
BW
2
11
I/O
SS
SS
4
I/O
V
V
V
V
NC
R/W
DD(1)
DD(1)
SS
DDQ
V
DD
12
DD
V
DD
DDQ
V
V
V
V
SS
3
I/O
K
L
NC
I/O
V
CLK
NC
NC
13
I/O
SS
2
I/O
NC
V
V
V
V
NC
BW
1
DDQ
15
14
I/O
SS
SS
SS
SS
SS
SS
DDQ
V
M
N
P
R
T
V
V
V
V
NC
CEN
1
A
1
I/O
I/O
NC
NC
P2
I/O
0
A
0
I/O
NC
NC
5
A
DD
V
12
A
NC
NC
NC
DDQ
V
DD(1)
LBO
(5)
10
15
A
14
11
A
A
NC
A
NC/ZZ
,
(3,4)
(3)
(3)
(3)
(3)
NC/TRST
DDQ
V
5281drw 13B
V
NC/TMS
NC/TDI
NC/TCK
NC/TDO
U
TopView
NOTES:
1. J3, J5, and R5 do not have to be directly connected to VDD as long as the input voltage is ≥ VIH.
2. G4 and A4 are reserved for future 8M and 16M respectively.
3. These pins are NC for the "S" version or the JTAG signal listed for the "SA" version.
4. TRST is offered as an optional JTAG reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.
5. Pin T7 does not have to be connected directly to VSS as long as the input voltage is ≤ VIL; on the latest die revision this pin supports ZZ (sleep mode).
6.42
7
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Pin Configuration - 128K x 36, 165 fBGA
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
NC(2)
NC
A
7
6
ADV/LD
OE
NC(2)
NC(2)
A
A
8
9
NC
CE1
BW
3
BW
2
CE
2
CEN
R/W
A
CE
2
CLK
NC(2)
I/OP2
I/O14
I/O12
I/O10
BW4
BW1
I/OP3
I/O17
I/O19
I/O21
I/O23
NC
V
V
V
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
V
V
V
V
V
V
V
V
V
V
V
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
V
V
V
V
V
V
V
V
V
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
V
V
V
V
V
V
V
V
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
V
V
V
V
V
V
V
V
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
V
V
V
V
V
V
V
V
V
V
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
V
DDQ
DDQ
DDQ
DDQ
DDQ
NC
I/O16
I/O18
I/O20
I/O22
V
V
V
V
I/O15
I/O13
I/O11
G
H
J
I/O
9
I/O8
(5)
V
DD(1)
V
DD(1)
I/O24
I/O26
I/O28
I/O30
NC
NC
NC
NC
NC/ZZ
I/O25
I/O27
I/O29
I/O31
I/OP4
NC
V
DDQ
DDQ
DDQ
DDQ
DDQ
V
DDQ
DDQ
DDQ
DDQ
DDQ
I/O
I/O
I/O
7
I/O6
I/O4
I/O2
I/O0
K
L
V
V
V
V
V
V
V
V
5
3
M
N
P
R
I/O
1
NC/TRST(3, 4)
NC/TDI(3)
NC
V
DD(1)
NC
I/OP1
NC
NC(2)
NC(2)
A
A
5
4
A
2
3
A
1
NC/TDO(3)
NC/TCK(3)
A
10
11
A
13
12
A
A
14
15
A
NC/TMS(3)
A
0
A
A
A
16
LBO
5281 tbl 25
Pin Configuration - 256K x 18, 165 fBGA
1
NC(2)
NC
NC
NC
NC
NC
NC
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
A
7
6
NC
ADV/LD
OE
NC(2)
NC(2)
A
A
8
9
A10
CE
1
BW
2
CE
2
CEN
R/W
A
CE
2
NC
CLK
NC(2)
I/OP1
BW
1
NC
V
DDQ
DDQ
DDQ
DDQ
DDQ
V
V
V
V
V
V
V
V
V
V
V
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
V
V
V
V
V
V
V
V
V
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
V
V
V
V
V
V
V
V
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
V
V
V
V
V
V
V
V
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
V
V
V
V
V
V
V
V
V
V
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
V
DDQ
DDQ
DDQ
DDQ
DDQ
NC
NC
NC
NC
NC
NC
I/O
8
V
V
V
V
V
V
V
V
I/O7
I/O6
I/O5
I/O4
I/O
9
I/O10
I/O11
G
H
J
(5)
V
DD(1)
I/O12
I/O13
I/O14
I/O15
I/OP2
NC
V
DD(1)
NC
NC
NC/ZZ
NC
V
DDQ
DDQ
DDQ
DDQ
DDQ
V
DDQ
DDQ
DDQ
DDQ
DDQ
I/O3
NC
K
L
NC
V
V
V
V
V
V
V
V
I/O2
NC
NC
I/O
I/O
NC
1
NC
M
N
P
R
NC
0
NC
NC
NC/TRST(3, 4)
NC/TDI(3)
NC
V
DD(1)
NC
NC(2)
NC(2)
A
A
5
4
A
2
3
A
1
NC/TDO(3)
NC/TCK(3)
A
11
A
14
13
A
A
15
16
NC
A
NC/TMS(3)
A
0
A
12
A
A
17
LBO
5281 tbl 25a
NOTES:
1. H1, H2, and N7 do not have to be directly connected to VDD as long as the input voltage is ≥ VIH.
2. A9, B9, B11, A1, R2 and P2 are reserved for future 9M, 18M, 36M, 72M, 144M and 288M respectively.
3. These pins are NC for the "S" version or the JTAG signal listed for the "SA" version.
4. TRST is offered as an optional JTAG reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.
5. Pin H11 does not have to be connected directly to VSS as long as the input voltage is ≤ VIL; on the latest die revision this pin supports ZZ (sleep mode).
6.42
8
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
SynchronousTruthTable (1)
Chip(5)
ADV/LD
ADDRESS
USED
PREVIOUS CYCLE
CURRENT CYCLE
I/O
CEN
BWx
R/W
Enable
(2 cycles later)
L
L
L
L
H
X
Select
Select
X
L
L
Valid
X
External
External
Internal
X
X
LOAD WRITE
LOAD READ
D(7)
Q(7)
D(7)
H
Valid
LOAD WRITE /
BURST WRITE
BURST WRITE
(Advance burst counter)(2)
L
X
X
H
X
Internal
LOAD READ /
BURST READ
BURST READ
Q(7)
(Advance burst counter)(2)
L
L
X
X
X
Deselect
L
H
X
X
X
X
X
X
X
X
DESELECT or STOP(3)
NOOP
HiZ
HiZ
X
X
DESELECT / NOOP
X
H
SUSPEND(4)
Previous Value
5281 tbl 08
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of
the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle.
3. Deselect cycle is initiated when either (CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will
tri-state two cycles after deselect is initiated.
4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the I/
Os remains unchanged.
5. To select the chip requires CE1 = L, CE2 = L, CE2 = H on these chip enables. Chip is deselected if any one of the chip enables is false.
6. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
7. Q - Data read from the device, D - data written to the device.
Partial Truth Table for Writes (1)
(3)
(3)
BW
1
BW
2
BW
3
BW4
OPERATION
R/W
H
L
READ
X
X
X
L
X
L
WRITE ALL BYTES
L
L
(2)
WRITE BYTE 1 (I/O[0:7], I/OP1
)
L
L
H
L
H
H
L
H
H
H
L
(2)
WRITE BYTE 2 (I/O[8:15], I/OP2
)
L
H
H
H
H
(2,3)
WRITE BYTE 3 (I/O[16:23], I/OP3
)
L
H
H
H
(2,3)
WRITE BYTE 4 (I/O[24:31], I/OP4
)
L
H
H
NO WRITE
L
H
5281 tbl 09
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Multiple bytes may be selected during the same cycle.
3. N/A for X18 configuration.
6.42
9
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Interleaved Burst Sequence Table (LBO=VDD)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
0
A1
A0
1
A1
A0
0
A1
A0
First Address
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
0
1
Second Address
Third Address
1
0
1
0
0
1
0
1
Fourth Address(1)
1
0
1
0
5281 tbl 10
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
LinearBurstSequenceTable(LBO=VSS)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
0
A1
A0
1
A1
1
A0
0
A1
1
A0
First Address
0
0
1
1
0
1
1
0
1
Second Address
Third Address
1
0
1
1
0
0
0
1
0
0
0
1
Fourth Address(1)
1
0
0
1
1
0
5281 tbl 11
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
Functional Timing Diagram (1)
CYCLE
n+29
n+30
n+31
n+32
n+33
n+34
n+35
n+36
n+37
CLOCK
(2)
ADDRESS
A29
C29
A30
C30
A31
C31
A32
C32
A33
C33
A34
C34
A35
C35
A36
C36
A37
C37
(A0 - A16)
(2)
CONTROL
(R/W, ADV/LD, BWx)
(2)
DATA
D/Q27
D/Q28
D/Q29
D/Q30
D/Q32
D/Q33
D/Q34
D/Q35
D/Q31
I/O [0:31], I/O P[1:4]
,
5281 drw 03
NOTES:
1. This assumes CEN, CE1, CE2, CE2 are all true.
2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data
delay from the rising edge of clock.
6.42
10
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Device Operation - Showing Mixed Load, Burst,
Deselect and NOOP Cycles (2)
(1)
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
I/O
Comments
CE
n
A
0
H
X
H
X
X
H
X
X
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
X
X
X
X
X
X
L
X
X
L
X
X
Load read
Burst read
Load read
n+1
X
X
L
n+2
A
1
Q0
n+3
X
X
L
H
X
L
L
Q0+1 Deselect or STOP
n+4
H
L
L
Q1
NOOP
n+5
A
2
X
X
L
Z
Z
Load read
n+6
X
X
H
L
X
H
L
Burst read
n+7
Q2
Deselect or STOP
n+8
A
3
L
L
Q2+1 Load write
n+9
X
X
L
H
L
X
L
L
X
X
X
X
X
X
X
L
Z
Burst write
Load write
n+10
n+11
n+12
n+13
n+14
n+15
n+16
n+17
n+18
n+19
A
4
L
D3
X
X
X
X
L
L
H
X
L
X
X
L
D3+1 Deselect or STOP
H
L
D4
NOOP
A
5
6
7
Z
Z
Load write
Load read
Load write
Burst write
Load read
A
A
H
L
L
L
X
L
L
L
D5
X
X
H
X
L
H
L
X
L
L
Q6
A
8
9
X
X
L
X
X
L
D7
X
H
L
X
L
D7+1 Burst read
A
Q8
Load write
5281 tbl 12
NOTES:
1. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
2. H = High; L = Low; X = Don’t Care; Z = High Impedance.
Read Operation (1)
(2)
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
I/O
Comments
CE
L
n
A
0
H
X
X
L
X
X
L
L
X
X
X
X
X
L
X
X
Address and Control meet setup
Clock Setup Valid
n+1
n+2
X
X
X
X
X
Q0
Contents of Address A0 Read Out
5281 tbl 13
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
6.42
11
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Burst Read Operation (1)
(2)
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
I/O
Comments
CE
n
A
0
H
X
X
X
X
H
X
X
H
L
L
L
L
L
L
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
L
X
X
Address and Control meet setup
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
X
H
H
H
H
L
X
X
X
X
L
Clock Setup Valid, Advance Counter
X
X
X
Q0
Address A0 Read Out, Inc. Count
Q
0+1
0+2
0+3
Address A0+1 Read Out, Inc. Count
Address A0+2 Read Out, Inc. Count
Q
Q
A
X
X
1
Address A0+3 Read Out, Load A1
H
H
L
X
X
L
Q0
Address A
Address A
0
1
Read Out, Inc. Count
Read Out, Inc. Count
Q1
A
2
Q1+1
Address A1+1 Read Out, Load A2
5281 tbl 14
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance..
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Write Operation (1)
(2)
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
I/O
Comments
CE
L
n
A
0
L
X
X
L
X
X
L
L
L
L
X
X
X
X
X
X
X
Address and Control meet setup
Clock Setup Valid
n+1
n+2
X
X
X
X
D0
Write to Address A0
5281 tbl 15
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Burst Write Operation (1)
(2)
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
I/O
Comments
CE
n
A
0
L
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
Address and Control meet setup
Clock Setup Valid, Inc. Count
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
X
H
H
H
H
L
X
X
X
X
L
X
X
D0
Address A0 Write, Inc. Count
D0+1
Address A0+1 Write, Inc. Count
Address A0+2 Write, Inc. Count
X
D
0+2
0+3
A1
X
D
Address A0+3 Write, Load A1
X
X
L
H
H
L
X
X
L
D0
Address A
Address A
0
1
Write, Inc. Count
Write, Inc. Count
X
D1
A
2
D1+1
Address A1+1 Write, Load A2
5281 tbl 16
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
6.42
12
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Read Operation with Clock Enable Used (1)
(2)
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
I/O
Comments
CE
n
A
0
H
X
H
X
X
H
H
H
L
X
L
X
X
L
L
L
L
L
H
L
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
X
X
X
Address and Control meet setup
Clock n+1 Ignored
n+1
n+2
n+3
n+4
n+5
n+6
n+7
X
X
L
A
1
Clock Valid
X
X
X
X
L
H
H
L
Q0
Q0
Q0
Clock Ignored. Data Q
0
0
is on the bus.
is on the bus.
Clock Ignored. Data Q
A
2
3
4
Address A
Address A
Address A
0
1
2
Read out (bus trans.)
Read out (bus trans.)
Read out (bus trans.)
A
A
L
L
Q1
L
L
Q2
5281 tbl 17
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Write Operation with Clock Enable Used (1)
(2)
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
I/O
Comments
CE
n
A
0
L
X
L
X
X
L
L
L
L
X
L
X
X
L
L
L
L
L
H
L
L
X
L
X
X
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
Address and Control meet setup.
Clock n+1 Ignored.
Clock Valid.
n+1
n+2
n+3
n+4
n+5
n+6
n+7
X
X
L
A
1
X
X
X
X
L
H
H
L
Clock Ignored.
Clock Ignored.
A
2
3
4
D0
Write Data D
Write Data D
Write Data D
0
A
A
L
L
D1
1
L
L
D2
2
5281 tbl 18
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
6.42
13
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Read Operation with CHIP Enable Used (1)
(2)
I/O(3)
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
Comments
CE
H
H
L
n
X
X
X
X
H
X
H
X
X
H
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
?
?
Z
Z
Deselected.
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9
Deselected.
A
0
Address and Control meet setup
Deselected or STOP.
X
H
L
A
1
Q0
Address A
Deselected or STOP.
Address A Read out. Deselected.
0 Read out. Load A1.
X
X
H
H
L
X
L
Z
Q
Z
Z
1
1
A
2
X
X
L
Address and control meet setup.
Deselected or STOP.
X
X
H
H
Q
2
Address A2 Read out. Deselected.
5281 tbl 19
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
3. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
Write Operation with Chip Enable Used (1)
(2)
I/O(3)
CEN
BWx
OE
Cycle
Address
R/W
ADV/LD
Comments
CE
H
H
L
n
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
?
?
Z
Z
Deselected.
Deselected.
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9
A
0
Address and Control meet setup
Deselected or STOP.
X
X
L
H
L
X
L
A
1
D0
Address D
Deselected or STOP.
Address D Write in. Deselected.
0 Write in. Load A1.
X
X
X
X
L
H
H
L
X
X
L
Z
D
Z
Z
1
1
A
2
Address and control meet setup.
Deselected or STOP.
X
X
X
X
H
H
X
X
D2
Address D2 Write in. Deselected.
5281 tbl 20
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
6.42
14
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V +/-5%)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
___
|ILI|
Input Leakage Current
V
DD = Max., VIN = 0V to VDD
5
µA
LBO, JTAG and ZZ Input Leakage Current(1)
Output Leakage Current
___
___
___
|ILI
|
V
V
DD = Max., VIN = 0V to VDD
30
5
µA
µA
V
|ILO
|
OUT = 0V to VDDQ, Device Deselected
V
OL
OH
Output Low Voltage
IOL = +8mA, VDD = Min.
0.4
___
V
Output High Voltage
IOH = -8mA, VDD = Min.
2.4
V
5281 tbl 21
NOTE:
1. The LBO, TMS, TDI, TCK and TRST pins will be internally pulled to VDD and ZZ will be internally pulled if they are not actively driven in the application.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (1) (VDD = 3.3V +/-5%)
200MHz
166MHz
133MHz
100MHz
Symbol
Parameter
Test Conditions
Com'l Only Com'l
Ind
Com'l
Ind
Com'l
Ind
Unit
I
DD
Device Selected, Outputs Open,
Operating Power
Supply Current
400
40
350
40
360
300
40
310
250
40
255
mA
ADV/LD = X, VDD = Max.,
(2)
V
IN > VIH or < VIL, f = fMAX
ISB1
Device Deselected, Outputs Open,
CMOS Standby
Power Supply Current
45
130
45
45
120
45
45
110
45
mA
mA
V
DD = Max., VIN > VHD or < VLD, f
= 0(2,3)
ISB2
Device Deselected, Outputs Open,
Clock Running Power
Supply Current
130
40
120
40
110
40
100
40
V
DD = Max., VIN > VHD or < VLD, f
(2.3)
= fMAX
ISB3
Device Selected, Outputs Open,
Idle Power
Supply Current
mA
CEN > VIH, VDD = Max.,
(2,3)
V
IN > VHD or < VLD, f = fMAX
5281 tbl 22
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC; f=0 means no input lines are changing.
3. For I/Os VHD = VDDQ – 0.2V, VLD = 0.2V. For other inputs VHD = VDD – 0.2V, VLD = 0.2V.
AC Test Loads
AC Test Conditions
V
DDQ/2
(VDDQ = 3.3V)
50Ω
Input Pulse Levels
0 to 3V
2ns
I/O
Z0
= 50Ω
,
6
5
4
Input Rise/Fall Times
5281 drw 04
Input Timing Reference Levels
Output Timing Reference Levels
AC Test Load
1.5V
Figure 1. AC Test Load
1.5V
See Figure 1
3
ΔtCD
(Typical, ns)
5281 tbl 23
2
1
,
20 30 50
80 100
Capacitance (pF)
200
5281 drw 05
Figure 2. Lumped Capacitive Load, Typical Derating
6.42
15
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = 3.3V +/-5%, Commercial and Industrial Temperature Ranges)
200MHz(6)
166MHz
133MHz
100MHz
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
____
____
____
____
t
CYC
Clock Cycle Time
5
6
7.5
10
ns
MHz
ns
____
____
____
____
(1)
Clock Frequence
200
166
133
100
tF
____
____
____
____
(2)
CH
Clock High Pulse Width
Clock Low Pulse Width
1.8
1.8
1.8
1.8
2.2
2.2
3.2
3.2
t
____
____
____
____
(2)
CL
ns
t
Output Parameters
____
____
____
____
t
CD
Clock High to Valid Data
Clock High to Data Change
Clock High to Output Active
3.2
3.5
4.2
5
ns
ns
ns
____
____
____
____
tCDC
1
1
1
1
1
1
1
1
____
____
____
____
(3, 4,5)
(3, 4,5)
tCL Z
Clock High to Data High-Z
1
3
1
3
1
3
1
3.3
ns
ns
ns
ns
tCHZ
____
____
____
____
tOE
Output Enable Access Time
Output Enable Low to Data Active
Output Enable High to Data High-Z
3.2
3.5
4.2
5
____
____
____
____
(3,4)
0
0
0
0
tOLZ
____
____
____
____
(3,4)
OHZ
3.5
3.5
4.2
5
t
Set Up Times
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
SE
SA
SD
SW
SADV
SC
SB
Clock Enable Setup Time
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.7
1.7
1.7
1.7
1.7
1.7
1.7
2.0
2.0
2.0
2.0
2.0
2.0
2.0
ns
ns
ns
ns
ns
ns
ns
t
Address Setup Time
t
Data In Setup Time
t
Read/Write (R/W) Setup Time
Advance/Load (ADV/LD) Setup Time
Chip Enable/Select Setup Time
Byte Write Enable (BWx) Setup Time
t
t
t
Hold Times
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
HE
HA
HD
HW
HADV
HC
HB
Clock Enable Hold Time
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
t
Address Hold Time
t
Data In Hold Time
t
Read/Write (R/W) Hold Time
Advance/Load (ADV/LD) Hold Time
Chip Enable/Select Hold Time
Byte Write Enable (BWx) Hold Time
t
t
t
ns
5281 tbl 24
NOTES:
1. tF = 1/tCYC.
2. Measured as HIGH above 0.6VDDQ and LOW below 0.4VDDQ.
3. Transition is measured ±200mV from steady-state.
4. These parameters are guaranteed with the AC load (Figure 1) by device characterization. They are not production tested.
5. To avoid bus contention, the output buffers are designed such that tCHZ (device turn-off) is about 1ns faster than tCLZ (device turn-on) at a given temperature and voltage.
The specs as shown do not imply bus contention because tCLZ is a Min. parameter that is worse case at totally different test conditions (0 deg. C, 3.465V) than tCHZ,
which is a Max. parameter (worse case at 70 deg. C, 3.135V).
6. Commercial temperature range only.
6.42
16
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle (1,2,3,4)
,
,
6.42
17
tCYC
CLK
tCH
tCL
tSE
tHE
CEN
tSADV
tHADV
ADV/LD
R/W
tSW
tHW
tSA
tHA
A2
ADDRESS
A1
t
SC
t
HC
HB
CE1, CE2 (2)
tSB
t
BW1 - BW4
OE
(CEN high, eliminates
current L-H clock edge)
(Burst Wraps around
to initial state)
tSD
tHD
tSD
tHD
DATAIN
D(A1)
D(A2)
D(A2+3
)
D(A2)
D(A2+1
)
D(A2+2
)
Pipeline
Write
Burst Pipeline Write
5281 drw 07
Pipeline
Write
NOTES:
1. D (A1) represents the first input to the external address A1. D (A2) represents the first input to the external address A2; D (A2+1) represents the next input data in the burst sequence of
the base address A2, etc. where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW.
4. R/Wisdon'tcarewhentheSRAMisbursting(ADV/LDsampledHIGH). Thenatureoftheburstaccess(ReadorWrite)isfixedbythestateoftheR/Wsignalwhennewaddressandcontrolare
loadedintotheSRAM.
5. IndividualByteWritesignals(BWx)mustbevalidonallwriteandburst-writecycles.AwritecycleisinitiatedwhenR/WsignalissampledLOW. Thebytewriteinformationcomesintwocyclesbefore
theactualdataispresentedtotheSRAM.
tCYC
CLK
tCH
tCL
tSE
tHE
CEN
tSADV
tHADV
ADV/LD
tSW
tHW
R/W
tSA
tHA
A2
A5
A3
A4
A8
A9
A1
A6
A7
ADDRESS
tSC
tHC
(2)
CE
1
, CE
2
tSB
tHB
BW1 - BW
4
OE
tSD tHD
D(A5)
D(A4)
D(A2)
DATAIN
Write
Write
t
tCLZ
CDC
t
CHZ
tCD
Q(A6)
Q(A3)
Q(A7)
Q(A1)
DATAOUT
Read
Read
Read
5281 drw 08
NOTES:
1. Q (A1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. IndividualByteWritesignals(BWx)mustbevalidonallwriteandburst-writecycles.AwritecycleisinitiatedwhenR/WsignalissampledLOW. Thebytewriteinformationcomesintwocyclesbefore
theactualdataispresentedtotheSRAM.
tCYC
CLK
t
CH
tCL
tSE
tHE
CEN
tSADV
t
HADV
ADV/LD
tSW
tHW
R/W
tSA
tHA
A2
A4
A5
A1
A3
ADDRESS
t
SC
tHC
(2)
CE1, CE2
tSB
tHB
B(A2)
BW1 - BW4
OE
tSD tHD
D(A2)
DATAIN
tCHZ
tCDC
tCD
Q(A1)
Q(A3)
Q(A1)
DATAOUT
t
CLZ
5281 drw 09
NOTES:
1. Q (A1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. CENwhensampledhighontherisingedgeofclockwillblockthatL-HtransitionoftheclockfrompropogatingintotheSRAM. ThepartwillbehaveasiftheL-Hclocktransitiondidnotoccur. All
internalregistersintheSRAMwillretaintheirpreviousstate.
4. IndividualByteWritesignals(BWx)mustbevalidonallwriteandburst-writecycles.AwritecycleisinitiatedwhenR/WsignalissampledLOW. Thebytewriteinformationcomesintwocyclesbefore
theactualdataispresentedtotheSRAM.
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of CS Operation (1,2,3,4)
,
6.42
21
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
JTAG Interface Specification (SA Version only)
t
JCYC
t
JR
tJF
t
JCL
tJCH
TCK
Device Inputs(1)/
TDI/TMS
tJDC
tJS
tJH
Device Outputs(2)/
TDO
t
JRSR
tJCD
3)
(
x
TRST
M5281 drw 01
t
JRST
NOTES:
1. Device inputs = All device inputs except TDI, TMS and TRST.
2. Device outputs = All device outputs except TDO.
3. During power up, TRST could be driven low or not be used since the JTAG circuit resets automatically. TRST is an optional JTAG reset.
JTAG AC Electrical
Characteristics(1,2,3,4)
Symbol
Parameter
JTAG Clock Input Period
JTAG Clock HIGH
JTAG Clock Low
JTAG Clock Rise Time
JTAG Clock Fall Time
JTAG Reset
Min.
100
40
Max.
Units
ns
ScanRegisterSizes
____
t
JCYC
JCH
JCL
JR
JF
JRST
JRSR
JCD
JDC
JS
JH
Register Name
Bit Size
____
____
t
ns
Instruction (IR)
4
1
t
40
ns
Bypass (BYR)
t
5(1)
ns
____
JTAG Identification (JIDR)
Boundary Scan (BSR)
32
t
5(1)
ns
____
Note (1)
____
t
50
ns
I5281 tbl 03
____
t
JTAG Reset Recovery
JTAG Data Output
JTAG Data Output Hold
JTAG Setup
50
ns
NOTE:
1. The Boundary Scan Descriptive Language (BSDL) file for this device is available
by contacting your local IDT sales representative.
____
t
20
ns
____
t
0
ns
____
____
t
25
25
ns
t
JTAG Hold
ns
I5281 tbl 01
NOTES:
1. Guaranteed by design.
2. AC Test Load (Fig. 1) on external output signals.
3. Refer to AC Test Conditions stated earlier in this document.
4. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet.
6.42
22
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
JTAG Identification Register Definitions (SA Version only)
Instruction Field
Revision Number (31:28)
Value
Description
0x2
Reserved for version number.
IDT Device ID (27:12)
0x208, 0x20A
Defines IDT part number 71V3556SA and 71V3558SA, respectively.
Allows unique identification of device vendor as IDT.
Indicates the presence of an ID register.
IDT JEDEC ID (11:1)
0x33
1
ID Register Indicator Bit (Bit 0)
I5281 tbl 02
AvailableJTAGInstructions
Instruction
Description
OPCODE
Forces contents of the boundary scan cells onto the device outputs(1).
Places the boundary scan register (BSR) between TDI and TDO.
EXTEST
0000
Places the boundary scan register (BSR) between TDI and TDO.
SAMPLE allows data from device inputs(2) and outputs(1) to be captured
in the boundary scan cells and shifted serially through TDO. PRELOAD
allows data to be input serially into the boundary scan cells via the TDI.
SAMPLE/PRELOAD
0001
Loads the JTAG ID register (JIDR) with the vendor ID code and places
the register between TDI and TDO.
DEVICE_ID
HIGHZ
0010
0011
Places the bypass register (BYR) between TDI and TDO. Forces all
device output drivers to a High-Z state.
RESERVED
RESERVED
RESERVED
RESERVED
0100
0101
0110
0111
Several combinations are reserved. Do not use codes other than those
identified for EXTEST, SAMPLE/PRELOAD, DEVICE_ID, HIGHZ, CLAMP,
VALIDATE and BYPASS instructions.
Uses BYR. Forces contents of the boundary scan cells onto the device
outputs. Places the bypass register (BYR) between TDI and TDO.
CLAMP
1000
RESERVED
RESERVED
RESERVED
RESERVED
1001
1010
1011
1100
Same as above.
Automatically loaded into the instruction register whenever the TAP
controller passes through the CAPTURE-IR state. The lower two bits '01'
are mandated by the IEEE std. 1149.1 specification.
VALIDATE
1101
RESERVED
BYPASS
Same as above.
1110
1111
The BYPASS instruction is used to truncate the boundary scan register
as a single bit in length.
I5281 tbl 04
NOTES:
1. Device outputs = All device outputs except TDO.
2. Device inputs = All device inputs except TDI, TMS, and TRST.
6.42
23
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
100-Pin Plastic Thin Quad Flatpack (TQFP) Package Diagram Outline
6.42
24
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
119 Ball Grid Array (BGA) Package Diagram Outline
6.42
25
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
165 Fine Pitch Ball Grid Array (fBGA) Package Diagram Outline
6.42
26
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of OE Operation (1)
OE
tOE
tOHZ
tOLZ
DATAOUT
Valid
,
5281 drw 11
NOTE:
1. A read operation is assumed to be in progress.
OrderingInformation
6.42
27
IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
DatasheetDocumentHistory
6/30/99
8/23/99
Updatedtonewformat
AddedSmartZBTfunctionality
Pg. 4, 5
Pg. 6
Added Note 4 and changed Pins 38, 42, and 43 to DNU
Changed U2–U6 to DNU
Pg. 14
Pg. 15
AddedSmartZBTACElectricalCharacteristics
Improved tCD and tOE(MAX)at166MHz
Revised tCHZ(MIN) for f ≤ 133 MHz
Revised tOHZ (MAX) for f ≤ 133 MHz
Improved tCH, tCL for f ≤166 MHz
Improvedsetuptimesfor100–200MHz
Pg. 22
Pg. 24
Pg. 14
Pg. 15
AddedBGApackagediagrams
AddedDatasheetDocumentHistory
RevisedACElectricalCharacteristicstable
Revised tCHZ to match tCLZ and tCDC at 133MHz and 100MHz
RemovedSmartfunctionality
AddedIndustrialTemperaturerangeofferingsatthe100to166MHzspeedgrades.
InsertclarificationnotetoRecommendedOperatingTemperature andAbsoluteMax
Ratingstables
10/4/99
12/31/99
04/30/00
Pg. 5, 6
Pg. 6
AddBGAcapacitancetable
Pg. 5,6, 7
Pg. 21
AddnotetoTQFPandBGAPinConfigurations;correctedtypoinpinout
Add100pinTQFPpackageDiagramOutline
Add new package offering, 13 x 15mm 165 fBGA
Correct119BGAPackageDiagramOutline
Add ZZ sleep mode reference note to BG119, PK100 and BQ165 pinouts
UpdateBQ165pinout
05/26/00
07/26/00
Pg. 23
Pg. 5-8
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UpdateBG119packagediagramoutlinedimensions
RemovePreliminarystatus
10/25/00
Pg. 8
Pg. 1-8, 15,22,23,27
Pg. 7
Add note to pin N5 on BQ165, reserved for JTAG TRST
AddedJTAG"SA"versionfunctionality
Updated pin configuration for the 119 BGA-reordered I/O signals on P6, P7 (128K x 36)
and P7, N6, L6, K7, H6, G7, F6, E7, D6 (256K x 18).
Adding"Restrictedhazardoussubstancedevice"toorderinginformation.
AddedXgenerationdiesteptodatasheet.
1/24/02
9/30 /04
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10/18/06
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for Tech Support:
sramhelp@idt.com
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408/284-4555
800-345-7015 or 408-284-8200
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TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
ZBT® andZeroBusTurnaroundaretrademarksofIntegratedDeviceTechnology,Inc.andthearchitectureissupportedbyMicronTechnologyandMotorolaInc.
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