IDT71V321S35J_技术文档

IDT71V321S/L

IDT71V421S/L

HIGH SPEED 3.3V

2K X 8 DUAL-PORT

STATIC RAM WITH INTERRUPTS

ꢀeatures

◆

MASTER IDT71V321 easily expands data bus width to 16-

or-more-bits using SLAVE IDT71V421

High-speed access

– Commercial: 25/35/55ns (max.)

– Industrial: 25ns (max.)

Low-power operation

◆

On-chip port arbitration logic (IDT71V321 only)

BUSY output flag on IDT71V321; BUSY input on IDT71V421

Fully asynchronous operation from either port

Battery backup operation—2V data retention (L only)

TTL-compatible, single 3.3V power supply

Available in 52-pin PLCC, 64-pin TQFP and STQFP

packages

◆

– IDT71V321/IDT71V421S

— Active: 325mW (typ.)

— Standby: 5mW (typ.)

– IDT71V321/V421L

— Active: 325mW (typ.)

— Standby: 1mW (typ.)

◆

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

◆

Two INT flags for port-to-port communications

ꢀunctionalBlockDiagram

OER

OEL

CER

CEL

R/WR

R/WL

I/O0L- I/O7L

I/O0R-I/O7R

I/O

Control

I/O

Control

(1,2)

BUSYR

BUSYL

A10L

A0L

A10R

Address

Decoder

MEMORY

ARRAY

Address

Decoder

A0R

11

ARBITRATION

and

INTERRUPT

LOGIC

CE_L

OE_L

CER

OER

R/WR

R/WL

(2)

INTL

INTR

3026 drw 01

NOTES:

1. IDT71V321 (MASTER): BUSY is an output. IDT71V421 (SLAVE): BUSY is input.

2. BUSY and INT are totem-pole outputs.

AUGUST 2001

1

DSC-3026/8

IDT71V321/71V421S/L

High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts

Industrial and Commercial Temperature Ranges

Description

The IDT71V321/IDT71V421 are high-speed 2K x 8 Dual-Port down feature, controlled by CE, permits the on chip circuitry of each

port to enter a very low standby power mode.

Static RAMs with internal interrupt logic for interprocessor communica-

tions. The IDT71V321 is designed to be used as a stand-alone 8-bit

Dual-Port RAM or as a "MASTER" Dual-Port RAM together with the

IDT71V421 "SLAVE" Dual-Port in 16-or-more-bit memory system ap-

plications results in full speed, error-free operation without the need for

additional discrete logic.

The device provides two independent ports with separate control,

address, and I/O pins that permit independent, asynchronous access

for reads or writes to any location in memory. An automatic power

Fabricated using IDT's CMOS high-performance technology, these

devices typically operate on only 325mW of power. Low-power (L)

versions offer battery backup data retention capability, with each Dual-

Port typically consuming 200µW from a 2V battery.

The IDT71V321/IDT71V421 devices are packaged in a 52-pin

PLCC, a 64-pin TQFP (thin quad flatpack), and a 64-pin STQFP

(super thin quad flatpack).

PinConfigurations^(1,2,3)

INDEX

7 6 5 4 3 2

52 51 50 49 48 47

46

OER

1L

2L

3L

4L

5L

6L

7L

8L

9L

0L

1L

2L

3L

A

8

9

1

0R

A

45

44

43

42

41

40

39

38

37

36

35

34

1R

A

10

11

12

13

14

15

16

17

18

2R

A

3R

A

IDT71V321/421J

J52-1⁽⁴⁾

4R

A

5R

A

52-Pin PLCC

Top View⁽⁵⁾

6R

A

7R

A

8R

I/O

A

9R

A

NC

19

20

7R

I/O

21 22 23 24 25 26 27 28 29 30 31 32 33

,

3026 drw 02

INDEX

OE_R

A0R

A1R

A2R

A3R

A4R

A5R

A6R

N/C

A7R

A8R

A9R

N/C

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

OE_L

A_0L

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

A_1L

A_2L

A_3L

A_4L

A_5L

A_6L

N/C

A_7L

A8L

IDT71V321/421PF or TF

PP64-1⁽⁴⁾

&

PN64-1⁽⁴⁾

64-Pin STQFP

64-Pin TQFP

Top View⁽⁵⁾

A

9L

N/C

I/O_0L

I/O1L

N/C

I/O7R

I/O_6R

NOTES:

1. All V^CCpins must be connected to power supply.

2. All GND pins must be connected to ground supply.

2L

I/O

3. J52-1 package body is approximately .75 in x .75 in x .17 in.

PP64-1 package body is approximately 10mm x 10mm x 1.4mm.

PN64-1 package body is approximately 14mm x 14mm x 1.4mm.

4. This package code is used to reference the package diagram.

5. This text does not indicate orientation of the actual part-marking.

3026 drw 03

2

6.42

IDT71V321/71V421S/L

High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts

Industrial and Commercial Temperature Ranges

Absolute Maximum Ratings⁽¹⁾

RecommendedOperating

TemperatureandSupplyVoltage^(1,2)

Symbol

Rating

Commercial

& Industrial

Unit

Grade

Ambient

GND

Vcc

Temperature

(2)

VTERM

Te rminal Vo ltag e

with Respect

to GND

-0.5 to +4.6

V

Commercial

0^OC to +70^OC

0V

3.3V + 0.3V

Industrial

-40^OC to +85^OC

Operating

Te mp e rature

T

A

0 to +70

°C

^oC

3026 tbl 02

NOTES:

1. This is the parameter T^A. This is the "instant on" case temperature.

2. Industrial temperature: for specific speeds, packages and powers contact your

sales office.

T

BIAS

Te mp e rature

Under Bias

-55 to +125

Storage

Te mp e rature

-65 to +150

50

^oC

TSTG

IOUT

DC Output

Current

mA

RecommendedDCOperating

Conditions

3026 tbl 01

NOTES:

Symbol

Parameter

Min.

Typ.

Max.

3.6

0

Unit

V

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS

may cause permanent damage to the device. This is a stress rating only

and functional operation of the device at these or any other conditions

above those indicated in the operational sections of the specification is not

implied. Exposure to absolute maximum rating conditions for extended

periods may affect reliability.

CC

V

Supply Voltage

3.0

3.3

GND Ground

0

V

____

(2)

V^IH

V^IL

Input High Voltage

Input Low Voltage

2.0

VCC+0.3

0.8

V

2. V^TERMmust not exceed VCC + 10% for more than 25% of the cycle time or 10ns

maximum, and is limited to < 20mA for the period of VTERM > VCC + 10%.

-0.3⁽¹⁾

V

____

3026 tbl 03

NOTES:

1. V^IL(min.) = -1.5V for pulse width less than 20ns.

2. V^TERMmust not exceed Vcc + 0.3V.

Capacitance⁽¹⁾

(TA = +25°C, f = 1.0MHz) TQꢀP Only

Symbol

C^IN

Parameter

Input Capacitance

Output Capacitance

Conditions^{(2 )}

Max. Unit

V^IN= 3dV

9

pF

C^OUT

V^OUT= 3dV

10

pF

3026 tbl 04

NOTES:

1. This parameter is determined by device characterization but is not production

tested.

2. 3dv references the interpolated capacitance when the input and output signals

switch from 0V to 3V or from 3V to 0V.

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range (VCC = 3.3V ± 0.3V)

71V321S

71V421S

71V321L

71V421L

Symbol

Parameter

Test Conditions

Min.

Max.

Min.

Max.

Unit

(1)

___

Input Leakage Current

CC

= 3.6V,

|I^LI|

V

10

5

µA

V^IN= 0V to V^CC

___

|I^LO|

Output Leakage Current

CE = V^IH, V^OUT= 0V to V^CC

10

5

µA

V

V^CC= 3.6V

___

V^OL

V^OH

Output Low Voltage

Output High Voltage

I^OL= 4mA

I^OH= -4mA

0.4

___

2.4

V

3026 tbl 05

NOTE:

1. At V^CC< 2.0V input leakages are undefined.

3

6.42

IDT71V321/71V421S/L

High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts

Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range^(1,2)(VCC = 3.3V ± 0.3V)

71V321X25

71V421X25

Com'l

71V321X35

71V321X55

71V421X55

Com'l Only

71V421X35

Com'l Only

& Ind

Symbol

Parameter

Test Condition

Version

COM'L

Typ.

Max.

Typ.

55

Max.

125

Typ.

55

Max. Unit

I^CC

Dynamic Operating

Current

(Both Ports Active)

S

L

55

130

100

115

85

mA

CE = V^IL, Outputs Disabled

SEM = V^IH

55

95

55

(3)

f = f^MAX

IND

S

L

55

150

130

___

I^SB1

I^SB2

I^SB3

I^SB4

Standby Current

(Both Ports - TTL

Level Inputs)

COM'L

IND

S

L

15

35

20

15

35

20

15

35

20

CE^R= CE^L= V^IH

SEM^R= SEM^L= V^IH

(3)

f = f^MAX

S

L

15

50

35

___

(5)

Standby Current

(One Port - TTL

Level Inputs)

COM'L

IND

S

L

25

75

55

25

70

50

25

60

40

CE^"A"= V^ILand CE^"B"= V^IH

Active Port Outputs Disabled,

(3)

f=f^MAX

S

L

25

95

75

SEM^R= SEM^L= V^IH

___

Full Standby Current

(Both Ports - All

CMOS Level Inputs)

Both Ports

^Land

CE

COM'L

IND

S

L

1.0

0.2

5

3

1.0

0.2

5

3

1.0

0.2

5

3

CE^R> V^CC- 0.2V

V^IN> V^CC- 0.2V or

V^IN< 0.2V, f = 0⁽⁴⁾

S

L

1.0

0.2

10

6

___

SEM^R= SEM^L> V^CC- 0.2V

Full Standby Current

(One Port - All

CMOS Level Inputs)

COM'L

IND

S

L

25

70

55

25

65

50

25

55

40

CE^"A"< 0.2V and

(5)

CE^"B"> V^CC- 0.2V

=

^L> V^CC- 0.2V

SEM^RSEM

S

L

25

85

70

V^IN> V^CC- 0.2V or V^IN< 0.2V

Active Port Outputs Disabled

___

(3)

f = f^MAX

3026 tbl 06

NOTES:

1. 'X' in part numbers indicates power rating (S or L).

2. V^CC= 3.3V, TA = +25°C, and are not production tested. ICCDC = 70mA (Typ.).

3. At f = f^MAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC and using "AC Test Conditions" of input levels

of GND to 3V.

4. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.

5. Port "A" may be either left or right port. Port "B" is opposite from port "A".

Data Retention Characteristics(L Version Only)

(1)

Symbol

V^DR

I^CCDR

Parameter

Test Condition

Min.

Typ.

Max.

Unit

V

___

VCC for Data Retention

2.0

0

___

Data Retention Current

µA

V^CC= 2^V,CE > V^CC- 0.2V

COM'L.

IND.

100

1500

(3)

___

t^CDR

IN

CC

IN

Chip Deselect to Data

Retention Time

V > V - 0.2V or V < 0.2V

100

4000

µA

V

___

0

(3)

(2)

___

t^R

Operation Recovery Time

t^RC

V

3026 tbl 07

NOTES:

1. V^CC= 2V, TA = +25°C, and is not production tested.

2. t^RC= Read Cycle Time.

3. This parameter is guaranteed by device characterization but not production tested.

4

6.42

IDT71V321/71V421S/L

High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts

Industrial and Commercial Temperature Ranges

AC Test Conditions

Input Pulse Levels

Data Retention Waveform

DATA RETENTION MODE

GND to 3.0V

5ns

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

Output Load

1.5V

CC

V

DR ≥

V

2.0V

3.0V

1.5V

CDR

R

t

Figures 1 and 2

DR

V

CE

3026 tbl 08

IH

V

IH

V

,

3026 drw 04

3.3V

590Ω

DATAOUT

435

BUSY

435

Ω

INT

30pF

5pF

3026 drw 05

Figure 1. AC Output Test Load

Figure 2. Output Test Load

(for t^HZ, tLZ, tWZ, and tOW)

* Including scope and jig.

AC Electrical Characteristics Over the

OperatingTemperatureSupplyVoltageRange⁽²⁾

71V321X25

71V421X25

Com'l

71V321X35

71V421X35

Com'l Only

71V321X55

71V421X55

Com'l Only

& Ind

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

READ CYCLE

____

RC

t

Read Cycle Time

25

35

55

ns

____

t^AA

t^ACE

t^AOE

t^OH

t^LZ

Address Access Time

25

35

55

____

Chip Enable Access Time

Output Enable Access Time

Output Hold from Address Change

Output Low-Z Time^(1,2)

12

20

25

____

3

____

0

Output High-Z Time^(1,2)

12

15

30

____

t^HZ

t^PU

t^PD

Chip Enable to Power Up Time⁽²⁾

Chip Disable to Power Down Time⁽²⁾

0

____

50

ns

3026 tbl 09

NOTES:

1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterization, but is not production tested.

3. 'X' in part numbers indicates power rating (S or L).

5

6.42

IDT71V321/71V421S/L

High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts

Industrial and Commercial Temperature Ranges

Timing Waveform of Read Cycle No. 1, Either Side⁽¹⁾

tRC

ADDRESS

tAA

tOH

PREVIOUS DATA VALID

DATA VALID

DATA_OUT

BUSYOUT

3026 drw 06

(2,3)

tBDD

NOTES:

1. R/W = V^IH, CE = VIL, and is OE = VIL. Address is valid prior to the coincidental with CE transition LOW.

2. t^BDDdelay is required only in the case where the opposite port is completing a write operation to the same address location. For simultaneous read operations

BUSY has no relationship to valid output data.

3. Start of valid data depends on which timing becomes effective last t^AOE, tACE, tAA, and tBDD.

Timing Waveform of Read Cycle No. 2, Either Side ⁽³⁾

t

ACE

CE

OE

(4)

(2)

tHZ

t

AOE

(2)

(1)

tHZ

tLZ

VALID DATA

DATAOUT

(1)

(4)

tLZ

tPD

tPU

ICC

CURRENT

ISS

50%

3026 drw 07

NOTES:

1. Timing depends on which signal is asserted last, OE or CE.

2. Timing depends on which signal is de-asserted first, OE or CE.

3. R/W = V^IHand the address is valid prior to or coincidental with CE transition LOW.

4. Start of valid data depends on which timing becomes effective last t^AOE, tACE, tAA, and tBDD.

6

6.42

IDT71V321/71V421S/L

High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts

Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

OperatingTemperatureandSupplyVoltageRange⁽⁴⁾

71V321X25

71V421X25

Com'l

71V321X35

71V421X35

Com'l Only

71V321X55

71V421X55

Com'l Only

& Ind

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

WRITE CYCLE

____

t^WC

t^EW

t^AW

t^AS

Write Cycle Time^{(5 )}

Chip Enable to End-of-Write

25

20

0

35

30

0

55

40

0

ns

Address Valid to End-of-Write

Address Set-up Time

Write Pulse Width

t^WP

t^WR

t^DW

t^HZ

20

0

30

0

40

0

Write Recovery Time

Data Valid to End-of-Write

Output High-Z Time^(1,2)

Data Hold Time^{(3 )}

12

20

____

12

15

30

____

t^DH

t^WZ

t^OW

0

(1,2)

____

Write Enable to Output in High-Z

Output Active from End-of-Write^(1,2)

15

30

____

0

ns

3026 tbl 10

NOTES:

1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterization but is not production tested.

3. The specification for t^DHmust be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over

voltage and temperature, the actual t^DHwill always be smaller than the actual tOW.

4. 'X' in part numbers indicates power rating (S or L).

5. For Master/Slave combination, t^WC= tBAA + tWP, since R/W = VIL must occur after tBAA.

7

6.42

IDT71V321/71V421S/L

High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts

Industrial and Commercial Temperature Ranges

Timing Waveform of Write Cycle No. 1, (R/W Controlled Timing)^(1,5,8)

tWC

ADDRESS

(7)

tHZ

OE

tAW

CE

(7)

(6)

tHZ

(2)

tWP

tAS

(3)

tWR

R/W

DATAOUT

DATAIN

(7)

tOW

tWZ

(4)

tDW

tDH

3026 drw 08

Timing Waveform of Write Cycle No. 2, (CE Controlled Timing)^(1,5)

tWC

ADDRESS

tAW

CE

(6)

(2)

(3)

tAS

tEW

tWR

R/W

tDW

tDH

DATA IN

3026 drw 09

NOTES:

1. R/W or CE must be HIGH during all address transitions.

2. A write occurs during the overlap (t^EWor tWP) of CE = VIL and R/W= VIL.

3. tWR is measured from the earlier of CE or R/W going HIGH to the end of the write cycle.

4. During this period, the l/O pins are in the output state and input signals must not be applied.

5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal (CE or R/W) is asserted last.

7. This parameter is determined to be device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test

Load (Figure 2).

8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t^WPor (tWZ + tDW) to allow the I/O drivers to turn off data to be

placed on the bus for the required t^DW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short

as the specified t^WP.

8

6.42

IDT71V321/71V421S/L

High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts

Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

OperatingTemperatureandSupplyVoltageRange⁽⁶⁾

71V321X25

71V421X25

Com'l

71V321X35

71V421X35

Com'l Only

71V321X55

71V421X55

Com'l Only

& Ind

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

BUSY Timing (For Master IDT71V321 Only)

____

t^BAA

t^BDA

t^BAC

t^BDC

t^WH

20

30

ns

BUSY Access Time from Address

BUSY Disable Time from Address

BUSY Access Time from Chip Enable

BUSY Disable Time from Chip Enable

Write Hold After BUSY⁽⁵⁾

20

30

____

12

15

20

t^WDD

t^DDD

t^APS

t^BDD

Write Pulse to Data Delay⁽¹⁾

50

60

80

____

Write Data Valid to Read Data Delay⁽¹⁾

Arbitration Priority Set-up Time⁽²⁾

BUSY Disable to Valid Data⁽³⁾

35

45

65

____

5

____

30

45

BUSY Timing (For Slave IDT71V421 Only)

____

BUSY Input to Write⁽⁴⁾

Write Hold After BUSY⁽⁵⁾

t^WB

0

ns

t^WH

12

15

20

Write Pulse to Data Delay⁽¹⁾

Write Data Valid to Read Data Delay⁽¹⁾

50

35

60

45

80

65

____

t^WDD

t^DDD

____

ns

3026 tbl 11

NOTES:

1. Port-to-port delay through RAM cells from the writing port to the reading port, refer to “Timing Waveform of Write with Port-to-Port Read and BUSY."

2. To ensure that the earlier of the two ports wins.

3. t^BDDis a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).

4. To ensure that a write cycle is inhibited on port "B" during contention on port "A".

5. To ensure that a write cycle is completed on port "B" after contention on port "A".

6. 'X' in part numbers indicates power rating (S or L).

Timing Waveform of Write with Port-to-Port Read and BUSY^(2,3,4)

tWC

ADDR"A"

MATCH

tWP

W"A"

R/

tDW

tDH

DATAIN "A"

VALID

(1)

tAPS

ADDR"B"

BUSY"B"

MATCH

tBDD

tBDA

tBAA

tWDD

DATAOUT"B"

VALID

tDDD

NOTES:

3026 drw 10

1. To ensure that the earlier of the two ports wins. t^APSis ignored for SLAVE (71V421).

2. CE^L= CER = VIL

3. OE = VIL for the reading port.

4. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is opposite from port "A".

9

6.42

IDT71V321/71V421S/L

High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts

Industrial and Commercial Temperature Ranges

Timing Waveform of Write with BUSY⁽⁴⁾

tWP

R/W^"A"

(3)

tWB

BUSY^"B"

(1)

WH

t

,

W^"B"

R/

(2)

3026 drw 11

NOTES:

1. t^WHmust be met for both BUSY input (71V421, slave) or output (71V321, master).

2. BUSY is asserted on port 'B' blocking R/W^'B', until BUSY'B' goes HIGH.

3. t^WBis for the slave version (71V421).

4. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is oppsite from port "A".

Timing Waveform of BUSY Arbitration Controlled by CE Timing⁽¹⁾

ADDR

ADDRESSES MATCH

"A" AND "B"

CE"B"

(2)

tAPS

CE"A"

tBAC

tBDC

BUSY"A"

3026 drw 12

Timing Waveform of BUSY Arbritration Controlled

by Address Match Timing⁽¹⁾

tRC OR tWC

ADDR"A"

ADDR"B"

BUSY"B"

ADDRESSES MATCH

ADDRESSES DO NOT MATCH

(2)

tAPS

tBAA

tBDA

3026 drw 13

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.

2. If t^APSis not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (71V321 only).

10

6.42

IDT71V321/71V421S/L

High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts

Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

OperatingTemperatureandSupplyVoltageRange⁽¹⁾

71V321X25

71V421X25

Com'l

71V321X35

71V421X35

Com'l Only

71V321X55

71V421X55

Com'l Only

& Ind

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

INTERRUPT TIMING

____

AS

t

Addre ss Set-up Time

0

ns

WR

t

Write Recove ry Time

Inte rrupt Se t Time

0

____

INS

t

25

45

____

INR

t

Inte rrupt Re se t Time

ns

3026 tbl 12

NOTES:

1. 'X' in part numbers indicates power rating (S or L).

TimingWaveformof InterruptMode⁽¹⁾

SET INT

WC

t

INTERRUPT ADDRESS⁽²⁾

ADDR"A"

(4)

(3)

AS

t

WR

t

R/W"A"

INT"B"

(3)

INS

t

3026 drw 14

CLEAR INT

tRC

INTERRUPT CLEAR ADDRESS⁽²⁾

ADDR"B"

(3)

tAS

OE"B"

INT"A"

(3)

tINR

3026 drw 15

NOTES:.

1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.

2. See Interrupt Truth Table.

3. Timing depends on which enable signal (CE or R/W) is asserted last.

4. Timing depends on which enable signal (CE or R/W) is de-asserted first.

11

6.42

IDT71V321/71V421S/L

High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts

Industrial and Commercial Temperature Ranges

TruthTables

Table I. Non-Contention

Read/WriteControl⁽⁴⁾

Left or Right Port⁽¹⁾

R/W

D^0-7

Function

CE

OE

Port Deselected and in Power-

Down Mode. I^SB2or I^SB4

X

H

X

Z

CE^R= CE^L= VIH, Power-Down Mode I^SB1

X

H

X

Z

or I^SB3

IN

DATA

L

H

L

X

L

Data on Port Written Into Memory⁽²⁾

(3)

DATAOUT Data in Memory Output on Port

H

Z

High-impedance Outputs

3026 tbl 13

NOTES:

1. A^0L– A10L ≠ A0R – A10R.

2. If BUSY = L, data is not written.

3. If BUSY = L, data may not be valid, see t^WDDand tDDD timing.

4. 'H' = V^IH, 'L' = VIL, 'X' = DON’T CARE, 'Z' = High-impedance.

Table II. Interrupt ꢀlag^(1,4)

Left Port

Right Port

R/W^L

L

A10L-A0L

7FF

X

R/W^R

A10R-A0R

X

Function

CE^L

L

OE^L

X

INT^L

X

CE^R

X

OE^R

X

INT

R

(2)

X

L

Set Right INT Flag

R

(3)

X

L

7FF

7FE

X

H

Reset Right INT Flag

R

(3)

X

L

X

Set Left

Flag

INT

L

(2)

X

L

7FE

H

X

Reset Left INT Flag

L

3026 tbl 14

NOTES:

1. Assumes BUSY^L= BUSYR = VIH

2. If BUSYL = VIL, then No Change.

3. If BUSY^R= VIL, then No Change.

4. 'H' = HIGH, 'L' = LOW, 'X' = DON’T CARE

TableIIIAddressBUSY Arbitration

Inputs

Outputs

AOL-A10L

AOR-A10R

(1)

Function

Normal

CE^L

X

CE^R

X

BUSY^L

BUSY^R

NO MATCH

MATCH

H

X

H

MATCH

H

(3)

L

MATCH

(2)

Write Inhibit

3026 tbl 15

NOTES:

1. Pins BUSY^Land BUSYR are both outputs for IDT71V321 (master). Both are inputs

for IDT71V421 (slave). BUSY^Xoutputs on the IDT71V321 are totem-pole. On

slaves the BUSY^Xinput internally inhibits writes.

2. 'L' if the inputs to the opposite port were stable prior to the address and enable

inputs of this port. 'H' if the inputs to the opposite port became stable after the

address and enable inputs of this port. If t^APSis not met, either BUSYL or BUSYR

= LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.

3. Writes to the left port are internally ignored when BUSY^Loutputs are driving LOW

regardless of actual logic level on the pin. Writes to the right port are internally

ignored when BUSY^Routputs are driving LOW regardless of actual logic level

on the pin.

12

6.42

IDT71V321/71V421S/L

High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts

Industrial and Commercial Temperature Ranges

beingexpandedindepth,thentheBUSYindicationfortheresultingarray

ꢀunctionalDescription

requires the use of an external AND gate.

TheIDT7V1321/IDT71V421providestwoportswithseparatecontrol,

addressandI/Opinsthatpermitindependentaccessforreadsorwrites

toanylocationinmemory.TheIDT71V321/IDT71V421hasanautomatic

power down feature controlled by CE. The CE controls on-chip power

downcircuitrythatpermitstherespectiveporttogointoastandbymode

whennotselected(CE=V^IH).Whenaportisenabled,accesstotheentire

memoryarrayispermitted.

Width Expansion with Busy Logic

Master/SlaveArrays

WhenexpandinganSRAMarrayinwidthwhileusingBUSYlogic,one

masterpartis usedtodecidewhichsideoftheSRAMarraywillreceive

a BUSY indication. Any number of slaves to be addressed in the same

addressrangeasthemaster,usetheBUSYsignalasawriteinhibitsignal.

ThusontheIDT71V321/IDT71V421SRAMstheBUSYpinisanoutput

ifthepartisMaster(IDT71V321),andtheBUSYpinisaninputifthepart

is a Slave (IDT71V421) as shown in Figure 3.

Interrupts

Iftheuserchoosestheinterruptfunction,amemorylocation(mailbox

ormessage center)is assignedtoeachport. The leftportinterruptflag

(INT^L) is asserted when the right port writes to memory location 7FE

(HEX), whereawriteisdefinedastheCER =R/WR=VILperTruthTable

II.Theleftportclearstheinterruptbyaccessingaddresslocation7FEwhen

CE^L= OEL = VIL, R/W is a "don't care". Likewise, the right port interrupt

flag(INTR)isassertedwhentheleftportwritestomemorylocation7FF

(HEX)andtocleartheinterruptflag(INTR),therightportmustaccessthe

memorylocation7FF.Themessage(8bits)at7FEor7FFisuser-defined,

sinceitisanaddressableSRAMlocation.Iftheinterruptfunctionisnotused,

address locations 7FEand7FFare notusedas mailboxes, butas part

of the random access memory. Refer to Truth Table II for the interrupt

operation.

SLAVE

Dual Port

RAM

MASTER

Dual Port

RAM

CE

BUSY_R

BUSY_L

MASTER

Dual Port

RAM

SLAVE

Dual Port

RAM

CE

BUSYL

BUSY_L

BUSY_R

BUSY

R

BUSY

L

3026 drw 16

Figure 3. Busy and chip enable routing for both width and depth

expansion with IDT71V321 (Master) and (Slave) IDT71V421 RAMs.

BusyLogic

BusyLogicprovidesahardwareindicationthatbothportsoftheRAM

haveaccessedthesamelocationatthesametime.Italsoallowsoneofthe

twoaccessestoproceedandsignalstheothersidethattheRAMis“Busy”.

TheBUSYpincanthenbeusedtostalltheaccessuntiltheoperationon

theothersideiscompleted.Ifawriteoperationhasbeenattemptedfrom

thesidethatreceivesabusyindication,thewritesignalisgatedinternally

topreventthewritefromproceeding.

TheuseofBUSYLogicisnotrequiredordesirableforallapplications.

InsomecasesitmaybeusefultologicallyORtheBUSYoutputstogether

anduse anyBUSYindicationas aninterruptsource toflagthe eventof

anillegalorillogicaloperation.

Iftwoormoremasterpartswereusedwhenexpandinginwidth,asplit

decisioncouldresultwithonemasterindicatingBUSYononesideofthe

arrayandanothermasterindicatingBUSYononeothersideofthearray.

Thiswouldinhibitthewriteoperationsfromoneportforpartofawordand

inhibitthewriteoperationsfromtheotherportfortheotherpartoftheword.

TheBUSYarbitration,onaMaster,is basedonthechipenableand

address signals only. Itignores whetheranaccess is a readorwrite. In

a master/slave array, bothaddress andchipenable mustbe validlong

enoughforaBUSYflagtobeoutputfromthemasterbeforetheactualwrite

pulsecanbeinitiatedwitheithertheR/Wsignalorthebyteenables. Failure

toobservethistimingcanresultinaglitchedinternalwriteinhibitsignaland

corrupteddataintheslave.

TheBUSYoutputsontheIDT71V321RAMmasteraretotem-poletype

outputsanddonotrequirepull-upresistorstooperate.IftheseRAMsare

13

6.42

IDT71V321/71V421S/L

High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts

Industrial and Commercial Temperature Ranges

OrderingInformation

IDT

XXXX

A

999

A

Device Type Power Speed Package

Process/

Temperature

Range

Blank

I⁽¹⁾

Commercial (0°C to +70°C)

Industrial (-40°C to +85°C)

J

PF

TF

52-pin PLCC (J52-1)

64-pin TQFP (PN64-1)

64-pin STQFP (PP64-1)

25

35

55

Commercial & Industrial

Commercial Only

Speed in nanoseconds

L

S

Low Power

Standard Power

71V321 16K (2K x 8-Bit) MASTER 3.3V

Dual-Port RAM w/ Interrupt

16K (2K x 8-Bit) SLAVE 3.3V

Dual-Port RAM w/ Interrupt

71V421

3026 drw 17

NOTE:

1. ContactyoursalesofficeIndustrialtemperaturerangeisavailableforselectedspeeds,packagesandpowers.

DatasheetDocumentHistory

03/24/99:

Initiateddatasheetdocumenthistory

Convertedtonewformat

Cosmeticandtypographicalcorrections

Page 2 Addedadditionalnotestopinconfigurations

Changeddrawingformat

Page 12 Changed open drain to totem-pole in Table III, note 1

Page 13 Deleted'does not'incopyfromBusyLogic

Replaced IDT logo

Pages 1 & 2 Moved full "Description" to page 2 and adjusted page layouts

Page 3 Increasedstoragetemperatureparameters

ClarifiedTAparameter

06/15/99:

10/15/99:

10/21/99:

11/12/99:

01/12/01:

Page 4 DCElectricalparameters–changedwordingfrom"open"to"disabled"

Changed±200mVto0mVinnotes

08/22/01:

Pages 4, 5, 7, 9 & 11 Industrial temp range offering removed from DC & AC Electrical Characteristics for 35 and 55ns

CORPORATE HEADQUARTERS

2975StenderWay

Santa Clara, CA 95054

for SALES:

for Tech Support:

831-754-4613

DualPortHelp@idt.com

800-345-7015 or 408-727-6116

fax: 408-492-8674

www.idt.com

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

14

6.42


型号：	IDT71V321S35J
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	HIGH-SPEED 3.3V 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPT HIGH -SPEED 3.3V 2K ×8双端口静态与中断RAM 存储内存集成电路静态存储器
文件：	总14页 (文件大小：130K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IDT71V321S35J [IDT]

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