IDT7164L20PE [IDT]
Standard SRAM, 8KX8, 19ns, CMOS, PDSO28, 0.330 INCH, SOIC-28;
| 型号： | IDT7164L20PE |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Standard SRAM, 8KX8, 19ns, CMOS, PDSO28, 0.330 INCH, SOIC-28 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总9页 (文件大小：95K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT7164S
IDT7164L
CMOS STATIC RAM
64K (8K x 8-BIT)
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• High-speed address/chip select access time
— Military: 20/25/30/35/45/55/70/85ns (max.)
— Commercial: 15/20/25/30/35ns (max.)
• Low power consumption
• Battery backup operation — 2V data retention voltage
(L Version only)
• Produced with advanced CMOS high-performance
technology
• Inputs and outputs directly TTL-compatible
• Three-state outputs
The IDT7164 is a 65,536 bit high-speed static RAM orga-
nized as 8K x 8. It is fabricated using IDT’s high-performance,
high-reliability CMOS technology.
Address access times as fast as 15ns are available and the
circuit offers a reduced power standby mode. When CS1 goes
HIGH or CS2 goes LOW, the circuit will automatically go to,
and remain in, a low-power stand by mode. The low-power (L)
version also offers a battery backup data retention capability
at power supply levels as low as 2V.
All inputs and outputs of the IDT7164 are TTL-compatible
and operation is from a single 5V supply, simplifying system
designs. Fully static asynchronous circuitry is used, requiring
no clocks or refreshing for operation.
• Available in:
— 28-pin DIP, SOIC, SOJ, and CERPACK
— 32-pin LCC
• Military product compliant to MIL-STD-883, Class B
The IDT7164 is packaged in a 28-pin 300 mil DIP and SOJ;
28-pin 330 mil SOIC; 28-pin 600 mil DIP; 32-pin LCC; and 28-
pin CERPACK.
Military grade product is manufactured in compliance with
the latest revision of MIL-STD-883, Class B, making it ideally
suited to military temperature applications demanding the
highest level of performance and reliability.
FUNCTIONAL BLOCK DIAGRAM
A0
VCC
GND
65,536 BIT
ADDRESS
DECODER
MEMORY ARRAY
A12
7
0
I/O
0
I/O CONTROL
I/O 7
CS1
CS2
OE
CONTROL
LOGIC
2967 drw 01
WE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
MAY 1994
1994 Integrated Device Technology, Inc.
6.5
DSC-1002/7
1
IDT7164S/L
CMOS STATIC RAM 64K (8K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
INDEX
1
V CC
WE
CS2
A8
A9
A11
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
28
27
26
25
24
2
32 31 30
4
3
2
1
3
A
A
6
5
29
A8
A9
A11
NC
OE
A10
CS1
I/O
I/O
5
4
28
27
26
25
24
23
22
21
6
D28-1
D28-3
E28-2
5
7
A
A
A
A
4
3
2
1
6
23
22
8
7
L32-1
9
OE
A10
CS1
P28-1
8
21
20
10
11
12
13
9
P28-2
A0
NC
0
10
11
12
13
14
I/O
I/O
I/O
I/O
I/O
19
18
17
16
7
6
5
4
3
7
6
SO28-3
SO28-5
I/O
0
1
2
I/O
14 15 16 17 18 19 20
I/O
I/O
15
GND
2967 drw 03
2967 drw 02
32-PIN LCC
TOP VIEW
DIP/SOIC/SOJ/CERPACK
TOP VIEW
PIN DESCRIPTIONS
TRUTH TABLE(1,2,3)
Name
A0–A12
I/O0–I/O7
CS1
Description
1
CS2
I/O
Function
WE CS
OE
Address
X
X
X
H
X
X
X
High-Z Deselected – Standby (ISB)
High-Z Deselected – Standby (ISB)
High-Z Deselected –Standby (ISB1)
Data Input/Output
Chip Select
Chip Select
Write Enable
Output Enable
Ground
L
X
VHC VHC or
VLC
X
CS2
WE
X
H
H
L
X
L
L
L
VLC
H
X
H
L
High-Z Deselected –Standby (ISB1)
High-Z Output Disabled
DataOUT Read Data
OE
GND
H
VCC
Power
H
X
DataIN Write Data
2967 tbl 01
NOTES:
2967 tbl 02
1. CS2 will power-down CS1, but CS1 will not power-down CS2.
2. H = VIH, L = VIL, X = don't care.
3. VLC = 0.2V, VHC = VCC - 0.2V
ABSOLUTE MAXIMUM RATINGS(1)
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Symbol
Rating
Com’l.
Mil.
Unit
(2)
VTERM
Terminal Voltage –0.5 to +7.0 –0.5 to +7.0
V
with Respect
to GND
Grade
Temperature
–55°C to +125°C
0°C to +70°C
GND
VCC
Military
0V
5V ± 10%
TA
Operating
Temperature
0 to +70
–55 to +125 °C
Commercial
0V
5V ± 10%
2967 tbl 05
TBIAS
TSTG
Temperature
Under Bias
–55 to +125 –65 to +135 °C
–55 to +125 –65 to +150 °C
RECOMMENDED DC OPERATING
CONDITIONS
Storage
Temperature
Symbol
VCC
GND
VIH
Parameter
Min. Typ. Max. Unit
PT
Power Dissipation
1.0
50
1.0
50
W
Supply Voltage
4.5
0
5.0
0
5.5
0
V
IOUT
DC Output
Current
mA
Supply Voltage
V
V
NOTES:
2967 tbl 03
Input HIGH Voltage
Input LOW Voltage
2.2
–0.5(1)
— VCC + 0.5
0.8
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
VIL
—
V
NOTE:
2967 tbl 06
1. VIL (min.) = –1.5V for pulse width less than 10ns, once per cycle.
2. VTERM must not exceed VCC + 0.5V.
6.5
2
IDT7164S/L
CMOS STATIC RAM 64K (8K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
Max. Unit
CIN
VIN = 0V
8
8
pF
pF
CI/O
VOUT = 0V
NOTE:
2967 tbl 04
1. This parameter is determined by device characterization, but is not
production tested.
DC ELECTRICAL CHARACTERISTICS(1)
(VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC - 0.2V)
7164S15
7164L15
7164S20
7164L20
7164S25
7164L25
7164S30
7164L30
Symbol
Parameter
Power Com’l. Mil. Com’l. Mil. Com’l.
Mil. Com’l. Mil.
Unit
ICC1
Operating Power Supply
S
110
—
100
110
90
110
90
100
mA
Current, CS1 = VIL, CS2 = VIH,
Outputs Open, VCC = Max., f = 0(3)
L
100
180
—
—
90
100
180
80
100
180
80
90
ICC2
ISB
Dynamic Operating Current
CS1 = VIL, CS2 = VIH,
Outputs Open, VCC = Max., f = fMAX(3)
S
170
170
160
170
mA
mA
mA
L
150
20
—
—
150
20
160
20
150
20
160
20
140
20
150
20
Standby Power Supply Current
S
(TTL Level), CS1 ≥ VIH or CS2 ≤ VIL
VCC = Max., Outputs Open, f = fMAX(3)
L
3
—
—
3
5
3
5
3
5
ISB1
Full Standby Power Supply Current
(CMOS Level), f = 0(3), VCC = Max.
1. CS1 ≥ VHC and CS2 ≥ VHC, or
2. CS2 ≤ VLC
S
15
15
20
15
20
15
20
L
0.2
—
0.2
1
0.2
1
0.2
1
DC ELECTRICAL CHARACTERISTICS(1) (Continued)
(VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC - 0.2V)
7164S35
7164L35
7164S45
7164L45
7164S55
7164L55
7164S70/85(2)
7164L70/85(2)
Symbol
Parameter
Power Com’l. Mil. Com’l. Mil. Com’l. Mil.
Com’l. Mil.
Unit
ICC1
Operating Power Supply
S
90
100
—
100
—
100
—
100
mA
Current, CS1 = VIL, CS2 = VIH,
Outputs Open, VCC = Max., f = 0(3)
L
80
90
—
—
90
—
—
90
—
—
90
ICC2
ISB
Dynamic Operating Current
CS1 = VIL, CS2 = VIH,
Outputs Open, VCC = Max., f = fMAX
S
150
160
160
160
160
mA
mA
mA
(3)
L
130
20
140
20
—
—
130
20
—
—
125
20
—
—
120
20
Standby Power Supply Current
S
(TTL Level), CS1 ≥ VIH, or CS2 ≤ VIL
VCC = Max., Outputs Open, f = fMAX
(3)
L
3
5
—
—
5
—
—
5
—
—
5
ISB1
Full Standby Power Supply Current
(CMOS Level), f = 0(3), VCC = Max.
1. CS1 ≥ VHC and CS2 ≥ VHC, or
2. CS2 ≤ VLC
S
15
20
20
20
20
L
0.2
1
—
1
—
1
—
1
NOTES:
2967 tbl 07
1. All values are maximum guaranteed values.
2. Also available: 100, 120, 150 and 200ns military devices.
3. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing.
6.5
3
IDT7164S/L
CMOS STATIC RAM 64K (8K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS
(VCC = 5.0V ± 10%)
IDT7164S
IDT7164L
Symbol
Parameter
Test Condition
VCC = Max.,
Min.
Max.
Min.
Max.
Unit
|ILI|
Input Leakage Current
MIL.
COM’L.
—
—
10
5
—
—
5
2
µA
VIN = GND to VCC
|ILO|
VOL
Output Leakage Current VCC = Max., CS1 = VIH,
VOUT = GND to VCC
MIL.
COM’L.
—
—
10
5
—
—
5
2
µA
Output Low Voltage
IOL = 8mA, VCC = Min.
IOL = 10mA, VCC = Min.
IOH = –4mA, VCC = Min.
0.4
0.5
—
—
—
0.4
0.5
—
V
—
VOH
Output High Voltage
2.4
2.4
V
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(L Version Only) (VLC = 0.2V, VHC = VCC - 0.2V)
Typ. (1)
VCC @
Max.
VCC @
Symbol
VDR
Parameter
Test Condition
Min.
2.0v
3.0V
2.0V
3.0V
Unit
V
VCC for Data Retention
Data Retention Current
—
2.0
—
—
—
—
ICCDR
MIL.
COM’L.
—
—
10
10
15
15
200
60
300
90
µA
(3)
tCDR
Chip Deselect to Data
Retention Time
1. CS1 ≥ VHC
CS2 ≥ VHC, or
0
—
—
—
—
ns
(3)
tR
|ILI|(3)
(2)
Operation Recovery Time
Input Leakage Current
2. CS2 ≤ VLC
tRC
—
—
—
—
—
2
—
2
ns
µA
—
NOTES:
1. TA = +25°C.
2. tRC = Read Cycle Time.
2967 tbl 10
3. This parameter is guaranteed by device characterization, but is not production tested.
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
5ns
1.5V
1.5V
See Figures 1 and 2
2967 tbl 08
5V
5V
480Ω
480Ω
DATAOUT
DATAOUT
255Ω
30pF*
255Ω
5pF*
2967 drw 06
2967 drw 07
Figure 2. AC Test Load
(for tCLZ1, tCLZ2, tOLZ, tCHZ1, tCHZ2, tOHZ, tOW, and tWHZ)
Figure 1. AC Test Load
*Includes scope and jig capacitances
6.5
4
IDT7164S/L
CMOS STATIC RAM 64K (8K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%, All Temperature Ranges)
7164S15(1)
7164S20
7164L20
7164S25
7164L25
7164S30
7164L30
7164L15(1)
Symbol
Parameter
Min. Max.
Min.
Max.
Min.
Max.
Min.
Max. Unit
Read Cycle
tRC
Read Cycle Time
Address Access Time
15
—
—
—
5
—
15
15
20
—
7
20
—
—
—
5
—
19
20
25
—
8
25
—
—
—
5
—
25
25
30
—
12
—
13
10
—
—
25
30
—
—
—
5
—
29
30
35
—
15
—
13
12
—
—
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
(3)
(3)
tACS1
tACS2
Chip Select-1 Access Tim
Chip Select-2 Access Time
(4)
tCLZ1,2
tOE
Chip Select-1, 2 to Output in Low-Z
Output Enable to Output Valid
Output Enable to Output in Low-Z
Chip Select-1, 2 to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change
Chip Select to Power Up Time
Chip Deselect to Power Down Time
—
0
—
0
—
0
—
0
(4)
tOLZ
—
8
—
9
(4)
tCHZ1,2
—
—
5
—
—
5
—
—
5
—
—
5
(4)
tOHZ
7
8
tOH
—
—
15
—
—
20
(4)
tPU
0
0
0
0
(4)
tPD
—
—
—
—
Write Cycle
tWC
Write Cycle Time
15
14
14
0
—
—
—
—
—
—
—
6
20
15
15
0
—
—
—
—
—
—
—
8
25
18
18
0
—
—
—
—
—
—
—
10
—
—
—
—
30
22
22
0
—
—
—
—
—
—
—
12
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCW1, 2
tAW
Chip Select to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
tAS
tWP
Write Pulse Width
14
0
15
0
21
0
23
0
tWR1
tWR2
Write Recovery Time (CS1, WE)
Write Recovery Time (CS2)
Write Enable to Output in High-Z
Data to Write Time Overlap
Data Hold from Write Time (CS1, WE)
Data Hold from Write Time (CS2)
Output Active from End-of-Write
5
5
5
5
(4)
tWHZ
—
8
—
10
0
—
13
0
—
13
0
tDW
—
—
—
—
—
—
—
—
tDH1
tDH2
0
5
5
5
5
(4)
tOW
4
4
4
4
ns
NOTES:
2967 tbl 11
1. 0° to +70°C temperature range only.
2. –55°C to +125°C temperature range only. Also available: 100, 120, 150 and 200ns military devices.
3. Both chip selects must be active for the device to be selected.
4. This parameter is guaranteed by device characterization, but is not production tested.
6.5
5
IDT7164S/L
CMOS STATIC RAM 64K (8K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS (Continued) (VCC = 5.0V ± 10%, All Temperature Ranges)
7164S35
7164L35
7164S45(2)
7164L45(2)
7164S55(2)
7164L55(2)
7164S70(2)/85(2)
7164L70(2)/85(2)
Symbol
Parameter
Min. Max.
Min.
Max.
Min.
Max.
Min.
Max. Unit
Read Cycle
tRC
Read Cycle Time
Address Access Time
35
—
—
—
5
—
35
35
40
—
18
—
15
15
—
—
35
45
—
—
—
5
—
45
45
45
—
25
—
20
20
—
—
45
55
—
—
—
5
—
55
55
55
—
30
—
25
25
—
—
55
70/85
—
—
—
5
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
70/85
70/85
70/85
—
(3)
(3)
tACS1
tACS2
Chip Select-1 Access Time
Chip Select-2 Access Time
(4)
tCLZ1,2
tOE
Chip Select-1, 2 to Output in Low-Z
Output Enable to Output Valid
Output Enable to Output in Low-Z
Chip Select-1, 2 to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change
Chip Select to Power Up Time
Chip Deselect to Power Down Time
—
0
—
0
—
0
—
0
35/40
—
(4)
tOLZ
(4)
tCHZ1,2
—
—
5
—
—
5
—
—
5
—
—
5
30/35
30/35
—
(4)
tOHZ
tOH
(4)
tPU
0
0
0
0
—
(4)
tPD
—
—
—
—
70/85
Write Cycle
tWC
Write Cycle Time
35
25
25
0
—
—
—
—
—
—
—
14
—
—
—
—
45
33
33
0
—
—
—
—
—
—
—
18
—
—
—
—
55
50
50
0
—
—
—
—
—
—
—
25
—
—
—
—
70/85
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCW1, 2
tAW
Chip Select to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
60/75
60/75
—
tAS
0
—
tWP
Write Pulse Width
25
0
25
0
50
0
60/75
—
tWR1
tWR2
Write Recovery Time (CS1, WE)
Write Recovery Time (CS2)
Write Enable to Output in High-Z
Data to Write Time Overlap
Data Hold from Write Time (CS1, WE)
Data Hold from Write Time (CS2)
Output Active from End-of-Write
0
—
5
5
5
5
—
—
(4)
tWHZ
—
15
0
—
20
0
—
25
0
30/35
—
tDW
30/35
0
tDH1
—
tDH2
5
5
5
5
—
(4)
tOW
4
4
4
4
—
ns
NOTES:
2967 tbl 11
1. 0° to +70°C temperature range only.
2. –55°C to +125°C temperature range only. Also available: 100, 120, 150, and 200ns military devices.
3. Both chip selects must be active for the device to be selected.
4. This parameter is guaranteed by device characterization, but is not production tested.
6.5
6
IDT7164S/L
CMOS STATIC RAM 64K (8K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
t
RC
ADDRESS
OE
t
AA
tOH
t
OE
(5)
t
OLZ
CS
2
tACS2
(5)
(5)
t
t
CHZ2
t
t
CLZ2
CLZ1
CS
1
(5)
t
ACS1
tOHZ
(5)
(5)
CHZ1
DATAOUT
DATA VALID
2967 drw 08
TIMING WAVEFORM OF READ CYCLE NO. 2(1, 2, 4)
tRC
ADDRESS
tAA
tOH
tOH
DATAOUT
DATA VALID
2967 drw 09
TIMING WAVEFORM OF READ CYCLE NO. 3(1, 3, 4)
CS1
CS2
tACS2
(5)
(5)
(5)
tCHZ2
tCLZ2
tACS1
t CLZ1
tCHZ1
(5)
DATAOUT
DATA VALID
tPU
ICC
ISB
POWER
SUPPLY
CURRENT
t PD
NOTES:
2967 drw 10
1. WE is HIGH for Read cycle.
2. Device is continuously selected, CS1 is LOW, CS2 is HIGH.
3. Address valid prior to or coincident with CS1 transition LOW and CS2 transition HIGH.
4. OE is LOW.
5. Transition is measured ±200mV from steady state.
6.5
7
IDT7164S/L
CMOS STATIC RAM 64K (8K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (
CONTROLLED TIMING)(1, 2, 6)
WE
tWC
ADDRESS
CS2
CS1
(3)
tWR1
tAW
tAS
WE
(6)
tWP
(4)
(7)
tOW
DATAOUT
tDW
t DH1, 2
(7)
tWHZ
DATAIN
DATA VALID
2967 drw 11
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (
CONTROLLED TIMING)(1, 2)
CS
tWC
ADDRESS
(3)
(3)
tAS
tWR2
CS2
CS1
tCW
tWR1
(5)
tAW
WE
tDW
t DH1,2
DATAIN
DATA VALID
2967 drw 12
NOTES:
1. WE, CS1 or CS2 must be inactive during all address transitions.
2. A write occurs during the overlap of a LOW WE, a LOW CS1 and a HIGH CS2.
3. tWR1, 2 is measured from the earlier of CS1 or WE going HIGH or CS2 going LOW to the end of the write cycle.
4. During this period, I/O pins are in the output state so that the input signals must not be applied.
5. If the CS1 LOW transition or CS2 HIGH transition occurs simultaneously with or after the WELOW transition, the outputs remain in a high-impedance state.
6. OE is continuously HIGH. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ +tDW) to allow the
I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not
apply and the minimum write pulse width is as short as the specified tWP.
7. Transition is measured ±200mV from steady state.
6.5
8
IDT7164S/L
CMOS STATIC RAM 64K (8K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
LOW VCC DATA RETENTION WAVEFORM
DATA
RETENTION
MODE
VCC
4.5V
4.5V
V
DR ≥2V
tCDR
tR
VIH
VIH
CS
VDR
2967 drw 05
ORDERING INFORMATION
IDT
7164
X
XX
XXX
X
Device
Type
Power
Speed
Package
Process/
Temperature
Range
Blank
B
Commercial (0
°
C to +70
°C)
Military (–55 C to +125
°
°C)
Compliant to MIL-STD-883, Class B
Y
300 mil SOJ (SO28-5)
PE
TD
D
330 mil SOIC (SO28-3)
300 mil CERDIP (D28-3)
600 mil CERDIP (D28-1)
600 mil Plastic DIP (P28-1)
300 mil Plastic DIP (P28-2)
32 Leadless Chip Carrier (L32-1)
CERPACK F11 (E28-2)
P
TP
L32
XE
15
20
25
30
35
45
55
70
85
Commercial Only
Military Only
Military Only
Military Only
Military Only
Military Only
Speed in nanoseconds
S
L
Standard Power
Low Power
2967 drw 13
6.5
9
相关型号：
IDT7164L20TPG
Standard SRAM, 8KX8, 19ns, CMOS, PDIP28, 0.300 INCH, ROHS COMPLIANT, PLASTIC, DIP-28
IDT
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