IDT71342LA20PFG_技术文档

IDT71342SA/LA

HIGH-SPEED

4K x 8 DUAL-PORT

STATIC RAM WITH SEMAPHORE

Integrated Device Technology, Inc.

FEATURES:

DESCRIPTION:

• High-speed access

TheIDT71342isanextremelyhigh-speed4Kx8Dual-Port

Static RAM with full on-chip hardware support of semaphore

signalling between the two ports.

— Commercial: 20/25/35/45/55/70ns (max.)

• Low-power operation

— IDT71342SA

TheIDT71342providestwoindependentportswithseparate

control, address, and I/O pins that permit independent,

asynchronous access for reads or writes to any location in

memory. To assist in arbitrating between ports, a fully

independent semaphore logic block is provided. This block

contains unassigned flags which can be accessed by either

side; however, only one side can control the flag at any time.

Active: 500mW (typ.)

Standby: 5mW (typ.)

— IDT71342LA

Active: 500mW (typ.)

Standby: 1mW (typ.)

• Fully asynchronous operation from either port

• Full on-chip hardware support of semaphore signalling An automatic power down feature, controlled by CEand SEM,

between ports

permits the on-chip circuitry of each port to enter a very low

standby power mode (both CE and SEM High).

• Battery backup operation—2V data retention

• TTL-compatible; single 5V (±10%) power supply

• Available in plastic packages

• Industrial temperature range (–40°C to +85°C) is avail-

able, tested to military electrical specifications

Fabricated using IDT’s CMOS high-performance

technology, this device typically operates on only 500mW of

power. Low-power (LA) versions offer battery backup data

retentioncapability,witheachporttypicallyconsuming200µW

from a 2V battery. The device is packaged in either a 64-pin

TQFP, thin quad plastic flatpack, or a 52-pin PLCC.

FUNCTIONAL BLOCK DIAGRAM

R/

WL

R/

WR

CER

CEL

OER

OEL

COLUMN

I/O

COLUMN

I/O

I/O0R - I/O7R

I/O0L- I/O7L

MEMORY

ARRAY

SEMAPHORE

LOGIC

SEM

R

SEM

L

LEFT SIDE

ADDRESS

DECODE

LOGIC

RIGHT SIDE

ADDRESS

DECODE

LOGIC

A

0R- A11R

A0L- A11L

2721 drw 01

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

COMMERCIAL TEMPERATURE RANGE

OCTOBER 1996

DSC-2721/4

For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.

1

6.05

IDT71342SA/LA

HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM WITH SEMAPHORE

COMMERCIAL TEMPERATURE RANGE

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

PIN CONFIGURATIONS^(1,2)

Symbol

Rating

Com’l.

Mil.

Unit

VTERM⁽²⁾Terminal Voltage

with Respect

–0.5 to +7.0 –0.5 to +7.0

V

INDEX

to Ground

7

6

5

4

3

2

52 51 50 49 48 47

1

46

45

44

43

42

41

40

39

38

37

36

35

34

8

A1L

OE

R

TA

Operating

Temperature

0 to +70

–55 to +125 °C

9

A

2L

3L

A

0R

10

11

12

13

14

15

16

17

18

19

20

1R

2R

3R

4R

5R

6R

7R

8R

9R

TBIAS

TSTG

Temperature

Under Bias

–55 to +125 –65 to +135 °C

–55 to +125 –65 to +150 °C

A

4L

5L

A

IDT71342

J52-1

Storage

Temperature

A6L

A7L

A8L

A9L

PLCC

TOP VIEW⁽³⁾

(3)

PT

Power Dissipation

DC Output Current

1.5

50

1.5

50

W

IOUT

mA

I/O0L

I/O1L

I/O2L

I/O3L

NOTES:

2721 tbl 01

1. StressesgreaterthanthoselistedunderABSOLUTEMAXIMUMRATINGS

may cause permanent damage to the device. This is a stress rating only

and functional operation of the device at these or any other conditions

abovethoseindicatedintheoperationalsectionsofthisspecificationisnot

implied. Exposure to absolute maximum rating conditions for extended

periods may affect reliability.

N/C

I/O7R

21 22 23 24 25 26 27 28 29 30 31 32 33

2721 drw 02

2. VTERM must not exceed Vcc + 0.5V for more than 25%of the cycle time or

10 ns maximum, and is limited to < 20mA for the period of VTERM > Vcc

+0.5V.

CAPACITANCE⁽¹⁾

(TA = +25°C, f = 1.0MHz) TQFP Only

INDEX

OE

1

2

3

L

48

47

46

OE

R

A

0L

Symbol

CIN

Parameter

Conditions⁽²⁾Max. Unit

A

0R

A

1L

1R

2R

3R

4R

5R

6R

4

5

6

Input Capacitance

Output Capacitance

VIN = 3dV

9

pF

A2L

45

44

43

A3L

A4L

A5L

A6L

COUT

VOUT = 3dV

10

71342

NOTES:

2721 tbl 02

7

8

9

PN64-1

42

41

40

1. This parameter is determined by device characterization but is not

production tested.

2. 3dv references the interpolated capacitance when the input and output

signals switch from 0V to 3V and from 3V to 0V.

64-PIN TQFP

TOP VIEW

(3)

N/C

10

11

12

A7L

A

7R

8R

9R

39

38

37

A

8L

A

9L

N/C

I/O0L

I/O1L

I/O2L

13

14

15

36

35

34

33

N/C

I/O7R

I/O6R

RECOMMENDED OPERATING

TEMPERATURE AND SUPPLY VOLTAGE

Ambient

16

2721 drw 03

Grade

Temperature

GND

VCC

Commercial

0°C to +70°C

0V

5.0V ± 10%

2721 tbl 03

NOTES:

1. All Vcc pins must be connected to the power supply.

2. All GND pins must be connected to the ground supply.

3. This text does not indicate orientation of the actual part-marking.

RECOMMENDEDDCOPERATINGCONDITIONS

Symbol

Parameter

Supply Voltage

Ground

Min. Typ. Max. Unit

VCC

4.5

0

5.0

0

5.5

0

V

GND

VIH

VIL

Input High Voltage

Input Low Voltage

2.2

–0.5⁽¹⁾

—

6.0⁽²⁾

0.8

V

NOTES:

2721 tbl 04

1. VIL (min.) > -1.5V for pulse width less than 10ns.

2. VTERM must not exceed Vcc + 0.5V.

6.05

2

IDT71342SA/LA

HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM WITH SEMAPHORE

COMMERCIAL TEMPERATURE RANGE

DC ELECTRICAL CHARACTERISTICS OVER THE

OPERATING TEMPERATURE AND SUPPLY VOLTAGE (VCC = 5V ± 10%)

IDT71342SA

IDT71342LA

Symbol

Parameter

Test Conditions

Min.

Max.

Min.

Max.

Unit

|ILI|

Input Leakage Current⁽¹⁾

Output Leakage Current

Output Low Voltage

VCC = 5.5V, VIN = 0V to VCC

CE = VIH, VOUT = 0V to VCC

IOL = 6mA

—

10

—

5

µA

V

|ILO|

VOL

—

0.4

0.5

—

0.4

0.5

—

IOL = 8mA

—

V

VOH

Output High Voltage

IOH = –4mA

2.4

V

NOTE:

1. At Vcc < 2.0V input leakages are undefined.

2721 tbl 05

DC ELECTRICAL CHARACTERISTICS OVER THE

OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE⁽¹⁾(VCC = 5.0V ± 10%)

71342X20 71342X25 71342X35 71342X45 71342X55 71342X70

Typ.⁽²⁾Max. Typ.⁽²⁾Max. Typ.⁽²⁾Max. Typ.⁽²⁾Max. Typ.⁽²⁾Max. Typ.⁽²⁾Max. Unit

Symbol

Parameter

Test Conditions

Version

COM’L. S

L

ICC

Dynamic Operating CE = VIL

—

280

240

—

280

240

—

260

220

—

240

200

—

240

200

—

240 mA

200

Current

Outputs Open

(Both Ports Active)

SEM = Don't Care

f = fMAX⁽³⁾

ICC1

Dynamic Operating CE = VIH

COM’L. S

L

—

280

240

—

200

170

—

185

155

—

170

140

—

170

140

—

170 mA

140

Current

Outputs Open

(Semaphores

Both Sides)

SEM < VIL

f = fMAX⁽³⁾

ISB1

ISB2

Standby Current

CEL and CER = VIH COM’L. S

25

80

25

80

50

25

75

45

25

70

40

25 70

25 40

25

70 mA

40

(Both Ports—TTL

Level Inputs)

SEML = SEMR > VIH

f = fMAX⁽³⁾

L

Standby Current

CE"A" = VIL and

CE"B" = VIH⁽⁵⁾

COM’L. S

L

—

180

150

—

180

150

—

170

140

—

160

130

—

160

130

—

160 mA

130

(One Port—TTL

Level Inputs)

Active Port Outputs

Open, f = fMAX⁽³⁾

ISB3

ISB4

Full Standby Current Both Ports CEL and COM’L. S

1.0

0.2

15

1.0

15

1.0

15

1.0

15

1.0 15

1.0 15 mA

0.2 4.0

(Both Ports—All

CER > VCC - 0.2V

L

4.5

0.2 4.0

0.2 4.0 0.2 4.0 0.2 4.0

CMOS Level Inputs) VIN > VCC - 0.2V or

VIN < 0.2V

SEML = SEMR >

VCC - 0.2V, f = 0⁽⁴⁾

Full Standby Current One Port CE"A" or

COM’L. S

L

—

170

140

—

170

140

—

150

130

—

150

120

—

150

120

—

150 mA

120

(One Port—All

CE"B" > VCC - 0.2V

CMOS Level Inputs) VIN > VCC - 0.2V or

VIN < 0.2V

SEML = SEMR >

V^CC- 0.2V

Active Port Outputs

Open, f = fMAX⁽³⁾

2721 tbl 06

NOTES:

1. “X” in part number indicates power rating (SA or LA).

2. VCC = 5V, TA = +25°C for typical values, and parameters are not production tested.

3. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except Output Enable).

4. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby ISB3.

5. Port "A" may be either left or right port. Port "B" is opposite from port "A".

6.05

3

IDT71342SA/LA

HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM WITH SEMAPHORE

COMMERCIAL TEMPERATURE RANGE

DATA RETENTION CHARACTERISTICS

(LA Version Only) VLC = 0.2V, VHC = VCC - 0.2V

Symbol

VDR

Parameter

VCC for Data Retention

Data Retention Current

Test Condition

—

Min. Typ.⁽¹⁾Max.

Unit

V

2.0

—

ICCDR

VCC = 2V, CE ≥ VHC

SEM ≥ VHC

COM’L.

100

1500

µA

(3)

tCDR

Chip Deselect to Data Retention Time

Operation Recovery Time

VIN ≥ VHC or ≤ VLC

0

—

ns

(3)

tR

(2)

tRC

ns

2721 tbl 07

NOTES:

1. VCC = 2V, TA = +25°C, and are not production tested.

2. tRC = Read Cycle Time.

3. This parameter is guaranteed by device characterization, but is not production tested.

DATA RETENTION WAVEFORM

DATA RETENTION MODE

DR ≥ 2V

V

CC

4.5V

V

tCDR

tR

VDR

CE

V

IH

VIH

2721 drw 04

AC TEST CONDITIONS

Input Pulse Levels

GND to 3.0V

5ns

1.5V

Figures 1 and 2

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

Output Load

2721 tbl 08

+5V

1250Ω

+5V

1250Ω

5pF *

DATAOUT

775Ω

30pF

775Ω

2721 drw 05

2721 drw 06

Figure 2. Output Test Load

(for tLZ, tHZ, tWZ, tOW)

Figure 1. AC Output Test Load

*Including scope and jig

6.05

4

IDT71342SA/LA

HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM WITH SEMAPHORE

COMMERCIAL TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS OVER THE

OPERATING TEMPERATURE AND SUPPLY VOLTAGE⁽⁴⁾

71342X20

71342X25

71342X35

Min. Max.

Symbol

Parameter

Min.

Max.

Min.

Max.

Unit

READ CYCLE

tRC

tAA

Read Cycle Time

20

—

0

—

20

15

—

25

—

0

—

25

15

—

35

—

ns

Address Access Time

—

0

35

20

—

20

—

50

—

60

tACE

tAOE

tOH

tLZ

Chip Enable Access Time⁽³⁾

Output Enable Access Time

Output Hold from Address Change

Output Low-Z Time^{(1, 2)}

0

tHZ

tPU

Output High-Z Time^{(1, 2)}

—

0

15

—

50

—

40

—

0

15

—

50

—

50

—

0

ns

Chip Enable to Power Up Time⁽²⁾

Chip Disable to Power Down Time⁽²⁾

SEM Flag Update Pulse (OE or SEM)

Write Pulse to Data Delay⁽⁴⁾

tPD

—

10

—

15

—

tSOP

tWDD

tDDD

tSAA

Write Data Valid to Read Data Delay⁽⁴⁾

—

30

—

30

25

—

35

ns

Semaphore Address Access Time

2721 tbl 09

AC ELECTRICAL CHARACTERISTICS OVER THE

OPERATING TEMPERATURE AND SUPPLY VOLTAGE⁽⁴⁾(CONT'D)

71342X45

71342X55

71342X70

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

READ CYCLE

tRC

tAA

Read Cycle Time

45

—

0

—

45

25

—

55

—

0

—

55

30

—

70

—

0

—

70

40

—

ns

Address Access Time

tACE

tAOE

tOH

tLZ

Chip Enable Access Time⁽³⁾

Output Enable Access Time

Output Hold from Address Change

Output Low-Z Time^{(1, 2)}

5

tHZ

tPU

Output High-Z Time^{(1, 2)}

—

0

20

—

50

—

70

—

0

25

—

50

—

80

—

0

30

—

50

—

90

ns

Chip Enable to Power Up Time⁽²⁾

Chip Disable to Power Down Time⁽²⁾

SEM Flag Update Pulse (OE or SEM)

Write Pulse to Data Delay⁽⁴⁾

tPD

—

15

—

20

—

20

—

tSOP

tWDD

tDDD

tSAA

Write Data Valid to Read Data Delay⁽⁴⁾

—

45

—

55

—

70

ns

Semaphore Address Access Time

2721 tbl 10

NOTES:

1. Transition is measured ±500mV from Low or High-impedance voltage with the Ouput Test Load (Figure 2).

2. This parameter is guaranteed by device characterization, but is not production tested.

3. To access RAM, CE = VIL, SEM = VIH. To access semaphore, CE = VIH, and SEM = VIL.

4. “X” in part number indicates power rating (SA or LA).

6.05

5

IDT71342SA/LA

HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM WITH SEMAPHORE

COMMERCIAL TEMPERATURE RANGE

TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE^{(1, 2, 4, 6)}

t

RC

ADDRESS

DATAOUT

t

AA or tSAA

tOH

PREVIOUS DATA VALID

DATA VALID

2721 drw 07

TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE^{(1, 3)}

tSOP

t

ACE

CE or SEM⁽⁵⁾

(2)

(4)

t

AOE

tHZ

tSOP

OE

(2)

(1)

t

HZ

tLZ

DATAOUT

VALID DATA ⁽⁴⁾

(1)

t

LZ

t

PU

tPD

I

CC

CURRENT

50%

I

SB

2721 drw 08

NOTES:

1. Timing depends on which signal is asserted last, OE or CE.

2. Timing depends on which signal is de-asserted first, OE or CE.

3. R/W = VIH and address is valid prior to or coincident with CE transition Low.

4. Start of valid data depends on which timing becomes effective last; tAOE, tACE, or tAA.

5. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tAA is for RAM Address Access and tSAA is for Semaphore

Address Access.

6. R/W = VIH, CE = VIL, and OE = VIL. Address is valid prior to or coincident with CE transition Low.

TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ ^{(1, 2)}

tWC

ADDR "A"

MATCH

tWP

(1)

R/W "A"

t

DH

t

DW

DATAIN "A"

ADDR "B"

VALID

MATCH

t

WDD

VALID

DATAOUT "B"

tDDD

2721 drw 09

NOTES:

1. Write cycle parameters should be adhered to, in order to ensure proper writing.

2. CEL = CER = VIL. CE"B" = VIL.

3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

6.05

6

IDT71342SA/LA

HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM WITH SEMAPHORE

COMMERCIAL TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS OVER THE

OPERATING TEMPERATURE AND SUPPLY VOLTAGE⁽⁵⁾

71342X20

71342X25

71342X35

Min. Max.

Symbol

Parameter

Min.

Max.

Min.

Max.

Unit

WRITE CYCLE

tWC

tEW

tAW

tAS

Write Cycle Time

20

15

0

—

25

20

0

—

35

30

0

—

ns

Chip Enable to End-of-Write⁽³⁾

Address Valid to End-of-Write

Address Set-up Time

tWP

tWR

Write Pulse Width

15

0

20

0

25

0

Write Recovery Time

tDW

tHZ

Data Valid to End-of-Write

15

—

0

—

15

—

15

—

15

—

0

—

15

—

15

—

20

—

3

—

20

—

20

—

ns

Output High-Z Time^{(1, 2)}

Data Hold Time⁽⁴⁾

Write Enabled to Output in High-Z^{(1, 2)}

Output Active from End-of-Write^{(1, 2, 4)}

SEM Flag Write to Read Time

SEM Flag Contention Window

tDH

tWZ

—

3

—

3

—

3

tOW

tSWR

tSPS

10

ns

2721 tbl 11

AC ELECTRICAL CHARACTERISTICS OVER THE

OPERATING TEMPERATURE AND SUPPLY VOLTAGE⁽⁵⁾(CONT'D)

71342X45

71342X55

71342X70

Min. Max.

Symbol

Parameter

Min.

Max.

Min.

Max.

Unit

WRITE CYCLE

tWC

tEW

tAW

tAS

Write Cycle Time

45

40

0

—

20

55

50

0

—

25

70

60

0

—

30

ns

Chip Enable to End-of-Write⁽³⁾

Address Valid to End-of-Write

Address Set-up Time

tWP

tWR

tDW

tHZ

Write Pulse Width

40

0

50

0

60

0

Write Recovery Time

Data Valid to End-of-Write

Output High-Z Time^{(1, 2)}

20

—

25

—

30

—

tDH

tWZ

Data Hold Time⁽⁴⁾

Write Enabled to Output in High-Z^{(1, 2)}

3

—

3

—

3

—

ns

—

20

—

25

—

30

tOW

tSWR

tSPS

Output Active from End-of-Write^{(1, 2, 4)}

SEM Flag Write to Read Time

SEM Flag Contention Window

3

—

3

—

3

—

ns

10

ns

2721 tbl 12

NOTES:

1. Transition is measured ±500mV from Low or High-impedance voltage with Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterization but is not production tested.

3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.

4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary

over voltage and temperature, the actual tDH will always be smaller than the actual tOW.

5. “X” in part number indicates power rating (SA or LA).

6.05

7

IDT71342SA/LA

HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM WITH SEMAPHORE

COMMERCIAL TEMPERATURE RANGE

TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/W CONTROLLED TIMING^{(1, 5, 8)}

t

WC

ADDRESS

OE

(6)

t

AS

(3)

tWR

t

AW

CE or SEM⁽⁹⁾

(7)

(2)

t

HZ

tWP

R/W

(7)

tHZ

tWZ

tLZ

t

OW

(4)

DATAOUT

DATAIN

tDH

tDW

2721 drw 10

TIMING WAVEFORM OF WRITE CYCLE NO. 2, CE CONTROLLED TIMING^{(1, 5)}

tWC

ADDRESS

tAW

CE or SEM ⁽⁹⁾

(6)

tAS

(3)

tWR

(2)

tEW

R/W

tDW

tDH

DATAIN

2721 drw 11

NOTES:

1. R/W or CE must be High during all address transitions.

2. A write occurs during the overlap (tEW or tWP) of either CE or SEM = VIL and R/W = VIL.

3. tWR is measured from the earlier of CE or R/W going High to the end-of-write cycle.

4. During this period, the I/O pins are in the output state, and input signals must not be applied.

5. If the CE Low transition occurs simultaneously with or after the R/W Low transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal (CE or R/W) is asserted last.

7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured + 500mV from steady state with the Output

Test Load (Figure 2).

8. If OE is Low during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to

be placed on the bus for the required tDW. If OE is High during an R/W controlled write cycle, this requirement does not apply and the write pulse can be

as short as the specified tWP.

9. To access RAM, CE =VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.

6.05

8

IDT71342SA/LA

HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM WITH SEMAPHORE

COMMERCIAL TEMPERATURE RANGE

TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE⁽¹⁾

tSAA

A0 - A2

SEM

VALID ADDRESS

tAW

tWR

tACE

tEW

tWP

tOH

tSOP

tDW

DATAOUT

DATA0

R/W

DATAIN VALID

tDH

VALID⁽²⁾

tAS

tSWRD

tAOE

OE

Write Cycle

Test Cycle

(Read Cycle)

2721 drw 12

NOTES:

1. CE = VIH for the duration of the above timing (both write and read cycle).

2. "DATAOUT VALID" represents all I/O's (I/O0-I/O7) equal to the semaphore value.

TIMING WAVEFORM OF SEMAPHORE CONTENTION^{(1, 3, 4)}

MATCH

A0"A" - A2"A"

SIDE⁽²⁾

"A"

R/W "A"

SEM "A"

t

SPS

A0"B" - A2"B"

MATCH

SIDE⁽²⁾"B"

R/W"B"

SEM "B"

2721 drw 13

NOTES:

1. D0R = D0L = VIL, CER = CEL = VIH, Semaphore Flag is released from both sides (reads as ones from both sides) at cycle start.

2. All timing is the same for left and right ports. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

3. This parameter is measured from the point where R/W "A" or SEM "A" goes High until R/W "B" or SEM "B" goes High.

4. If tSPS is not satisfied, there is no guarantee which side will be granted the semaphore flag.

6.05

9

IDT71342SA/LA

HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM WITH SEMAPHORE

COMMERCIAL TEMPERATURE RANGE

reading it. If it was successful, it proceeds to assume control

overthesharedresource. Ifitwasnotsuccessfulinsettingthe

latch, it determines that the right side processor had set the

latchfirst, hasthetokenandisusingthesharedresource. The

left processor can then either repeatedly request that

semaphore’s status or remove its request for that semaphore

toperformanothertaskandoccasionallyattemptagaintogain

control of the token via the set and test sequence. Once the

right side has relinquished the token, the left side should

succeed in gaining control.

FUNCTIONAL DESCRIPTION

The IDT71342 is an extremely fast Dual-Port 4K x 8 CMOS

Static RAM with an additional 8 address locations dedicated

tobinarysemaphoreflags. Theseflagsalloweitherprocessor

on the left or right side of the Dual-Port RAM to claim a

privilege over the other processor for functions defined by the

system designer’s software. As an example, the semaphore

can be used by one processor to inhibit the other from

accessing a portion of the Dual-Port RAM or any other shared

resource.

The semaphore flags are active low. A token is requested

by writing a zero into a semaphore latch and is released when

the same side writes a one to that latch.

The Dual-Port RAM features a fast access time, and both

ports are completely independent of each other. This means

that the activity on the left port in no way slows the access time

oftherightport. Bothportsareidenticalinfunctiontostandard

CMOS Static RAMs and can be read from or written to at the

same time, with the only possible conflict arising from the

simultaneous writing of, or a simultaneous READ/WRITE of,

anon-semaphorelocation. Semaphoresareprotectedagainst

such ambiguous situations and may be used by the system

program to avoid any conflicts in the non-semaphore portion

of the Dual-Port RAM. These devices have an automatic

power-down feature controlled by CE, the Dual-Port RAM

enable, and SEM, the semaphore enable. The CE and SEM

pins control on-chip power down circuitry that permits the

respective port to go into standby mode when not selected.

This is the condition which is shown in Table 1 where CE and

SEM are both high.

SystemswhichcanbestusetheIDT71342containmultiple

processors or controllers and are typically very high-speed

systems which are software controlled or software intensive.

These systems can benefit from a performance increase

offered by the IDT71342’s hardware semaphores, which

provide a lockout mechanism without requiring complex

programming.

Software handshaking between processors offers the

maximum in system flexibility by permitting shared resources

to be allocated in varying configurations. The IDT71342 does

not use its semaphore flags to control any resources through

hardware, thus allowing the system designer total flexibility in

system architecture.

An advantage of using semaphores rather than the more

common methods of hardware arbitration is that wait states

are never incurred in either processor. This can prove to be

a major advantage in very high-speed systems.

The eight semaphore flags reside within the IDT71342 in a

separate memory space from the Dual-Port RAM. This

address space is accessed by placing a low input on the SEM

pin (which acts as a chip select for the semaphore flags) and

using the other control pins (Address, OE, and R/W) as they

would be used in accessing a standard Static RAM. Each of

the flags has a unique address which can be accessed by

either side through the address pins A0–A2. When accessing

the semaphores, none of the other address pins has any

effect.

When writing to a semaphore, only data pin D0 is used. If

a low level is written into an unused semaphore location, that

flagwillbesettoazeroonthatsideandaoneontheother(see

Table II). That semaphore can now only be modified by the

side showing the zero. When a one is written into the same

locationfromthesameside,theflagwillbesettoaoneforboth

sides (unless a semaphore request from the other side is

pending) and then can be written to by both sides. The fact

that the side which is able to write a zero into a semaphore

subsequently locks out writes from the other side is what

makes semaphore flags useful in interprocessor

communications. (A thorough discussion on the use of this

feature follows shortly.) A zero written into the same location

from the other side will be stored in the semaphore request

latch for that side until the semaphore is freed by the first side.

When a semaphore flag is read, its value is spread into all

data bits so that a flag that is a one reads as a one in all data

bits and a flag containing a zero reads as all zeros. The read

valueislatchedintooneside’soutputregisterwhenthatside’s

semaphore select (SEM) and output enable (OE) signals go

active. This serves to disallow the semaphore from changing

state in the middle of a read cycle due to a write cycle from the

other side. Because of this latch, a repeated read of a

semaphoreinatestloopmustcauseeithersignal(SEMorOE)

to go inactive or the output will never change.

HOW THE SEMAPHORE FLAGS WORK

The semaphore logic is a set of eight latches which are

independent of the Dual-Port RAM. These latches can be

used to pass a flag, or token, from one port to the other to

indicate that a shared resource is in use. The semaphores

provideahardwareassistforauseassignmentmethodcalled

“Token Passing Allocation.” In this method, the state of a

semaphore latch is used as a token indicating that a shared

resource is in use. If the left processor wants to use this

resource, it requests the token by setting the latch. This

processor then verifies its success in setting the latch by

A sequence of WRITE/READ must be used by the

semaphore in order to guarantee that no system level

contention will occur. A processor requests access to shared

resources by attempting to write a zero into a semaphore

location. If the semaphore is already in use, the semaphore

request latch will contain a zero, yet the semaphore flag will

appear as a one, a fact which the processor will verify by the

subsequent read (see Table II). As an example, assume a

6.05

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IDT71342SA/LA

HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM WITH SEMAPHORE

COMMERCIAL TEMPERATURE RANGE

processor writes a zero in the left port at a free semaphore thesemaphoreflagwillforceitssideofthesemaphoreflaglow

location. On a subsequent read, the processor will verify that andtheothersidehigh. Thisconditionwillcontinueuntilaone

it has written successfully to that location and will assume is written to the same semaphore request latch. Should the

controlovertheresourceinquestion. Meanwhile,ifaprocessor other side’s semaphore request latch have been written to a

ontherightsideattemptstowriteazerotothesamesemaphore zero in the meantime, the semaphore flag will now stay low

flag it will fail, as will be verified by the fact that a one will be until its semaphore request latch is written to a one. From this

readfromthatsemaphoreontherightsideduringasubsequent it is easy to understand that, if a semaphore is requested and

read. Had a sequence of READ/WRITE been used instead, theprocessorwhichrequesteditnolongerneedstheresource,

system contention problems could have occurred during the theentirecanhangupuntilaoneiswrittenintothatsemaphore

gap between the read and write cycles.

request latch.

It is important to note that a failed semaphore request must

The critical case of semaphore timing is when both sides

be followed by either repeated reads or by writing a one into request a single token by attempting to write a zero into it at

the same location. The reason for this is easily understood by the same time. The semaphore logic is specially designed to

looking at the simple logic diagram of the semaphore flag in resolve this problem. If simultaneous requests are made, the

Figure 3. Two semaphore request latches feed into a logic guarantees that only one side receives the token. If one

semaphore flag. Whichever latch is first to present a zero to side is earlier than the other in making the request, the first

TABLE I — NON-CONTENTION READ/WRITE CONTROL

Left or Right Port⁽¹⁾

R/W

X

CE

H

X

SEM

H

OE

X

D0-7

Z

Function

Port Disabled and in Power Down Mode

Data in Semaphore Flag Output on Port

Output Disabled

H

L

DATAOUT

Z

X

H

X

H

L

DATAIN

DATAOUT

DATAIN

—

Port Data Bit D0 Written Into Semaphore Flag

Data in Memory Output on Port

Data on Port Written Into Memory

Not Allowed

H

L

H

L

H

X

L

X

2721 tbl 13

NOTE:

1. AOL = A10L ≠ A0R - A10R.

"H" = HIGH, "L" = LOW, "X" = Don’t Care, "Z" = High-impedance, and " " = Low-to-High transition.

TABLE II — EXAMPLE SEMAPHORE PROCUREMENT SEQUENCE^(1,2)

Function

D0 - D7 Left

D0 - D7 Right

Status

No Action

1

0

1

0

1

0

1

0

1

0

1

Semaphore free

Left port has semaphore token

Left Port Writes “0” to Semaphore

Right Port Writes “0” to Semaphore

Left Port Writes “1” to Semaphore

Left Port Writes “0” to Semaphore

Right Port Writes “1” to Semaphore

Left Port Writes “1” to Semaphore

Right Port Writes “0” to Semaphore

Right Port Writes “1” to Semaphore

Left Port Writes “0” to Semaphore

Left Port Writes “1” to Semaphore

No change. Right side has no write access to semaphore

Right port obtains semaphore token

No change. Left side has no write access to semaphore

Left port obtains semaphore token

Semaphore free

Right port has semaphore token

Semaphore free

Left port has semaphore token

Semaphore free

2721 tbl 14

NOTES:

1. This table denotes a sequence of events for only one of the eight semaphores on the IDT71342.

2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O7). These eight semaphores are addressed by A0 - A2.

6.05

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IDT71342SA/LA

HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM WITH SEMAPHORE

COMMERCIAL TEMPERATURE RANGE

side to make the request will receive the token. If both a one to Semaphore 0 and may then try to gain access to

requests arrive at the same time, the assignment will be Semaphore 1. If Semaphore 1 was still occupied by the right

arbitrarily made to one port or the other.

side, the left side could undo its semaphore request and

One caution that should be noted when using semaphores perform other tasks until it was able to write, then read a zero

is that semaphores alone do not guarantee that access to a into Semaphore 1. If the right processor performs a similar

resource is secure. As with any powerful programming task with Semaphore 0, this protocol would allow the two

technique, if semaphores are misused or misinterpreted, a processors to swap 2K blocks of Dual-Port RAM with each

software error can easily happen. Code integrity is of the other.

utmost importance when semaphores are used instead of

slower, more restrictive hardware intensive schemes.

The blocks do not have to by any particular size and can

even be variable, depending upon the complexity of the

Initialization of the semaphores is not automatic and must software using the semaphore flags. All eight semaphores

be handled via the initialization program at power up. Since could be used to divide the Dual-Port RAM or other shared

any semaphore request flag which contains a zero must be resourcesintoeightparts. Semaphorescanevenbeassigned

reset to a one, all semaphores on both sides should have a different meanings on different sides rather than being given

one written into them at initialization from both sides to assure a common meaning as was shown in the example above.

that they will be free when needed.

Semaphores are a useful form of arbitration in systems like

disk interfaces where the CPU must be locked out of a section

ofmemoryduringatransferandtheI/Odevicecannottolerate

any wait states. With the use of semaphores, once the two

devices had determined which memory area was “off limits” to

the CPU, both the CPU and the I/O devices could access their

assigned portions of memory continuously without any wait

states.

Semaphores are also useful in applications where no

memory “WAIT” state is available on one or both sides. Once

asemaphorehandshakehasbeenperformed,bothprocessors

can access their assigned RAM segments at full speed.

Anotherapplicationisintheareaofcomplexdatastructures.

In this case, block arbitration is very important. For this

applicationoneprocessormayberesponsibleforbuildingand

updating a data structure. The other processor then reads

andinterpretsthatdatastructure. Iftheinterpretingprocessor

reads an incomplete data structure, a major error condition

may exist. Therefore, some sort of arbitration must be used

between the two different processors. The building processor

arbitrates for the block, locks it and then is able to go in and

update the data structure. When the update is completed, the

data structure block is released. This allows the interpreting

processortocomebackandreadthecompletedatastructure,

thereby guaranteeing a consistent data structure.

USING SEMAPHORES–Some examples

Perhaps the simplest application of semaphores is their

application as resource markers for the IDT71342’s Dual-Port

RAM. Say the 4K x 8 RAM was to be divided into two 2K x 8

blockswhichweretobededicatedatanyonetimetoservicing

either the left or right port. Semaphore 0 could be used to

indicate the side which would control the lower section of

memory, and Semaphore 1 could be defined as the indicator

for the upper section of the memory.

To take a resource, in this example the lower 2K of Dual-

Port RAM, the processor on the left port could write and then

read a zero into Semaphore 0. If this task were successfully

completed (a zero was read back rather than a one), the left

processor would assume control of the lower 2K. Meanwhile,

therightprocessorwouldattempttoperformthesamefunction.

Since this processor was attempting to gain control of the

resource after the left processor, it would read back a one in

response to the zero it had attempted to write into Semaphore

0. At this point, the software could choose to try and gain

controlofthesecond2Ksectionbywriting,thenreadingazero

into Semaphore 1. If it succeeded in gaining control, it would

lock out the left side.

Once the left side was finished with its task, it would write

L PORT

R PORT

SEMAPHORE

REQUEST FLIP FLOP

SEMAPHORE

REQUEST FLIP FLOP

D

Q

D

D0

WRITE

SEMAPHORE

READ

SEMAPHORE

READ

2721 drw 14

Figure 3. IDT71342 Semaphore Logic

6.05

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IDT71342SA/LA

HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM WITH SEMAPHORE

COMMERCIAL TEMPERATURE RANGE

ORDERING INFORMATION

IDT

XXXX

A

999

A

Device Type Power

Speed

Package

Process/

Temperature

Range

Blank

Commercial (0°C to +70°C)

J

PF

52-pin PLCC (J52-1)

64-pin TQFP (PN64-1)

20

25

35

45

55

70

Speed in nanoseconds

LA

SA

Low Power

Standard Power

32K (4K x 8-Bit) Dual-Port RAM w/ Semaphore

71342

2721 drw 15

6.05

13


型号：	IDT71342LA20PFG
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Dual-Port SRAM, 4KX8, 20ns, CMOS, PQFP64, PLASTIC, TQFP-64
文件：	总13页 (文件大小：147K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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