IDT71321LA55J8 [IDT]
Dual-Port SRAM, 2KX8, 55ns, CMOS, PQCC52, 0.750 X 0.750 INCH, 0.170 INCH HEIGHT, PLASTIC, LCC-52;
| 型号： | IDT71321LA55J8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Dual-Port SRAM, 2KX8, 55ns, CMOS, PQCC52, 0.750 X 0.750 INCH, 0.170 INCH HEIGHT, PLASTIC, LCC-52 静态存储器 内存集成电路 |
| 文件： | 总17页 (文件大小：159K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT71321SA/LA
IDT71421SA/LA
HIGH SPEED
2K X 8 DUAL-PORT
STATIC RAM WITH INTERRUPTS
Features
◆
◆
MASTER IDT71321 easily expands data bus width to 16-or-
more-bits using SLAVE IDT71421
High-speed access
– Commercial: 20/25/35/55ns (max.)
– Industrial: 55ns (max.)
Low-power operation
◆
◆
◆
◆
◆
◆
◆
On-chip port arbitration logic (IDT71321 only)
BUSY output flag on IDT71321; BUSY input on IDT71421
Fully asynchronous operation from either port
Battery backup operation – 2V data retention (LA only)
TTL-compatible, single 5V ±10% power supply
Available in 52-Pin PLCC, 64-Pin TQFP, and 64-Pin STQFP
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
◆
– IDT71321/IDT71421SA
— Active: 325mW (typ.)
— Standby: 5mW (typ.)
– IDT71321/421LA
— Active: 325mW (typ.)
— Standby: 1mW (typ.)
Two INT flags for port-to-port communications
◆
FunctionalBlockDiagram
OER
OEL
CEL
R/WL
CER
R/WR
I/O0L- I/O7L
I/O0R-I/O7R
I/O
Control
I/O
Control
(1,2)
BUSYL
(1,2)
BUSYR
A10L
A0L
A10R
Address
Decoder
MEMORY
ARRAY
Address
Decoder
A0R
11
11
ARBITRATION
and
INTERRUPT
LOGIC
CEL
OEL
CER
OER
R/WR
R/WL
(2)
INTR
(2)
INTL
2691 drw 01
NOTES:
1. IDT71321 (MASTER): BUSY is open drain output and requires pullup resistor of 270Ω.
IDT71421 (SLAVE): BUSY is input.
2. Open drain output: requires pullup resistor of 270Ω.
MARCH 1999
1
DSC-2691/8
©1999IntegratedDeviceTechnology,Inc.
1
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Description
The IDT71321/IDT71421 are high-speed 2K x 8 Dual-Port Static address, and I/O pins that permit independent, asynchronous access
for reads or writes to any location in memory. An automatic power
down feature, controlled by CE, permits the on chip circuitry of each
port to enter a very low standby power mode.
Fabricated using IDT's CMOS high-performance technology, these
devices typically operate on only 325mW of power. Low-power (LA)
versions offer battery backup data retention capability, with each Dual-
Port typically consuming 200µW from a 2V battery.
RAMs with internal interrupt logic for interprocessor communications.
The IDT71321 is designed to be used as a stand-alone 8-bit Dual-
Port Static RAM or as a "MASTER" Dual-Port Static RAM together
with the IDT71421 "SLAVE" Dual-Port in 16-bit-or-more word width
systems. Using the IDT MASTER/SLAVE Dual-Port Static RAM ap-
proach in 16-or-more-bit memory system applications results in full
speed, error-free operation without the need for additional discrete
logic.
The IDT71321/IDT71421 devices are packaged in 52-pin PLCCs,
64-pin TQFPs, and 64-pin STQFPs.
Both devices provide two independent ports with separate control,
PinConfigurations(1,2,3)
INDEX
7
6
5
4
3
2
52 51 50 49 48 47
46
1L
2L
3L
4L
5L
6L
7L
8L
9L
0L
1L
2L
3L
A
OER
8
9
1
45
44
43
42
41
40
39
38
37
36
35
34
A
0R
1R
2R
3R
4R
5R
6R
7R
8R
9R
A
A
A
A
A
A
A
A
A
A
10
11
12
13
14
15
16
17
18
A
A
A
IDT71321/421J
J52-1(4)
A
A
A
PLCC
Top View(5)
A
I/O
I/O
I/O
I/O
19
20
NC
7R
I/O
21 22 23 24 25 26 27 28 29 30 31 32 33
,
2691 drw 02
INDEX
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
OEL
A0L
A1L
A2L
A3L
A4L
A5L
A6L
N/C
A7L
A8L
A9L
N/C
I/O0L
I/O1L
I/O2L
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
OER
A0R
A1R
A2R
A3R
A4R
A5R
A6R
IDT71321/421PF or TF
PN64-1 / PP64-1(4)
64-Pin TQFP
64-Pin STQFP
Top View(5)
N/C
A7R
A8R
A9R
NOTES:
N/C
N/C
I/O7R
I/O6R
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. J52-1 package body is approximately .75 in x .75 in x .17 in.
PN64-1 package body is approximately 14mm x 14mm x 1.4mm.
PP64-1 package body is approximately 10mm x 10mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
,
2691 drw 03
2
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Capacitance(1)
RecommendedOperating
TemperatureandSupplyVoltage(1,2)
(TA = +25°C, f = 1.0MHz) TQFP Only
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions(2)
Max. Unit
Grade
Ambient
Temperature
GND
Vcc
CIN
VIN = 3dV
9
pF
Commercial
0OC to +70OC
0V
0V
5.0V+ 10%
5.0V+ 10%
COUT
VOUT = 3dV
10
pF
Industrial
-40OC to +85OC
2691 tbl 00
NOTES:
2691 tbl 02
1. This parameter is determined by device characterization but is not production
tested.
2. 3dv references the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
NOTES:
1. This is the parameter TA.
2. Industrial temperature: for specific speeds, packages and powers contact your
sales office.
Absolute Maximum Ratings(1)
RecommendedDCOperating
Conditions
Symbol
Rating
Commercial
& Industrial
Unit
Symbol
Parameter
Min.
Typ.
Max. Unit
(2)
VTERM
Terminal Voltage
with Respect
to GND
-0.5 to +7.0
V
VCC
Supply Voltage
4.5
5.0
5.5
0
V
V
V
GND Ground
0
0
Temperature
Under Bias
-55 to +125
-55 to +125
50
oC
oC
(2)
____
TBIAS
TSTG
IOUT
VIH
VIL
Input High Voltage
Input Low Voltage
2.2
6.0
0.8
-0.5(1)
V
____
Storage
Temperature
2691 tbl 03
NOTES:
1. VIL (min.) = -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 10%.
DC Output
Current
mA
2691 tbl 01
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. VTERM must not exceed VCC + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > VCC + 10%.
3
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1,4,6) (VCC = 5.0V ± 10%)
71321X20
71321X25
71421X25
Com'l Only
71421X20
Com'l Only
Symbol
Parameter
Test Condition
Version
COM'L
Typ.
Max.
Typ.
Max.
Unit
I
CC
Dynamic Operating
Current
(Both Ports Active)
SA
LA
110
110
250
200
110
110
220
170
mA
CE
L
and CE = VIL,
R
Outputs Open
f = fMAX
(2)
____
____
____
____
____
____
____
____
IND
SA
LA
I
SB1
Standby Current
(Both Ports - TTL
Level Inputs)
COM'L
IND
SA
LA
30
30
65
45
30
30
65
45
mA
mA
mA
CE
L
and CE = VIH
R
(2)
f = fMAX
____
____
____
____
____
____
____
____
SA
LA
(5)
I
SB2
Standby Current
(One Port - TTL
Level Inputs)
COM'L
IND
SA
LA
65
65
165
125
65
65
150
115
CE"A" = VIL and CE"B" = VIH
Active Port Outputs Open,
(2)
f=fMAX
____
____
____
____
____
____
____
____
SA
LA
I
SB3
Full Standby Current
COM'L
IND
SA
LA
1.0
0.2
15
5
1.0
0.2
15
5
CE
L
and
> VCC - 0.2V,
(Both Ports
-
CE
R
CMOS Level Inputs)
V
V
IN > VCC - 0.2V or
____
____
____
____
____
____
____
____
IN < 0.2V, f = 0(3)
SA
LA
I
SB4
Full Standby Current
(One Port -
CMOS Level Inputs)
COM'L
IND
SA
LA
60
60
155
115
60
60
145
105
mA
CE"A" < 0.2V and
(5)
CE"B" > VCC - 0.2V
V
IN > VCC - 0.2V o r V IN < 0.2V
____
____
____
____
____
____
____
____
SA
LA
Active Port Outputs Open,
(2)
f = fMAX
2691 tbl 04a
71321X35
71321X55
71421X35
71421X55
Com'l
Com'l Only
& Ind
Symbol
Parameter
Test Condition
Version
Typ.
Max.
Typ.
Max.
Unit
I
CC
Dynamic Operating
Current
(Both Ports Active)
COM'L
SA
LA
80
165
65
65
155
110
mA
CE
L
and CE = VIL,
R
80
120
Outputs Open
f = fMAX
(2)
____
____
____
____
IND
SA
LA
65
65
190
140
I
SB1
Standby Current
(Both Ports - TTL
Level Inputs)
COM'L
IND
SA
LA
25
25
65
45
20
20
65
35
mA
mA
mA
CE
L
and CE = VIH
R
(2)
f = fMAX
____
____
____
____
SA
LA
20
20
65
45
(5)
I
SB2
Standby Current
(One Port - TTL
Level Inputs)
COM'L
IND
SA
LA
50
50
125
90
40
40
110
75
CE"A" = VIL and CE"B" = VIH
Active Port Outputs Open,
(2)
f=fMAX
____
____
____
____
SA
LA
40
40
125
90
I
SB3
Full Standby Current
CE
L
and
> VCC - 0.2V,
COM'L
IND
SA
LA
1.0
0.2
15
4
1.0
0.2
15
4
(Both Ports
-
CE
R
CMOS Level Inputs)
V
V
IN > VCC - 0.2V or
____
____
____
____
IN < 0.2V, f = 0(3)
SA
LA
1.0
0.2
30
10
I
SB4
Full Standby Current
(One Port -
CMOS Level Inputs)
COM'L
IND
SA
LA
45
45
110
85
40
40
100
70
mA
CE"A" < 0.2V and
(5)
CE"B" > VCC - 0.2V
V
IN > VCC - 0.2V or VIN < 0.2V
____
____
____
____
SA
LA
40
40
110
85
Active Port Outputs Open,
(2)
f = fMAX
2691 tbl 04b
NOTES:
1. 'X' in part numbers indicates power rating (SA or LA).
2. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC TEST CONDITIONS” of input
levels of GND to 3V.
3. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
4. Vcc = 5V, TA=+25°C for Typ and is not production tested. Vcc DC = 100mA (Typ)
5. Port "A" may be either left or right port. Port "B" is opposite from port "A".
6. Industrial temperature: for other speeds, packages and powers contact your sales office.
4
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 5.0V ± 10%)
71321SA
71421SA
71321LA
71421LA
Symbol
|ILI|
Parameter
Test Conditions
Min.
Max.
10
Min.
Max.
5
Unit
µA
µA
(1)
___
___
Input Leakage Current
VCC = 5.5V, VIN = 0V to VCC
(1)
___
___
Output Leakage Current
IH OUT
CC
|ILO|
CE = V , V = 0V to V ,
10
5
VCC - 5.5V
___
___
___
___
VOL
Output Low Voltage (I/O0-I/O7)
IOL = 4mA
0.4
0.5
0.4
0.5
V
V
Open Drain Output
Low Voltage (BUSY/INT)
IOL = 16mA
OL
V
___
___
VOH
Output High Voltage
IOH = -4mA
2.4
2.4
V
2691 tbl 05
NOTE:
1. At Vcc < 2.0V leakages are undefined.
Data Retention Characteristics (LA Version Only)
Symbol
VDR
ICCDR
Parameter
Test Condition
Min.
Typ.(1)
Max.
Unit
V
____
VCC for Data Retention
2.0
0
____
Data Retention Current
µA
µA
VCC = 2.0V, CE > VCC - 0.2V
COM'L
IND
100
1500
____
VIN > VCC - 0.2V or VIN < 0.2V
100
4000
(3)
____
____
tCDR
Chip Deselect to Data Retention Time
Operation Recovery Time
0
ns
(3)
(2)
____
____
tR
tRC
ns
2691 tbl 06
NOTES:
1. VCC = 2V, TA = +25°C, and is not production tested.
2. tRC = Read Cycle Time
3. This parameter is guaranteed but not production tested.
Data Retention Waveform
DATA RETENTION MODE
VCC
VDR
2.0V
≥
4.5V
4.5V
tR
tCDR
VDR
CE
VIH
VIH
,
2691 drw 04
5
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
AC Test Conditions
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
5ns
1.5V
1.5V
Figures 1,2 and 3
2691 tbl 07
5V
5V
1250Ω
1250Ω
OUT
DATA
OUT
DATA
Ω
775
30pF*
775Ω
5pF*
*100pF for 55ns versions
Figure 1. AC Output Test Load
Figure 2. Output Test Load
(for tHZ, tLZ, tWZ, and tOW)
* Including scope and jig.
5V
270Ω
2691 drw 05
BUSY or INT
30pF*
*100pF for 55ns versions
Figure 3. BUSY and INT
AC Output Test Load
6
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureSupplyVoltageRange(2,4)
71321X20
71421X20
Com'l Only
71321X25
71421X25
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
tRC
tAA
tACE
tAOE
tOH
tLZ
Read Cycle Time
20
25
ns
ns
ns
ns
ns
ns
ns
ns
____
____
Address Access Time
20
20
25
25
____
____
____
____
Chip Enable Access Time
Output Enable Access Time
Output Hold from Address Change
Output Low-Z Time(1,3)
11
12
____
____
3
3
____
____
0
0
Output High-Z Time(1,3)
10
10
____
____
tHZ
tPU
tPD
Chip Enable to Power Up Time(3)
Chip Disable to Power Down Time(3)
0
0
____
____
____
____
20
25
ns
2691 tbl 08a
71321X35
71421X35
Com'l Only
71321X55
71421X55
Com'l
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
tRC
tAA
tACE
tAOE
tOH
tLZ
Read Cycle Time
35
55
ns
ns
ns
ns
ns
ns
ns
ns
____
____
Address Access Time
35
35
55
55
____
____
____
____
Chip Enable Access Time
Output Enable Access Time
Output Hold from Address Change
Output Low-Z Time(1,3)
20
25
____
____
3
3
____
____
0
5
Output High-Z Time(1,3)
15
25
____
____
tHZ
tPU
tPD
Chip Enable to Power Up Time(3)
Chip Disable to Power Down Time(3)
0
0
____
____
____
____
35
50
ns
2691 tbl 08b
NOTES:
1. Transition is measured ±500mV from Low or High-impedance voltage Output Test Load (Figure 2).
2. 'X' in part numbers indicates power rating (SA or LA).
3. This parameter is guaranteed by device characterization, but is not production tested.
4. Industrial temperature: for other speeds, packages and powers contact your sales office.
7
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle No. 1, Either Side(1)
tRC
ADDRESS
tOH
tAA
tOH
DATAOUT
PREVIOUS DATA VALID
DATA VALID
BUSYOUT
2691 drw 06
(2,3)
tBDDH
NOTES:
1. R/W = VIH, CE = VIL, and is OE = VIL. Address is valid prior to the coincidental with CE transition LOW.
2. tBDD delay is required only in the case where the opposite port is completing a write operation to the same address location. For simultaneous read operations
BUSY has no relationship to valid output data.
3. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.
Timing Waveform of Read Cycle No. 2, Either Side(3)
tACE
CE
(4)
(2)
tHZ
tAOE
OE
(2)
(1)
tHZ
tLZ
DATAOUT
VALID DATA
(1)
(4)
tLZ
tPD
tPU
ICC
CURRENT
ISS
50%
50%
2691 drw 07
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first, OE or CE.
3. R/W = VIH and OE = VIL, and the address is valid prior to or coincidental with CE transition LOW.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.
8
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemepratureandSupplyVoltageRange(4,5)
71321X20
71421X20
Com'l Only
71321X25
71421X25
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
tWC
tEW
tAW
tAS
Write Cycle Time(2)
20
15
15
0
25
20
20
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Enable to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
Write Pulse Width(3)
tWP
tWR
tDW
tHZ
15
0
15
0
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time(1)
Data Hold Time
10
12
____
____
10
10
____
____
tDH
tWZ
tOW
0
0
(1)
____
____
Write Enable to Output in High-Z
Output Active from End-of-Write(1)
10
10
____
____
0
0
ns
2691 tbl 09a
71321X35
71421X35
Com'l Only
71321X55
71421X55
Com'l & Ind
Symbol
WRITE CYCLE
tWC
Parameter
Min.
Max.
Min.
Max.
Unit
Write Cycle Time(2)
35
30
30
0
55
40
40
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
____
____
____
____
____
____
____
____
____
____
____
____
____
____
EW
t
Chip Enable to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
Write Pulse Width(3)
tAW
tAS
tWP
tWR
25
0
30
0
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time(1)
Data Hold Time
DW
t
15
20
____
____
tHZ
15
25
____
____
tDH
tWZ
tOW
0
0
(1)
____
____
Write Enable to Output in High-Z
Output Active from End-of-Write(1)
15
30
____
____
0
0
ns
2691 tbl 09b
NOTES:
1. Transition is measured ±500mV from Low or High-impedance voltage with Output Test Load (Figure 2). This parameter is guaranteed by
device characterization but is not production tested.
2. For Master/Slave combination, tWC = tBAA + tWP, since R/W = VIL must occur after tBAA .
3. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be
placed on the bus for the required tDW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short
as the specified tWP.
4. 'X' in part numbers indicates power rating (SA or LA).
5. Industrial temperature: for other speeds, packages and powers contact your sales office.
9
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, (R/W Controlled Timing)(1,5,8)
tWC
ADDRESS
(7)
tHZ
OE
tAW
CE
(3)
(6)
(2)
(7)
(4)
tWR
tAS
tWP
tHZ
R/W
DATA OUT
DATA IN
(7)
tWZ
tOW
(4)
tDW
tDH
2691 drw 08
Timing Waveform of Write Cycle No. 2, (CE Controlled Timing)(1,5)
tWC
ADDRESS
AW
t
CE
R/W
IN
(6)
(2)
(3)
WR
tAS
tEW
t
tDW
tDH
DATA
2691 drw 09
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of CE = VIL and R/W= VIL.
3. tWR is measured from the earlier of CE or R/W going HIGH to the end of the write cycle.
4. During this period, the l/O pins are in the output state and input signals must not be applied.
5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal (CE or R/W) is asserted last.
7. This parameter is determined to be device characterization, but is not production tested. Transition is measured ±500mV from steady state with the Output Test
Load (Figure 2).
8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be
placed on the bus for the required tDW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short
as the specified tWP.
10
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(6,7)
71321X20
71421X20
71321X25
71421X25
Com'l Only
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (For MASTER 71321)
____
____
____
____
____
____
____
____
tBAA
tBDA
20
20
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
BUSY Access Time from Address
BUSY Disable Time from Address
BUSY Access Time from Chip Enable
BUSY Disable Time from Chip Enable
Write Hold After BUSY(5)
BAC
t
tBDC
tWH
20
20
____
____
12
15
tWDD
tDDD
tAPS
tBDD
Write Pulse to Data Delay(1)
50
50
____
____
Write Data Valid to Read Data Delay (1)
Arbitration Priority Set-up Time(2)
BUSY Disable to Valid Data(3)
35
35
____
____
____
____
5
5
____
____
25
35
BUSY INPUT TIMING (For SLAVE 71421)
(4)
____
____
____
____
tWB
Write to BUSY Input
0
0
ns
ns
ns
tWH
Write Hold After BUSY(5)
12
15
Write Pulse to Data Delay(1)
Write Data Valid to Read Data Delay (1)
40
30
50
35
____
____
tWDD
tDDD
____
____
ns
2691 tbl 10a
71321X35
71421X35
Com'l Only
71321X55
71421X55
Com'l
& Ind
Symbol
BUSY TIMING (For MASTER 71321)
Parameter
Min.
Max.
Min.
Max.
Unit
____
____
____
____
____
____
____
____
tBAA
tBDA
tBAC
tBDC
tWH
20
20
20
30
30
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
BUSY Access Time from Address
BUSY Disable Time from Address
BUSY Access Time from Chip Enable
BUSY Disable Time from Chip Enable
Write Hold After BUSY(5)
20
30
____
____
20
20
tWDD
tDDD
tAPS
tBDD
Write Pulse to Data Delay(1)
60
80
____
____
Write Data Valid to Read Data Delay (1)
Arbitration Priority Set-up Time(2)
35
55
____
____
____
____
5
5
____
____
BUSY Disable to Valid Data(3)
35
50
BUSY INPUT TIMING (For SLAVE 71421)
(4)
____
____
____
____
tWB
Write to BUSY Input
0
0
ns
ns
ns
tWH
Write Hold After BUSY(5)
20
20
Write Pulse to Data Delay(1)
Write Data Valid to Read Data Delay (1)
60
35
80
55
____
____
tWDD
tDDD
____
____
ns
2691 tbl 10b
NOTES:
1. Port-to-port delay through RAM cells from the writing port to the reading port, refer to “Timing Waveform of Write with Port-to-Port Read and BUSY."
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that a write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. 'X' in part numbers indicates power rating (SA or LA).
7. Industrial temperature: for other speeds, packages and powers contact your sales office.
11
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Port-to-Port Read and BUSY(2,3,4)
tWC
ADDR"A"
MATCH
tWP
R/W"A"
tDW
tDH
DATAIN "A"
VALID
(1)
tAPS
MATCH
ADDR"B"
BUSY"B"
tBAA
tBDD
tBDA
tWDD
DATAOUT"B"
VALID
tDDD
NOTES:
2691 drw 10
1. To ensure that the earlier of the two ports wins. tAPS is ignored for Slave (71421).
2. CEL = CER = VIL
3. OE = VIL for the reading port.
4. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is opposite from port "A".
Timing Waveform of Write with BUSY(4)
WP
t
R/W"A"
(3)
tWB
BUSY"B"
(1)
tWH
,
W"B"
R/
(2)
2691 drw 11
NOTES:
1. tWH must be met for both BUSY input (71421, slave) or output (71321, Master).
2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.
3. tWB is only for the slave version (71421).
4. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is opposite from port "A".
12
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Timing Waveform of BUSY Arbitration Controlled by CE Timing(1)
ADDR "A"
ADDRESSES MATCH
AND "B"
CE"B"
(2)
tAPS
CE"A"
tBAC
tBDC
BUSY"A"
2691 drw 12
Timing Waveform of BUSY Arbritration Controlled
by Address Match Timing(1)
tRC or tWC
ADDR"A"
ADDR"B"
ADDRESSES MATCH
ADDRESSES DO NOT MATCH
(2)
tAPS
tBAA
tBDA
BUSY"B"
2691 drw 13
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. If tAPS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (71321 only).
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(1,2)
71321X20
71421X20
Com'l Only
71321X25
71421X25
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
____
____
____
____
tAS
Address Set-up Time
0
0
ns
ns
ns
tWR
tINS
tINR
Write Recovery Time
Interrupt Set Time
0
0
____
____
20
20
25
25
____
____
Interrupt Reset Time
ns
2691 tbl 11a
NOTES:
1. 'X' in part numbers indicates power rating (SA or LA).
2. Industrial temperature: for other speeds, packages and powers contact your sales office.
13
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureSupplyVoltageRange(1,2)
71321X35
71421X35
Com'l Only
71321X55
71421X55
Com'l
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
____
____
____
____
tAS
Address Set-up Time
0
0
ns
ns
ns
tWR
tINS
tINR
Write Recovery Time
Interrupt Set Time
0
0
____
____
25
25
45
45
____
____
Interrupt Reset Time
ns
2691 tbl 11b
NOTES:
1. 'X' in part numbers indicates power rating (SA or LA).
2. Industrial temperature: for other speeds, packages and powers contact your sales office.
TimingWaveformof InterruptMode(1)
SET INT
WC
t
INTERRUPT ADDRESS (2)
ADDR"A"
(4)
(3)
AS
t
WR
t
R/W"A"
INT"B"
(3)
INS
t
2691 drw 14
CLEAR INT
tRC
(2)
ADDR"B"
INTERRUPT CLEAR ADDRESS
(3)
tAS
OE"B"
(3)
tINR
INT"A"
2691 drw 15
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. See Interrupt Truth Table.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
14
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
TruthTables
Truth Table I. Non-Contention Read/Write Control(4)
Left or Right Port(1)
R/W
X
D0-7
Function
CE
H
H
L
OE
X
X
X
L
Z
Z
Port Disabled and in Power-Down Mode, ISB2 or ISB4
X
CER = CEL = VIH, Power-Down Mode, ISB1 or ISB3
L
DATAIN
DATAOUT
Z
Data on Port Written Into Memory(2)
(3)
H
L
Data in Memory Output on Port
H
L
H
High Impedance Outputs
2691 tbl 12
NOTES:
1. A0L – A10L ≠ A0R – A10R.
2. If BUSY = L, data is not written.
3. If BUSY = L, data may not be valid, see tWDD and tDDD timing.
4. 'H' = VIH, 'L' = VIL, 'X' = DON’T CARE, 'Z' = HIGH IMPEDANCE
Truth Table II. Interrupt Flag(1,4)
Left Port
Right Port
WL
R/
WR
R/
A10L-A0L
7FF
X
A10R-A0R
X
Function
Set Right INTR Flag
Reset Right INTR Flag
Set Left INTL Flag
CEL
L
OEL
X
INTL
X
CER
X
OER
X
INTR
(2)
L
X
X
X
X
X
L
L
(3)
X
X
X
L
L
7FF
7FE
X
H
(3)
X
X
X
L
L
X
X
X
(2)
L
L
7FE
H
X
X
X
Reset Left INTL Flag
2691 tbl 13
NOTES:
1. Assumes BUSYL = BUSYR = VIH
2. If BUSYL = VIL, then No Change.
3. If BUSYR = VIL, then No Change.
4. 'H' = HIGH, 'L' = LOW, 'X' = DON’T CARE
Truth Table III Address BUSY Arbitration
Inputs
Outputs
A0L-A10L
0R-A10R
(1)
(1)
A
Function
Normal
Normal
Normal
CE
L
CER
X
BUSYL
BUSYR
X
H
X
L
NO MATCH
MATCH
H
H
H
H
X
H
MATCH
H
H
L
MATCH
(2)
(2)
Write Inhibit(3)
2691 tbl 14
NOTES:
1. Pins BUSYL and BUSYR are both outputs for 71321 (Master). Both are inputs for 71421 (Slave). BUSYX outputs on the 71321 are open drain, not push-pull outputs.
On slaves the BUSYX input internally inhibits writes.
2. 'L' if the inputs to the opposite port were stable prior to the address and enable inputs of this port. 'H' if the inputs to the opposite port became stable after the address
and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored
when BUSYR outputs are driving LOW regardless of actual logic level on the pin.
15
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
FunctionalDescription
The IDT71321/IDT71421provides twoports withseparate control,
addressandI/Opinsthatpermitindependentaccessforreadsorwrites
toanylocationinmemory. The IDT71321/IDT71421has anautomatic
power down feature controlled by CE. The CE controls on-chip power
downcircuitrythatpermitstherespectiveporttogointoastandbymode
whennotselected(CE=VIH).Whenaportisenabled,accesstotheentire
memoryarrayispermitted.
beingexpandedindepth,thentheBUSYindicationfortheresultingarray
does not require the use of an external AND gate.
Width Expansion with Busy Logic
Master/SlaveArrays
WhenexpandinganSRAMarrayinwidthwhileusingBUSYlogic,one
masterpartis usedtodecidewhichsideoftheSRAMarraywillreceive
aBUSYindication,andtooutputthatindication.Anynumberofslavesto
beaddressedinthesameaddress rangeas themaster,usetheBUSY
signalasawriteinhibitsignal.ThusontheIDT71321/IDT71421SRAMs
theBUSYpinisanoutputifthepartisMaster(IDT7132),andthe BUSY
pin is an input if the part is a Slave (IDT7142) as shown in Figure 3.
Interrupts
Iftheuserchoosestheinterruptfunction,amemorylocation(mailbox
ormessage center)is assignedtoeachport. The leftportinterruptflag
(INTL) is asserted when the right port writes to memory location 7FE
(HEX), whereawriteisdefinedastheCER=R/WR=VIL,perTruthTable
II.Theleftportclearstheinterruptbyaccessingaddresslocation7FEwhen
CEL = OEL = VIL, R/W is a "don't care". Likewise, the right port interrupt
flag(INTR)isassertedwhentheleftportwritestomemorylocation7FF
(HEX)andtocleartheinterruptflag(INTR),therightportmustaccessthe
memorylocation7FF.Themessage(8bits)at7FEor7FFisuser-defined,
sinceitisanaddressableSRAMlocation.Iftheinterruptfunctionisnotused,
address locations 7FEand7FFare notusedas mailboxes, butas part
of the random access memory. Refer to Truth Table II for the interrupt
operation.
SLAVE
Dual Port
SRAM
5V
270Ω
MASTER
Dual Port
SRAM
CE
CE
5V
BUSYL
BUSYL
BUSYR
BUSYR
270Ω
MASTER
Dual Port
SRAM
SLAVE
Dual Port
SRAM
CE
CE
BUSYR
BUSYL
BUSYR
BUSYL
BUSYR
BUSYL
2691 drw 16
BusyLogic
Figure 3. Busy and chip enable routing for both width and depth
expansion with IDT71321 (Master) and (Slave) IDT71421 SRAMs.
BusyLogicprovidesahardwareindicationthatbothportsoftheRAM
haveaccessedthesamelocationatthesametime.Italsoallowsoneofthe
twoaccessestoproceedandsignalstheothersidethattheRAMis“Busy”.
TheBUSYpincanthenbeusedtostalltheaccessuntiltheoperationon
theothersideiscompleted.Ifawriteoperationhasbeenattemptedfrom
thesidethatreceivesabusyindication,thewritesignalisgatedinternally
topreventthewritefromproceeding.
Iftwoormoremasterpartswereusedwhenexpandinginwidth,asplit
decisioncouldresultwithonemasterindicatingBUSYononesideofthe
arrayandanothermasterindicatingBUSYononeothersideofthearray.
Thiswouldinhibitthewriteoperationsfromoneportforpartofawordand
inhibitthewriteoperationsfromtheotherportfortheotherpartoftheword.
TheBUSYarbitration,onaMaster,is basedonthechipenableand
address signals only. Itignores whetheranaccess is a readorwrite. In
a master/slave array, bothaddress andchipenable mustbe validlong
enoughforaBUSYflagtobeoutputfromthemasterbeforetheactualwrite
pulsecanbeinitiatedwitheithertheR/Wsignalorthebyteenables. Failure
toobservethistimingcanresultinaglitchedinternalwriteinhibitsignaland
corrupteddataintheslave.
TheuseofBUSYLogicisnotrequiredordesirableforallapplications.
InsomecasesitmaybeusefultologicallyORtheBUSYoutputstogether
anduse anyBUSYindicationas aninterruptsource toflagthe eventof
anillegalorillogicaloperation.InslavemodetheBUSYpinoperatessolely
asawriteinhibitinputpin.Normaloperationcanbeprogrammedbytying
the BUSY pins HIGH. If desired, unintended write operations can be
prevented to a port by tying the BUSY pinfor thatport LOW.
The BUSY outputs on the IDT71321 (Master) are open drain type
outputsandrequireopendrainresistorstooperate.IftheseSRAMsare
16
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
OrderingInformation
IDT
XXXX
A
999
A
A
Device Type Power Speed Package
Process/
Temperature
Range
BLANK Commercial (0°C to +70°C)
(1)
I
Industrial (-40°C to +85°C)
J
PF
TF
52-pin PLCC (J52-1)
64-pin TQFP (PN64-1)
64-pin STQFP (PP64-1)
20
25
35
55
Commercial Only
Commercial Only
Commercial Only
Commercial & Industrial
Speed in nanoseconds
Low Power
Standard Power
LA
SA
71321 16K (2K x 8-Bit) MASTER Dual-Port SRAM
w/ Interrupt
71421 16K (2K x 8-Bit) SLAVE Dual-Port SRAM
w/ Interrupt
2691 drw 17
NOTE:
1. Industrial temperature range is available in selected PLCC packages in standard power.
For other speeds, packages and powers contact your sales office.
DatasheetDocumentHistory
3/24/99:
Initiateddatasheetdocumenthistory
Convertedtonewformat
Cosmetictypographicalcorrections
Pages2and3Addedadditionalnotestopinconfigurations
Changeddrawingformat
6/7/99:
CORPORATE HEADQUARTERS
2975StenderWay
Santa Clara, CA 95054
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
for Tech Support:
831-754-4613
DualPortHelp@idt.com
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
17
6.42
相关型号：
IDT71321LA55JG
Dual-Port SRAM, 2KX8, 55ns, CMOS, PQCC52, 0.750 X 0.750 INCH, 0.170 INCH HEIGHT, GREEN, PLASTIC, LCC-52
IDT
IDT71321LA55JI8
Dual-Port SRAM, 2KX8, 55ns, CMOS, PQCC52, 0.750 X 0.750 INCH, 0.170 INCH HEIGHT, PLASTIC, LCC-52
IDT
©2020 ICPDF网 联系我们和版权申明