IDT7130SA35F [IDT]
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM; HIGH -SPEED 1K ×8双端口静态RAM
| 型号： | IDT7130SA35F |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM |
| 文件： | 总14页 (文件大小：219K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT7130SA/LA
IDT7140SA/LA
HIGH-SPEED
1K x 8 DUAL-PORT
STATIC RAM
Integrated Device Technology, Inc.
FEATURES
• High-speed access
—Military: 25/35/55/100ns (max.)
—Commercial: 25/35/55/100ns (max.)
—Commercial: 20ns 7130 in PLCC and TQFP
• Low-power operation
—IDT7130/IDT7140SA
—Active: 550mW (typ.)
—Standby: 5mW (typ.)
—IDT7130/IDT7140LA
—Active: 550mW (typ.)
—Standby: 1mW (typ.)
• MASTER IDT7130 easily expands data bus width to
16-or-more-bits using SLAVE IDT7140
• On-chip port arbitration logic (IDT7130 Only)
• BUSY output flag on IDT7130; BUSY input on IDT7140
• Interrupt flags for port-to-port communication
• Fully asynchronous operation from either port
• Battery backup operation–2V data retention (LA only)
• TTL-compatible, single 5V ±10% power supply
• Military product compliant to MIL-STD-883, Class B
• Standard Military Drawing #5962-86875
• Industrial temperature range (–40°C to +85°C) is avail-
able, tested to military electrical specifications
DESCRIPTION
The IDT7130/IDT7140 are high-speed 1K x 8 Dual-Port
Static RAMs. The IDT7130 is designed to be used as a
stand-alone 8-bit Dual-Port RAM or as a "MASTER" Dual-
Port RAM together with the IDT7140 "SLAVE" Dual-Port in
16-bit-or-more word width systems. Using the IDT MAS-
TER/SLAVE Dual-Port RAM approach in 16-or-more-bit
memory system applications results in full-speed, error-free
operation without the need for additional discrete logic.
Both devices provide two independent ports with sepa-
rate control, address, and I/O pins that permit independent
asynchronous access for reads or writes to any location in
memory. An automatic power down feature, controlled by
CE, permits the on chip circuitry of each port to enter a very
low standby power mode.
Fabricated using IDT's CMOS high-performance tech-
nology, these devices typically operate on only 550mW of
power. Low-power (LA) versions offer battery backup data
retention capability, with each Dual-Port typically consum-
ing 200µW from a 2V battery.
The IDT7130/IDT7140 devices are packaged in 48-pin
sidebraze or plastic DIPs, LCCs, or flatpacks, 52-pin PLCC,
and 64-pin TQFP and STQFP. Military grade product is
manufactured in compliance with the latest revision of MIL-
STD-883, Class B, making it ideally suited to military tem-
perature applications demanding the highest level of per-
formance and reliability.
FUNCTIONAL BLOCK DIAGRAM
OER
OEL
CEL
R/WL
CER
R/WR
I/O0L- I/O7L
I/O0R-I/O7R
I/O
Control
I/O
Control
(1,2)
(1,2)
BUSYR
BUSYL
A9L
A0L
A9R
Address
Decoder
MEMORY
ARRAY
Address
Decoder
A0R
10
10
NOTES:
ARBITRATION
and
INTERRUPT
LOGIC
1. IDT7130 (MASTER): BUSY is open
drain output and requires pullup
resistor of 270Ω.
CEL
OEL
CER
OER
R/WR
R/WL
IDT7140 (SLAVE): BUSY is input.
2. Open drain output: requires pullup
resistor of 270Ω.
(2)
(2)
INTL
INTR
2689 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
OCTOBER 1996
©1996 Integrated Device Technology, Inc.
DSC-2689/7
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
6.01
1
IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS (1,2)
CE
R/W
BUSY
INT
OE
L
L
L
L
1
48
47 CE
46 R/W
45 BUSY
44 INT
43 OE
V
CC
R
2
INDEX
3
R
4
R
7
6
5
4
3
2
52 51 50 49 48 47
1
L
8
46
45
44
43
42
41
40
39
38
37
36
35
34
5
R
R
A
1L
2L
3L
4L
5L
6L
7L
8L
9L
OER
A0L
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
A9L
6
9
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
0R
7
42
41
40
39
38
37
36
35
34
33
A
A
A
A
A
A
A
A
A
A
0R
10
11
12
13
14
15
16
17
18
19
20
1R
2R
3R
4R
5R
6R
7R
8R
9R
8
1R
2R
3R
4R
5R
6R
7R
8R
9R
IDT7130/
IDT7140
P48-1
&
9
IDT7130/40
J52-1
10
11
12
13
14
15
16
17
18
C48-2
52-PIN PLCC
TOP VIEW (3)
DIP
TOP
VIEW (3)
I/O0L
I/O1L
I/O2L
I/O3L
I/O0L
I/O1L
I/O2L
I/O3L 19
I/O4L 20
I/O5L 21
I/O6L 22
I/O7L 23
GND 24
32 I/O7R
31 I/O6R
30 I/O5R
29 I/O4R
28 I/O3R
27 I/O2R
26 I/O1R
25 I/O0R
N/C
I/O7R
21 22 23 24 25 26 27 28 29 30 31 32 33
2689 drw 04
2689 drw 02
INDEX
INDEX
OE
6
5
4
3
2
48 47 46 45 44 43
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
L
48
47
46
OE
R
1
A
0R
A
1L
2L
3L
4L
5L
6L
7L
8L
9L
7
42
41
40
39
38
37
36
35
34
33
32
31
A
A
A
A
A
A
A
0L
1L
2L
3L
4L
5L
6L
A
A
A
A
A
A
A
0R
A
A
A
A
A
A
A
A
8
A1R
1R
2R
3R
4R
5R
6R
A
2R
3R
9
45
44
43
42
41
40
39
38
37
36
35
34
33
10
11
12
13
14
15
16
17
18
A
IDT7130/40
L48-1
&
IDT7130/40
A4R
A5R
A6R
PP64-1 & PN64-1
F48-1
64-PIN STQFP
64-PIN TQFP
TOP VIEW (3)
N/C
N/C
48-PIN LCC/ FLATPACK
TOP VIEW (3)
A
7R
8R
9R
A
A
A
7R
8R
9R
A
A
A
7L
8L
9L
A
I/O0L
I/O1L
I/O2L
A
N/C
I/O0L
I/O1L
I/O2L
N/C
N/C
I/O7R
I/O6R
I/O7R
I/O6R
19 20 21 22 23 24 25 26 27 28 29 30
2689 drw 05
2689 drw 03
NOTES:
1. All Vcc pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. This text does not indicate orientation of the actual part-marking.
6.01
2
IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
RECOMMENDED
DC OPERATING CONDITIONS
Symbol
Rating
Commercial
Military
Unit
(2)
Symbol
Parameter
Supply Voltage
Supply Voltage
Min. Typ. Max. Unit
VTERM
Terminal Voltage –0.5 to +7.0 –0.5 to +7.0
V
VCC
4.5
0
5.0
0
5.5
0
V
V
with Respect to
GND
GND
TA
Operating
Temperature
0 to +70
–55 to +125
°C
°C
°C
VIH
VIL
Input High Voltage
Input Low Voltage
2.2
–0.5(1)
—
—
6.0(2)
V
V
0.8
TBIAS
TSTG
Temperature
Under Bias
–55 to +125 –65 to +135
–55 to +125 –65 to +150
NOTES:
2689 tbl 02
1. VIL (min.) > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 0.5V.
Storage
Temperature
IOUT
DC Output
Current
50
50
mA
2689 tbl 01
NOTES:
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
1. StressesgreaterthanthoselistedunderABSOLUTEMAXIMUMRATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
abovethoseindicatedintheoperationalsectionsofthespecificationisnot
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. VTERM must not exceed Vcc + 0.5 for more than 25% of the cycle time
or10nsmaximum, andislimitedto<20mAfortheperiodofVTERM> Vcc
+ 0.5V.
Ambient
Grade
Military
Commercial
Temperature
–55°C to +125°C
0°C to +70°C
GND
0V
VCC
5.0V ± 10%
5.0V ± 10%
0V
2689 tbl 03
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (VCC = 5.0V ± 10%)
7130SA
7130LA
7140SA
7140LA
Symbol
Parameter
Test Conditions
VCC = 5.5V,
Min.
Max.
Max.
Max.
Unit
|lLl|
Input Leakage
Current(1)
—
10
—
5
µA
VIN = 0V to VCCIN = GND to VCC
|lLO|
Output Leakage
Current(1)
VCC = 5.5V,
—
10
—
5
µA
CE = VIH, VOUT = 0V to VCCC
VOL
VOL
Output Low Voltage
(l/O0-l/O7)
lOL = 4mA
lOL= 16mA
—
—
0.4
0.5
—
—
—
0.4
0.5
—
V
V
Open Drain Output
Low Voltage (BUSY, INT)
lOL = 16mA
VOH
Output High Voltage
lOH = -4mA
2.4
2.4
V
NOTE:
2689 tbl 04
1. At Vcc < 2.0V leakages are undefined.
CAPACITANCE(1)
(TA = +25°C, f = 1.0MHz) TQFP ONLY(3)
Symbol
CIN
COUT
Parameter
Input Capacitance
Output Capacitance
Conditions(2) Max. Unit
VIN = 3dV
VIN = 3dV
9
10
pF
pF
2689 tbl 05
NOTES:
1. This parameter is determined by device characterization but is not
production tested.
2. 3dv references the interpolated capacitance when the input and
output signals switch from 0V to 3V or from 3V to 0V.
3. 11pF max. for other packages.
6.01
3
IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1,6) (VCC = 5.0V ± 10%)
7130X20(2) 7130X25(3) 7130X35 7130X55 7130X100
7140X25(3) 7140X35 7140X55 7140X100
Symbol
Parameter
Test Conditions
Version Typ. Max. Typ. Max. Typ. Max. Typ. Max. Typ. Max. Unit
ICC
Dynamic Operating
Current (Both Ports
Active)
CEL and CER = VIL, MIL.
Outputs open,
SA
LA
—
—
—
—
110 280 110 230 110 190 110 190 mA
110 220 110 170 110 140 110 140
(4)
f = fMAX
COM'L. SA 110 250 110 220 110 165 110 155 110 155
LA 110 200 110 170 110 120 110 110 110 110
ISB1
ISB2
Standby Current
(Both Ports - TTL
Level Inputs)
CEL and CER = VIH, MIL.
f = fMAX
SA
LA
—
—
—
—
65
45
30
30
30
30
80
60
65
45
25
25
25
25
80
60
65
45
20 65
20 45
20 65
20 35
20 65
20 45
20 55
20 35
mA
(4)
COM'L. SA 30
LA 30
Standby Current
(One Port - TTL
Level Inputs)
CE"A" = VIL and
MIL.
SA
LA
—
—
—
—
65 160
65 125
50 150
50 115
50 125
40 125 40 125 mA
40 90 40 90
40 110 40 110
(7)
CE"B" = VIH
Active Port Outputs COM'L. SA 65 165 65 150
(4)
Open, f = fMAX
LA 65 125 65 115
50
90
40 75
40 75
ISB3
ISB4
Full Standby Current CEL and
MIL.
SA
LA
—
—
—
—
1.0 30
0.2 10
1.0 30
0.2 10
1.0 15
1.0 30
0.2 10
1.0 15
1.0 30
0.2 10
1.0 15
mA
(Both Ports - All
CER > VCC -0.2V,
CMOS Level Inputs
VIN > VCC -0.2V or COM'L. SA 1.0 15 1.0 15
VIN < 0.2V,f = 0(5)
LA 0.2
5
0.2
5
0.2
4
0.2
4
0.2
4
Full Standby Current CE"A" < 0.2V and
(One Port - All
CE"B" > VCC -0.2V(7)
CMOS Level Inputs) VIN > VCC -0.2V or COM'L. SA 60 155 60 145
MIL.
SA
LA
—
—
—
—
60 155
60 115
45 145
45 105
45 110
40 110 40 110 mA
40 85 40 80
40 100 40 95
40 70 40 70
VIN < 0.2V,
LA 60 115 60 105
45
85
Active Port Outputs
(4)
Open, f = fMAX
NOTES:
2689 tbl 06
1. 'X' in part numbers indicates power rating (SA or LA).
2. Com'l Only, 0°C to +70°C temperature range. PLCC and TQFP packages.
3. Not available in DIP packages.
4. At f = fMax, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC TEST CONDITIONS”
of input levels of GND to 3V.
5. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
6. Vcc = 5V, TA=+25°C for Typ and is not production tested. Vcc DC = 100 mA (Typ.)
7. Port "A" may be either left or right port. Port "B" is opposite from port "A".
DATA RETENTION CHARACTERISTICS (LA Version Only)
lDT7130LA/IDT7140LA
Test Conditions
Symbol
VDR
Parameter
Min.
2.0
—
Typ.(1)
—
Max.
—
Unit
V
VCC for Data Retention
Data Retention Current
Mil.
ICCDR
100
100
—
4000
1500
—
µA
µA
ns
VCC = 2.0V, CE> VCC -0.2V
VIN > VCC -0.2V or VIN < 0.2V
Com’l.
—
(3)
tCDR
Chip Deselect to Data
Retention Time
Operation Recovery
Time
0
(2)
(3)
tR
tRC
—
—
ns
2689 tbl 07
NOTES:
1. VCC = 2V, TA = +25°C, and is not production tested.
2. tRC = Read Cycle Time
3. This parameter is guaranteed but not production tested.
6.01
4
IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DATA RETENTION WAVEFORM
DATA RETENTION MODE
VCC
VDR
≥
2.0V
4.5V
4.5V
tCDR
t
R
VDR
CE
VIH
VIH
2692 drw 06
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
5ns
1.5V
1.5V
Figures 1, 2, and 3
2689 tbl 08
5V
5V
1250Ω
1250Ω
DATA OUT
DATA OUT
775Ω
30pF*
775Ω
5pF*
(*100pF for 55 and
100ns versions)
Figure 1. Output Test Load
Figure 2. Output Test Load
(for tHZ, tLZ, tWZ, and tOW)
* including scope and jig
5V
270Ω
BUSY or INT
30pF*
*100pF for 55 and 100ns versions
2689 drw 07
Figure 3. BUSY and INT
AC Output Test Load
6.01
5
IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(3)
7130X20(2) 7130X25(5) 7130X35
7140X25(5) 7140X35
7130X55
7140X55
7130X100
7140X100
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Read Cycle
tRC
tAA
tACE
tAOE
tOH
tLZ
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Output Hold From Address Change
Output Low-Z Time(1,4)
Output High-Z Time(1,4)
Chip Enable to Power Up Time(4)
Chip Disable to Power Down Time(4)
20
—
—
—
20
20
11
—
—
10
25
—
—
—
3
—
25
25
12
—
—
10
35
—
—
—
3
—
35
35
20
—
—
15
55
—
—
—
3
—
55
55
25
—
—
25
100
—
—
—
10
5
—
ns
100 ns
100 ns
40
—
—
40
ns
ns
ns
ns
3
0
0
0
5
tHZ
—
0
—
—
—
—
tPU
tPD
—
0
—
0
—
0
—
0
—
ns
ns
—
20
—
25
—
35
—
50
—
50
NOTES:
2689 tbl 09
1. Transition is measured ±500mV from Low or High-impedance voltage Output Test Load (Figure 2).
2. Com'l Only, 0°C to +70°C temperature range. PLCC and TQFP package.
3. “X” in part numbers indicates power rating (SA or LA).
4. This parameter is guaranteed by device characterization, but is not production tested.
5. Not available in DIP packages.
TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE(1)
tRC
ADDRESS
tAA
tOH
tOH
PREVIOUS DATA VALID
DATA VALID
DATAOUT
BUSYOUT
2689 drw 08
(2,3)
t
BDD
NOTES:
1. R/W = VIH, CE = VIL, and is OE = VIL. Address is valid prior to the coincidental with CE transition Low.
2. tBDD delay is required only in the case where the opposite port is completing a write operation to the same the
address location. For simultaneous read operations, BUSY has no relationship to valid output data.
3. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.
6.01
6
IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE(3)
t
ACE
(4)
t
HZ (2)
tAOE
t
HZ(2)
(1)
t
LZ
VALID DATA
DATAOUT
(1)
PD(4)
t
LZ
t
t
PU
ICC
CURRENT
50%
50%
I
SS
2689 drw 09
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is deaserted first, OE or CE.
3. R/W = VIH and the address is valid prior to or coincidental with CE transition Low.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(5)
(2)
(6)
7130X20
7130X25
7130X35
7130X55
7140X55
7130X100
7140X100
(6)
7140X25
7140X35
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Write Cycle
tWC
tEW
tAW
tAS
tWP
tWR
tDW
tHZ
Write Cycle Time(3)
20
15
15
0
15
0
10
—
0
—
0
—
—
—
—
—
—
—
10
—
10
—
25
20
20
0
15
0
12
—
0
—
0
—
—
—
—
—
—
—
10
—
10
—
35
30
30
0
25
0
15
—
0
—
0
—
—
—
—
—
—
—
15
—
15
—
55
40
40
0
30
0
20
—
0
—
0
—
—
—
—
—
—
—
25
—
25
—
100
90
90
0
55
0
40
—
0
—
0
—
—
—
—
—
—
—
40
—
40
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Enable to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
Write Pulse Width(4)
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time(1)
tDH
Data Hold Time
tWZ
tOW
Write Enabled to Output in High-Z(1)
Output Active From End-of-Write(1)
ns
ns
NOTES:
2689 tbl 10
1. Transition is measured ±500mV from Low or High-impedance voltage with Output Test Load (Figure 2). This parameter is guaranteed by
device characterization but is not production tested.
2. 0°C to +70°C temperature range only, PLCC and TQFP packages.
3. For MASTER/SLAVE combination, tWC = tBAA + tWP, since R/W = VIL must occur after tBAA.
4. If OE is low during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off
data to be placed on the bus for the required tDW. If OE is High during a R/W controlled write cycle, this requirement does not apply and the
write pulse can be as short as the specified tWP.
5. “X” in part numbers indicates power rating (SA or LA).
6. Not available in DIP packages.
6.01
7
IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 1, (R/W CONTROLLED TIMING)(1,5,8)
tWC
ADDRESS
OE
(7)
tHZ
tAW
CE
(7)
tHZ
(3)
(2)
(6)
tAS
tWP
tWR
R/W
(7)
tOW
tWZ
(4)
(4)
DATA OUT
DATA IN
tDW
tDH
2689 drw 10
TIMING WAVEFORM OF WRITE CYCLE NO. 2, (CE CONTROLLED TIMING)(1,5)
tWC
ADDRESS
CE
t
AW
(6)
(3)
WR
(2)
tAS
tEW
t
R/W
t
DW
tDH
DATA IN
2689 drw 11
NOTES:
1. R/W or CE must be High during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of CE = VIL and R/W = VIL.
3. tWR is measured from the earlier of CE or R/W going High to the end of the write cycle.
4. During this period, the l/O pins are in the output state and input signals must not be applied.
5. If the CE Low transition occurs simultaneously with or after the R/W Low transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal (CE or R/W) is asserted last.
7. This parameter is determined be device characterization, but is not production tested. Transition is measured +/- 500mV from steady state
with the Output Test Load (Figure 2).
8. If OE is low during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off
and data to be placed on the bus for the required tDW. If OE is High during a R/W controlled write cycle, this requirement does not apply and
the write pulse can be as short as the specified tWP.
6.01
8
IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(7)8M824S258M824S30 7132158M824S4
7130X20(1) 7130X25(9)
7140X25(9)
7130X35
7130X55 7130X100
7140X35
7140X55 7140X100
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Unit
Busy Timing (For Master lDT7130 Only)
tBAA
tBDA
tBAC
tBDC
tWH
BUSY Access Time from Address
BUSY Disable Time from Address
BUSY Access Time from Chip Enable
BUSY Disable Time from Chip Enable
Write Hold After BUSY(6)
—
—
—
—
12
—
—
5
20
20
20
20
—
40
30
—
25
—
—
—
40
30
—
—
—
—
15
—
—
5
20
20
20
20
—
50
35
—
35
—
—
—
50
35
—
—
—
—
20
—
—
5
20
20
20
20
—
60
35
—
35
—
—
—
60
35
—
—
—
—
20
—
—
5
30
30
30
30
—
80
55
—
50
—
—
—
80
55
—
—
—
—
20
—
—
5
50
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
50
50
—
tWDD
tDDD
tAPS
tBDD
Write Pulse to Data Delay(2)
120
100
—
Write Data Valid to Read Data Delay(2)
Arbitration Priority Set-up Time(3)
BUSY Disable to Valid Data(4)
—
5
—
5
—
5
—
5
—
5
65
Busy Timing (For Slave IDT7140 Only)e
tWB
Write to BUSY Input(5)
Write Hold After BUSY(6)
Write Pulse to Data Delay(2)
Write Data Valid to Read Data Delay(2)
0
0
0
0
0
—
—
ns
ns
ns
ns
tWH
12
—
—
15
—
—
20
—
—
20
—
—
20
—
—
tWDD
tDDD
120
100
NOTES:
2689 tbl 11
1. Com'l Only, 0°C to +70°C temperature range. PLCC and TQFP packages only.
2. Port-to-port delay through RAM cells from the writing port to the reading port, refer to “Timing Waveform of Write with Port-to-Port Read and BUSY."
3. To ensure that the earlier of the two ports wins.
4. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual), or tDDD – tDW (actual).
5. To ensure that a write cycle is inhibited on port 'B' during contention on port 'A'.
6. To ensure that a write cycle is completed on port 'B' after contention on port 'A'.
7. “X” in part numbers indicates power rating (SA or LA).
8. Not available in DIP packages.
(2,3,4)
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ AND BUSY
t
WC
ADDR’A’
MATCH
t
WP
R/W’A’
t
DW
t
DH
DATAIN’A’
VALID
(1)
t
APS
ADDR’B’
MATCH
t
BDD
tBDA
BUSY’B’
t
WDD
DATAOUT’B’
VALID
t
DDD
NOTES:
1. To ensure that the earlier of the two ports wins. tBDD is ignored for slave (IDT7140).
2. CEL = CER = VIL.
2689 drw 12
3. OE = VIL for the reading port.
4. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port "B" is opposite from port "A".
6.01
9
IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE WITH BUSY(3)
tWP
R/W'A'
tWB
BUSY'B'
R/W'B'
(1)
tWH
(2)
2689 drw 13
NOTES:
1. tWH must be met for both BUSY Input (IDT7140, slave) or Output (IDT7130 master).
2. BUSY is asserted on port 'B' blocking R/W'B', until BUSY'B' goes High.
3. All timing is the same for the left and right ports. Port 'A' may be either the left or right
port. Port "B" is opposite from port "A".
TIMING WAVEFORM OF BUSY ARBITRATION CONTROLLED BY CETIMING (1)
ADDR
ADDRESSES MATCH
'A' AND 'B'
CE'B'
(2)
tAPS
CE'A'
tBAC
t
BDC
BUSY'A'
2689 drw 14
TIMING WAVEFORM OF BUSY ARBITRATION CONTROLLED BY ADDRESS MATCH TIMING (1)
tRC OR tWC
ADDR'A'
ADDR'B'
BUSY'B'
ADDRESSES MATCH
ADDRESSES DO NOT MATCH
(2)
APS
t
tBAA
tBDA
2689 drw 15
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. If tAPS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be
asserted (7130 only).
6.01
10
IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(2) 8M824S25
8M824S308M824S35
7130X100
7140X100
7130X20(1)
7130X25(3)
7140X25(3)
7130X35
7140X35
7130X55
7140X55
Symbol
Parameter
Min. Max.
Min.
Max.
Min. Max.
Min.
Max.
Min. Max.
Unit
Interrupt Timing
tAS
Address Set-up Time
0
0
—
—
20
20
0
0
—
—
25
25
0
0
—
—
25
25
0
0
—
—
45
45
0
0
—
—
60
60
ns
ns
ns
tWR
tINS
tINR
Write Recovery Time
Interrupt Set Time
—
—
—
—
—
—
—
—
—
—
Interrupt Reset Time
ns
2689 tbl 12
NOTES:
1. 0°C to +70°C temperature range only, PLCC and TQFP packages.
2. “X” in part numbers indicates power rating (SA or LA).
3. Not available in DIP packages .
TIMING WAVEFORM OF INTERRUPT MODE
INT SET:
t
WC
INTERRUPT ADDRESS(2)
ADDR'A'
(4)
WR
t
AS (3)
t
R/W'A'
INT'B'
t
INS(3)
2689 drw 16
INT CLEAR:
ADDR'B'
t
RC
INTERRUPT CLEAR ADDRESS
t
AS (3)
OE'B'
INT'B'
t
INR (3)
2689 drw 17
NOTES:.
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. See Interrupt Truth Table.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
6.01
11
IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLES
TABLE I — NON-CONTENTION
READ/WRITE CONTROL(4)
Left or Right Port(1)
R/W CE OE
D0–7
Function
X
H
X
Z
Port Disabled and in Power-
Down Mode, ISB2 or ISB4
X
H
X
Z
CER = CEL = VIH, Power-Down
Mode, ISB1 or ISB3
L
H
H
L
L
L
X
L
DATAIN Data on Port Written Into Memory(2)
DATAOUT Data in Memory Output on Port(3)
H
Z
High Impedance Outputs
NOTES:
2689 tbl 13
1. A0L – A10L ≠ A0R – A10R.
2. If BUSY = L, data is not written.
3. If BUSY = L, data may not be valid, see tWDD and tDDD timing.
4. 'H' = VIH, 'L' = VIL, 'X' = DON’T CARE, 'Z' = HIGH IMPEDANCE
TABLE II — INTERRUPT FLAG(1,4)
Left Port
Right Port
R/WL
CEL
L
OEL
X
A9L – A0L
INTL
X
R/WR
CER
X
OER
X
A9L – A0R
INTR
L(2)
H(3)
X
Function
L
X
X
X
3FF
X
X
X
L
X
Set Right INTR Flag
Reset Right INTR Flag
Set Left INTL Flag
Reset Left INTL Flag
X
X
X
L
L
3FF
3FE
X
X
X
X
L(3)
H(2)
L
X
L
L
3FE
X
X
X
X
NOTES:
2689 tbl 14
1. Assumes BUSYL = BUSYR = VIH
2. If BUSYL = VIL, then No Change.
3. If BUSYR = VIL, then No Change.
4. 'H' = HIGH,' L' = LOW,' X' = DON’T CARE
TABLE III — ADDRESS BUSY ARBITRATION
Inputs
Outputs
A0L-A9L
(1)
(1)
CEL
CER
X
A0R-A9R
NO MATCH
MATCH
BUSYL
BUSYR
Function
Normal
X
H
H
H
H
H
X
Normal
X
L
H
MATCH
H
H
Normal
Write Inhibit(3)
L
MATCH
(2)
(2)
NOTES:
2689 tbl 15
1. Pins BUSYL and BUSYR are both outputs for IDT7130 (master). Both are
inputsforIDT7140(slave).BUSYX outputsontheIDT7130areopendrain,
notpush-pulloutputs. Onslavesthe BUSYX inputinternallyinhibitswrites.
2. 'L' if the inputs to the opposite port were stable prior to the address and
enable inputs of this port. 'H' if the inputs to the opposite port became
stable after the address and enable inputs of this port. If tAPS is not met,
either BUSYL or BUSYR = Low will result. BUSYL and BUSYR outputs can
not be low simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are
driving Low regardless of actual logic level on the pin. Writes to the right
port are internally ignored when BUSYR outputs are driving Low regard-
less of actual logic level on the pin.
6.01
12
IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTIONAL DESCRIPTION
The Busy outputs on the IDT7130 RAM (Master) are open
drain type outputs and require open drain resistors to operate.
If these RAMs are being expanded in depth, then the Busy
indication for the resulting array does not require the use of an
external AND gate.
The IDT7130/IDT7140 provides two ports with separate con-
trol, address and I/O pins that permit independent access for
reads or writes to any location in memory. The IDT7130/
IDT7140 has an automatic power down feature controlled by
CE.TheCEcontrolson-chippowerdowncircuitrythatpermits
the respective port to go into a standby mode when not
selected (CE = VIH). When a port is enabled, access to the
entire memory array is permitted.
WIDTH EXPANSION WITH BUSY LOGIC
MASTER/SLAVE ARRAYS
When expanding an RAM array in width while using busy
logic, one master part is used to decide which side of the RAM
array will receive a busy indication, and to output that indica-
tion. Any number of slaves to be addressed in the same
address range as the master, use the busy signal as a write
inhibit signal. Thus on the IDT7130/IDT7140 RAMs the Busy
pin is an output if the part is Master (IDT7130), and the Busy
pin is an input if the part is a Slave (IDT7140) as shown in
Figure 4.
INTERRUPTS
If the user chooses to use the interrupt function, a memory
location (mail box or message center) is assigned to each
port. The left port interrupt flag (INTL) is asserted when the
right port writes to memory location 3FE (HEX), where a write
is defined as the CE = R/W = VIL per the Truth Table. The left
port clears the interrupt by access address location 3FE
accesswhenCER =OER= VIL, R/W isa"don'tcare". Likewise,
therightportinterruptflag(INTR)isassertedwhentheleftport
writestomemorylocation3FF(HEX)andtocleartheinterrupt
flag (INTR), the right port must access the memory location
3FF. The message (8 bits) at 3FE or 3FF is user-defined,
since it is an addressable SRAM location. If the interrupt
function is not used, address locations 3FE and 3FF are not
used as mail boxes, but as part of the random access
memory. Refer to Table II for the interrupt operation.
CE
CE
5V
MASTER
Dual Port
RAM
SLAVE
Dual Port
RAM
5V
270Ω
BUSY (L)
BUSY (R)
BUSY (L) BUSY (R)
270Ω
CE
CE
MASTER
Dual Port
RAM
SLAVE
Dual Port
RAM
BUSY (L)
BUSY (L)
BUSY (R)
BUSY (R)
BUSY
R
BUSY
L
BUSY LOGIC
2689 drw 18
Busy Logic provides a hardware indication that both ports of
the RAM have accessed the same location at the same time.
It also allows one of the two accesses to proceed and signals
the other side that the RAM is “Busy”. The Busy pin can then
beusedtostalltheaccessuntiltheoperationon theotherside
iscompleted. Ifawriteoperationhasbeenattemptedfromthe
side that receives a busy indication, the write signal is gated
internally to prevent the write from proceeding.
The use of busy logic is not required or desirable for all
applications. In some cases it may be useful to logically OR
the busy outputs together and use any busy indication as an
interrupt source to flag the event of an illegal or illogical
operation. In slave mode the BUSYpin operates solely as a
write inhibit input pin. Normal operation can be programmed
by tying the BUSY pins High. If desired, unintended write
operations can be prevented to a port by tying the Busy pin for
that port Low.
Figure 4. Busy and chip enable routing for both width and depth
expansion with IDT7130 (Master) and IDT7140 (Slave) RAMs.
If two or more master parts were used when expanding in
width, a split decision could result with one master indicating
busy on one side of the array and another master indicating
busyononeothersideofthearray. Thiswouldinhibitthewrite
operations from one port for part of a word and inhibit the write
operations from the other port for the other part of the word.
The Busy arbitration, on a Master, is based on the chip enable
and address signals only. It ignores whether an access is a
read or write. In a master/slave array, both address and chip
enable must be valid long enough for a busy flag to be output
from the master before the actual write pulse can be initiated
with either the R/W signal or the byte enables. Failure to
observe this timing can result in a glitched internal write inhibit
signal and corrupted data in the slave.
6.01
13
IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
XXXX
A
999
A
A
Device Type Power Speed Package
Process/
Temperature
Range
Commercial (0°C to +70°C)
Blank
B
Military (–55°C to +125°C)
Compliant to MIL-STD-883, Class B
48-pin Plastic DIP (P48-1)
48-pin Sidebraze DIP (C48-2)
52-pin PLCC (J52-1)
P
C
J
48-pin LCC (L48-1)
L48
F
48-pin Ceramic Flatpack (F48-1)
64-pin TQFP (PN64-1)
64-pin STQFP (PP64-1)
PF
TF
20
25
35
55
100
Commercial PLCC and TQFP Only
LCC, PLCC, and TQFP Only
Speed in nanoseconds
Low Power
Standard Power
LA
SA
7130
7140
8K (1K x 8-Bit) MASTER Dual-Port RAM
8K (1K x 8-Bit) SLAVE Dual-Port RAM
2689 drw 19
6.01
14
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