IDT71256S70L32BG [IDT]
Standard SRAM, 32KX8, 70ns, CMOS, CQCC32, LCC-32;
| 型号： | IDT71256S70L32BG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Standard SRAM, 32KX8, 70ns, CMOS, CQCC32, LCC-32 静态存储器 内存集成电路 |
| 文件： | 总10页 (文件大小：108K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT71256S
IDT71256L
CMOS Static RAM
256K (32K x 8-Bit)
Description
Features
◆
High-speed address/chip select time
TheIDT71256isa262,144-bithigh-speedstaticRAMorganizedas
32K x 8. It is fabricated using IDT's high-performance, high-reliability
CMOStechnology.
– Military:25/35/45/55/70/85/100ns (max.)
– Industrial:25/35ns (max.)
– Commercial:20/25/35ns (max.)lowpoweronly
Low-power operation
Battery Backup operation – 2V data retention
Produced with advanced high-performance CMOS
technology
Input and output directly TTL-compatible
Available in standard 28-pin (300 or 600 mil) ceramic DIP,
28-pin (600 mil) plastic DIP, 28-pin (300 mil) SOJ and
32-pin LCC
Address access times as fast as 20ns are available with power
consumptionofonly350mW(typ.).Thecircuitalsooffersareducedpower
standbymode.WhenCSgoesHIGH,thecircuitwillautomaticallygotoand
remain in, a low-power standby mode as long as CS remains HIGH. In
thefullstandbymode,thelow-powerdeviceconsumeslessthan15µW,
typically. This capability provides significant system level power and
coolingsavings.Thelow-power(L)versionalsooffersabatterybackup
dataretentioncapabilitywherethecircuittypicallyconsumesonly5µW
whenoperatingoffa 2Vbattery.
◆
◆
◆
◆
◆
◆
Military product compliant to MIL-STD-883, Class B
TheIDT71256ispackagedina28-pin(300or600mil)ceramicDIP,
a 28-pin 300 mil SOJ, a 28-pin (600 mil) plastic DIP, and a 32-pin LCC
providinghighboardlevelpackingdensities.
TheIDT71256militaryRAMismanufacturedincompliancewiththe
latestrevisionofMIL-STD-883,ClassB,makingitideallysuitedtomilitary
temperatureapplicationsdemandingthehighestlevelofperformanceand
reliability.
FunctionalBlockDiagram
A0
VCC
GND
262,144 BIT
MEMORY ARRAY
ADDRESS
DECODER
A14
I/O
0
I/O CONTROL
INPUT
DATA
CIRCUIT
I/O7
,
CS
OE
CONTROL
CIRCUIT
2946 drw 01
WE
NOVEMBER 2008
1
©2008IntegratedDeviceTechnology,Inc.
DSC-2946/11
IDT71256S/L
CMOS Static RAM 256K (32K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
PinConfigurations
Truth Table(1)
WE
CS
OE
X
X
H
L
I/O
Function
Standby (ISB)
1
V
WE
CC
28
27
26
25
24
A
A
A
A
A
A
A
A
A
A
I/O
I/O
I/O
14
12
X
H
High-Z
High-Z
High-Z
2
3
7
6
5
4
3
2
1
0
X
VHC
Standby (ISB1
Output Disabled
Read Data
)
A
A
13
8
4
H
L
L
L
5
A9
6
D28-3
P28-1
D28-1
SO28-5
23
22
A11
H
DOUT
7
OE
A10
L
X
DIN
Write Data
8
21
20
9
2946 tbl 02
CS
I/O
I/O
I/O
I/O
NOTE:
10
11
12
13
14
19
18
7
1. H = VIH, L = VIL, X = Don't care.
0
6
17
16
15
1
5
2
4
GND
I/O
3
AbsoluteMaximumRatings(1)
2946 drw 02
DIP/SOJ
Top View
Symbol
Rating
Com'l.
Ind.
Mil.
Unit
VTERM
Terminal Voltage -0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0
with Respect
to GND
V
-40 to +85 -55 to +125 oC
INDEX
Operating
Te mp e rature
0 to +70
TA
4
3
2
32 31
30
29
Te mp e rature
Under Bias
-55 to +125 -55 to +125 -65 to +135 oC
-55 to +125 -55 to +125 -65 to +150 oC
T
BIAS
1
5
6
7
8
9
A
A
A
A
A
A
A
6
5
4
3
2
1
0
A
A
A
8
28
27
26
9
Storage
Te mp e rature
11
TSTG
NC
25
24
OE
L32-1
Power
P
T
1.0
50
1.0
50
1.0
50
W
10
11
12
13
A10
Dissipation
23
22
21
CS
IOUT
DC Output Current
mA
NC
I/O
I/O
I/O
7
2946 tbl 03
0
6
NOTE:
18 19 20
,
15 16 17
14
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
,
2946 drw 03
32-PinLCC
Top View
Capacitance (TA = +25°C, f = 1.0MHz)
PinDescriptions
Symbol
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
Max.
Unit
Name
Description
CIN
VIN = 0V
11
pF
A0
- A14
Address Inputs
Data Input/Output
Chip Select
Write Enable
Output Enable
Ground
CI/O
VOUT = 0V
11
pF
I/O0
- I/O
7
2946 tbl 04
NOTE:
CS
1. This parameter is determined by device characterization, but is not production
tested.
WE
OE
GND
VCC
Power
2946 tbl 01
2
IDT71256S/L
CMOS Static RAM 256K (32K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
RecommendedDCOperating
Conditions
RecommendedOperating
TemperatureandSupplyVoltage
Grade
Temperature
-55OC to +125OC
-40OC to +85OC
0OC to +70OC
GND
Vcc
Symbol
Parameter
Min.
4.5
0
Typ.
Max.
5.5
0
Unit
V
Military
0V
5V ± 10%
5V ± 10%
5V ± 10%
VCC
Supply Voltage
5.0
Industrial
0V
GND Ground
0
V
____
Commercial
0V
V
IH
Input High Voltage
Input Low Voltage
2.2
6.0
0.8
V
2946 tbl 05
(1)
____
VIL
-0.5
V
2946 tbl 06
NOTE:
1. VIL (min.) = –3.0V for pulse width less than 20ns, once per cycle.
DC Electrical Characteristics(1,2) (VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC - 0.2V)
71256S/L20
71256S/L25
71256S/L35
71256S/L45
Power Com'l. Mil. Com'l Mil. Com'l. Mil. Com'l. Mil.
Symbol
Parameter
Dynamic Operating Current
& Ind
& Ind
& Ind
Unit
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
ICC
mA
S
L
S
L
S
L
150
130
20
140
120
20
135
115
20
CS < VIL, Outputs Open
(2)
135
125
115
V
CC = Max., fMAX
____
____
____
ISB
Standby Power Supply Current
mA
(TTL Level), CS > VIH, VCC = Max.,
(2)
3
3
3
3
3
3
Outputs Open, f = fMAX
____
____
____
ISB1
Full Standby Power Supply Current
mA
20
20
20
(CMOS Level), CS > VHC
,
0.6
0.6
1.5
0.6
1.5
1.5
VCC = Max., f = 0
2946 tbl 07
71256S/L55
71256S/L70
71256S/L85
71256S/L100
Symbol
Parameter
Power
Mil.
135
115
20
Mil.
135
115
20
Mil.
135
115
20
Mil.
135
115
20
Unit
ICC
Dynamic Operating Current
CS < VIL, Outputs Open
S
L
S
L
S
L
mA
(2)
V
CC = Max., fMAX
ISB
Standby Power Supply Current
mA
(TTL Level), CS > VIH, VCC = Max.,
(2)
3
3
3
3
Outputs Open, f = fMAX
ISB1
Full Standby Power Supply Current
mA
20
20
20
20
(CMOS Level), CS > VHC
,
1.5
1.5
1.5
1.5
V
CC = Max., f = 0
2946 tbl 08
NOTES:
1. All values are maximum guaranteed values.
2. fMAX = 1/tRC, all address inputs are cycling at fMAX; f = 0 means no address pins are cycling.
6.42
3
IDT71256S/L
CMOS Static RAM 256K (32K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
AC Test Conditions
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
5ns
1.5V
Input Timing Reference Levels
Output Reference Levels
AC Test Load
1.5V
See Figures 1 and 2
2946 tbl 09
5V
5V
480Ω
480Ω
OUT
DATA
OUT
DATA
30pF*
5pF*
255Ω
255Ω
,
,
2946 drw 04
2946 drw 05
Figure 1. AC Test Load
Figure 2. AC Test Load
(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)
*Includes scope and jig capacitances
DC Electrical Characteristics (VCC = 5.0V ± 10%)
IDT71256S
IDT71256L
Typ.
Symbol
|ILI
Parameter
Test Conditions
MIL.
Min.
Typ.
Max.
Min.
Max.
Unit
____
____
____
____
____
____
____
____
Input Leakage Current
|
V
CC = Max.,
10
5
5
2
µA
V
IN = GND to VCC
COM"L & IND.
____
____
____
____
____
____
____
____
|ILO
|
Output Leakage Current
Output Low Voltage
V
CC = Max., CS = VIH
,
MIL.
COM"L & IND.
10
5
5
2
µA
V
V
OUT = GND to VCC
____
____
____
____
____
____
____
____
____
____
I
OL = 8mA, VCC = Min.
OL = 10mA, VCC = Min.
OH = -4mA, VCC = Min.
0.4
0.4
VOL
I
0.5
0.5
____
____
VOH
Output High Voltage
I
2.4
2.4
V
2946 tbl 10
Data Retention Characteristics Over All Temperature Ranges
(L Version Only) (VLC = 0.2V, VHC = VCC - 0.2V)
Typ.(1)
Max.
VCC @
VCC @
Symbol
Parameter
Test Condition
Min.
2.0V
3.0V
2.0V
3.0V
Unit
V
____
____
____
____
____
V
DR
V
CC for Data Retention
2.0
____
____
____
____
____
____
Data Retention Current
MIL.
COM'L. & IND.
500
120
800
200
µA
ICCDR
____
____
____
____
____
____
t
CDR
Chip Deselect to Data
Retention Time
0
ns
CS > VHC
____
____
(3)
(2)
Operation Recovery Time
ns
tR
t
RC
2946 tbl 11
NOTES:
1. TA = +25°C.
2. tRC = Read Cycle Time.
3. This parameter is guaranteed by device characterization, but is not production tested.
4
IDT71256S/L
CMOS Static RAM 256K (32K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
Low VCC Data Retention Waveform
DATA
RETENTION
MODE
VCC
4.5V
4.5V
VDR ≥ 2V
tCDR
tR
CS
VIH
VIH
VDR
2946 drw 06
AC Electrical Characteristics (VCC = 5.0V ± 10%, All Temperature Ranges)
71256S25
71256L25
71256S35
71256L35
71256S45(3)
71256L45(3)
71256L20(1)
Symbol
Parameter
Unit
Min. Max.
Min.
Max.
Min.
Max.
Min. Max.
Read Cycle
____
____
____
____
t
RC
AA
ACS
Read Cycle Time
20
25
35
45
ns
ns
ns
ns
____
____
____
____
t
Address Access Time
20
25
35
45
____
____
____
____
t
Chip Select Access Time
20
25
35
45
____
____
____
____
(2)
CL Z
Chip Select to Output in Low-Z
Chip Deselect to Output in High-Z
Output Enable to Output Valid
Output Enable to Output in Low-Z
Output Disable to Output in High-Z
Output Hold from Address Change
5
5
5
5
t
____
____
____
____
(2)
10
11
15
20
ns
ns
ns
ns
ns
tCHZ
____
____
____
____
tOE
10
11
15
20
____
____
____
____
(2)
(2)
2
2
5
2
2
5
2
2
5
0
tOLZ
____
8
10
15
20
tOHZ
____
____
____
____
tOH
5
Write Cycle
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
CW
AW
AS
WP
WR
DW
Write Cycle Time
20
15
15
0
25
20
20
0
35
30
30
0
45
40
40
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Chip Select to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
t
t
t
Write Pulse Width
15
0
20
0
30
0
35
0
t
Write Recovery Time
t
Data to Write Time Overlap
Write Enable to Output in High-Z
Data Hold from Write Time
Output Active from End-of-Write
11
13
15
20
____
____
____
____
(2)
WHZ
10
11
15
20
t
____
____
____
____
tDH
0
5
0
5
0
5
0
5
____
____
____
____
(2)
OW
ns
t
2946 tbl 12
NOTES:
1. 0° to +70°C temperature range only.
2. This parameter is guaranteed by device characterization, but is not production tested.
3. –55°C to +125°C temperature range only.
6.42
5
IDT71256S/L
CMOS Static RAM 256K (32K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
AC Electrical Characteristics (VCC = 5.0V ± 10%, Military Temperature Ranges)
71256S55(1)
71256L55(1)
71256S70(1)
71256L70(1)
71256S85(1)
71256L85(1)
71256S100(1)
71256L100(1)
Symbol
Parameter
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Read Cycle
____
____
____
____
t
RC
AA
ACS
Read Cycle Time
55
70
85
100
ns
ns
ns
ns
____
____
____
____
t
Address Access Time
55
70
85
100
____
____
____
____
t
Chip Select Access Time
55
70
85
100
____
____
____
____
(2)
CL Z
Chip Select to Output in Low-Z
Chip Deselect to Output in High-Z
Output Enable to Output Valid
Output Enable to Output in Low-Z
Output Disable to Output in High-Z
Output Hold from Address Change
5
5
5
5
t
(2)
____
____
____
____
25
30
35
40
ns
ns
ns
ns
ns
tCHZ
____
____
____
____
tOE
25
30
35
40
____
____
____
____
(2)
(2)
0
0
5
0
0
5
0
0
tOLZ
____
____
25
30
35
40
tOHZ
____
____
____
____
tOH
5
5
Write Cycle
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
CW
AW
AS
WP
WR
DW
Write Cycle Time
55
50
50
0
70
60
60
0
85
70
70
0
100
80
80
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Chip Select to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
t
t
t
Write Pulse Width
40
0
45
0
50
0
55
0
t
Write Recovery Time
t
Data to Write Time Overlap
Write Enable to Output in High-Z
Data Hold from Write Time (WE)
25
30
35
40
____
____
____
____
(2)
WHZ
25
30
35
40
t
____
____
____
____
tDH
0
5
0
5
0
5
0
5
____
____
____
____
(2)
OW
Output Active from End-of-Write
ns
t
2946 tbl 13
NOTES:
1. -55° to +125°C temperature range only.
2. This parameter is guaranteed by device characterization, but is not production tested.
6
IDT71256S/L
CMOS Static RAM 256K (32K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
Timing Waveform of Read Cycle No. 1(1)
tRC
ADDRESS
tOH
t
AA
OE
t
OE
(5)
OLZ
(5)
(5)
t
OHZ
t
CS
t
ACS
t
CHZ
(5)
CLZ
t
DATAOUT
2946 drw 07
Timing Waveform of Read Cycle No. 2(1,2,4)
tRC
ADDRESS
t
AA
t
OH
t
OH
DATAOUT
,
2946 drw 08
Timing Waveform of Read Cycle No. 2(1,3,4)
CS
t
ACS
(5)
CHZ
t
(5)
CLZ
t
DATAOUT
2946 drw 09
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected, CS is LOW.
3. Address valid prior to or coincident with CS transition LOW.
4. OE is LOW.
5. Transition is measured ±200mV from steady state.
6.42
7
IDT71256S/L
CMOS Static RAM 256K (32K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,4,6)
tWC
ADDRESS
(5)
OHZ
t
OE
tAW
CS
(6)
WR
t
WP
t
tAS
WE
(5)
WZ
t
t
OW
(3)
(3)
OUT
DATA
DW
DH
t
t
IN
DATA
2946 drw 10
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,2,4)
WC
t
ADDRESS
AW
t
CS
(6)
t
AS
tCW
tWR
WE
tDW
tDH2
IN
DATA
2946 drw 11
NOTES:
1. A write occurs during the overlap of a LOW CS and a LOW WE.
2. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle.
3. During this period, I/O pins are in the output state so that the input signals must not be applied.
4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
5. Transition is measured ±200mV from steady state.
6. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ +tDW) to allow the I/O drivers to turn off and data to be placed
on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse width can be as short
as the specified tWP. For a CS controlled write cycle, OE may be LOW with no degradation to tCW.
8
IDT71256S/L
CMOS Static RAM 256K (32K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
Ordering Information — Commercial & Industrial
Ordering Information — Military
6.42
9
IDT71256S/L
CMOS Static RAM 256K (32K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
DatasheetDocumentHistory
11/4/99
Updatedtonewformat
Pp. 1–5, 9
Pg. 1
Pg. 2
AddedIndustrialTemperatureRangeofferings
Removed30,120,and150ns militaryand45ns commercialspeedgradeofferings.
RemovedP28-2package fromDIP/SOJ TopView
Removed30nsand45ns(Commercialonly)speedgradeofferingsfromDCElectricaltable
Revisednotesandfootnotes
Pg. 3
Pg. 5
Pg. 6
Removed30nsspeedgradeofferingfromACElectricaltable
Revisednotesandfootnotes
ExpressedMilitaryTemperaturerangeonACElectricaltable
Revisednotesandfootnotes
Pg. 8
Pg. 9
Pg. 10
RemovedNote1andrenumberednotesandfootnotes
RevisedOrderingInformationandpresentedbytemperaturerangeoffering
AddedDatasheetDocumentHistory
08/09/00
02/01/01
Notrecommendedfornewdesigns
Remove"Notrecommendedfornewdesigns"
11/15/06
11/01/08
Pg.3
Changed powerlimitsforcommercialandindustrial.RefertoPCNSR-0602-03. AddedRestrictedhazardous
substancedevcetoorderinginformation.
Pg.2,9
Corrected typo on pin 21 in 32-Pin LCC diagram. Updated the ordering information by removing the
"IDT"notation.
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10
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