IDT71256L25TDB 概述
CMOS STATIC RAM 256K (32K x 8-BIT) CMOS静态RAM 256K ( 32K ×8位) SRAM
IDT71256L25TDB 规格参数
是否无铅: | 含铅 | 是否Rohs认证: | 不符合 |
生命周期: | Active | 零件包装代码: | DIP |
包装说明: | DIP, DIP28,.3 | 针数: | 28 |
Reach Compliance Code: | not_compliant | ECCN代码: | 3A001.A.2.C |
HTS代码: | 8542.32.00.41 | 风险等级: | 5.07 |
最长访问时间: | 25 ns | I/O 类型: | COMMON |
JESD-30 代码: | R-GDIP-T28 | JESD-609代码: | e0 |
长度: | 37.1475 mm | 内存密度: | 262144 bit |
内存集成电路类型: | STANDARD SRAM | 内存宽度: | 8 |
功能数量: | 1 | 端口数量: | 1 |
端子数量: | 28 | 字数: | 32768 words |
字数代码: | 32000 | 工作模式: | ASYNCHRONOUS |
最高工作温度: | 125 °C | 最低工作温度: | -55 °C |
组织: | 32KX8 | 输出特性: | 3-STATE |
可输出: | YES | 封装主体材料: | CERAMIC, GLASS-SEALED |
封装代码: | DIP | 封装等效代码: | DIP28,.3 |
封装形状: | RECTANGULAR | 封装形式: | IN-LINE |
并行/串行: | PARALLEL | 峰值回流温度(摄氏度): | 225 |
电源: | 5 V | 认证状态: | Not Qualified |
筛选级别: | MIL-STD-883 Class B | 座面最大高度: | 5.08 mm |
最大待机电流: | 0.0005 A | 最小待机电流: | 2 V |
子类别: | SRAMs | 最大压摆率: | 0.13 mA |
最大供电电压 (Vsup): | 5.5 V | 最小供电电压 (Vsup): | 4.5 V |
标称供电电压 (Vsup): | 5 V | 表面贴装: | NO |
技术: | CMOS | 温度等级: | MILITARY |
端子面层: | Tin/Lead (Sn/Pb) | 端子形式: | THROUGH-HOLE |
端子节距: | 2.54 mm | 端子位置: | DUAL |
处于峰值回流温度下的最长时间: | 20 | 宽度: | 7.62 mm |
Base Number Matches: | 1 |
IDT71256L25TDB 数据手册
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PDF下载IDT71256S
IDT71256L
CMOS STATIC RAM
256K (32K x 8-BIT)
Integrated Device Technology, Inc.
FEATURES:
• High-speed address/chip select time
DESCRIPTION:
— Military: 25/30/35/45/55/70/85/100/120/150ns (max.)
— Commercial: 20/25/35/45ns (max.) Low Power only.
• Low-power operation
The IDT71256 is a 262,144-bit high-speed static RAM
organized as 32K x 8. It is fabricated using IDT’s high-
performance, high-reliability CMOS technology.
• Battery Backup operation — 2V data retention
• Produced with advanced high-performance CMOS
technology
• Input and output directly TTL-compatible
• Available in standard 28-pin (300 or 600 mil) ceramic
DIP, 28-pin (600 mil) plastic DIP, 28-pin (300 mil) SOJ
and 32-pin LCC
Address access times as fast as 20ns are available with
power consumption of only 350mW (typ.). The circuit also
offers a reduced power standby mode. When CSgoes HIGH,
the circuit will automatically go to, and remain in, a low-power
standbymodeaslongasCSremainsHIGH. Inthefullstandby
mode, the low-power device consumes less than 15µW,
typically. This capability provides significant system level
power and cooling savings. The low-power (L) version also
offers a battery backup data retention capability where the
circuit typically consumes only 5µW when operating off a 2V
battery.
• Military product compliant to MIL-STD-883, Class B
The lDT71256 is packaged in a 28-pin (300 or 600 mil)
ceramic DIP, a 28-pin 300 mil J-bend SOlC, and a 28-pin (600
mil) plastic DIP, and 32-pin LCC providing high board-level
packing densities.
TheIDT71256militaryRAMismanufacturedincompliance
with the latest revision of MIL-STD-883, Class B, making it
ideally suited to military temperature applications demanding
the highest level of performance and reliability.
FUNCTIONAL BLOCK DIAGRAM
A0
VCC
GND
262,144 BIT
MEMORY ARRAY
ADDRESS
DECODER
A14
I/O 0
I/O CONTROL
INPUT
DATA
CIRCUIT
I/O 7
CS
CONTROL
CIRCUIT
WE
OE
2946 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AUGUST 1996
1996 Integrated Device Technology, Inc.
DSC-2946/7
7.2
1
IDT71256 S/L
CMOS STATIC RAM 256K (32K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
TRUTH TABLE(1)
A14
A12
A7
A6
A5
A4
A3
A2
A1
1
VCC
WE
A13
A8
A9
A11
OE
28
27
2
I/O
Function
Standby (ISB)
Standby (ISB1)
WE
X
CS
H
OE
X
3
26
25
24
High-Z
High-Z
4
5
X
VHC
L
X
D28-3
P28-1
P28-2
D28-1
SO28-5
6
23
22
H
H
L
High-Z Output Disabled
7
H
L
DOUT
DIN
Read Data
Write Data
8
A10
CS
21
20
9
L
L
X
A0
10
11
12
13
14
I/O 7
I/O 6
I/O 5
I/O 4
I/O 3
19
18
17
NOTE:
1. H = VIH, L = VIL, X = Don’t Care
2946 tbl 02
I/O 0
I/O 1
I/O 2
GND
16
15
2946 drw 02
ABSOLUTE MAXIMUM RATINGS(1)
DIP/SOJ
TOP VIEW
Symbol
Rating
Com’l.
Mil.
Unit
VTERM
Terminal Voltage –0.5 to +7.0 –0.5 to +7.0
V
with Respect
to GND
TA
Operating
Temperature
0 to +70
–55 to +125 °C
INDEX
TBIAS
TSTG
Temperature
Under Bias
–55 to +125 –65 to +135 °C
–55 to +125 –65 to +150 °C
32 31 30
4
3
2
1
A6
A5
29
28
27
A8
A9
A11
NC
OE
A10
CS
I/O
I/O6
5
6
Storage
Temperature
7
A4
A3
A2
A1
A0
NC
I/O0
26
25
24
23
22
21
8
L32-1
PT
Power Dissipation
1.0
50
1.0
50
W
9
10
11
12
13
IOUT
DC Output
Current
mA
7
NOTE:
2946 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating con-
ditions for extended periods may affect reliability.
14 15 16 17 18 19 20
2946 drw 03
32-Pin LCC
TOP VIEW
PIN DESCRIPTIONS
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Name
Description
Symbol
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
Max. Unit
A0–A14
I/O0–I/O7
CS
Addresses
Data Input/Output
CIN
VIN = 0V
11
11
pF
pF
CI/O
VOUT = 0V
Chip Select
Write Enable
Output Enable
Ground
NOTE:
2946 tbl 04
WE
1. This parameter is determined by device characterization, but is not
production tested.
OE
GND
VCC
Power
2946 tbl 01
7.2
2
IDT71256S/L
CMOS STATIC RAM 256K (32K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
Parameter
Min. Typ. Max. Unit
Grade
Military
Commercial
Temperature
–55°C to +125°C
0°C to +70°C
GND
VCC
VCC
Supply Voltage
4.5
0
5.0
0
5.5
0
V
V
V
0V
5.0V ± 10%
GND
VIH
Supply Voltage
0V
5.0V ± 10%
Input High Voltage
Input Low Voltage
2.2
—
—
6.0
0.8
2946 tbl 05
VIL
–0.5(1)
V
NOTE:
2946 tbl 06
1. VIL (min.) = –3.0V for pulse width less than 20ns, once per cycle.
DC ELECTRICAL CHARACTERISTICS(1, 2)
(VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC - 0.2V)
71256S/L20
71256S/L25
71256S/L30
71256S/L35
Symbol
Parameter
Power Com’l. Mil. Com’l. Mil. Com’l. Mil.
Com’l. Mil.
Unit
ICC
Dynamic Operating Current
S
—
—
—
150
—
145
—
140
mA
CS ≤ VIL, Outputs Open
(2)
VCC = Max., f = fMAX
L
135
—
—
—
115
—
130
20
—
—
125
20
105
—
120
20
ISB
Standby Power Supply
Current (TTL Level)
CS ≥ VIH, VCC = Max.,
S
mA
mA
L
3
—
3
3
—
3
3
3
(2)
Outputs Open, f = fMAX
ISB1
Full Standby Power Supply
Current (CMOS Level)
CS ≥ VHC, VCC = Max., f = 0
S
L
—
—
—
—
20
—
—
20
—
20
0.4
0.4
1.5
1.5
0.4
1.5
71256S/L45 71256S/L55
Power Com’l. Mil. Com’l. Mil. Com’l. Mil. Com’l. Mil. Com'l. Mil.
71256S/L70 71256S/L85(3) 71256S/L100(3)
Symbol
Parameter
Unit
ICC
Dynamic Operating Current
S
—
135
—
135
—
135
—
135
—
135
mA
CS ≤ VIL, Outputs Open
(2)
VCC = Max., f = fMAX
L
100 115
—
—
115
20
—
—
115
20
—
—
115
20
—
—
115
20
ISB
Standby Power Supply
Current (TTL Level)
CS ≥ VIH, VCC = Max.,
S
—
3
20
3
mA
L
—
3
—
3
—
3
—
3
(2)
Outputs Open, f = fMAX
ISB1
Full Standby Power Supply
Current (CMOS Level)
CS ≥ VHC, VCC = Max., f = 0
S
L
—
20
—
—
20
—
—
20
—
—
20
—
—
20
mA
0.4
1.5
1.5
1.5
1.5
1.5
NOTES:
2946 tbl 07
1. All values are maximum guaranteed values.
2. fMAX = 1/tRC, all address inputs cycling at fMAX; f = 0 means no address pins are cycling.
3. Also available: 120 and 150 ns military devices.
7.2
3
IDT71256 S/L
CMOS STATIC RAM 256K (32K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
5ns
1.5V
Input Timing Reference Levels
Output Reference Levels
AC Test Load
1.5V
See Figures 1 and 2
2946 tbl 08
5V
5V
480Ω
480Ω
DATAOUT
DATAOUT
255Ω
255
Ω
30pF*
5pF*
2946 drw 05
2946 drw 04
Figure 2. AC Test Load
Figure 1. AC Test Load
(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, tWHZ)
*Includes scope and jig capacitances
DC ELECTRICAL CHARACTERISTICS
VCC = 5.0V ± 10%
IDT71256S
Typ.
IDT71256L
Min. Typ. Max.
Symbol
Parameter
Test Condition
VCC = Max.,
VIN = GND to VCC
Min.
Max.
Unit
|ILI|
Input Leakage Current
MIL.
COM’L.
—
—
—
—
10
5
—
—
—
—
5
2
µA
|ILO|
VOL
Output Leakage Current VCC = Max., CS= VIH,
VOUT = GND to VCC
MIL.
COM’L.
—
—
—
—
10
5
—
—
—
—
5
2
µA
Output Low Voltage
IOL = 8mA, VCC = Min.
IOL = 10mA, VCC = Min.
IOH = –4mA, VCC = Min.
—
—
—
0.4
0.5
—
—
—
—
—
—
0.4
0.5
—
V
—
VOH
Output High Voltage
2.4
2.4
V
2946 tbl 09
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(L Version Only) VLC = 0.2V, VHC = VCC – 0.2V
Typ. (1)
VCC @
Max.
VCC @
Symbol
VDR
Parameter
Test Condition
Min.
2.0v
3.0V
2.0V
3.0V
Unit
V
VCC for Data Retention
Data Retention Current
—
2.0
—
—
—
—
ICCDR
MIL.
COM’L.
—
—
—
—
—
—
500
120
800
200
µA
tCDR
Chip Deselect to Data
Retention Time
CS ≥ VHC
0
—
—
—
—
ns
(3)
tR
(2)
Operation Recovery Time
tRC
—
—
—
—
ns
NOTES:
1. TA = +25°C.
2946 tbl 10
2. tRC = Read Cycle Time.
3. This parameter is guaranteed, but not tested.
7.2
4
IDT71256S/L
CMOS STATIC RAM 256K (32K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
LOW VCC DATA RETENTION WAVEFORM
DATA
RETENTION
MODE
VCC
4.5V
4.5V
tR
VDR≥2V
tCDR
VIH
VIH
CS
VDR
2946 drw 06
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%, All Temperature Ranges)
71256S25
71256L25
71256S30(3)
71256L30(3)
71256S35
71256L35
71256S45
71256L45
71256L20(1)
Min. Max.
Symbol
Parameter
Min. Max. Min. Max. Min. Max.
Min. Max. Unit
Read Cycle
tRC
tAA
Read Cycle Time
20
—
—
5
—
20
20
—
10
10
—
8
25
—
—
5
—
25
25
—
11
11
—
10
—
30
—
—
5
—
30
30
—
15
13
—
12
—
35
—
—
5
—
35
35
—
15
15
—
15
—
45
—
—
5
—
45
45
—
20
20
—
20
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
tACS
Chip Select Access Time
(2)
tCLZ
tCHZ
tOE
Chip Select to Output in Low-Z
Chip Deselect to Output in High-Z
Output Enable to Output Valid
Output Enable to Output in Low-Z
Output Disable to Output in High-Z
Output Hold from Address Change
(2)
—
—
2
—
—
2
—
—
2
—
—
2
—
—
0
(2)
tOLZ
(2)
tOHZ
tOH
2
2
2
2
—
5
5
—
5
5
5
Write Cycle
tWC
tCW
tAW
tAS
Write Cycle Time
20
15
15
0
—
—
—
—
—
—
—
10
—
—
25
20
20
0
—
—
—
—
—
—
—
11
—
—
30
25
25
0
—
—
—
—
—
—
—
15
—
—
35
30
30
0
—
—
—
—
—
—
—
15
—
—
45
40
40
0
—
—
—
—
—
—
—
20
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Select to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
tWP
tWR
tDW
tWHZ
tDH
Write Pulse Width
15
0
20
0
25
0
30
0
35
0
Write Recovery Time
Data to Write Time Overlap
Write Enable to Output in High-Z
Data Hold from Write Time
Output Active from End-of-Write
11
—
0
13
—
0
14
—
0
15
—
0
20
—
0
(2)
(2)
tOW
NOTES:
1. 0° to +70°C temperature range only.
5
5
5
5
5
ns
2946 tbl 11
2. This parameter guaranteed by device characterization, but is not production tested.
3. –55° to +125°C temperature range only.
7.2
5
IDT71256 S/L
CMOS STATIC RAM 256K (32K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%, All Temperature Ranges)
71256S55(1)
71256L55(1)
71256S70(1)
71256L70(1)
71256S85(1)
71256L85(1)
71256S100(1,3)
71256L100(1,3)
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max. Unit
Read Cycle
tRC
tAA
Read Cycle Time
55
—
—
5
—
55
55
—
25
25
—
25
—
70
—
—
5
—
70
70
—
30
30
—
30
—
85
—
—
5
—
85
85
—
35
35
—
35
—
100
—
—
5
—
100
100
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
tACS
Chip Select Access Time
(2)
tCLZ
tCHZ
tOE
Chip Deselect to Output in Low-Z
Output Enable to Output in Low-Z
Output Enable to Output Valid
Output Enable to Output in Low-Z
Output Disable to Output in High-Z
Output Hold from Address Change
(2)
—
—
0
—
—
0
—
—
0
—
—
0
40
40
(2)
tOLZ
—
(2)
tOHZ
tOH
0
0
—
5
—
5
40
5
5
—
Write Cycle
tWC
tCW
tAW
tAS
Write Cycle Time
55
50
50
0
—
—
—
—
—
—
—
—
25
—
70
60
60
0
—
—
—
—
—
—
—
—
30
—
85
70
70
0
—
—
—
—
—
—
—
—
35
—
100
80
80
0
—
—
—
—
—
—
—
—
40
—
ns
ns
Chip Select to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
ns
ns
tWP
tWR
tDW
tDH
Write Pulse Width
40
0
45
0
50
0
55
0
ns
Write Recovery Time
ns
Data to Write Time Overlap
Data Hold from Write Time (WE)
Write Enable to Output in High-Z
Output Active from End-of-Write
25
0
30
0
35
0
40
0
ns
ns
(2)
tWHZ
—
5
—
5
—
5
—
5
ns
(2)
tOW
ns
NOTES:
2946 tbl 11
1. –55°C to +125°C temperature range only.
2. This parameter guaranteed by device characterization, but is not production tested.
3. Also available: 120 and 150 ns military devices.
7.2
6
IDT71256S/L
CMOS STATIC RAM 256K (32K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
tRC
ADDRESS
tAA
tOH
OE
tOE
(5)
(5)
tOHZ
tOLZ
CS
tACS
(5)
(5)
tCHZ
tCLZ
DATA OUT
2946 drw 07
TIMING WAVEFORM OF READ CYCLE NO. 2(1, 2, 4)
tRC
ADDRESS
tAA
tOH
tOH
DATA OUT
2946 drw 08
TIMING WAVEFORM OF READ CYCLE NO. 3(1, 3, 4)
CS
t
ACS
(5)
CLZ
(5)
CHZ
t
t
DATA OUT
2946 drw 09
NOTES:
1. WE is HIGH for Read cycle.
2. Device is continuously selected, CS is LOW.
3. Address valid prior to or coincident with CS transition LOW.
4. OE is LOW.
5. Transition is measured ±200mV from steady state.
7.2
7
IDT71256 S/L
CMOS STATIC RAM 256K (32K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (
CONTROLLED TIMING)(1, 2, 3, 5, 7)
WE
tWC
ADDRESS
(6)
tOHZ
OE
tAW
CS
(7)
tWP
tWR
tAS
WE
(6)
tWHZ
tOW
DATA OUT
DATA IN
(4)
(4)
tDW
tDH
2946 drw 10
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (
CONTROLLED TIMING)(1, 2, 3, 5)
CS
t
WC
ADDRESS
t
AW
CS
(7)
t
AS
t
CW
tWR
WE
t
DW
tDH2
DATA IN
2946 drw 11
NOTES:
1. WE or CS must be HIGH during all address transitions.
2. A write occurs during the overlap of a LOW CS and a LOW WE.
3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle.
4. During this period, I/O pins are in the output state so that the input signals must not be applied.
5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
6. Transition is measured ±200mV from steady state.
7. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data
to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse can
be as short as the spectified tWP. For a CS controlled write cycle, OE may be LOW with no degradation to tCW.
7.2
8
IDT71256S/L
CMOS STATIC RAM 256K (32K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT
71256
X
XXX
XXX
X
Device
Type
Power
Speed
Package
Process/
Temperature
Range
Blank
Commercial (0°C to +70°C)
B
Military (–55°C to +125°C)
Compliant to MIL-STD-883, Class B
TD
D
Y
300 mil CERDIP (D28-3)
600 mil CERDIP (D28-1)
300 mil SOJ (SO28-5)
600 mil Plastic DIP (P28-1)
Leadless Chip Carrier (32-pin) (L32-1)
P
L
20
Commercial Only
Military Only
25
30
35
45
55
Military Only
Military Only
Military Only
Military Only
Military Only
Military Only
Speed in nanoseconds
70
85
100
120
150
S
L
Standard Power
Low Power
2946 drw 12
7.2
9
IDT71256L25TDB 相关器件
型号 | 制造商 | 描述 | 价格 | 文档 |
IDT71256L25TP | IDT | Standard SRAM, 32KX8, 25ns, CMOS, PDIP28, 0.300 INCH, PLASTIC, DIP-28 | 获取价格 | |
IDT71256L25XE | IDT | Standard SRAM, 32KX8, 25ns, CMOS, CDFP28, CERPACK-28 | 获取价格 | |
IDT71256L25XEB | IDT | Standard SRAM, 32KX8, 25ns, CMOS, CDFP28, CERPACK-28 | 获取价格 | |
IDT71256L25Y | IDT | CMOS STATIC RAM 256K (32K x 8-BIT) | 获取价格 | |
IDT71256L25Y8 | IDT | Standard SRAM, 32KX8, 25ns, CMOS, PDSO28, 0.300 INCH, SOJ-28 | 获取价格 | |
IDT71256L25YB | IDT | CMOS STATIC RAM 256K (32K x 8-BIT) | 获取价格 | |
IDT71256L25YG | IDT | 暂无描述 | 获取价格 | |
IDT71256L25YG8 | IDT | Standard SRAM, 32KX8, 25ns, CMOS, PDSO28, 0.300 INCH, ROHS COMPLIANT, SOJ-28 | 获取价格 | |
IDT71256L25YGI | IDT | 暂无描述 | 获取价格 | |
IDT71256L25YGI8 | IDT | Standard SRAM, 32KX8, 25ns, CMOS, PDSO28, 0.300 INCH, SOJ-28 | 获取价格 |
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