IDT70V3569S6BC_技术文档

HIGH-SPEED 3.3V 16K x 36

SYNCHRONOUS PIPELINED

DUAL-PORT STATIC RAM

WITH 3.3V OR 2.5V INTERFACE

IDT70V3569S

Features:

address inputs @ 133MHz

– Data input, address, byte enable and control registers

– Self-timedwriteallowsfastcycletime

Separate byte controls for multiplexed bus and bus

matching compatibility

LVTTL- compatible, single 3.3V (±150mV) power supply for

core

LVTTL- compatible, selectable 3.3V (±150mV)/2.5V (±125mV)

power supply for I/Os and control signals on each port

Industrial temperature range (-40°C to +85°C) is

available for selected speeds

Available in a 208-pin Plastic Quad Flatpack (PQFP),

208-ball fine-pitch Ball Grid Array, and 256-pin Ball

GridArray

◆

True Dual-Port memory cells which allow simultaneous

access of the same memory location

High-speed clock to data access

◆

– Commercial:4.2/5/6ns (max.)

– Industrial:5/6ns (max)

Pipelined output mode

◆

Counter enable and reset features

Dual chip enables allow for depth expansion without

additional logic

Full synchronous operation on both ports

– 7.5ns cycle time, 133MHzoperation(9.6Gbps bandwidth)

– Fast 4.2ns clock to data out

◆

– 1.8ns setup to clock and 0.7ns hold on all control, data, and

FunctionalBlockDiagram

BE3L

BE3R

2R

BE

BE2L

BE1L

BE1R

BE0R

BE0L

L

W

R/

WR

R/

B

B B B

W W W W W WW W

0

L

1

L

2

L

3

L

3

R

2

1

0

R

CE0L

R R

CE0R

1R

1L

CE

OEL

OER

Dout0-8_L

Dout0-8_R

Dout9-17_R

Dout18-26_R

Dout9-17_L

Dout18-26_L

Dout27-35_L

Dout27-35_R

16K x 36

MEMORY

ARRAY

0L

35L

I/O - I/O

Din_L

0R

35R

I/O - I/O

Din_R

,

L

CLK

R

CLK

13L

A

13R

0R

A

Counter/

Address

Reg.

Counter/

Address

Reg.

0L

A

ADDR_L

ADDR_R

CNTRSTL

CNTRSTR

R

ADS

ADSL

L

R

CNTEN

4831 tbl 01

APRIL 2001

1

DSC 4831/8

IDT70V3569S

High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM

Industrial and Commercial Temperature Ranges

Description:

TheIDT70V3569isahigh-speed16Kx36bitsynchronousDual-Port inbursts.Anautomaticpowerdownfeature,controlledbyCE⁰andCE1,

RAM. The memory array utilizes Dual-Port memory cells to allow permitstheon-chipcircuitryofeachporttoenteraverylowstandbypower

simultaneousaccessofanyaddressfrombothports.Registersoncontrol, mode.

data,andaddressinputsprovideminimalsetupandholdtimes.Thetiming

The 70V3569 can support an operating voltage of either 3.3V or

latitudeprovidedbythisapproachallowssystemstobedesignedwithvery 2.5V on one or both ports, controllable by the OPT pins. The power

shortcycletimes.Withaninputdataregister,theIDT70V3569hasbeen supply for the core of the device (VDD) remains at 3.3V.

optimizedforapplicationshavingunidirectionalorbidirectionaldataflow

PinConfiguration^(1,2,3,4)

A8

A9

A11

A12

A13

A14

A17

A1

A2

A3

A6

A7

A10

A15

A16

A4

A5

A^8L

1L

0L

CLK^L

L

A^4L

A^0L

V^SS

CNTEN

IO^19LIO^18LV^SS

NC

A^12L

BE

V^DD

OPT^LI/O^17L

NC

B1

B2

B3

B6

B7

B9

B11

L

B12

B13

B17

B4

B5

B8

B10

B14

B15

B16

I/O_20RV_SSI/O_18R

A_13L

A_9L

A_5L

A_1L

I/O_15R

V_SSV_DDQRI/O_16L

V_SS

NC

CE

V_SSADS

2L

BE

C1

C5

C6

C2

C3

C4

C7

C8

C9

C10

C11

C12

C13

C16

C14

C15

C17

V_DDQL

NC

I/O_19RV_DDQRV_DD

A_10L

CE_1LV_SSR/

A_6L

A_2L

I/O_15L

3L

BE

L

W

V^DDI/O^16R

V^SS

D1

D2

D6

D9

D11

D3

D5

D7

D8

D10

D12

D13

D14

D15

D16

D17

D4

I/O^22LV^SS

A^11L

V^DD

L

CNTRST

I/O^21L

NC

A^7L

0L

BE

L

OE

A^3L

V^DDI/O^17RV^DDQLI/O^14LI/O^14R

I/O^20L

E1

E2

E3

E4

E14

E16

E17

E15

I/O^23LI/O^22RV^DDQRI/O^21R

I/O^12L

V^SSI/O^13L

I/O^13R

F1

F2

F3

F14

F15

F16

F17

F4

V^DDQLI/O^23RI/O^24L

V^SSI/O^12RI/O^11LV^DDQR

V^SS

G1

G2

G4

G14

G15

G16

G3

G17

I/O^26L

V^SS

I/O^24R

I/O^9LV^DDQLI/O^10L

I/O^11R

I/O^25L

H3

H4

H1

H2

H16

H17

H14

H15

70V3569BF

BF-208⁽⁵⁾

V^DDQRI/O^25R

V^DDI/O^26R

V^SSI/O^10R

V^DD

IO^9R

J1

J2

J3

J4

J14

J15

J16

J17

V^DDQL

V^DD

V^SS

V^DD

V^SSV^DDQR

208-Pin fpBGA

Top View⁽⁶⁾

K2

K4

K15

K16

K1

K3

K14

K17

V^SS

V^DDQLI/O^8R

I/O^28R

I/O^27R

I/O^7R

V^SS

L3

L4

L15

L16

L17

L1

L2

L14

V^DDQRI/O^27L

I/O^7LV^SS

I/O^8L

I/O_29RI/O_28L

I/O_6R

M1

M2

M3

M4

M16

M17

M14

M15

V^DDQLI/O^29LI/O^30RV^SS

I/O^5RV^DDQR

I/O^6L

V^SS

N16

N17

N4

N15

N1

N2

N3

N14

I/O^4RI/O^5L

I/O^30L

V^DDQL

I/O_31LV_SSI/O_31R

I/O_3R

P1

P2

P3

P4

P5

P7

P8

P9

P10

P11

P12

P14

P15

P16

P17

P6

P13

I/O^32RI/O^32LV^DDQRI/O^35RNC

A^12R

A^8RBE^1RV^DDCLK^RCNTEN

R

I/O^2LI/O^3L

V^SSI/O^4L

NC

A_4R

R5

R6

R7

R8

R9

R10

R11

R16

R1

R2

R3

R4

R12

R13

R14

R17

R15

NC

A^13R

A^9R

2R

3R

0R

V^SS

R

I/O^1R

V^DDQR

V_DDQL

BE

CE

ADS

V^SSI/O^33LI/O^34RNC

A^5R

A^1R

V^SS

T2

T3

T1

T4

T5

T8

T9

T15

T16

T17

T6

T7

T10

T11

T12

T13

T14

I/O^34LV^DDQL

I/O_33R

V_SS

NC

CE_1R

I/O_0RV_SSI/O_2R

NC A_10RBE

V_SSR/

A_6R

A_2R

V_SS

R

W

U1

U2

U3

U4

U5

U6

U7

U17

U8

U9

U10

U12

U13

U14

U16

U15

V^SSI/O^35LV^DD

NC

A^11R

A^7R

I/O^1L

V_DD

A_3R

A_0R

V_DD

I/O_0L

OPT_R

0R

BE

R

OE

,

4831 drw 02c

NOTES:

1. All V^DDpins must be connected to 3.3V power supply.

2. All V^DDQpins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is

set to V^IL(0V).

3. All V^SSpins must be connected to ground supply.

4. Package body is approximately 15mm x 15mm x 1.4mm, with 0.8mm ball pitch.

5. This package code is used to reference the package diagram.

6. This text does not indicate orientation of the actual part-marking.

6.42

2

IDT70V3569S

High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM

Industrial and Commercial Temperature Ranges

Pin Configuration^(1,2,3,4)(con't.)

70V3569BC

BC-256⁽⁵⁾

256-Pin BGA

Top View⁽⁶⁾

A1

A2

A3

A6

A7

A8

A9

A11

A12

A13

A14

A4

A5

A10

A15

A16

NC

A_11L

A_8L

CE_1L

A_5L

A_2L

A_0L

BE2L

CNTENL

NC

OEL

B1

B2

B3

B6

B7

B9

CE0L

B11

B12

B13

B4

B5

B8

B10

B14

B15

B16

I/O_18LNC

NC

A_12L

A_9L

A_4L

A_1L

CNTRST

L

NC

R/

V_DDI/O_17LNC

BE3L

WL

C1

C5

C6

C2

C3

C4

C7

C8

C9

C10

C11

C12

C13

C16

C14

C15

I/O^18R

A^13L

A^10L

I/O_19LV_SS

NC

A_7L

CLK_L

A_6L

A_3L

I/O_16L

BE1L BE0L

ADSL

OPT_LI/O_17R

D1

D2

D6

D9

D11

D3

D5

D7

D8

D10

D12

D13

D14

D15

D16

D4

I/O_20RI/O_19R

V_DDQL

V_DDQR

V_DDQRV_DDI/O_15RI/O_15LI/O_16R

I/O_20L

V_DDQL

V_DDQRV_DDQR

V_DDQL

V_DD

E5

E6

E7

E8

E9

E10

E11

E12

E13

E1

E2

E3

E4

E14

E16

E15

V_DDV_DD

V_SS

V_DD

V_DDV

^DDQRI/O_13L

I/O_21RI/O_21LI/O_22LV_DDQL

I/O_14R

I/O_14L

F7

F5

F6

F9

F10

F1

F2

F3

F11

F13

F14

F15

F16

F8

F12

F4

V_SS

I/O_23LI/O_22RI/O_23R

V_DDV_SS

V_SS

I/O_12RI/O_13RI/O_12L

V_DDQR

V_SS

V_DDQL

V_SS

V_DD

G1

G5

G2

G4

G6

G8

G9

G3

G14

G15

G16

G7

G10

G12

G13

G11

I/O_24R

V_SS

I/O_24L

V_DDQR

V_SS

I/O^25L

I/O^10LI/O^11LI/O^11R

V^SS

V^DDQL

V^SS

H11

H12

H16

H13

H7

H8

H9

H10

H14

H15

H5

H6

H3

H4

H1

H2

V_SSV_SS

I/O_10R

V_DDQL

I/O_9RIO_9L

V_SSV_SS

V_SS

I/O_26RV_DDQRV_SS

V_SS

I/O_26LI/O_25R

J1

J2

J3

J4

J5

J6

J7

J8

J9

J13

J10

J11

J12

J14

J15

J16

I/O_27L

V_SS

I/O_28RI/O_27RV_DDQL

V_SS

V_DDQR

V_SS

I/O_8R

I/O_7RI/O_8L

K6

K8

K10

K12

K13

K2

K4

K5

K7

K9

K11

K15

K16

K1

K3

K14

V_SS

V_DDQR

I/O_29L

V_DDQLV_SS

V_SS

I/O_6LI/O_7L

I/O^29R

I/O^28L

I/O^6R

L7

L8

L11

L12

L13

L5

L6

L9

L10

L3

L4

L15

L16

L1

L2

L14

V_SS

V_SSV_DD

V_DDQL

I/O_30RV_DDQRV_DD

V_SS

I/O_4RI/O_5R

I/O_30LI/O_31R

I/O_5L

M5

M6

M7

M8

M9

M10

M11

M12

M13

M1

M2

M3

M4

M16

M14

M15

V_DDV_DD

V_SS

V_DDV_DD

V_DDQL

I/O_32RI/O_32LI/O_31LV_DDQR

I/O_4L

I/O_3RI/O_3L

N8

N12

N13

N16

N4

N5

N6

N7

N9

N10

N11

N15

N1

N2

N3

N14

V_DDQL

I/O_2R

I/O^1R

V_DD

V^DDV^DDQRV^DDQRV^DDQL

V^DDQRV^DDQRV^DDQL

I/O^33LI/O^34RI/O^33R

I/O^2L

P1

P2

P3

P4

P5

P7

P8

P9

P10

P11

P12

P14

P15

P16

P6

P13

I/O_35RI/O_34LNC

NC A_13R

A_7R

CLK_R

A_6R

I/O_0LI/O_0RI/O_1L

BE1R BE0R

ADSR

A_10R

A_3R

R5

R6

R7

R8

R9

R10

R11

R16

R1

R2

R3

R4

R12

R13

R14

R15

,

NC A_12RA_9R

R/

NC

BE3R CE0R

WR CNTRSTR

I/O_35LNC

NC

A_4R

A_1ROPT_R

NC

T2

T3

T1

T4

T5

T8

T9

T15

T16

T6

T7

T10

T11

T12

T13

T14

NC

2R CE^1R

NC

BE

A^11R

A^8R

R

A^5R

A^2R

A^0R

OE CNTEN

4831 drw 02d

NOTES:

1. All V^DDpins must be connected to 3.3V power supply.

2. All V^DDQpins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is

set to V^IL(0V).

,

3. All V^SSpins must be connected to ground supply.

4. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.

5. This package code is used to reference the package diagram.

6. This text does not indicate orientation of the actual part-marking.

6.42

3

IDT70V3569S

High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM

Industrial and Commercial Temperature Ranges

Pin Configuration^(1,2,3,4)(con't.)

I/O16L

156

1

2

3

4

5

6

7

8

I/O19L

I/O19R

I/O20L

I/O20R

VDDQL

VSS

I/O16R

155

I/O15L

154

I/O15R

153

VSS

152

VDDQL

151

I/O14L

150

I/O

21L

I/O14R

149

I/O

21R

I/O13L

148

I/O

22L

22R

9

I/O13R

147

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

VSS

146

V

DDQR

VDDQR

145

V

SS

I/O12L

144

I/O

23L

I/O12R

143

I/O

23R

I/O11L

142

I/O

24L

I/O11R

141

I/O

24R

VSS

140

VDDQL

VSS

VDDQL

139

I/O10L

138

I/O25L

I/O25R

I/O26L

I/O26R

VDDQR

VSS

VDD

VSS

I/O10R

137

I/O9L

136

I/O9R

135

VSS

134

VDDQR

133

70V3569DR

DR-208

VDD

132

(5)

VDD

131

VSS

130

VSS

129

VSS

128

VDDQL

V

VDDQL

127

SS

208-Pin PQFP

I/O8R

126

I/O27R

I/O27L

I/O28R

I/O28L

VDDQR

VSS

I/O29R

I/O29L

I/O30R

I/O30L

VDDQL

VSS

(6)

I/O8L

125

Top View

I/O7R

124

I/O7L

123

VSS

122

VDDQR

121

I/O6R

120

I/O6L

119

I/O5R

118

I/O5L

117

VSS

116

VDDQL

115

I/O4R

114

I/O31R

I/O31L

I/O32R

I/O32L

I/O4L

113

I/O3R

112

I/O3L

111

VSS

110

V

DDQR

VDDQR

109

V

SS

I/O2R

108

I/O

33R

I/O2L

107

I/O

33L

I/O1R

106

I/O

34R

I/O1L

105

I/O34L

4831 drw 02a

NOTES:

1. All V^DDpins must be connected to 3.3V power supply.

2. All V^DDQpins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is

set to V^IL(0V).

3. All V^SSpins must be connected to ground supply.

4. Package body is approximately 28mm x 28mm x 3.5mm.

5. This package code is used to reference the package diagram.

6. This text does not indicate orientation of the actual part-marking.

6.42

4

IDT70V3569S

High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM

Industrial and Commercial Temperature Ranges

PinNames

Left Port

Right Port

Names

CE^0L

1L

CE^0R1R

, CE

Chip Enables

, CE

W^L

R/

W^R

R/

Read/Write Enable

Output Enable

OE^L

OE^R

0L

A

13L

- A

0R

A

13R

- A

Address

0L

35L

0R

35R

I/O - I/O

Data Input/Output

Clock

L

CLK

R

CLK

ADS^L

ADS^R

Address Strobe Enable

Counter Enable

Counter Reset

Byte Enables (9-bit bytes)

CNTEN^L

CNTRST^L

CNTEN^R

CNTRST^R

NOTES:

1. V^DD, OPTX, and VDDQX must be set to appropriate operating levels prior to

applying inputs on the I/Os and controls for that port.

BE^0LBE^3L

BE^0RBE^3R

-

2. OPT^Xselects the operating voltage levels for the I/Os and controls on that port.

If OPT^Xis set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V

levels and V^DDQXmust be supplied at 3.3V. If OPTX is set to VIL (0V), then that

port's I/Os and controls will operate at 2.5V levels and V^DDQXmust be supplied

at 2.5V. The OPT pins are independent of one another—both ports can operate

at 3.3V levels, both can operate at 2.5V levels, or either can operate at 3.3V

with the other at 2.5V.

(1)

(3.3V or 2.5V)

Power (I/O Bus)

DDQL

DDQR

V

(1,2)

DDQX

L

OPT

R

OPT

Option for selection V

(1)

DD

(3.3V)

V

Power

SS

V

(0V)

Ground

4831 tbl 01

Truth Table IRead/Write and Enable Control^(1,2,3,4)

Byte 3

I/O27-35

Byte 2

I/O18-26

Byte 1

I/O9-17

Byte 0

I/O0-8

CLK

↑

CE1

X

L

R/W

X

L

MODE

OE

CE⁰

H

X

L

BE³

X

H

L

BE²

X

H

L

BE¹

X

H

L

BE⁰

X

H

L

X

High-Z

DIN

High-Z

DIN

High-Z

DIN

High-Z Deselected–Power Down

High-Z All Bytes Deselected

X

↑

X

↑

H

X

DIN

Write to Byte 0 Only

↑

X

H

L

High-Z Write to Byte 1 Only

High-Z Write to Byte 2 Only

High-Z Write to Byte 3 Only

↑

X

H

L

High-Z

DIN

↑

X

H

L

High-Z

DIN

↑

X

↑

H

L

High-Z

DIN

Write to Lower 2 Bytes Only

X

H

L

H

L

High-Z

DIN

High-Z Write to Upper 2 bytes Only

↑

X

L

DIN

Write to All Bytes

Read Byte 0 Only

↑

L

H

L

H

L

H

L

H

X

High-Z

DOUT

High-Z

DOUT

↑

L

H

L

High-Z Read Byte 1 Only

High-Z Read Byte 2 Only

High-Z Read Byte 3 Only

↑

OUT

D

L

↑

H

L

High-Z

DOUT

L

H

L

High-Z

DOUT

↑

L

H

L

High-Z

DOUT

Read Lower 2 Bytes Only

↑

L

H

L

H

L

High-Z

DOUT

High-Z Read Upper 2 Bytes Only

↑

L

DOUT

Read All Bytes

↑

H

↑

L

High-Z

High-Z Outputs Disabled

4831 tbl 02

NOTES:

1. "H" = V^IH,"L" = VIL, "X" = Don't Care.

2. ADS, CNTEN, CNTRST = V^IH.

3. OE is an asynchronous input signal.

4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.

6.42

5

IDT70V3569S

High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM

Industrial and Commercial Temperature Ranges

Truth Table IIAddress Counter Control^(1,2)

Addr

Used

(6)

(3)

Address

CLK

I/O

D^I/O(0)

D^I/O(n) External Address Used

MODE

ADS CNTEN CNTRST

(4)

X

An

X

0

An

X

H

L

Counter Reset to Address 0

↑

(4)

L

H

Ap

H

D^I/O(p)

External Address Blocked—Counter disabled (Ap reused)

(5)

Ap + 1

L

D^I/O(p+1) Counter Enabled—Internal Address generation

4831 tbl 03

NOTES:

1. "H" = V^IH,"L" = VIL, "X" = Don't Care.

2. Read and write operations are controlled by the appropriate setting of R/W, CE⁰, CE1, BEn and OE.

3. Outputs are in Pipelined mode: the data out will be delayed by one cycle.

4. ADS and CNTRST are independent of all other memory control signals including CE⁰, CE1 and BEn

5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE1, BEn.

RecommendedDCOperating

Conditions with VDDQ at 2.5V

RecommendedOperating

TemperatureandSupplyVoltage^(1,2)

Symbol

Parameter

Core Supply Voltage

I/O Supply Voltage⁽³⁾

Ground

Min. Typ.

3.15 3.3

2.375 2.5

Max.

3.45

2.625

0

Unit

V

Ambient

Grade

Commercial

Temperature

0^OC to +70^OC

-40^OC to +85^OC

GND

0V

V^DD

3.3V + 150mV

V^DDQ

V^SS

V

0

V

Industrial

0V

(2)

Input High Voltage⁽³⁾

1.7

V

____

4831 tbl 04

V^DDQ+ 125mV

IH

V

NOTES:

(Address & Control Inputs)

1. Industrial temperature: for specific speeds, packages and powers contact your

sales office.

2. This is the parameter T^A. This is the "instant on" case temperature.

(3)

(2)

____

IH

DDQ

V

Input High Voltage - I/O

1.7

+ 125mV

V

Input Low Voltage

-0.3⁽¹⁾

0.7

V

IL

V

4831 tbl 05a

NOTES:

1. V^{IL >}-1.5V for pulse width less than 10 ns.

2. V^TERMmust not exceed VDDQ + 125mV.

3. To select operation at 2.5V levels on the I/Os and controls of a given port, the

OPT pin for that port must be set to V^IL(0V), and VDDQX for that port must be

supplied as indicated above.

AbsoluteMaximumRatings⁽¹⁾

Symbol

Rating

Commercial

& Industrial

Unit

(2)

V^{TE RM}

Terminal Voltage

with Respect to

GND

-0.5 to +4.6

V

RecommendedDCOperating

Conditions with VDDQ at 3.3V

Temperature

Under Bias

-55 to +125

-65 to +150

50

^oC

T^BIAS

Symbol

Parameter

Core Supply Voltage

I/O Supply Voltage⁽³⁾

Ground

Min. Typ.

3.15 3.3

Max.

3.45

0

Unit

V

Storage

Temperature

T^STG

V^DD

V^DDQ

V^SS

V

I^OUT

DC Output Current

mA

0

V

4831 tbl 06

NOTES:

(2)

____

Input High Voltage

(Address & Control Inputs)

2.0

V^DDQ+ 150mV

V

V^IH

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated

in the operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect reliability.

2. V^TERMmust not exceed VDD + 150mV for more than 25% of the cycle time or

4ns maximum, and is limited to < 20mA for the period of VTERM > VDD + 150mV.

(3)

____

(2)

V^IH

Input High Voltage - I/O

2.0

V^DDQ+ 150mV

V

(1)

V

IL

Input Low Voltage

-0.3

0.8

V

4831 tbl 05b

NOTES:

1. V^{IL >}-1.5V for pulse width less than 10 ns.

2. V^TERMmust not exceed VDDQ + 150mV.

3. To select operation at 3.3V levels on the I/Os and controls of a given port, the

OPT pin for that port must be set to V^IH(3.3V), and VDDQX for that port must be

supplied as indicated above.

6.42

6

IDT70V3569S

High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM

Industrial and Commercial Temperature Ranges

Capacitance⁽¹⁾

(TA = +25°C, F = 1.0MHZ) PQFP ONLY

Symbol

Parameter

Input Capacitance

Output Capacitance

Conditions^{(2 )}

Max. Unit

C^IN

V^IN= 3dV

8

pF

(3 )

C^OUT

V^OUT= 3dV

10.5

pF

4831 tbl 07

NOTES:

1. These parameters are determined by device characterization, but are not

production tested.

2. 3dV references the interpolated capacitance when the input and output switch

from 0V to 3V or from 3V to 0V.

3. C^OUTalso references CI/O.

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range (VDD = 3.3V ± 150mV)

70V3569S

Symbol

|I^LI|

Parameter

Test Conditions

V^DDQ= Max., V^IN= 0V to V^DDQ

Min.

Max.

10

Unit

µA

V

(1)

___

Input Leakage Current

|I^LO|

Output Leakage Current

0

IH

1

IL OUT

DDQ

10

CE = V or CE = V , V = 0V to V

V^OL(3.3V) Output Low Voltage⁽²⁾

V^OH(3.3V) Output High Voltage⁽²⁾

V^OL(2.5V) Output Low Voltage⁽²⁾

V^OH(2.5V) Output High Voltage⁽²⁾

I^OL= +4mA, V^DDQ= Min.

0.4

___

I^OH= -4mA, V^DDQ= Min.

2.4

V

___

I^OL= +2mA, V^DDQ= Min.

0.4

V

___

I^OH= -2mA, V^DDQ= Min.

2.0

V

4831 tbl 08

NOTE:

1. At V^DD< - 2.0V input leakages are undefined.

2. V^DDQis selectable (3.3V/2.5V) via OPT pins. Refer to p.4 for details.

6.42

7

IDT70V3569S

High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM

Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range⁽³⁾(VDD = 3.3V ± 150mV)

70V3569S4

Com'l Only

70V3569S5

Com'l

70V3569S6

Com'l

& Ind

Symbol

DD

Parameter

Test Condition

Version

COM'L

Typ.⁽⁴⁾

375

Max.

460

Typ.⁽⁴⁾

Max.

Typ.⁽⁴⁾

Max.

Unit

I

Dynamic Ope rating

Current (Both

Ports Active )

mA

L

R

CE and CE = VIL

,

S

285

105

190

6

360

245

95

310

360

125

150

225

260

15

Outputs Disabled,

____

(1)

IND

415

145

175

260

300

15

f = fMAX

I

SB1

Standby Current

(Both Ports - TTL

Le ve l Inputs)

mA

CE

L

f = fMAX

=

CE = VIH

R

COM'L

IND

145

190

(1)

____

95

(5)

I

SB2

Standby Current

(One Port - TTL

Le ve l Inputs)

CE^"A"= VIL and CE^"B"= VIH

Active Port Outputs Disable d,

COM'L

IND

265

325

175

6

____

(1)

f=fMAX

CE

L

and

I

SB3

Full Standby Current Both Ports

(Both Ports - CMOS CE

Le ve l Inputs)

COM'L

IND

6

15

R

> VDD - 0.2V, VIN > VDD - 0.2V

____

or VIN < 0.2V, f = 0⁽²⁾

6

30

6

30

(5)

I

SB4

Full Standby Current

(One Port - CMOS

Le ve l Inputs)

mA

CE^"A"< 0.2V and CE^"B"> VDD - 0.2V

IN > VDD - 0.2V or VIN < 0.2V, Active

Port, Outputs Disable d, f = fMAX

COM'L

IND

265

325

180

260

300

170

225

260

V

____

(1)

4831 tbl 09

NOTES:

1. At f = f^MAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input

levels of GND to 3V.

2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.

3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

4. V^DD= 3.3V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 120mA (Typ).

5. CE^X= VIL means CE0X = VIL and CE1X = VIH

CEX = VIH means CE0X = VIH or CE1X = VIL

CEX < 0.2V means CE0X < 0.2V and CE1X > VCC - 0.2V

CE^X> VCC - 0.2V means CE0X > VCC - 0.2V or CE1X - 0.2V

"X" represents "L" for left port or "R" for right port.

6.42

8

IDT70V3569S

High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM

Industrial and Commercial Temperature Ranges

2.5V

AC Test Conditions

Input Pulse Levels (Address & Controls)

Input Pulse Levels (I/Os)

Input Rise/Fall Times

GND to 3.0V/GND to 2.35V

3ns

833Ω

DATAOUT

Input Timing Reference Levels

Output Reference Levels

Output Load

1.5V/1.25V

5pF*

770

Ω

Figures 1, 2, and 3

4831 tbl 10

,

3.3V

590Ω

5pF*

50Ω

,

DATAOUT

1.5V/1.25

DATAOUT

10pF

(Tester)

4831 drw 03

435Ω

Figure 1. AC Output Test load.

,

4831 drw 04

Figure 2. Output Test Load

(For t^CKLZ, tCKHZ, tOLZ, and tOHZ).

*Including scope and jig.

10.5pF is the I/O capacitance of this

device, and 10pF is the AC Test Load

Capacitance.

7

6

5

4

3

∆tCD

(Typical, ns)

2

1

•

,

20.5

50

80 100

200

30

-1

Capacitance (pF)

4831 drw 05

Figure 3. Typical Output Derating (Lumped Capacitive Load).

·

6.42

9

IDT70V3569S

High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM

Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the Operating

Temperature Range (Read and Write Cycle Timing)^(1,2)

(VDD = 3.3V ± 150mV, TA = 0°C to +70°C)

70V3569S4

Com'l Only

70V3569S5

Com'l

70V3569S6

Com'l

& Ind

Symbol

Parameter

Clock Cycle Time (Pipelined)

Clock High Time (Pipelined)

Clock Low Time (Pipelined)

Clock Rise Time

Min.

7.5

3

Max.

Min.

10

Max.

Min.

12

Max.

Unit

ns

____

tCYC2

tCH2

tCL2

tR

4

5

3

4

5

____

3

____

tF

Clock Fall Time

3

____

tSA

tHA

tSC

tHC

tSB

Address Setup Time

1.8

0.7

1.8

0.7

1.8

0.7

1.8

0.7

1.8

0.7

1.8

0.7

1.8

0.7

1.8

2.0

0.7

2.0

0.7

2.0

0.7

2.0

0.7

2.0

0.7

2.0

0.7

2.0

0.7

2.0

1.0

2.0

1.0

2.0

1.0

2.0

1.0

2.0

1.0

2.0

1.0

2.0

1.0

2.0

____

Address Hold Time

Chip Enable Setup Time

Chip Enable Hold Time

Byte Enable Setup Time

Byte Enable Hold Time

R/W Setup Time

HB

t

tSW

tHW

tSD

R/W Hold Time

Input Data Setup Time

Input Data Hold Time

tHD

tSAD

tHAD

tSCN

tHCN

tSRST

ADS Setup Time

ADS Hold Time

CNTEN Setup Time

CNTEN Hold Time

CNTRST Setup Time

tHRST

(1)

0.7

1.0

CNTRST Hold Time

____

OE

t

Output Enable to Data Valid

Output Enable to Output Low-Z

Output Enable to Output High-Z

Clock to Data Valid (Pipelined)

Data Output Hold After Clock High

Clock High to Output High-Z

Clock High to Output Low-Z

4

5

6

____

tOLZ

tOHZ

tCD2

tDC

0

1

4

1

4.5

1

5

____

4.2

5

6

____

1

1.5

1

tCKHZ

tCKLZ

3

4.5

6

____

Port-to-Port Delay

____

tCO

Clock-to-Clock Offset

6

8

10

ns

4831 tbl 11

NOTES:

1. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE).

2. These values are valid for either level of V^DDQ(3.3V/2.5V). See page 4 for details on selecting the desired I/O voltage levels for each port.

6.42

10

IDT70V3569S

High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM

Industrial and Commercial Temperature Ranges

Timing Waveform of Read Cycle for Pipelined Operation⁽²⁾

tCYC2

t_CH2

t_CL2

CLK

CE0

tSC tHC

(3)

tSC tHC

CE1

tSB

(5)

tHB

tSB

BE(0-3)

R/W

tHW

tHA

tSW

tSA

ADDRESS⁽⁴⁾

An

An + 1

An + 2

Qn

An + 3

(1 Latency)

tDC

tCD2

Qn + 2 ⁽⁵⁾

DATAOUT

Qn + 1

(1)

tCKLZ

tOHZ

tOLZ

tOE

(1)

OE

NOTES:

4831 drw 06

1. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.

2. ADS = V^IL, CNTEN and CNTRST = VIH.

3. The output is disabled (High-Impedance state) by CE⁰= VIH, CE1 = VIL, BEn = VIH following the next rising edge of the clock. Refer to

Truth Table 1.

4. Addresses do not have to be accessed sequentially since ADS = V^ILconstantly loads the address on the rising edge of the CLK; numbers

are for reference use only.

5. If BEⁿwas HIGH, then the appropriate Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state).

Timing Waveform of a Multi-Device Pipelined Read^(1,2)

tCYC2

tCH2

tCL2

CLK

tSA tHA

6

A

A5

A4

A3

A2

0

A

1

A

ADDRESS(B1)

tSC tHC

CE

0(B1)

tSC tHC

tCD2

tCKHZ

DC

tCD2

Q0

Q3

A5

Q1

A3

DATAOUT(B1)

tDC

CKLZ

t

tCKHZ

tSA tHA

6

A

A4

A2

0

A

1

A

(B2)

ADDRESS

tSC tHC

CE

0(B2)

tSC tHC

tCD2

tCKHZ

tCD2

DATAOUT(B2)

4

Q

Q2

CKLZ

t

CKLZ

t

NOTES:

4831 drw 07

1. B1 Represents Device #1; B2 Represents Device #2. Each Device consists of one IDT70V3569 for this waveform,

and are setup for depth expansion in this example. ADDRESS^(B1)= ADDRESS(B2) in this situation.

2. BEⁿ, OE, and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH.

6.42

11

IDT70V3569S

High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM

Industrial and Commercial Temperature Ranges

Timing Waveform of Left Port Write to Pipelined

Right Port Read^(1,2)

L

CLK

t^SWt^HW

R/W^L

t^SAt^HA

NO

MATCH

ADDRESS^L

DATA^INL

CLK^R

MATCH

t^SDt^HD

VALID

(3)

t^CO

t^CD2

W^R

R/

t^SWt^HW

t^SAt^HA

NO

ADDRESS^R

DATA^OUTR

MATCH

VALID

t^DC

4831 drw 08

NOTES:

1. CE⁰, BEn, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.

2. OE = V^ILfor the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.

3. If t^CO< minimum specified, then data from right port read is not valid until following right port clock cycle (ie, time from write to valid read on opposite port will

be t^CO+ 2 tCYC2 + tCD2). If tCO > minimum, then data from right port read is available on first right port clock cycle (ie, time from write to valid read on opposite

port will be t^CO+ tCYC + tCD2).

Timing Waveform of Pipelined Read-to-Write-to-Read

(OE = VIL)⁽²⁾

t_CYC2

tCH2

tCL2

CLK

CE

0

tSC tHC

CE1

tSB

tHB

BEn

R/W

t_SWt_HW

tSW tHW

ADDRESS⁽³⁾

An + 3

An + 4

An

t_SAt_HA

An +1

An + 2

tSD

Dn + 2

tHD

DATAIN

tCD2

(1)

tCKHZ

tCKLZ

Qn + 3

Qn

DATAOUT

READ

NOP⁽⁴⁾

WRITE

READ

4831 drw 09

NOTES:

1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.

2. CE⁰, BEn, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. "NOP" is "No Operation".

3. Addresses do not have to be accessed sequentially since ADS = V^ILconstantly loads the address on the rising edge of the CLK; numbers

are for reference use only.

4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.

6.42

12

IDT70V3569S

High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM

Industrial and Commercial Temperature Ranges

Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled)⁽²⁾

tCYC2

tCH2

tCL2

CLK

CE0

tSC tHC

CE1

tSB

tHB

BEn

tSW tHW

R/W

tSW tHW

(3)

An + 4

An

An +1

An + 2

An + 3

Dn + 3

An + 5

ADDRESS

tSA tHA

tSD tHD

DATAIN

Dn + 2

tCD2

tCKLZ

(1)

Qn

Qn + 4

DATAOUT

(4)

tOHZ

OE

READ

WRITE

READ

4831 drw 10

NOTES:

1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.

2. CE⁰, BEn, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.

3. Addresses do not have to be accessed sequentially since ADS = V^ILconstantly loads the address on the rising edge of the CLK; numbers are for reference use

only.

4. This timing does not meet requirements for fastest speed grade. This waveform indicates how logically it could be done if timing so allows.

Timing Waveform of Pipelined Read with Address Counter Advance⁽¹⁾

tCYC2

tCH2

tCL2

CLK

tSA tHA

An

ADDRESS

tSAD tHAD

ADS

tSAD tHAD

tSCN tHCN

CNTEN

tCD2

Qn + 2⁽²⁾

Qx - 1⁽²⁾

Qx

Qn + 3

Qn + 1

Qn

DATAOUT

tDC

READ

EXTERNAL

ADDRESS

READ

WITH

COUNTER

HOLD

READ WITH COUNTER

4831 drw 11

NOTES:

1. CE⁰, OE, BEn = VIL; CE1, R/W, and CNTRST = VIH.

2. If there is no address change via ADS = V^IL(loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then

the data output remains constant for subsequent clocks.

6.42

13

IDT70V3569S

High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM

Industrial and Commercial Temperature Ranges

Timing Waveform of Write with Address Counter Advance⁽¹⁾

tCYC2

tCH2

tCL2

CLK

tSA tHA

An

ADDRESS

INTERNAL⁽³⁾

ADDRESS

An⁽⁷⁾

An + 4

An + 2

An + 1

An + 3

tSAD tHAD

ADS

tSCN tHCN

CNTEN

tSD tHD

Dn

Dn + 4

Dn + 1

Dn + 3

Dn + 1

Dn + 2

DATAIN

WRITE

EXTERNAL

ADDRESS

WRITE

WITH COUNTER

WRITE

COUNTER HOLD

WRITE WITH COUNTER

4831 drw 12

Timing Waveform of Counter Reset⁽²⁾

tCYC2

tCH2

tCL2

CLK

tSA tHA

(4)

An + 2

An

An + 1

ADDRESS

INTERNAL⁽³⁾

ADDRESS

Ax

0

1

An

An + 1

tSW tHW

R/W

ADS

tSAD tHAD

tSCN tHCN

CNTEN

tSRST

tHRST

CNTRST

tSD

tHD

D0

DATAIN

(5)

Qn

Q1

Q0

DATAOUT

COUNTER⁽⁶⁾

RESET

WRITE

ADDRESS 0

READ

ADDRESS 0

READ

ADDRESS 1

ADDRESS n ADDRESS n+1

NOTES:

1. CE⁰, BEn, and R/W = VIL; CE1 and CNTRST = VIH.

CE⁰, BEn = VIL; CE1 = VIH.

4831 drw 13

2.

3. The "Internal Address" is equal to the "External Address" when ADS = V^ILand equals the counter output when ADS = VIH.

4. Addresses do not have to be accessed sequentially since ADS = V^ILconstantly loads the address on the rising edge of the CLK; numbers are for reference

use only.

5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.

6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset cycle: A^DDR0 will be accessed. Extra cycles

are shown here simply for clarification.

7. CNTEN = V^ILadvances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is

written to during this cycle.

6.42

14

IDT70V3569S

High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM

Industrial and Commercial Temperature Ranges

FunctionalDescription

Depth and Width Expansion

TheIDT70V3569providesatruesynchronousDual-PortStaticRAM

interface. Registered inputs provide minimal set-up and hold times on

address,data,andallcriticalcontrolinputs.Allinternalregistersareclocked

ontherisingedgeoftheclock signal,however,theself-timedinternalwrite

pulseisindependentoftheLOWtoHIGHtransitionoftheclocksignal.

An asynchronous output enable is provided to ease asyn-

chronousbusinterfacing.Counterenableinputsarealsoprovidedtostall

the operation of the address counters for fast interleaved

memoryapplications.

The IDT70V3569 features dual chip enables (refer to Truth

Table I) in order to facilitate rapid and simple depth expansion with no

requirements for external logic. Figure 4 illustrates how to control the

various chip enables in order to expand two devices in depth.

TheIDT70V3569canalsobeusedinapplicationsrequiringexpanded

width,asindicatedinFigure4.Throughcombiningthecontrolsignals,the

devices can be grouped as necessary to accommodate applications

needing 72-bits or wider.

AHIGHonCE⁰oraLOWonCE1foroneclockcyclewillpowerdown

the internal circuitry to reduce static power consumption. Multiple chip

enablesalloweasierbankingofmultipleIDT70V3569sfordepthexpan-

sion configurations. Two cycles are required with CE⁰LOW and CE1

HIGHtore-activatetheoutputs.

A¹⁵

IDT70V3569

CE₀

CE¹

V^DD

Control Inputs

IDT70V3569

CE¹

CE⁰

BE

W

R/ ,

,

Control Inputs

OE,

CLK,

ADS

,

4831 drw 14

CNTRST

,

CNTEN

Figure 4. Depth and Width Expansion with IDT70V3569

6.42

15

IDT70V3569S

High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM

Industrial and Commercial Temperature Ranges

OrderingInformation

IDT XXXXX

A

99

A

Device

Type

Power Speed

Package

Process/

Temperature

Range

Blank

I

Commercial (0°C to +70°C)

Industrial (-40°C to +85°C)

BF

DR

BC

208-pin fpBGA (BF-208)

208-pin PQFP (DR-208)

256-pin BGA (BC-256)

4

5

6

Commercial Only

Speed in nanoseconds

Commercial & Industrial

S

Standard Power

,

70V3569 576Kbit (16K x 36-Bit) Synchronous Dual-Port RAM

4831 drw 15A

DatasheetDocumentHistory

1/8/99:

3/12/99:

4/28/99:

6/8/99:

InitialPublicRelease

AddedfpBGApackage

Fixed typo on page 10

Changeddrawingformat

Page 2 Changedpackagebodydimensions

Page 3 Fixed typo

6/15/99:

8/4/99:

Page 5 Deleted note 6 for Table II

Page 2 Fixed typographical error

Page 6 Improved power number

Upgraded speed to 133MHz, added 2.5V I/O capability

Page 4 Corrected I/O numbers in Truth Table I

Replaced IDT logo

10/14/99:

10/19/99:

11/12/99:

4/10/00:

1/12/01:

AddednewBGApackages,addedfull2.5Vinterfacecapability

Page 6 Updated Truth Table II

Increatedstoragetemperatureparameter

ClarifiedTAParameter

Page 8 DCElectricalparameters–changedwordingfrom"open"to"disabled"

Removednote7onDCElectricalCharacteristicstable

RemovedPreliminarystatus

4/10/01:

AddedIndustrialTemperatureRangesandremovedrelatednotes

CORPORATE HEADQUARTERS

2975StenderWay

Santa Clara, CA 95054

for SALES:

for Tech Support:

831-754-4613

DualPortHelp@idt.com

800-345-7015 or 408-727-5166

fax: 408-492-8674

www.idt.com

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

6.42

16


型号：	IDT70V3569S6BC
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	HIGH-SPEED 3.3V 16K x 36 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE 高速3.3V 16K ×36同步流水式双端口静态3.3V或2.5V接口RAM
文件：	总16页 (文件大小：188K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IDT70V3569S6BC [IDT]

相关型号：

IDT70V3569S6BCG

IDT70V3569S6BCI

IDT70V3569S6BF

IDT70V3569S6BFG

IDT70V3569S6BFG8

IDT70V3569S6BFGI

IDT70V3569S6BFI

IDT70V3569S6DR

IDT70V3569S6DR8

IDT70V3569S6DRG

IDT70V3569S6DRG8

IDT70V3569S6DRGI