IDT70V06S55PFG [IDT]
Dual-Port SRAM, 16KX8, 55ns, CMOS, PQFP64, TQFP-64;
| 型号： | IDT70V06S55PFG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Dual-Port SRAM, 16KX8, 55ns, CMOS, PQFP64, TQFP-64 存储 内存集成电路 静态存储器 |
| 文件： | 总22页 (文件大小：172K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT70V06S/L
HIGH-SPEED 3.3V
16K x 8 DUAL-PORT
STATIC RAM
Features
◆
◆
M/S = VIH for BUSY output flag on Master
M/S = VIL for BUSY input on Slave
Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
Battery backup operation—2V data retention
TTL-compatible, single 3.3V (±0.3V) power supply
Available in 68-pin PGA and PLCC, and a 64-pin TQFP
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
– Commercial:15/20/25/35/55ns(max.)
– Industrial:20/25/35/55ns(max.)
Low-power operation
◆
◆
◆
◆
◆
◆
◆
◆
◆
◆
– IDT70V06S
Active:400mW(typ.)
Standby: 3.3mW (typ.)
– IDT70V06L
Active:380mW(typ.)
Standby: 660mW (typ.)
◆
IDT70V06 easily expands data bus width to 16 bits or more
using the Master/Slave select when cascading more than
one device
Functional Block Diagram
OEL
OER
CEL
CER
R/WL
R/WR
,
I/O0L- I/O7L
I/O0R-I/O7R
I/O
Control
I/O
Control
(1,2)
BUSYL
(1,2)
BUSYR
A13L
A13R
Address
MEMORY
ARRAY
Address
Decoder
Decoder
A0L
A0R
14
14
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CEL
OEL
CER
OER
R/WR
WL
R/
SEML
INTL
SEMR
INTR
M/S
(2)
(2)
2942 drw 01
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY outputs and INT outputs are non-tri-stated push-pull.
MARCH 2000
1
©2000IntegratedDeviceTechnology,Inc.
DSC-2942/7
6.07
IDT70V06S/L
High-Speed 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description
address,andI/Opinsthatpermitindependent,asynchronousaccessfor
reads or writes to any location in memory. An automatic power down
featurecontrolledbyCE permitstheon-chipcircuitryofeachporttoenter
a very low standby power mode.
FabricatedusingIDT’sCMOShigh-performancetechnology,these
devices typicallyoperate ononly400mWofpower.
The IDT70V06is a high-speed16Kx8Dual-PortStaticRAM. The
IDT70V06 is designed to be used as a stand-alone 128K-bit Dual-Port
Static RAM or as a combination MASTER/SLAVE Dual-Port Static
RAM for 16-bit-or-more word systems. Using the IDT MASTER/
SLAVE Dual-Port Static RAM approach in 16-bit or wider memory
system applications results in full-speed, error-free operation without
the need for additional discrete logic.
The IDT70V06 is packaged in a ceramic 68-pin PGA and PLCC
and a 64-pin thin quad flatpack (TQFP).
This device provides two independent ports with separate control,
Pin Configurations(1,2,3)
INDEX
9
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61
60
I/O2L
I/O3L
I/O4L
I/O5L
GND
I/O6L
I/O7L
VCC
GND
I/O0R
I/O1R
I/O2R
VCC
A5L
A4L
A3L
A2L
A1L
A0L
INTL
BUSY
GND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
59
58
57
56
55
IDT70V06J
J68-1(4)
54
53
52
51
50
49
48
47
46
45
44
L
68-Pin PLCC
Top View(5)
M/
S
BUSY
R
R
INT
A0R
A1R
A2R
A3R
A4R
I/O3R
I/O4R
I/O5R
I/O6R
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
2942 drw 02
INDEX
1
2
3
4
5
6
A4L
48
47
46
I/O2L
I/O3L
I/O4L
I/O5L
GND
A3L
A2L
A1L
45
44
43
42
41
40
39
38
37
A0L
INTL
BUSYL
70V06PF
PN-64(4)
I/O
I/O
6L
7
8
9
7L
GND
VCC
GND
I/O0R
I/O1R
I/O2R
VCC
64-Pin TQFP
Top View(5)
,
M/S
BUSYR
10
11
12
INTR
A0R
A1R
A2R
A3R
A4R
13
14
15
36
35
34
33
I/O
3R
I/O
4R
I/O
5R
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. J68-1 package body is approximately .95 in x .95 in x .17 in
PN-64 package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part marking.
16
2942 drw 03
2
IDT70V06S/L
High-Speed 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Configurations(1,2,3) (con't.)
51
A5L
52
A6L
54
A8L
56
50
A4L
48
A2L
46
44
42
40
38
36
A3R
11
10
09
08
07
A0L BUSYL M/S
INTR A1R
53
A7L
49
A3L
47
A1L
45
INTL
43
GND
41
BUSYR
39
37
35
A4R
34
A5R
A0R A2R
55
A9L
32
A7R
33
A6R
57
A11L
30
A9R
31
A8R
A10L
58
A12L
60
A13L
62
SEML CEL
59
VCC
28
A11R
29
A10R
IDT70V06G
G68-1(4)
61
26
GND
27
A12R
06
05
N/C
68-Pin PGA
Top View(5)
63
24
N/C
25
A13R
65
64
22
SEMR
23
CE
04
03
02
01
R
OEL
R/WL
67
I/O0L
66
20
OER
21
R/WR
N/C
1
3
5
7
9
68
I/O1L
11
13
VCC
15
18
I/O7R
19
N/C
GND
GND
I/O7L
I/O4L
I/O
I/O
I/O
4R
2L
1R
2
4
6
8
10
12
14
16
17
I/O5L
I/O0R I/O2R I/O3R I/O5R I/O6R
VCC
E
I/O
6L
I/O3L
,
A
B
C
D
F
G
H
J
K
L
INDEX
2942 drw 04
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 1.18 in x 1.18 in x .16 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part marking.
Pin Names
Left Port
Right Port
Names
L
CE
R
CE
Chip Enable
WL
R/
WR
R/
Read/Write Enable
Output Enable
Address
OEL
OER
0L
A
13L
0R
A
13R
- A
- A
0L
7L
0R
7R
I/O - I/O
I/O - I/O
SEMR
INTR
Data Input/Output
Semaphore Enable
Interrupt Flag
Busy Flag
SEML
INTL
BUSYL
BUSYR
S
M/
Master or Slave Select
Power
CC
V
GND
Ground
2942 tbl 01
6.42
3
IDT70V06S/L
High-Speed 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table I: Non-Contention Read/Write Control
Inputs(1)
Outputs
I/O0-7
Mode
R/W
CE
H
L
OE
X
X
L
SEM
H
X
L
High-Z
DATAIN
DATAOUT
High-Z
Deselected: Power-Down
Write to Memory
H
L
H
X
H
Read Memory
X
H
X
Outputs Disabled
2942 tbl 02
NOTE:
1. A0L — A13L ≠ A0R — A13R
Truth Table II: Semaphore Read/Write Control(1)
Inputs
Outputs
R/W
H
I/O0-7
Mode
CE
H
OE
L
SEM
L
DATAOUT
Read Data in Semaphore Flag
Write I/O0 into Semaphore Flag
Not Allowed
H
X
L
DATAIN
↑
____
L
X
X
L
2942 tbl 03
NOTE:
1. There are eight semaphore flags written to via I/O0 and read from I/O0 - I/O7. These eight semaphores are addressed by A0 - A2.
4
IDT70V06S/L
High-Speed 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AbsoluteMaximumRatings(1)
MaximumOperatingTemperature
andSupplyVoltage(1)
Symbol
Rating
Commercial
& Industrial
Unit
Grade
GND
Vcc
(2)
Ambient Temperature
0OC to +70OC
VTERM
Terminal Voltage
with Respect
to GND
-0.5 to +4.6
V
+
3.3V 0.3V
Commercial
Industrial
0V
0V
Temperature
Under Bias
-55 to +125
-55 to +125
50
oC
oC
-40OC to +85OC
+
3.3V 0.3V
TBIAS
TSTG
IOUT
2942 tbl 05
NOTE:
Storage
Temperature
1. This is the parameter TA.
DC Output
Current
mA
2942 tbl 04
NOTES:
RecommendedDCOperating
Conditions
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + 0.3V.
Symbol
Parameter
Min.
3.0
0
Typ.
Max.
3.6
0
Unit
V
VCC
Supply Voltage
3.3
GND Ground
0
V
(2)
____
VIH
VIL
Input High Voltage
Input Low Voltage
2.0
VCC+0.3
0.8
V
Capacitance(TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1 )
Input Capacitance
Output Capacitance
Conditions
VIN = 3dV
VOUT = 3dV
Max. Unit
(1)
____
-0.5
V
2942 tbl 06
CIN
9
pF
NOTES:
1. VIL> -1.5V for pulse width less than 10ns.
2. VTERM must not exceed VCC +0.3V.
COUT
10
pF
2942 tbl 07
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dV references the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 3.3V ± 0.3V)
70V06S
70V06L
Min.
Symbol
|ILI|
Parameter
Test Conditions
VCC = 3.6V, VIN = 0V to VCC
VOUT = 0V to VCC
IOL = +4mA
Min.
Max.
10
Max.
5
Unit
µA
µA
V
(1)
___
___
___
___
Input Leakage Current
___
___
|ILO|
Output Leakage Current
Output Low Voltage
Output High Voltage
10
5
VOL
0.4
0.4
___
___
VOH
IOH = -4mA
2.4
2.4
V
2942 tbl 08
NOTE:
1. At Vcc < 2.0V input leakages are undefined.
6.42
5
IDT70V06S/L
High-Speed 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1) (VCC = 3.3V ± 0.3V)
70V06X15
Com'l Only
70V06X20
Com'l
& Ind
70V06X25
Com'l
& Ind
Symbol
Parameter
Test Condition
Version
COM'L
Typ.(2)
Max.
Typ.(2)
Max.
Typ.(2)
Max.
Unit
ICC
Dynamic Operating
Current
(Both Ports Active)
S
L
150
140
215
185
140
130
200
175
130
125
190
165
mA
CE = VIL, Outputs Open
SEM = VIH
f = fMAX
(3)
____
____
____
____
IND
S
L
140
130
225
195
130
125
210
180
mA
mA
mA
mA
mA
mA
mA
mA
mA
ISB1
ISB2
ISB3
ISB4
Standby Current
(Both Ports - TTL
Level Inputs)
COM'L
IND
S
L
25
20
35
30
20
15
30
25
16
13
30
25
CER = CEL = VIH
SEMR = SEML = VIH
(3)
f = fMAX
____
____
____
____
S
L
20
15
45
40
16
13
45
40
Standby Current
(One Port - TTL
Level Inputs)
COM'L
IND
S
L
85
80
120
110
80
75
110
100
75
72
110
95
CEL or CER = VIH
Active Port Outputs Open,
(3)
f=fMAX
____
____
____
____
S
L
80
75
130
115
75
72
125
110
Full Standby Current
Both Ports CEL and
CER > VCC - 0.2V,
COM'L
IND
S
L
1.0
0.2
5
2.5
1.0
0.2
5
2.5
1.0
0.2
5
2.5
(Both Ports
-
IN
V
CC
CMOS Level Inputs)
> V - 0.2V or
____
____
____
____
VIN < 0.2V, f = 0(4)
SEM = SEM > V - 0.2V
S
L
1.0
0.2
15
5
1.0
0.2
15
5
R
L
CC
Full Standby Current
(One Port -
CMOS Level Inputs)
One Port CEL or
COM'L
IND
S
L
85
80
125
105
80
75
115
100
75
70
105
90
CER > VCC - 0.2V
SEMR = SEML > VCC - 0.2V
____
____
____
____
IN
V
CC IN
> V - 0.2V or V < 0.2V
S
L
80
75
130
115
75
70
120
105
Active Port Outputs Open,
(3)
f = fMAX
2942 tbl 09a
70V06X35
Com'l
& Ind
70V06X55
Com'l
& Ind
Symbol
Parameter
Test Condition
Version
Typ.(2)
Max.
Typ.(2)
Max.
Unit
ICC
Dynamic Operating
Current
(Both Ports Active)
COM'L
S
120
115
180
155
120
115
180
155
mA
CE = VIL, Outputs Open
SEM = VIH
L
(3)
f = fMAX
IND
S
L
120
115
200
170
120
115
200
170
mA
mA
mA
mA
mA
mA
mA
mA
mA
ISB1
ISB2
ISB3
ISB4
Standby Current
(Both Ports - TTL
Level Inputs)
COM'L
IND
S
L
13
11
25
20
13
11
25
20
CER = CEL = VIH
SEMR = SEML = VIH
(3)
f = fMAX
S
L
13
11
40
35
13
11
40
35
Standby Current
(One Port - TTL
Level Inputs)
COM'L
IND
S
L
70
65
100
90
70
65
100
90
CEL or CER = VIH
Active Port Outputs Open,
(3)
f=fMAX
S
L
70
65
120
105
70
65
120
105
Full Standby Current
Both Ports CEL and
CER > VCC - 0.2V,
VIN > VCC - 0.2V or
VIN < 0.2V, f = 0(4)
COM'L
IND
S
L
1.0
0.2
5
2.5
1.0
0.2
5
2.5
(Both Ports
-
CMOS Level Inputs)
S
L
1.0
0.2
15
5
1.0
0.2
15
5
SEMR = SEML > VCC - 0.2V
Full Standby Current
(One Port -
CMOS Level Inputs)
One Port CEL or
COM'L
IND
S
L
65
60
100
85
65
60
100
85
CER
CC
> V - 0.2V
SEMR = SEML > VCC - 0.2V
IN
CC IN
> V - 0.2V or V < 0.2V
S
L
65
60
115
100
65
60
115
100
V
Active Port Outputs Open,
f = f
(3)
MAX
2942 tbl 09b
NOTES:
1. 'X' in part number indicates power rating (S or L)
2. VCC = 3.3, TA = +25°C.
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input levels of
GND to 3V.
4. f = 0 means no address or control lines change.
6
IDT70V06S/L
High-Speed 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
3.3V
3.3V
AC Test Conditions
Input Pulse Levels
GND to 3.0V
3ns Max.
1.5V
590
Ω
590
Ω
Input Rise/Fall Times
DATAOUT
BUSY
Input Timing Reference Levels
Output Reference Levels
Output Load
DATAOUT
I
NT
1.5V
5pF*
435
30pF
Ω
435
Ω
Figures 1 and 2
,
2942 tbl 10
2942 drw 05
Figure 1. AC Output Test Load
Figure 2. Output Test Load
(For tLZ, tHZ, tWZ, tOW)
*Including scope and jig.
Timing of Power-Up Power-Down
CE
tPU
tPD
ICC
ISB
,
2942 drw 06
6.42
7
IDT70V06S/L
High-Speed 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(4)
70V06X15
Com'l Only
70V06X20
Com'l
& Ind
70V06X25
Com'l
& Ind
Symbol
READ CYCLE
tRC
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
____
____
____
Read Cycle Time
15
20
25
ns
ns
ns
____
____
____
tAA
Address Access Time
15
15
20
20
25
25
____
____
____
____
____
____
Chip Enable Access Time(3)
ACE
t
Output Enable Access Time(3)
tAOE
tOH
tLZ
10
12
13
ns
ns
ns
ns
ns
ns
ns
____
____
____
Output Hold from Address Change
3
3
3
Output Low-Z Time(1,2)
____
____
____
3
3
3
____
____
____
Output High-Z Time(1,2)
tHZ
10
12
15
Chip Enable to Power Up Time(1,2)
____
____
____
tPU
0
0
0
____
____
____
Chip Disable to Power Down Time(1,2)
Semaphore Flag Update Pulse (OE or SEM)
Semaphore Address Access(3)
PD
t
15
20
25
____
____
____
tSOP
tSAA
10
10
10
____
____
____
15
20
25
ns
2942 tbl 11a
70V06X35
Com'l
& Ind
70V06X55
Com'l
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
tRC
Read Cycle Time
35
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
____
____
tAA
tACE
tAOE
tOH
tLZ
Address Access Time
35
35
55
55
Chip Enable Access Time(3)
Output Enable Access Time(3)
Output Hold from Address Change
Output Low-Z Time(1,2)
____
____
____
____
20
30
____
____
3
3
____
____
3
3
Output High-Z Time(1,2)
15
25
____
____
tHZ
tPU
tPD
tSOP
tSAA
Chip Enable to Power Up Time(1,2)
Chip Disable to Power Down Time(1,2)
Semaphore Flag Update Pulse (OE or SEM)
Semaphore Address Access(3)
0
0
____
____
____
____
35
50
____
____
15
15
____
____
35
55
ns
2942 tbl 11b
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed but not tested.
3. To access SRAM, CE = VIL, SEM = VIH.
4. 'X' in part number indicates power rating (S or L).
8
IDT70V06S/L
High-Speed 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of Read Cycles(5)
tRC
ADDR
(4)
tAA
(4)
tACE
CE
(4)
tAOE
OE
R/W
(1)
tOH
tLZ
VALID DATA(4)
DATAOUT
(2)
tHZ
BUSYOUT
(3,4)
2942 drw 07
tBDD
NOTES:
1. Timing depends on which signal is asserted las OE or CE.
2. Timing depends on which signal is de-asserted first CE or OE.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no
relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
6.42
9
IDT70V06S/L
High-Speed 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltage(5)
70V06X15
Com'l Only
70V06X20
Com'l
& Ind
70V06X25
Com'l
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
tWC
tEW
tAW
tAS
Write Cycle Time
15
12
12
0
20
15
15
0
25
20
20
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Enable to End-of-Write(3)
Address Valid to End-of-Write
Address Set-up Time(3)
Write Pulse Width
tWP
12
0
15
0
20
0
tWR
tDW
tHZ
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time(1,2)
Data Hold Time(4)
10
15
15
____
____
____
10
12
15
____
____
____
tDH
0
0
0
(1,2)
____
____
____
tWZ
tOW
tSWRD
tSPS
Write Enable to Output in High-Z
Output Active from End-of-Write(1,2,4)
SEM Flag Write to Read Time
SEM Flag Contention Window
10
12
15
____
____
____
0
5
5
0
5
5
0
5
5
____
____
____
____
____
____
ns
2942 tbl 12a
70V06X35
Com'l
& Ind
70V06X55
Com'l
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
tWC
tEW
tAW
tAS
Write Cycle Time
35
30
30
0
55
45
45
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Enable to End-of-Write(3)
Address Valid to End-of-Write
Address Set-up Time(3)
Write Pulse Width
tWP
25
0
40
0
tWR
tDW
tHZ
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time(1,2)
Data Hold Time(4)
15
30
____
____
15
25
____
____
tDH
0
0
(1,2)
____
____
tWZ
tOW
tSWRD
tSPS
Write Enable to Output in High-Z
15
25
Output Active from End-of-Write(1,2,4)
0
5
5
0
5
5
____
____
____
____
____
____
SEM Flag Write to Read Time
ns
Flag Contention Window
SEM
2942 tbl 12b
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. This parameter is guaranteed but not tested.
3. To access SRAM, CE = VIL, SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and
temperature, the actual tDH will always be smaller than the actual tOW.
5. 'X' in part number indicates power rating (S or L).
10
IDT70V06S/L
High-Speed 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,3,5,8)
tWC
ADDRESS
(7)
tHZ
OE
tAW
CE or SEM(9)
(6)
(3)
(2)
tAS
tWR
tWP
R/W
DATAOUT
DATAIN
(7)
tOW
tWZ
(4)
(4)
tDW
tDH
2942 drw 08
Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,3,5,8)
tWC
ADDRESS
tAW
(9)
CE or SEM
(6)
(3)
(2)
tWR
tAS
tEW
R/
W
tDW
tDH
DATAIN
2942 drw 09
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a LOW CE and a LOW R/W for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W low transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE, or R/W.
7. Timing depends on which enable signal is de-asserted first, CE, or R/W.
8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the
bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
9. To access SRAM, CE = VIL and SEM = VIH. To access Semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.
6.42
11
IDT70V06S/L
High-Speed 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
tSAA
tOH
A0-A2
VALID ADDRESS
VALID ADDRESS
tAW
tWR
tACE
tEW
SEM
tDW
tSOP
OUT
DATA
DATA0
DATAIN VALID
tWP tDH
VALID(2)
tAS
R/W
tSWRD
tAOE
OE
tSOP
Write Cycle
Read Cycle
2942 drw 10
NOTES:
1. CE = VIH for the duration of the above timing (both write and read cycle).
2. “DATAOUT VALID” represents all I/O's (I/O0 - I/O7) equal to the semaphore value.
Timing Waveform of Semaphore Write Contention(1,3,4)
A0"A"-A2"A"
MATCH
(2)
SIDE
"A"
R/W"A"
SEM"A"
tSPS
A0"B"-A2"B"
MATCH
(2)
SIDE
R/W"B"
SEM"B"
"B"
2942 drw 11
NOTES:
1. DOR = DOL = VIL, CER = CEL = VIH, Semaphore Flag is released from both sides (reads as ones from both sides) at cycle start.
2. “A” may be either left or right port. “B” is the opposite port from “A”.
3. This parameter is measured from R/W“A” or SEM“A” going HIGH to R/W“B” or SEM“B” going HIGH.
4. If tSPS is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.
12
IDT70V06S/L
High-Speed 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(6)
70V06X15
Com'l Ony
70V06X20
Com'l
& Ind
70V06X25
Com'l
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (M/S = VIH)
____
____
____
____
____
____
____
____
____
____
____
____
tBAA
tBDA
tBAC
tBDC
tAPS
tBDD
tWH
15
15
15
20
20
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
BUSY Access Time from Address Match
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable LOW
BUSY Disable Time from Chip Enable HIGH
Arbitration Priority Set-up Time(2)
15
17
17
____
____
____
5
5
5
____
____
____
BUSY Disable to Valid Data(3)
Write Hold After BUSY(5)
18
30
30
____
____
____
12
15
17
BUSY TIMING (M/S = VIL)
____
____
____
____
____
____
BUSY Input to Write(4)
Write Hold After BUSY(5)
PORT-TO-PORT DELAY TIMING
tWDD
Write Pulse to Data Delay(1)
tDDD
Write Data Valid to Read Data Delay(1)
tWB
0
0
0
ns
ns
tWH
12
15
17
____
____
____
____
____
____
30
25
45
35
50
35
ns
ns
2942 tbl 13a
70V06X35
Com'l
& Ind
70V06X55
Com'l
& Ind
Symbol
BUSY TIMING (M/S = VIH)
Parameter
Min.
Max.
Min.
Max.
Unit
____
____
____
____
____
____
____
____
tBAA
tBDA
tBAC
tBDC
tAPS
tBDD
tWH
20
20
20
45
40
40
ns
ns
ns
ns
ns
ns
ns
BUSY Access Time from Address Match
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable LOW
BUSY Disable Time from Chip Enable HIGH
Arbitration Priority Set-up Time(2)
20
35
____
____
5
5
____
____
BUSY Disable to Valid Data(3)
Write Hold After BUSY(5)
35
40
____
____
25
25
BUSY TIMING (M/S = VIL)
____
____
____
____
BUSY Input to Write(4)
Write Hold After BUSY(5)
PORT-TO-PORT DELAY TIMING
tWDD
Write Pulse to Data Delay(1)
tDDD
Write Data Valid to Read Data Delay(1)
tWB
0
0
ns
ns
tWH
25
25
____
____
____
____
60
45
80
65
ns
ns
2942 tbl 13b
NOTES:
1. Port-to-port delay through SRAM cells from writing port to reading port, refer to "Timing Waveform of Read With BUSY (M/S = VIH) or "Timing Waveform of Write With
Port-To-Port Delay (M/S=VIL)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited during contention.
5. To ensure that a write cycle is completed after contention.
6. "X" is part numbers indicates power rating (S or L).
6.42
13
IDT70V06S/L
High-Speed 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Port-To-Port Read and BUSY(2,4,5)
(M/S = VIH)
tWC
MATCH
ADDR"A"
R/W"A"
tWP
tDW
tDH
VALID
DATAIN "A"
(1)
tAPS
MATCH
tWDD
ADDR"B"
BUSY"B"
tBDA
tBDD
tBAA
DATAOUT "B"
VALID
(3)
tDDD
2942 drw 12
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE).
2. CEL = CER = VIL
3. OE = VIL for the reading port.
4. If M/S = VIL(slave) then BUSY is input. Then for this example BUSY“A” = VIH and BUSY“B” input is shown above.
5. All timing is the same for left and right port. Port "A" may be either left or right port. Port "B" is the port opposite from Port "A".
14
IDT70V06S/L
High-Speed 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with BUSY
tWP
R/
W"A"
(3)
tWB
BUSY"B"
(1)
tWH
(2)
R/
W"B"
2942 drw 13
NOTES:
1. tWH must be met for both BUSY input (slave) output master.
2. BUSY is asserted on Port “B” Blocking R/W“B”, until BUSY“B” goes HIGH.
3. tWB is only for the slave version.
Waveform of BUSY Arbitration Controlled by CE Timing(1) (M/S = VIH)
ADDR"A"
ADDRESSES MATCH
and "B"
CE"A"
(2)
tAPS
CE"B"
tBAC
tBDC
BUSY"B"
2942 drw 14
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing(1) (M/S = VIH)
ADDR"A"
ADDRESS "N"
(2)
tAPS
ADDR"B"
MATCHING ADDRESS "N"
tBAA
tBDA
BUSY"B"
2942 drw 15
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
6.42
15
IDT70V06S/L
High-Speed 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(1)
70V06X15
Com'l Only
70V06X20
Com'l
& Ind
70V06X25
Com'l
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
____
____
____
____
____
____
tAS
Address Set-up Time
0
0
0
ns
ns
ns
tWR
tINS
tINR
Write Recovery Time
Interrupt Set Time
0
0
0
____
____
____
15
15
20
20
20
20
____
____
____
Interrupt Reset Time
ns
2942 tbl 14a
70V06X35
Com'l
& Ind
70V06X55
Com'l
& Ind
Symbol
INTERRUPT TIMING
Parameter
Min.
Max.
Min.
Max.
Unit
____
____
____
____
tAS
Address Set-up Time
0
0
ns
ns
ns
tWR
tINS
tINR
Write Recovery Time
Interrupt Set Time
0
0
____
____
25
25
40
40
____
____
Interrupt Reset Time
ns
2942 tbl 14b
NOTE:
1. 'X' in part number indicates power rating (S or L).
Waveform of Interrupt Timing(1)
tWC
INTERRUPT SET ADDRESS(2)
ADDR"A"
(3)
(4)
tAS
tWR
CE
"A"
R/
W"A"
(3)
tINS
I
NT"B"
2942 drw 16
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. See Interrupt Truth Table III.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
16
IDT70V06S/L
High-Speed 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of Interrupt Timing(1) (con't.)
tRC
INTERRUPT CLEAR ADDRESS (2)
ADDR"B"
(3)
tAS
CE"B"
OE"B"
(3)
tINR
I
NT"B"
2942 drw 17
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. See Interrupt Truth Table III.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
Truth Table III Interrupt Flag(1)
Left Port
Right Port
R/WL
L
A13L-A0L
3FFF
X
R/WR
X
A13R-A0R
X
Function
Set Right INTR Flag
Reset Right INTR Flag
Set Left INTL Flag
CEL
L
OEL
X
INTL
X
CER
X
OER
X
INTR
(2)
L
(3)
X
X
X
X
X
L
L
3FFF
3FFE
X
H
(3)
X
X
X
X
L
L
L
X
X
X
(2)
X
L
L
3FFE
H
X
X
X
Reset Left INTL Flag
2942 tbl 15
NOTES:
1. Assumes BUSYL = BUSYR = VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
6.42
17
IDT70V06S/L
High-Speed 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table IV Address BUSY
Arbitration
Inputs
Outputs
A13L-A0L
13R-A0R
(1)
(1)
A
Function
Normal
Normal
Normal
CE
L
CER
X
BUSYL
BUSYR
X
H
X
L
NO MATCH
MATCH
H
H
H
X
H
H
MATCH
H
H
(3)
L
MATCH
(2)
(2)
Write Inhibit
2942 tbl 16
NOTES:
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYX outputs on the IDT70V06 are push
pull, not open drain outputs. On slaves the BUSYX input internally inhibits writes.
2. L if the inputs to the opposite port were stable prior to the address and enable inputs of this port. H if the inputs to the opposite port became stable after the address and enable
inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs cannot be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when
BUSYR outputs are driving LOW regardless of actual logic level on the pin.
Truth Table V Example of Semaphore Procurement Sequence(1,2,3)
Functions
D0 - D7 Left
D0 - D7 Right
Status
No Action
1
0
0
1
1
0
1
1
1
0
1
1
1
1
0
0
1
1
0
1
1
1
Semaphore free
Left Port Writes "0" to Semaphore
Right Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "1" to Semaphore
Right Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
2942 tbl 17
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V06.
2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0 - I/O7). These eight semaphores are addressed by A0 -A2.
3. CE = VIH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
Functional Description
The IDT70V06 provides two ports with separate control, address
and I/O pins that permit independent access for reads or writes to any
location in memory. The IDT70V06 has an automatic power down
featurecontrolledbyCE.TheCEcontrolson-chippowerdowncircuitry
that permits the respective port to go into a standby mode when not
selected (CE = VIH). When a port is enabled, access to the entire
memory array is permitted.
(HEX). Theleftportclearstheinterruptbyreadingaddresslocation3FFE.
Likewise,therightportinterruptflag(INTR)issetwhentheleftportwrites
tomemorylocation3FFF(HEX)andtocleartheinterruptflag(INTR),the
rightportmustreadthememorylocation3FFF.Themessage(8bits)at
3FFEor3FFFisuser-defined.Iftheinterruptfunctionisnotused,address
locations 3FFEand3FFFarenotusedas mailboxes,butas partofthe
random access memory. Refer to Truth Table III for the interrupt
operation.
Interrupts
Busy Logic
Busy Logic provides a hardware indication that both ports of the
SRAM have accessed the same location at the same time. It also
If the user chooses the interrupt function, a memory location (mail
boxormessagecenter)is assignedtoeachport. Theleftportinterrupt
flag (INTL) is set when the right port writes to memory location 3FFE
18
IDT70V06S/L
High-Speed 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
CE
BUSY
CE
MASTER
SLAVE
Dual Port
SRAM
Dual Port
SRAM
BUSY
BUSY
BUSY
(L) (R)
(L)
(R)
MASTER
Dual Port
SRAM
CE
SLAVE
Dual Port
SRAM
CE
BUSY (R)
BUSY
(R)
BUSY (R)
BUSY
BUSY
(L)
(L)
BUSY
(L)
2942 drw 18
Figure 3. Busy and chip enable routing for both width and depth expansion with IDT70V06 SRAMs.
enoughforaBUSYflagtobeoutputfromthemasterbeforetheactualwrite
allowsoneofthetwoaccessestoproceedandsignalstheothersidethat
the SRAMis “busy”. TheBUSY pincanthenbeusedtostalltheaccess
untiltheoperationon theothersideiscompleted.Ifawriteoperationhas
beenattemptedfromthesidethatreceivesaBUSYindication,thewrite
signalisgatedinternallytopreventthewritefromproceeding.
pulsecanbeinitiatedwiththeR/Wsignal. Failuretoobservethistiming
canresultinaglitchedinternalwriteinhibitsignalandcorrupteddatainthe
slave.
TheuseofBUSYlogicisnotrequiredordesirableforallapplications.
InsomecasesitmaybeusefultologicallyORtheBUSYoutputstogether
anduseanyBUSYindicationasaninterruptsourcetoflagtheeventofan
illegalorillogicaloperation.IfthewriteinhibitfunctionofBUSYlogicisnot
desirable,theBUSYlogiccanbedisabledbyplacingthepartinslavemode
with the M/S pin. Once in slave mode the BUSYpin operates solely as
apin.NormaloperationcanbeprogrammedbytyingtheBUSYpinsHIGH.
Ifdesired,unintendedwriteoperationscanbepreventedtoaportbytying
theBUSYpinforthatportLOW.
The BUSY outputs on the IDT 70V06 RAM in master mode, are
push-pull type outputs and do not require pull up resistors to operate.
If these RAMs are being expanded in depth, then the busy indication
for the resulting array requires the use of an external AND gate.
Semaphores
The IDT70V06is anextremelyfastDual-Port16Kx8CMOSStatic
RAM with an additional 8 address locations dedicated to binary
semaphore flags. These flags alloweitherprocessoronthe leftorright
sideoftheDual-PortSRAMtoclaimaprivilegeovertheotherprocessor
for functions defined by the system designer’s software. As an ex-
ample, the semaphore can be used by one processor to inhibit the
otherfromaccessingaportionoftheDual-PortSRAMoranyothershared
resource.
The Dual-Port SRAM features a fast access time, and both ports
are completelyindependentofeachother. This means thatthe activity
on the left port in no way slows the access time of the right port. Both
ports are identical in function to standard CMOS Static RAM and can
be read from, or written to, at the same time with the only possible
conflict arising from the simultaneous writing of, or a simultaneous
READ/WRITE of, a non-semaphore location. Semaphores are pro-
tected against such ambiguous situations and may be used by the
system program to avoid any conflicts in the non-semaphore portion
of the Dual-Port SRAM. These devices have an automatic power-
downfeaturecontrolledbyCE,theDual-PortSRAMenable,andSEM,
the semaphore enable. The CE and SEM pins control on-chip power
downcircuitrythatpermits the respective porttogointostandbymode
when not selected. This is the condition which is shown in Truth Table
I where CE and SEM are both HIGH.
Width Expansion with Busy Logic
Master/Slave Arrays
When expanding an IDT70V06 SRAM array in width while using
BUSYlogic,onemasterpartisusedtodecidewhichsideoftheSRAMarray
willreceiveaBUSYindication,andtooutputthatindication.Anynumber
ofslavestobeaddressedinthesameaddressrangeasthemasteruse
theBUSYsignalasawriteinhibitsignal.ThusontheIDT70V06RAMthe
BUSYpinisanoutputifthepartisusedasamaster(M/Spin=VIH),and
theBUSYpinisaninputifthepartusedasaslave(M/Spin=VIL)asshown
in Figure 3.
Systems which can best use the IDT70V06 contain multiple
processors or controllers and are typically very high-speed systems
which are software controlled or software intensive. These systems
can benefit from a performance increase offered by the IDT70V06's
hardware semaphores, which provide a lockout mechanism without
requiring complex programming.
Softwarehandshakingbetweenprocessors offers themaximumin
system flexibility by permitting shared resources to be allocated in
varyingconfigurations.TheIDT70V06doesnotuseitssemaphoreflags
If two or more master parts were used when expanding in width, a
splitdecisioncouldresultwithonemasterindicatingBUSYononeside
of the array and another master indicating BUSY on one other side of
the array. This would inhibit the write operations from one port for part
of a word and inhibit the write operations from the other port for part of
the other word.
TheBUSYarbitration,onamaster,is basedonthechipenableand
address signals only. It ignores whether an access is a read or write.
Inamaster/slavearray,bothaddressandchipenablemustbevalidlong
6.42
19
IDT70V06S/L
High-Speed 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
to control any resources through hardware, thus allowing the system output enable (OE) signals go active. This serves to disallow
designertotalflexibilityinsystemarchitecture. the semaphore from changing state in the middle of a read cycle
An advantage of using semaphores rather than the more common duetoawritecyclefromtheotherside.Becauseofthislatch,arepeated
methods of hardware arbitration is that wait states are never incurred readofasemaphoreinatestloopmustcauseeithersignal(SEMorOE)
in either processor. This can prove to be a major advantage in very togoinactive orthe outputwillneverchange.
high-speed systems.
A sequence WRITE/READ must be used by the semaphore in
order to guarantee that no system level contention will occur. A
processor requests access to shared resources by attempting to write
a zero into a semaphore location. If the semaphore is already in use,
the semaphore request latch will contain a zero, yet the semaphore
flag will appear as one, a fact which the processor will verify by the
subsequent read (see Table V). As an example, assume a processor
writes a zero to the left port at a free semaphore location. On a
subsequent read, the processor will verify that it has written success-
fully to that location and will assume control over the resource in
question. Meanwhile, if a processor on the right side attempts to write
a zero to the same semaphore flag it will fail, as will be verified by the
factthataonewillbereadfromthatsemaphoreontherightsideduring
subsequent read. Had a sequence of READ/WRITE been used
instead, system contention problems could have occurred during the
gap between the read and write cycles.
It is important to note that a failed semaphore request must be
followed by either repeated reads or by writing a one into the same
location. The reason for this is easily understood by looking at the
simple logic diagram of the semaphore flag in Figure 4. Two sema-
phore request latches feed into a semaphore flag. Whichever latch is
first to present a zero to the semaphore flag will force its side of the
semaphore flag LOW and the other side HIGH. This condition will
continue until a one is written to the same semaphore request latch.
Should the other side’s semaphore request latch have been written to
a zero in the meantime, the semaphore flag will flip over to the other
side as soon as a one is written into the first side’s request latch. The
secondside’s flagwillnowstay LOWuntilits semaphore requestlatch
is written to a one. From this it is easy to understand that, if a
semaphore is requested and the processor which requested it no
longer needs the resource, the entire system can hang up until a one
is written into that semaphore request latch.
How the Semaphore Flags Work
The semaphore logic is a set of eight latches which are indepen-
dentofthe Dual-PortSRAM. These latches canbe usedtopass a flag,
or token, from one port to the other to indicate that a shared resource
is in use. The semaphores provide a hardware assist for a use
assignmentmethodcalled“TokenPassingAllocation.”Inthis method,
the state of a semaphore latch is used as a token indicating that a
shared resource is in use. If the left processor wants to use this
resource,itrequeststhetokenbysettingthelatch.Thisprocessorthen
verifiesitssuccessinsettingthelatchbyreadingit.Ifitwassuccessful,
it assumes control over the shared resource. If it was not successful
in setting the latch, it determines that the right side processor has set
the latch first, has the token and is using the shared resource. The left
processor can then either repeatedly request that semaphore’s status
or remove its request for that semaphore to perform another task and
occasionally attempt again to gain control of the token via the set and
test sequence. Once the right side has relinquished the token, the left
side should succeed in gaining control.
The semaphore flags are active LOW. A token is requested by
writing a zero into a semaphore latch and is released when the same
side writes a one to that latch.
The eight semaphore flags reside within the IDT70V06 in a
separate memory space from the Dual-Port SRAM. This address
space is accessed by placing a LOW input on the SEM pin (which
acts as a chip select for the semaphore flags) and using the other
control pins (Address, OE, and R/W) as they would be used in
accessing a standard Static RAM. Each of the flags has a unique
address which can be accessed by either side through address pins
A0 – A2. When accessing the semaphores, none of the other address
pins has any effect.
The critical case of semaphore timing is when both sides request
a single tokenbyattemptingtowrite a zerointoitatthe same time. The
semaphore logic is specially designed to resolve this problem. If
simultaneous requests are made, the logic guarantees that only one
side receives the token. If one side is earlier than the other in making
the request, the first side to make the request will receive the token. If
bothrequests arriveatthesametime,theassignmentwillbearbitrarily
made to one port or the other.
One caution that should be noted when using semaphores is that
semaphores alone do not guarantee that access to a resource is
secure. As with any powerful programming technique, if semaphores
are misused or misinterpreted, a software error can easily happen.
Initialization of the semaphores is not automatic and must be
handled via the initialization program at power-up. Since any sema-
phore request flag which contains a zero must be reset to a one, all
semaphores on both sides should have a one written into them at
initialization from both sides to assure that they will be free when
needed.
Whenwritingtoasemaphore,onlydatapinD0 isused.Ifalowlevel
is written into an unused semaphore location, that flag will be set to a
zero on that side and a one on the other side (see Truth Table V). That
semaphore can now only be modified by the side showing the zero.
When a one is written into the same location from the same side, the
flag will be set to a one for both sides (unless a semaphore request
fromtheothersideispending)andthencanbewrittentobybothsides.
The fact that the side which is able to write a zero into a semaphore
subsequently locks out writes from the other side is what makes
semaphore flags useful in interprocessor communications. (A thor-
ough discussion on the use of this feature follows shortly.) A zero
written into the same location from the other side will be stored in the
semaphore request latch for that side until the semaphore is freed by
the first side.
Whena semaphore flagis read, its value is spreadintoalldata bits
so that a flag that is a one reads as a one in all data bits and a flag
containinga zeroreads as allzeros. The readvalue is latchedintoone
side’s output register when that side's semaphore select (SEM) and
20
IDT70V06S/L
High-Speed 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
UsingSemaphoresSomeExamples
Perhapsthesimplestapplicationofsemaphoresistheirapplicationas
resource markers for the IDT70V06’s Dual-Port SRAM. Say the 16K x
8 SRAM was to be divided into two 8K x 8 blocks which were to be
dedicatedatanyonetimetoservicingeithertheleftorrightport.Semaphore
0couldbeusedtoindicatethesidewhichwouldcontrolthelowersection
of memory, and Semaphore 1 could be defined as the indicator for the
uppersectionofmemory.
To take a resource, in this example the lower 8K of Dual-Port
SRAM,theprocessorontheleftportcouldwriteandthenreadazeroin
toSemaphore0.Ifthistaskweresuccessfullycompleted(azerowasread
backratherthana one), the leftprocessorwouldassume controlofthe
lower8K.Meanwhiletherightprocessorwasattemptingtogaincontrolof
the resourceaftertheleftprocessor,itwouldreadbackaoneinresponse
tothezeroithadattemptedtowriteintoSemaphore0.Atthis point,the
softwarecouldchoosetotryandgaincontrolofthesecond8Ksectionby
writing,thenreadingazerointoSemaphore1.Ifitsucceededingaining
control,itwouldlockouttheleftside.
Once the left side was finished with its task, it would write a one to
Semaphore 0 and may then try to gain access to Semaphore 1. If
Semaphore 1 was still occupied by the right side, the left side could
undo its semaphore request and perform other tasks until it was able
to write, then read a zero into Semaphore 1. If the right processor
performsasimilartaskwithSemaphore0,thisprotocolwouldallowthe
twoprocessors toswap8Kblocks ofDual-PortSRAMwitheachother.
The blocks do not have to be any particular size and can even be
variable, depending upon the complexity of the software using the
semaphore flags. All eight semaphores could be used to divide the
Dual-PortSRAMorothersharedresourcesintoeightparts.Semaphores
canevenbeassigneddifferentmeaningsondifferentsidesratherthan
being given a common meaning as was shown in the example above.
Semaphores are a useful form of arbitration in systems like disk
interfaces where the CPU must be locked out of a section of memory
during a transfer and the I/O device cannot tolerate any wait states.
With the use of semaphores, once the two devices has determined
which memory area was “off-limits” to the CPU, both the CPU and the
I/O devices could access their assigned portions of memory continu-
ously without any wait states.
Semaphores are also useful in applications where no memory
“WAIT” state is available on one or both sides. Once a semaphore
handshake has been performed, both processors can access their
assignedSRAMsegmentsatfullspeed.
Anotherapplicationisintheareaofcomplexdatastructures.Inthis
case, block arbitration is very important. For this application one
processor may be responsible for building and updating a data
structure. The other processor then reads and interprets that data
structure. If the interpreting processor reads an incomplete data
structure, a major error condition may exist. Therefore, some sort of
arbitration must be used between the two different processors. The
building processor arbitrates for the block, locks it and then is able to
goinandupdatethedatastructure.Whentheupdateiscompleted,the
data structure blockis released. This allows the interpretingprocessor
to come back and read the complete data structure, thereby guaran-
teeing a consistent data structure.
L PORT
R PORT
SEMAPHORE
REQUEST FLIP FLOP
SEMAPHORE
REQUEST FLIP FLOP
D0
D0
D
D
Q
Q
WRITE
WRITE
SEMAPHORE
READ
SEMAPHORE
READ
,
2942 drw 19
Figure 4. IDT70V06 Semaphore Logic
6.42
21
IDT70V06S/L
High-Speed 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Ordering Information
IDT XXXXX
A
999
A
A
Device
Type
Power Speed
Package
Process/
Temperature
Range
Blank
I(1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
PF
G
J
64-pin TQFP (PN64-1)
68-pin PGA (G68-1)
68-pin PLCC (J68-1)
15
20
25
35
55
Commercial Only
Commercial & Industrial
Speed in Nanoseconds
Commercial & Industrial
Commercial & Industrial
Commercial & Industrial
S
L
Standard Power
Low Power
70V06 128K (16K x 8) 3.3V Dual-Port RAM
2942 drw 20
Datasheet Document History
3/10/99:
Initiated datasheet document history
Converted to new format
Cosmetic and typographical corrections
Page 2 and 3 Added additional notes to pin configurations
Changeddrawingformat
6/9/99:
11/10/99:
3/10/00:
Replaced IDT logo
Added 15 & 20ns speed grades
UpgradedDCparameters
AddedIndustrialTemperatureinformation
Changed±200mVto0mV
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22
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