IDT70T3519S133BC [IDT]
HIGH-SPEED 2.5V 256/128/64K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE; HIGH -SPEED 2.5V一百二十八分之二百五十六/ 64K ×36同步双端口静态3.3V或2.5V接口RAM
| 型号： | IDT70T3519S133BC |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | HIGH-SPEED 2.5V 256/128/64K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE |
| 文件： | 总28页 (文件大小：431K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HIGH-SPEED 2.5V
256/128/64K x 36
IDT70T3519/99/89S
SYNCHRONOUS
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
Features:
– Data input, address, byte enable and control registers
– Self-timedwriteallowsfastcycletime
Separate byte controls for multiplexed bus and bus
matching compatibility
Dual Cycle Deselect (DCD) for Pipelined Output Mode
2.5V (±100mV) power supply for core
LVTTL compatible, selectable 3.3V (±150mV) or 2.5V
(±100mV) power supply for I/Os and control signals on
each port
Industrial temperature range (-40°C to +85°C) is
available at 166MHz and 133MHz
Available in a 256-pin Ball Grid Array (BGA), a 208-pin
Plastic Quad Flatpack (PQFP) and 208-pin fine pitch Ball
Grid Array (fpBGA)
Supports JTAG features compliant with IEEE 1149.1
Due to limited pin count JTAG is not supported on the 208-
pin PQFP package
◆
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed data access
◆
◆
– Commercial: 3.4 (200MHz)/3.6ns (166MHz)/
4.2ns (133MHz)(max.)
◆
◆
◆
– Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)
Selectable Pipelined or Flow-Through output mode
Counter enable and repeat features
Dual chip enables allow for depth expansion without
additional logic
Interrupt and Collision Detection Flags
Full synchronous operation on both ports
– 5ns cycle time, 200MHz operation (14Gbps bandwidth)
– Fast 3.4ns clock to data out
◆
◆
◆
◆
◆
◆
◆
◆
◆
– 1.5ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 200MHz
FunctionalBlockDiagram
BE3R
BE3L
BE2L
BE1L
BE0L
BE2R
BE1R
BE0R
FT/PIPE
L
0a 1a
a
0b 1b
b
0c 1c
c
0d 1d
d
1d 0d
d
1c 0c
c
1b 0b
b
1a 0a
a
FT/PIPER
1/0
1/0
R/WL
R/WR
CE0L
CE0R
1
1
CE1R
CE1L
0
0
B
B B B
B
B B B
1/0
1/0
W W W W W W W W
0
L
1
L
2
L
3
L
3
R
2
1
R
0
R
R
OE
R
OE
L
Dout0-8_L
Dout0-8_R
Dout9-17_L
Dout18-26_L
Dout27-35_L
Dout9-17_R
Dout18-26_R
Dout27-35_R
,
1d 0d 1c 0c
1b 0b 1a 0a
0a 1a 0b 1b
0c 1c 0d 1d
d c b a
0/1
0/1
FT/PIPE
R
FT/PIPE
L
a bc d
256/128/64K x 36
MEMORY
ARRAY
I/O0L - I/O35L
I/O0R - I/O35R
Din_L
Din_R
,
CLK
R
CLK
L
(1)
17R
(1)
17L
A
A
Counter/
Address
Reg.
Counter/
Address
Reg.
A
0L
REPEAT
ADS
A
0R
REPEAT
ADS
CNTEN
ADDR_R
ADDR_L
L
R
R
L
R
CNTEN
L
TDI
TCK
TMS
TRST
INTERRUPT
CE0
CE1
R
CE
0
L
JTAG
COLLISION
DETECTION
LOGIC
R
CE1
TDO
L
R/
W
L
R/W
R
COL
L
COL
R
INT
L
INT
R
(2)
(2)
ZZR
ZZ
CONTROL
LOGIC
ZZ
L
5666 drw 01
NOTES:
1. Address A17 is a NC for the IDT70T3599. Also, Addresses A17 and A16 are NC's for the IDT70T3589.
2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and OPTx
APRIL 2004
and the sleep mode pins themselves (ZZx) are not affected during sleep mode.
1
DSC 5666/6
©2004IntegratedDeviceTechnology,Inc.
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Description:
The IDT70T3519/99/89 is a high-speed 256/128/64K x 36 bit tionalorbidirectionaldataflowinbursts.Anautomaticpowerdownfeature,
synchronous Dual-Port RAM. The memory array utilizes Dual-Port controlled by CE0 and CE1, permits the on-chip circuitry of each port to
memorycellstoallowsimultaneousaccessofanyaddressfrombothports. enter a very low standby power mode.
Registersoncontrol,data,andaddressinputsprovideminimalsetupand
The70T3519/99/89 cansupportanoperatingvoltageofeither3.3V
holdtimes.Thetiminglatitudeprovidedbythisapproachallowssystems or 2.5V on one or both ports, controllable by the OPT pins. The power
tobedesignedwithveryshortcycletimes.Withaninputdataregister,the supply for the core of the device (VDD) is at 2.5V.
IDT70T3519/99/89hasbeenoptimizedforapplicationshavingunidirec-
6.42
2
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Pin Configuration (3,4,5,6,9)
70T3519/99/89BC
BC-256(7)
256-Pin BGA
Top View(8)
06/19/02
A1
A2
A3
A6
A7
A8
A9
A11
A12
A13
A14
A4
A5
A10
A15
A16
(1)
NC
TDI
NC
A
11L
A
8L
9L
7L
BE2L CE1L
CNTEN
L
A
5L
A
2L
A
0L
A
17L
A
14L
OE
L
NC
NC
B1
B2
B3
B6
B7
B9
CE0L
B11
B12
B13
B4
B5
B8
B10
B14
B15
B16
I/O18L NC TDO
A
12L
10L
A
REPEAT
L
A4L
A
1L
NC
A
15L
BE3L
R/W
L
VDD I/O17L NC
C1
C5
C6
C2
C3
C4
C7
C8
C9
C10
C11
C12
C13
C16
C14
C15
(2)
16L
I/O18R
A
13L
A
I/O19L
V
SS
A
BE1L BE0L CLK
L
ADS
L
A
6L
A
3L
I/O16L
A
OPT
L
I/O17R
D1
D2
D6
DDQL
D9
D11
DDQR
D3
D5
VDDQL
L
D7
DDQR
D8
D10
D12
D13
D14
D15
D16
D4
I/O20R I/O19R
V
VDDQL
V
VDDQL
I/O20L
V
V
DDQR
VDDQR
VDD I/O15R I/O15L I/O16R
PIPE/FT
E6
E5
E7
E8
E9
E10
E11
E12
E13
E1
E2
E3
E4
E14
E16
E15
V
DD
V
DD
INT
L
V
SS
SS
SS
V
SS
V
SS
V
DD
V
DD
V
DDQR
I/O21R I/O21L I/O22L
V
DDQL
I/O13L
I/O14R
I/O14L
F7
F1 F2 F3
F5
F6
F9
F10
F14
F15
F16
F11
F13
F4
F8
F12
COL
L
VDD
NC
VSS
V
SS
I/O23L I/O22R I/O23R
G1
VSS
VDDQR I/O12R I/O13R I/O12L
V
VDD
V
DDQL
G5
G2
G4
G6
G8
G9
G3
G7
G10
G12
G13 G14 G15 G16
G11
I/O24R
V
SS
I/O24L
V
DDQR
VSS
V
V
SS
SS
I/O25L
I/O10L I/O11L I/O11R
H16
VSS
V
SS
VSS
V
DDQL
VSS
H11
H12
H13
H7
H8
H9
H10
H14
H15
H3
H4
H5
H6
H1
H2
V
SS
VSS
VDDQL
I/O10R
VSS
VSS
V
V
SS
SS
I/O9R IO9L
V
SS
VSS
I/O26R
V
DDQR
I/O26L I/O25R
J1
J2
J3
J4
J5
J6
J7
J8
J9
J13
J10
J11
J12
J14
J15
J16
I/O27L
I/O28R I/O27R
V
DDQL ZZ
R
V
SS
V
SS
VSS
VSS
VDDQR
V
VSS
ZZ
L
I/O8R
I/O7R I/O8L
K6
K8
K10
K12
K13
K5
K7
L7
K9
K11
K2
K4
K15
K16
K1
K3
K14
V
SS
V
SS
V
SS
SS
VSS
VDDQR
I/O29L
VDDQL
V
SS
V
SS
V
SS
V
SS
I/O6L I/O7L
I/O29R
I/O28L
I/O6R
L8
M8
N8
L11
L12
L13
L3
L4
L5
L6
L9
L10
L15
L16
L1
L2
L14
COL
R
V
SS
V
SS
V
DD
VDDQL
I/O30R
V
DDQR
V
DD
NC
V
SS
V
I/O4R I/O5R
I/O30L I/O31R
I/O5L
M5
M6
M7
M9
M10
M11
M12
M13
M1 M2
M3
M4
M16
M14
M15
V
DD
V
DD INT
R
V
SS
V
SS
V
SS
V
DD
VDD
VDDQL
I/O32R I/O32L I/O31L
V
DDQR
I/O4L
I/O3R I/O3L
N12
N16
N13
N4
N5
N6
DDQR
N7
N9
N10
N11
N15
N1
N2
N3
N14
VDDQL
VDDQL
VDD
I/O2R
I/O1R
VDDQR
V
VDDQL
VDDQR
VDDQR
V
DDQL
PIPE/FT
R
I/O33L I/O34R I/O33R
I/O2L
P1
P2
P3
P4
P5
P7
P8
P9
P10
P11
P12
P14
P15
P16
P6
P13
(2)
A
16R
I/O35R I/O34L TMS
A
13R
A
7R BE1R BE0R CLK
R
ADS
R
A
6R
I/O0L I/O0R I/O1L
A
10R
A
3R
R5
R6
R7
R8
R9
R10
R11
R16
R1
R2
R3
R4
R12
R13
R14
R15
,
A
15R
A
12R
A
9R
BE3R CE0R R/W
R
REPEAT
R
NC
I/O35L NC TRST NC
A
4R
A1R OPT
R
NC
T2
T3
T4
17R
T1
T5
T8
T9
T15
T16
T6
T7
T10
T11
T12
T13
T14
(1)
A
TCK
NC
NC
A
14R
BE2R CE1R
NC
NC
A
11R
A
8R
OE
R
CNTEN
R
A
5R
A
2R
A0R
5666 drw 02d
NOTES:
1. Pin is a NC for IDT70T3599 and IDT70T3589.
2. Pin is a NC for IDT70T3589.
3. All VDD pins must be connected to 2.5V power supply.
,
4. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V), and 2.5V if OPT pin for that port is
set to VSS (0V).
5. All VSS pins must be connected to ground supply.
6. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.
7. This package code is used to reference the package diagram.
8. This text does not indicate orientation of the actual part-marking.
9. Pins A15 and T15 will be VREFL and VREFR respectively for future HSTL device.
6.42
3
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Pin Configuration (3,4,5,6,9,10) (con't.)
06/19/02
I/O16L
156
1
2
3
4
I/O19L
I/O19R
I/O20L
I/O20R
I/O16R
155
I/O15L
154
I/O15R
153
VSS
5
VDDQL
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
V
DDQL
6
7
8
9
V
SS
I/O14L
I/O14R
I/O13L
I/O13R
I/O21L
I/O21R
I/O22L
I/O22R
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
VSS
V
DDQR
VDDQR
VSS
I/O12L
I/O12R
I/O11L
I/O11R
I/O23L
I/O23R
I/O24L
I/O24R
VSS
V
DDQL
VDDQL
VSS
I/O10L
I/O10R
I/O9L
I/O25L
I/O25R
I/O26L
I/O26R
I/O9R
V
V
V
V
V
V
SS
V
DDQR
DDQR
DD
70T3519/99/89DR
ZZ
R
VDD
(7)
DD
VDD
DR-208
SS
V
V
SS
SS
SS
ZZ
L
V
DDQL
VDDQL
208-Pin PQFP
VSS
I/O8R
I/O8L
I/O7R
I/O7L
I/O27R
I/O27L
I/O28R
I/O28L
(8)
Top View
VSS
V
DDQR
VDDQR
VSS
I/O6R
I/O6L
I/O5R
I/O5L
I/O29R
I/O29L
I/O30R
I/O30L
VSS
V
DDQL
VDDQL
VSS
I/O4R
I/O4L
I/O3R
I/O3L
I/O31R
I/O31L
I/O32R
I/O32L
VSS
V
DDQR
VDDQR
VSS
I/O2R
I/O2L
I/O1R
I/O1L
I/O33R
I/O33L
I/O34R
I/O34L
,
5666 drw 02a
NOTES:
1. Pin is a NC for IDT70T3599 and IDT70T3589.
2. Pin is a NC for IDT70T3589.
3. All VDD pins must be connected to 2.5V power supply.
4. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V), and 2.5V if OPT pin for that port is set to Vss (0V).
5. All VSS pins must be connected to ground supply.
6. Package body is approximately 28mm x 28mm x 3.5mm.
7. This package code is used to reference the package diagram.
8. This text does not indicate orientation of the actual part-marking.
9. Due to limited pin count, JTAG is not supported in the DR-208 package.
10. Pins 162 and 99 will be VREFL and VREFR respectively for future HSTL device.
6.42
4
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Pin Configuration (3,4,5,6,9) (con't.)
01/23/03
A1
A2
A3
A6
A7
A8
A9
BE1L
A11
A12
A13
A14
A17
A4
A10
A15
A16
A5
(2)
16L
I/O19L I/O18L
V
SS
A
12L
A
8L
CLK
L
CNTEN
L
A4L
A
0L
V
SS
TDO
A
V
DD
OPT
L
I/O17L
COL
L
B1
B2
B3
B6
B7
B9
CE0L
B11
B12
B13
B17
B4
B5
B8
B10
B14
B15
B16
(1)
I/O20R
V
SS I/O18R
A17L
A
13L
A
9L
ADS
L
A
5L
A
1L
I/O15R
TDI
BE2L
V
SS
NC
V
DDQR I/O16L
C1
C6
C2
C3
C4
C5
C7
C8
C9
C10
C11
C12
C13
C16
C14
C15
C17
V
DDQL
A
14L
11L
I/O19R
V
DDQR PL/FT
L
INT
L
A
10L BE3L CE1L
V
SS R/W
L
A
6L
A
2L
I/O15L
V
DD I/O16R
V
SS
D1
D2
D6
D9
D11
REPEATL
D3
D5
D7
D8
D10
D12
D13
D14
D15
D16
D17
D4
I/O22L
V
SS
A
V
DD
I/O21L
A
15L
A
7L BE0L
OE
L
A
3L
V
DD I/O17R
V
DDQL I/O14L I/O14R
I/O20L
E1
E2
E3
E4
E14
E16
E17
E15
I/O23L I/O22R
V
DDQR I/O21R
I/O12L
V
SS I/O13L
I/O13R
F1
F2
F3
F14
F15
F16
F17
F4
V
DDQL I/O23R I/O24L
VSS I/O12R I/O11L VDDQR
V
SS
G1
G2
G4
G14
G15
G16
G3
G17
I/O26L
V
SS
I/O24R
I/O9L
V
DDQL I/O10L
I/O25L
I/O11R
H3
H4
H1
H2
H16
H17
H14
H15
70T3519/99/89BF
BF-208(7)
V
DDQR I/O25R
V
DD I/O26R
V
SS I/O10R
V
DD I/O9R
J1
J2
J3 J4
J14
J15
J16
J17
V
DDQL
V
DD
SS
V
SS
ZZ
R
ZZ
L
V
DD
V
SS
VDDQR
208-Pin fpBGA
Top View(8)
K2
K4
K15
K16
K1
K3
K14
K17
V
V
SS
VDDQL I/O8R
I/O7R
I/O28R
I/O27R
V
SS
L3
L4
L15
L16
L17
L1
L2
L14
V
DDQR I/O27L
I/O7L
V
SS
I/O8L
I/O29R I/O28L
I/O6R
M1
M2
M3
M4
M16
M17
DDQR
M14
M15
VDDQL I/O29L I/O30R
V
SS
I/O5R V
V
SS
I/O6L
N16
N17
N4
N15
N1
N2
N3
N14
I/O4R I/O5L
DDQL
I/O30L
V
I/O31L
V
SS I/O31R
I/O3R
P12
P1
P2
P3
P4
P5
P7
P8
P9
P10
P11
P14
P15
P16
P17
P6
P13
(2)
A
16R
I/O32R I/O32L
V
DDQR I/O35R TRST
A
12R
A
8R BE1R
V
DD CLK
R
I/O2L I/O3L
V
SS I/O4L
CNTEN
R
A
4R
R5
R6
R7
R8
R9
R10
R11
R16
R1
R2
R3
R4
R12
R13
R14
R17
R15
(1)
A
17R
A
13R
A
9R
BE2R CE0R
V
SS ADS
R
R
I/O1R
V
SS I/O33L I/O34R TCK
A
5R
A
1R
2R
NC
V
DDQR
V
DDQL
T2
I/O34L
T3
T1
T4
T5
T8
T9
T15
T16
T17
T6
T7
T10
T11
T12
T13
T14
SS
V
DDQL
TMS INT
I/O33R
R
BE3R CE1R
I/O0R
V
SS I/O2R
A
14R
A
10R
V
SS R/W
A
6R
A
V
U1
U2
U3
U4
U5
U6
U7
U17
U8
BE0R
U9
U10
U12
U13
U14
DD
U16
U15
V
SS I/O35L PL/FT
R
COL
R
A
15R
A
11R
A
7R
I/O1L
V
DD OE
R
A3R
A
0R
V
I/O0L
OPT
R
5666 drw 02c
NOTES:
1. Pin is a NC for IDT70T3599 and IDT70T3589.
2. Pin is a NC for IDT70T3589.
3. All VDD pins must be connected to 2.5V power supply.
4. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V), and 2.5V if OPT pin for that port is
set to VSS (0V).
5. All VSS pins must be connected to ground supply.
6. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.
7. This package code is used to reference the package diagram.
8. This text does not indicate orientation of the actual part-marking.
9. Pins B14 and R14 will be VREFL and VREFR respectively for future HSTL device.
6.42
5
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
PinNames
Left Port
Right Port
CE0R CE1R
R/W
OE
Names
Chip Enables (Input)(7)
CE0L
R/W
OE
,
CE1L
,
L
R
Read/Write Enable (Input)
Output Enable (Input)
L
R
(6)
(6)
A
0L - A17L
A
0R - A17R
I/O0R - I/O35R
CLK
PL/FT
ADS
CNTEN
REPEAT
BE0R - BE3R
Address (Input)
I/O0L - I/O35L
CLK
PL/FT
ADS
CNTEN
REPEAT
BE0L - BE3L
Data Input/Output
L
R
Clock (Input)
L
R
Pipeline/Flow-Through (Input)
Address Strobe Enable (Input)
Counter Enable (Input)
Counter Repeat(3)
L
R
L
R
L
R
Byte Enables (9-bit bytes) (Input)(7)
Power (I/O Bus) (3.3V or 2.5V)(1) (Input)
Option for selecting VDDQX(1,2) (Input)
Sleep Mode pin(4) (Input)
Power (2.5V)(1) (Input)
V
DDQL
V
DDQR
R
OPT
L
OPT
ZZ
ZZL
R
V
V
DD
SS
NOTES:
1. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to
applying inputs on the I/Os and controls for that port.
Ground (0V) (Input)
TDI(5)
TDO(5)
TCK(5)
TMS(5)
Test Data Input
2. OPTX selects the operating voltage levels for the I/Os and controls on that port.
If OPTX is set to VDD (2.5V), then that port's I/Os and controls will operate at 3.3V
levels and VDDQX must be supplied at 3.3V. If OPTX is set to VSS (0V), then that
port's I/Os and address controls will operate at 2.5V levels and VDDQX must be
supplied at 2.5V. The OPT pins are independent of one another—both ports can
operate at 3.3V levels, both can operate at 2.5V levels, or either can operate
at 3.3V with the other at 2.5V.
Test Data Output
Test Logic Clock (10MHz) (Input)
Test Mode Select (Input)
Reset (Initialize TAP Controller) (Input)
Interrupt Flag (Output)
(5)
TRST
3. When REPEATX is asserted, the counter will reset to the last valid address loaded
via ADSX.
INT
R
INT
L
4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when
asserted. All static inputs, i.e., PL/FTx and OPTx and the sleep mode pins
themselves (ZZx) are not affected during sleep mode. It is recommended that
boundry scan not be operated during sleep mode.
COL
R
COL
L
Collision Alert (Output)
5666 tbl 01
5. Due to limited pin count, JTAG is not supported in the DR-208 package.
6. Address A17x is a NC for the IDT70T3599. Also, Addresses A17x and A16x are
NC's for the IDT 70T3589.
7. Chip Enables and Byte Enables are double buffered when PL/FT = VIH, i.e., the
signals take two cycles to deselect.
6.42
6
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
(1,2,3,4)
Truth Table I—Read/Write and Enable Control
Byte 3
I/O27-35
Byte 2
I/O18-26
Byte 1
I/O9-17
Byte 0
I/O0-8
CLK
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
X
CE
1
R/W
X
X
X
L
ZZ
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
MODE
OE
X
X
X
X
X
X
X
X
X
X
L
CE
0
BE
3
BE
2
BE
1
BE0
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
X
X
X
H
H
H
H
L
X
X
H
H
H
L
X
X
H
H
L
X
X
H
L
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z Deselected–Power Down
High-Z Deselected–Power Down
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
High-Z
All Bytes Deselected
Write to Byte 0 Only
Write to Byte 1 Only
Write to Byte 2 Only
Write to Byte 3 Only
Write to Lower 2 Bytes Only
Write to Upper 2 bytes Only
Write to All Bytes
DIN
H
H
H
L
L
DIN
High-Z
High-Z
High-Z
H
H
L
L
DIN
High-Z
High-Z
H
H
L
L
DIN
High-Z
High-Z
H
L
L
High-Z
DIN
DIN
H
L
H
L
L
D
IN
IN
DIN
High-Z
High-Z
L
L
L
D
DIN
DIN
DIN
H
H
H
L
H
H
L
H
L
L
H
H
H
H
H
H
H
X
X
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
DOUT
Read Byte 0 Only
L
H
H
H
L
DOUT
High-Z Read Byte 1 Only
High-Z Read Byte 2 Only
High-Z Read Byte 3 Only
L
H
H
L
DOUT
High-Z
High-Z
L
H
H
L
DOUT
High-Z
High-Z
L
H
L
High-Z
DOUT
DOUT
Read Lower 2 Bytes Only
High-Z Read Upper 2 Bytes Only
Read All Bytes
L
H
L
H
L
D
OUT
OUT
D
OUT
OUT
High-Z
L
L
L
D
D
DOUT
DOUT
H
X
X
X
X
X
X
X
X
X
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z Outputs Disabled
High-Z Sleep Mode
X
5666 tbl 02
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, REPEAT = VIH.
3. OE and ZZ are asynchronous input signals.
4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.
(1,2)
Truth Table II—Address Counter Control
Previous
Internal
Address
Internal
Address
Used
MODE
ADS CNTEN REPEAT(6)
Address
CLK
↑
I/O(3)
I/O (n) External Address Used
I/O(n+1) Counter Enabled—Internal Address generation
I/O(n+1) External Address Blocked—Counter disabled (An + 1 reused)
I/O(n) Counter Set to last valid ADS load
An
X
X
An
An
L(4)
X
H
H
D
An + 1
An + 1
An
H
L(5)
H
D
D
↑
X
An + 1
X
H
H
↑
X
X
X
L(4)
D
↑
5666 tbl 03
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. Read and write operations are controlled by the appropriate setting of R/W, CE0, CE1, BEn and OE.
3. Outputs configured in flow-through output mode: if outputs are in pipelined mode the data out will be delayed by one cycle.
4. ADS and REPEAT are independent of all other memory control signals including CE0, CE1 and BEn
5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE1, BEn.
6. When REPEAT is asserted, the counter will reset to the last valid address loaded via ADS. This value is not set at power-up: a known location should be loaded
via ADS during initialization if desired. Any subsequent ADS access during operations will update the REPEAT address location.
6.42
7
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
RecommendedOperating
(1)
Temperature and Supply Voltage
Ambient
Grade
Commercial
Temperature
0OC to +70OC
-40OC to +85OC
GND
0V
V
+
+
DD
2.5V
2.5V
100mV
100mV
Industrial
0V
5666 tbl 04
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
RecommendedDCOperating
Conditions with VDDQ at 2.5V
Symbol
Parameter
Core Supply Voltage
I/O Supply Voltage(3)
Ground
Min.
2.4
2.4
0
Typ.
2.5
2.5
0
Max.
Unit
V
V
DD
DDQ
SS
2.6
2.6
0
V
V
V
V
Input High Volltage
(Address, Control &
Data I/O Inputs)(3)
____
V
DDQ + 100mV(2)
1.7
1.7
V
V
V
IH
IH
Input High Voltage _
JTAG
____
V
V
DD + 100mV(2)
Input High Voltage -
ZZ, OPT, PIPE/FT
____
____
____
VIH
VIL
VIL
V
DD - 0.2V
-0.3(1)
V
DD + 100mV(2)
V
V
Input Low Voltage
0.7
0.2
Input Low Voltage -
ZZ, OPT, PIPE/FT
-0.3(1)
V
5666 tbl 05a
NOTES:
1. VIL (min.) = -1.0V for pulse width less than tCYC/2 or 5ns, whichever is less.
2. VIH (max.) = VDDQ + 1.0V for pulse width less than tCYC/2 or 5ns, whichever is less.
3. To select operation at 2.5V levels on the I/Os and controls of a given port, the OPT
pinforthatportmustbesettoVss(0V), andVDDQX forthatportmustbesuppliedasindicated
above.
RecommendedDCOperating
Conditions with VDDQ at 3.3V
Symbol
Parameter
Core Supply Voltage
I/O Supply Voltage(3)
Ground
Min.
2.4
3.15
0
Typ.
2.5
3.3
0
Max.
2.6
3.45
0
Unit
V
V
DD
DDQ
SS
V
V
V
V
Input High Voltage
(Address, Control
&Data I/O Inputs)(3)
____
2.0
1.7
V
DDQ + 150mV(2)
V
V
V
IH
IH
_
Input High Voltage
JTAG
DD + 100mV(2)
____
V
V
Input High Voltage -
ZZ, OPT, PIPE/FT
____
____
____
VIH
VIL
VIL
V
DD - 0.2V
-0.3(1)
V
DD + 100mV(2)
V
V
Input Low Voltage
0.8
0.2
Input Low Voltage -
ZZ, OPT, PIPE/FT
-0.3(1)
V
5666 tbl 05b
NOTES:
1. VIL (min.) = -1.0V for pulse width less than tCYC/2, or 5ns, whichever is less.
2. VIH (max.) = VDDQ + 1.0V for pulse width less than tCYC/2 or 5ns, whichever is less.
3. To select operation at 3.3V levels on the I/Os and controls of a given port, the OPT pin
for that port must be set to VDD (2.5V), and VDDQX for that port must be supplied as indicated
above.
6.42
8
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Absolute Maximum Ratings (1)
Symbol
Rating
Commercial
& Industrial
Unit
V
VTERM
V
DD Terminal Voltage
-0.5 to 3.6
(VDD
)
with Respect to GND
(2)
V
(VDDQ
TERM
V
DDQ Terminal Voltage
-0.3 to VDDQ + 0.3
-0.3 to VDDQ + 0.3
V
)
with Respect to GND
(2)
VTERM
Input and I/O Terminal
V
(INPUTS and I/O's)
Voltage with Respect to GND
(3)
T
BIAS
STG
JN
Temperature Under Bias
Storage Temperature
Junction Temperature
-55 to +125
-65 to +150
+150
oC
oC
T
T
oC
IOUT(For VDDQ = 3.3V) DC Output Current
50
mA
IOUT(For VDDQ = 2.5V) DC Output Current
40
mA
5666 tbl 06
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. This is a steady-state DC parameter that applies after the power supply has reached its
nominal operating value. Power sequencing is not necessary; however, the voltage on
any Input or I/O pin cannot exceed VDDQ during power supply ramp up.
3. Ambient Temperature under DC Bias. No AC Conditions. Chip Deselected.
Capacitance(1)
(TA = +25°C, F = 1.0MHZ) PQFP ONLY
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions(2)
IN = 3dV
OUT = 3dV
Max. Unit
CIN
V
8
pF
(3)
OUT
C
V
10.5
pF
5666 tbl 07
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch
from 0V to 3V or from 3V to 0V.
3. COUT also references CI/O.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 2.5V ± 100mV)
70T3519/99/89S
Symbol
|ILI
|ILI
|ILO
Parameter
Test Conditions
DDQ = Max., VIN = 0V to VDDQ
DD = Max. IN = 0V to VDD
= VIH or CE = VIL, VOUT = 0V to VDDQ
OL = +4mA, VDDQ = Min.
OH = -4mA, VDDQ = Min.
OL = +2mA, VDDQ = Min.
OH = -2mA, VDDQ = Min.
Min.
Max.
Unit
µA
µA
µA
V
___
|
Input Leakage Current(1)
V
V
10
±30
10
___
___
___
|
JTAG & ZZ Input Leakage Current(1,2)
Output Leakage Current(1,3)
, V
|
CE
0
1
V
OL (3.3V) Output Low Voltage(1)
OH (3.3V) Output High Voltage(1)
OL (2.5V) Output Low Voltage(1)
OH (2.5V) Output High Voltage(1)
I
0.4
___
V
I
2.4
V
___
V
I
0.4
V
___
V
I
2.0
V
5666 tbl 08
NOTES:
1. VDDQ is selectable (3.3V/2.5V) via OPT pins. Refer to p.5 for details.
2. Applicable only for TMS, TDI and TRST inputs.
3. Outputs tested in tri-state mode.
6.42
9
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
(3)
Temperature and Supply Voltage Range
(VDD = 2.5V ± 100mV)
70T3519/99/89
S200
70T3519/99/89
S166
70T3519/99/89
S133
Com'l Only(8)
Com'l
Com'l
& Ind
& Ind(7)
Symbol
Parameter
Test Condition
Version
COM'L
Typ.(4)
Max.
Typ.(4)
320
320
175
175
250
250
5
Max.
450
510
230
275
325
365
15
Typ.(4)
260
260
140
140
200
200
5
Max. Unit
IDD
Dynamic Operating
Current (Both
Ports Active)
CE
L
and CER= VIL,
S
S
S
S
S
S
S
S
S
S
S
S
375
525
370
450
190
235
250
310
15
mA
mA
mA
mA
mA
Outputs Disabled,
___
___
(1)
IND
f = fMAX
I
SB1(6)
Standby Current
(Both Ports - TTL
Level Inputs)
CE
L = CER = VIH
(1)
COM'L
IND
205
270
f = fMAX
___
___
SB2(6)
Standby Current
(One Port - TTL
Level Inputs)
(5)
I
CE"A" = VIL and CE"B" = VIH
COM'L
IND
300
375
Active Port Outputs Disabled,
___
___
(1)
f=fMAX
ISB3
Full Standby Current
(Both Ports - CMOS
Level Inputs)
Both Ports CEL and
COM'L
IND
5
15
CER > VDDQ - 0.2V, VIN > VDDQ - 0.2V
___
___
or VIN < 0.2V, f = 0(2)
5
20
5
20
SB4(6)
Full Standby Current
(One Port - CMOS
Level Inputs)
CE"A" < 0.2V and CE"B" > VDDQ - 0.2V(5)
IN > VDDQ - 0.2V or VIN < 0.2V
Active Port, Outputs Disabled, f = fMAX
I
COM'L
IND
300
375
250
250
5
325
365
15
200
200
5
250
310
15
V
___
___
(1)
Izz
Sleep Mode Current
(Both Ports - TTL
Level Inputs)
ZZL = ZZR =
f=fMAX
VIH
COM'L
IND
5
15
(1)
mA
___
___
5
20
5
20
5666 tbl 09
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS".
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. VDD = 2.5V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 15mA (Typ).
5. CEX = VIL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VDD - 0.2V
CEX > VDD - 0.2V means CE0X > VDD - 0.2V or CE1X - 0.2V
"X" represents "L" for left port or "R" for right port.
6. ISB1, ISB2 and ISB4 will all reach full standby levels (ISB3) on the appropriate port(s) if ZZL and/or ZZR = VIH.
7. 166MHz I-Temp is not available in the BF-208 package.
8. 200Mhz is not available in the BF-208 and DR-208 packages.
6.42
10
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
AC Test Conditions (VDDQ - 3.3V/2.5V)
Input Pulse Levels (Address & Controls)
Input Pulse Levels (I/Os)
Input Rise/Fall Times
GND to 3.0V/GND to 2.4V
GND to 3.0V/GND to 2.4V
2ns
Input Timing Reference Levels
Output Reference Levels
Output Load
1.5V/1.25V
1.5V/1.25V
Figure 1
5666 tbl 10
50Ω
50Ω
,
DATAOUT
1.5V/1.25
10pF
(Tester)
5666 drw 03
Figure 1. AC Output Test load.
∆
tCD
(Typical, ns)
5666 drw 04
∆
Capacitance (pF) from AC Test Load
6.42
11
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing) (2,3) (VDD = 2.5V ± 100mV, TA = 0°C to +70°C)
70T3519/99/89
S200
70T3519/99/89
S166
70T3519/99/89
S133
Com'l Only(5)
Com'l
Com'l
& Ind(4)
& Ind
Symbol
Parameter
Min.
15
5
Max.
Min.
20
Max.
Min.
25
Max.
Unit
ns
t
CYC1
CYC2
CH1
CL1
CH2
CL2
SA
HA
SC
HC
SB
HB
SW
HW
SD
HD
SAD
HAD
SCN
HCN
SRPT
HRPT
OE
Clock Cycle Time (Flow-Through)(1)
Clock Cycle Time (Pipelined)(1)
Clock High Time (Flow-Through)(1)
Clock Low Time (Flow-Through)(1)
Clock High Time (Pipelined)(2)
Clock Low Time (Pipelined)(1)
Address Setup Time
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
6
7.5
10
ns
t
6
8
ns
t
6
8
10
ns
t
2
2.4
2.4
1.7
0.5
1.7
0.5
1.7
0.5
1.7
0.5
1.7
0.5
1.7
0.5
1.7
0.5
1.7
3
ns
t
2
3
ns
t
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
1.8
0.5
1.8
0.5
1.8
0.5
1.8
0.5
1.8
0.5
1.8
0.5
1.8
0.5
1.8
ns
t
Address Hold Time
ns
t
Chip Enable Setup Time
Chip Enable Hold Time
Byte Enable Setup Time
Byte Enable Hold Time
R/W Setup Time
ns
t
ns
t
ns
t
ns
t
ns
t
R/W Hold Time
ns
t
Input Data Setup Time
ns
t
Input Data Hold Time
ns
t
ns
ADS Setup Time
t
ns
ADS Hold Time
t
ns
CNTEN Setup Time
t
ns
CNTEN Hold Time
t
ns
REPEAT Setup Time
t
0.5
0.5
0.5
ns
REPEAT Hold Time
____
____
____
t
Output Enable to Data Valid
Output Enable to Output Low-Z
Output Enable to Output High-Z
Clock to Data Valid (Flow-Through)(1)
Clock to Data Valid (Pipelined)(1)
Data Output Hold After Clock High
Clock High to Output High-Z
Clock High to Output Low-Z
Interrupt Flag Set Time
4.4
4.4
4.6
ns
(6)
____
____
____
t
OLZ
1
1
1
ns
(6)
OHZ
t
1
3.4
10
1
3.6
12
1
4.2
15
ns
____
____
____
t
CD1
CD2
DC
CKHZ
ns
____
____
____
t
3.4
3.6
4.2
ns
____
____
____
t
1
1
1
1
1
1
ns
(6)
t
3.4
3.6
4.2
ns
(6)
CKLZ
____
____
____
t
1
1
1
ns
____
____
____
t
INS
INR
COLS
COLR
ZZSC
ZZRC
7
7
7
7
7
7
ns
____
____
____
____
____
____
____
____
____
t
Interrupt Flag Reset Time
Collision Flag Set Time
Collision Flag Reset Time
Sleep Mode Set Cycles
Sleep Mode Recovery Cycles
ns
t
3.4
3.6
4.2
ns
t
3.4
3.6
4.2
ns
____
____
____
t
2
3
2
3
2
3
cycles
cycles
____
____
____
t
Port-to-Port Delay
Clock-to-Clock Offset
Clock-to-Clock Offset for Collision Detection
____
____
____
t
CO
4
5
6
ns
tOFS
Please refer to Collision Detection Timing Table on Page 21
5666 tbl 11
NOTES:
1. The Pipelined output parameters (tCYC2, tCD2) apply to either or both left and right ports when FT/PIPEX = VDD (2.5V). Flow-through parameters (tCYC1, tCD1)
apply when FT/PIPE = Vss (0V) for that port.
2. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE), FT/PIPE and OPT. FT/PIPE and OPT should be
treated as DC signals, i.e. steady state during operation.
3. These values are valid for either level of VDDQ (3.3V/2.5V). See page 6 for details on selecting the desired operating voltage levels for each port.
4. 166MHz I-Temp is not available in the BF-208 package.
5. 200Mhz is not available in the BF-208 and DR-208 packages.
6. Guaranteed by design (not production tested).
6.42
12
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle for Pipelined Operation
(FT/PIPE'X' = VIH)(1,2)
t
CYC2
tCH2
tCL2
CLK
CE
0
t
SC
tHC
t
SC
SB
t
HC
HB
(3)
CE1
t
SB
tHB
t
t
(5)
BEn
R/W
tHW
tSW
tSA
tHA
ADDRESS(4)
DATAOUT
An
An + 1
An + 2
Qn
An + 3
(1 Latency)
t
DC
tCD2
Qn + 1
Qn + 2 (5)
(1)
tCKLZ
t
OHZ
tOLZ
(1)
OE
tOE
5666 drw 05
Timing Waveform of Read Cycle for Flow-through Output
(FT/PIPE"X" = VIL)(1,2,6)
tCYC1
tCH1
tCL1
CLK
CE
0
tSC
tHC
tSC
tHC
(3)
CE1
tSB
tHB
tHB
BEn
tSB
R/W
tSW
tHW
tSA
tHA
ADDRESS(4)
DATAOUT
An
An + 1
An + 2
An + 3
tDC
tCD1
tCKHZ
Qn
Qn + 1
Qn + 2(5)
tCKLZ
tDC
tOHZ
tOLZ
OE(1)
tOE
5666 drw 06
NOTES:
1. OE is asynchronously controlled; all other inputs depicted in the above waveforms are synchronous to the rising clock edge.
2. ADS = VIL, CNTEN and REPEAT = VIH.
3. The output is disabled (High-Impedance state) by CE0 = VIH, CE1 = VIL, BEn = VIH following the next rising edge of the clock. Refer to
Truth Table 1.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
5. If BEn was HIGH, then the appropriate Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state).
6. "x" denotes Left or Right port. The diagram is with respect to that port.
6.42
13
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
(1,2)
Timing Waveform of a Multi-Device Pipelined Read
t
CYC2
tCH2
tCL2
CLK
ADDRESS(B1)
CE0(B1)
tSA tHA
A6
A5
A4
A3
A2
A0
A1
tSC tHC
t
SC
tHC
tCD2
tCD2
tCKHZ
tCD2
Q0
A2
Q3
Q
1
DATAOUT(B1)
ADDRESS(B2)
tDC
tCKLZ
tDC
tCKHZ
tSA tHA
A6
A5
A4
A3
A0
A1
tSC tHC
CE0(B2)
tSC tHC
tCD2
tCKHZ
tCD2
DATAOUT(B2)
Q4
Q2
tCKLZ
tCKLZ
5666 drw 07
(1,2)
Timing Waveform of a Multi-Device Flow-Through Read
t
CYC1
tCH1
tCL1
CLK
tSA
tHA
A6
A5
A4
A3
A2
A0
A1
ADDRESS(B1)
tSC
tHC
CE0(B1)
tSC
tHC
(1)
t
CD1
tCD1
tCKHZ
tCD1
tCD1
D
0
D
3
D5
D
1
DATAOUT(B1)
ADDRESS(B2)
(1)
(1)
(1)
tDC
t
CKLZ
tCKLZ
tDC
t
CKHZ
tSA
tHA
A6
A
5
A4
A3
A2
A
0
A1
tSC
tHC
CE0(B2)
tSC
t
HC
(1)
(1)
tCD1
tCKHZ
tCD1
tCKHZ
D4
DATAOUT(B2)
D2
(1)
(1)
t
CKLZ
tCKLZ
5666 drw 08
NOTES:
1. B1 Represents Device #1; B2 Represents Device #2. Each Device consists of one IDT70T3519/99/89 for this waveform,
and are setup for depth expansion in this example. ADDRESS(B1) = ADDRESS(B2) in this situation.
2. BEn, OE, and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and REPEAT = VIH.
6.42
14
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
(1,2,4)
Timing Waveform of Left Port Write to Pipelined Right Port Read
CLK"A"
tSW
tHW
R/W"A"
ADDRESS"A"
DATAIN"A"
t
SA
MATCH
SD HD
VALID
tHA
NO
MATCH
t
t
(3)
CO
t
CLK"B"
t
CD2
R/W"B"
t
SW
SA
t
HW
HA
t
t
NO
ADDRESS"B"
DATAOUT"B"
MATCH
MATCH
VALID
tDC
5666 drw 09
NOTES:
1. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
2. OE = VIL for Port "B", which is being read from. OE = VIH for Port "A", which is being written to.
3. If tCO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (ie, time from write to valid read on opposite port will be
tCO + 2 tCYC2 + tCD2). If tCO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (ie, time from write to valid read on opposite port
will be tCO + tCYC2 + tCD2).
4. All timing is the same for Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite of Port "A"
(1,2,4)
Timing Waveform with Port-to-Port Flow-Through Read
CLK "A"
tSW
tHW
R/W "A"
ADDRESS "A"
DATAIN "A"
CLK "B"
t
SA
MATCH
SD HD
VALID
tHA
NO
MATCH
t
t
(3)
t
CO
t
CD1
R/W "B"
t
HW
HA
t
SW
t
t
SA
NO
MATCH
ADDRESS "B"
DATAOUT "B"
MATCH
t
CD1
VALID
VALID
tDC
t
DC
5666 drw 10
NOTES:
1. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
2. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
3. If tCO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (i.e., time from write to valid read on opposite port will be
tCO + tCYC + tCD1). If tCO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (i.e., time from write to valid read on opposite port will
be tCO + tCD1).
4. All timing is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A".
6.42
15
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read-to-Write-to-Read
(OE = VIL)(2)
tCYC2
tCH2
tCL2
CLK
CE
CE
BE
0
1
n
t
SC
tHC
tSB
tHB
tSW tHW
R/W
tSW tHW
ADDRESS(3)
An + 3
An + 4
An
An +1
An + 2
An + 2
t
SA
tHA
t
SD
t
HD
DATAIN
Dn + 2
tCD2
tCD2
(1)
tCKHZ
tCKLZ
Qn + 3
Qn
DATAOUT
READ
NOP(4)
WRITE
READ
5666 drw 11
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH. "NOP" is "No Operation".
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
Timing Waveform of Pipelined Read-to-Write-to-Read ( OE Controlled) (2)
t
CYC2
tCH2
tCL2
CLK
CE0
tSC
tHC
CE1
t
SB
tHB
BEn
tSW tHW
R/W
tSW tHW
ADDRESS(3)
DATAIN
An + 4
An
An +1
An + 2
An + 3
Dn + 3
An + 5
t
SA
tHA
t
SD
tHD
Dn + 2
tCD2
tCD2
tCKLZ
(1)
Qn
Qn + 4
DATAOUT
(4)
tOHZ
OE
READ
WRITE
READ
5666 drw 12
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference
use only.
4. This timing does not meet requirements for fastest speed grade. This waveform indicates how logically it could be done if timing so allows.
6.42
16
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Flow-Through Read-to-Write-to-Read ( OE = VIL)(2)
t
CYC1
t
CH1
tCL1
CLK
CE0
tSC
tHC
CE1
t
SB
tHB
BEn
t
SW tHW
R/
W
tSW tHW
(3)
An + 4
An
An + 3
An +1
An + 2
An + 2
ADDRESS
tSA
tHA
t
SD
t
HD
DATAIN
Dn + 2
t
CD1
t
CD1
t
CD1
tCD1
(1)
Qn + 3
Qn
READ
Qn + 1
DATAOUT
t
DC
tCKLZ
tDC
t
CKHZ
NOP(5)
READ
WRITE
5666 drw 13
TimingWaveformof Flow-ThroughRead-to-Write-to-Read(OE Controlled)(2)
tCYC1
CH1
t
tCL1
CLK
CE0
tSC
tHC
CE1
t
SB
tHB
BEn
tSW tHW
t
SW tHW
R/
W
(3)
An + 5
An
An + 4
An +1
An + 2
An + 3
Dn + 3
ADDRESS
DATAIN
t
SA
tHA
t
SD tHD
Dn + 2
t
OE
CD1
tDC
t
CD1
t
CD1
t
(1)
Qn + 4
Qn
DATAOUT
t
CKLZ
t
DC
t
OHZ
OE
READ
WRITE
READ
5666 drw 14
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for
reference use only.
4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
6.42
17
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
(1)
Timing Waveform of Pipelined Read with Address Counter Advance
tCYC2
tCH2
tCL2
CLK
tSA
tHA
ADDRESS
An
t
SAD tHAD
ADS
t
SAD tHAD
CNTEN
t
SCN tHCN
tCD2
Qn + 2(2)
Qn + 3
Qx - 1(2)
Qx
Qn + 1
Qn
DATAOUT
tDC
READ
EXTERNAL
ADDRESS
READ
WITH
COUNTER
COUNTER
HOLD
READ WITH COUNTER
5666 drw 15
TimingWaveformof Flow-ThroughReadwithAddressCounterAdvance (1)
t
CYC1
t
CH1
tCL1
CLK
t
SA
tHA
An
ADDRESS
tSAD tHAD
t
SAD
tHAD
ADS
tSCN
tHCN
CNTEN
t
CD1
Qn + 3(2)
Qx(2)
Qn + 4
Qn + 1
Qn + 2
Qn
DATAOUT
tDC
READ
WITH
COUNTER
READ
EXTERNAL
ADDRESS
READ WITH COUNTER
COUNTER
HOLD
5666 drw 16
NOTES:
1. CE0, OE, BEn = VIL; CE1, R/W, and REPEAT = VIH.
2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then
the data output remains constant for subsequent clocks.
6.42
18
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Address Counter Advance
(1)
(Flow-through or Pipelined Inputs)
tCYC2
tCH2
tCL2
CLK
tSA
tHA
An
ADDRESS
INTERNAL(3)
ADDRESS
An(7)
An + 1
An + 3
An + 4
An + 2
tSAD tHAD
ADS
tSCN tHCN
CNTEN
tSD tHD
Dn + 4
Dn + 1
Dn + 3
Dn
Dn + 1
Dn + 2
DATAIN
WRITE
EXTERNAL
ADDRESS
WRITE
WITH COUNTER
WRITE
COUNTER HOLD
WRITE WITH COUNTER
5666 drw 17
(2,6)
Timing Waveform of Counter Repeat
tCYC2
CLK
t
SA
tHA
An
ADDRESS
INTERNAL(3)
ADDRESS
An+2
An+1
An+2
An+2
An
An
An+1
An+2
tSAD tHAD
ADS
tSW tHW
R/W
t
SCN tHCN
CNTEN
(4)
REPEAT
tHRPT
SRPT
t
tSD
tHD
D3
D2
D
0
D1
DATAIN
tCD1
An
An+1
An+2
An+2
DATAOUT
,
ADVANCE
COUNTER
WRITE TO
An+2
ADVANCE
HOLD
REPEAT
READ LAST
ADS
ADDRESS
An
ADVANCE
COUNTER
READ
WRITE TO
ADS
ADDRESS
An
ADVANCE
COUNTER
READ
HOLD
COUNTER
READ
COUNTER
WRITE TO
An+1
COUNTER
WRITE TO
An+2
An+1
An+2
An+2
5666 drw 18
NOTES:
1. CE0, BEn, and R/W = VIL; CE1 and REPEAT = VIH.
CE0, BEn = VIL; CE1 = VIH.
2.
3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.
4. No dead cycle exists during REPEAT operation. A READ or WRITE cycle may be coincidental with the counter REPEAT cycle: Address loaded by last valid
ADS load will be accessed. For more information on REPEAT function refer to Truth Table II.
5. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is
written to during this cycle.
6. For Pipelined Mode user should add 1 cycle latency for outputs as per timing waveform of read cycle for pipelined operations.
6.42
19
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Waveform of Interrupt Timing (2)
CLK
L
tSW
tHW
R/W
L
t
SA
3FFFF
SC
t
HA
ADDRESSL(3)
CEL(1)
t
t
HC
t
INS
INT
R
t
INR
CLKR
t
SC
tHC
CER(1)
R/WR
t
SW
SA
3FFFF
t
HW
t
HA
t
ADDRESSR(3)
5666 drw 19
NOTES:
1. CE0 = VIL and CE1 = VIH
2. All timing is the same for Left and Right ports.
3. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.
Truth Table III — Interrupt Flag (1)
Left Port
Right Port
(2)
(2)
(3,4,5)
(2)
(2)
(3,4,5)
CLK
L
R/W
L
L
CE
L
A
17L-A0L
CLK
R
R/W
R
CE
R
A
17R-A0R
Function
Set Right INT Flag
Reset Right INT Flag
Set Left INT Flag
Reset Left INT Flag
INT
X
L
INT
L
R
↑
↑
↑
↑
↑
↑
↑
↑
L
3FFFF
X
X
X
X
R
X
X
X
L
X
H
L
L
L
3FFFF
3FFFE
X
H
R
X
X
L
X
L
H
3FFFE
H
X
X
X
L
5666 tbl 12
NOTES:
1. INTL and INTR must be initialized at power-up by Resetting the flags.
2. CE0 = VIL and CE1 = VIH. R/W and CE are synchronous with respect to the clock and need valid set-up and hold times.
3. A17X is a NC for IDT70T3599, therefore Interrupt Addresses are 1FFFF and 1FFFE.
4. A17X and A16X are NC's for IDT70T3589, therefore Interrupt Addresses are FFFF and FFFE.
5. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.
6.42
20
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Waveform of Collision Timing(1,2)
Both Ports Writing with Left Port Clock Leading
CLK
L
tOFS
tSA tHA
ADDRESS(4)
L
A
3
A
2
A1
A0
tCOLR
tCOLS
COL
L
(3)
tOFS
CLK
R
tSA
tHA
(4)
ADDRESS
R
A3
A
2
A0
A1
tCOLR
tCOLS
COL
R
5666 drw 20
NOTES:
1. CE0 = VIL, CE1 = VIH.
2. For reading port, OE is a Don't care on the Collision Detection Logic. Please refer to Truth Table IV for specific cases.
3. Leading Port Output flag might output 3tCYC2 + tCOLS after Address match.
4. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.
Collision Detection Timing(3,4)
tOFS (ns)
Cycle Time
NOTES:
1. Region 1
(1)
(2)
Region 1 (ns)
Region 2 (ns)
Both ports show collision after 2nd cycle for Addresses 0, 2, 4 etc.
2. Region 2
Leading port shows collision after 3rd cycle for addresses 0, 3, 6, etc.
while trailing port shows collision after 2nd cycle for addresses 0, 2, 4 etc.
3. All the production units are tested to midpoint of each region.
5ns
6ns
0 - 2.8
2.81 - 4.6
0 - 3.8
0 - 5.3
3.81 - 5.6
5.31 - 7.1
7.5ns
4. These ranges are based on characterization of a typical device.
5666 tbl 13
Truth Table IV — Collision Detection Flag
Left Port
Right Port
(1)
(1)
(2)
(1)
(1)
(2)
CLK
L
R/W
L
CE
L
A
17L-A0L
CLK
R
R/W
R
CE
R
A
17R-A0R
Function
COL
H
L
COL
R
Both ports reading. Not a valid collision.
No flag output on either port.
↑
↑
↑
↑
H
H
L
L
MATCH
MATCH
MATCH
MATCH
H
L
L
MATCH
MATCH
MATCH
MATCH
H
Left port reading, Right port writing.
Valid collision, flag output on Left port.
↑
L
L
L
L
L
L
L
H
Right port reading, Left port writing.
Valid collision, flag output on Right port.
↑
H
H
L
L
Both ports writing. Valid collision. Flag
output on both ports.
↑
↑
L
L
L
5666 tbl 14
NOTES:
1. CE0 = VIL and CE1 = VIH. R/W and CE are synchronous with respect to the clock and need valid set-up and hold times.
2. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.
6.42
21
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform - Entering Sleep Mode (1,2)
R/W
(3)
Timing Waveform - Exiting Sleep Mode (1,2)
An
An+1
(5)
R/W
OE
(5)
Dn
Dn+1
DATAOUT
(4)
NOTES:
1. CE1 = VIH.
2. All timing is same for Left and Right ports.
3. CE0 has to be deactivated (CE0 = VIH) three cycles prior to asserting ZZ (ZZx = VIH) and held for two cycles after asserting ZZ (ZZx = VIH).
4. CE0 has to be deactivated (CE0 = VIH) one cycle prior to de-asserting ZZ (ZZx = VIL) and held for three cycles after de-asserting ZZ (ZZx = VIL).
5. The device must be in Read Mode (R/W High) when exiting sleep mode. Outputs are active but data is not valid until the following cycle.
6.42
22
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
flag. Athirdcollisionwillgeneratethealertflagasappropriate. Inthe
eventthatauserinitiatesaburstaccessonbothportswiththesame
starting address on both ports and one or both ports writing during
eachaccess(i.e.,imposesalongstringofcollisionsoncontiguous
clock cycles), the alert flag will be asserted and cleared every other
cycle.PleaserefertotheCollisionDetectiontimingwaveformonPage
21C. ollision detection on the IDT70T3519/99/89 represents a
significantadvanceinfunctionalityovercurrentsyncmulti-ports,which
havenosuchcapability. Inadditiontothisfunctionalitythe
IDT70T3519/99/89sustainsthekeyfeaturesofbandwidthand
flexibility. Thecollisiondetectionfunctionisveryusefulinthecaseof
burstingdata,orastringofaccessesmadetosequentialaddresses,in
thatitindicatesaproblemwithintheburst,givingtheusertheoptionof
eitherrepeatingtheburstorcontinuingtowatchthealertflagtosee
whetherthenumberofcollisionsincreasesaboveanacceptable
thresholdvalue.Offeringthisfunctiononchipalsoallowsusersto
reducetheirneedforarbitrationcircuits, typicallydoneinCPLD’sor
FPGA’s. This reduces board space and design complexity, and gives
FunctionalDescription
TheIDT70T3519/99/89providesatruesynchronousDual-PortStatic
RAM interface.Registeredinputsprovideminimalset-upandholdtimes
onaddress, data, andallcriticalcontrolinputs. Allinternalregistersare
clocked on the rising edge of the clock signal, however, the self-timed
internalwritepulsewidthisindependentofthecycletime.
An asynchronous output enable is provided to ease asyn-
chronousbusinterfacing.Counterenableinputsarealsoprovidedtostall
the operation of the address counters for fast interleaved
memoryapplications.
A HIGHonCE0oraLOWonCE1foroneclockcyclewillpowerdown
the internal circuitry to reduce static power consumption. Multiple chip
enablesalloweasierbankingofmultipleIDT70T3519/99/89sfordepth
expansionconfigurations. Twocyclesarerequiredwith CE0 LOWand
CE1HIGHtore-activatetheoutputs.
Interrupts
If the user chooses the interrupt function, a memory location (mail theusermoreflexibilityindevelopingasolution.
boxormessagecenter)isassignedtoeachport. Theleftportinterrupt
flag (INTL) is asserted when the right port writes to memory location
3FFFE (HEX), where a write is defined as CER = R/WR = VIL per the
SleepMode
The IDT70T3519/99/89 is equipped with an optional sleep or low
Truth Table. The left port clears the interrupt through access of
addresslocation3FFFEwhen CEL = VIL andR/WL= VIH.Likewise,the
right port interrupt flag (INTR) is asserted when the left
port writes to memory location 3FFFF (HEX) and to clear the interrupt
flag(INTR),therightportmustreadthememorylocation3FFFF(1FFFF
or 1FFFE for IDT70T3599 and FFFF or FFFE for IDT70T3589). The
message(36bits)at3FFFEor3FFFF(1FFFFor1FFFEforIDT70T3599
and FFFF or FFFE for IDT70T3589) is user-defined since it is an
addressableSRAMlocation.Iftheinterruptfunctionisnotused,address
locations 3FFFE and 3FFFF (1FFFF or 1FFFE for IDT70T3599 and
FFFForFFFEforIDT70T3589)arenotusedasmailboxes, butaspart
of the random access memory. Refer to Truth Table III for the interrupt
operation.
power mode on both ports. The sleep mode pin on both ports is
asynchronous and active high. During normal operation, the ZZ pin is
pulledlow.WhenZZispulledhigh,theportwillentersleepmodewhere
it will meet lowest possible power conditions. The sleep mode timing
diagramshowsthemodes ofoperation:NormalOperation,NoRead/Write
Allowed and Sleep Mode.
Fornormaloperationallinputsmustmeetsetupandholdtimesprior
tosleepand afterrecoveringfromsleep.Clocksmustalsomeetcyclehigh
and low times during these periods. Three cycles prior to asserting ZZ
(ZZx=VIH)andthreecyclesafterde-assertingZZ(ZZx=VIL),thedevice
mustbedisabledviathechipenablepins.Ifawriteorreadoperationoccurs
duringtheseperiods,thememoryarraymaybecorrupted.Validityofdata
outfromtheRAMcannotbeguaranteedimmediatelyafterZZisasserted
(priortobeinginsleep).Whenexitingsleepmode,thedevicemustbein
Read mode (R/Wx = VIH)when chip enable is asserted, and the chip
enablemustbevalidforonefullcyclebeforeareadwillresultintheoutput
ofvaliddata.
CollisionDetection
Collision is defined as an overlap in access between the two ports
resultinginthepotentialforeitherreadingorwritingincorrectdatatoa
specific address. For the specific cases: (a) Both ports reading - no
dataiscorrupted,lost,orincorrectlyoutput,sonocollisionflagisoutput
on either port. (b) One port writing, the other port reading - the end
result of the write will still be valid. However, the reading port might
capturedatathatisinastateoftransitionandhencethereadingport’s
collisionflagisoutput. (c)Bothportswriting-thereisariskthatthetwo
portswillinterferewitheachother, andthedatastoredinmemorywill
not be a valid write from either port (it may essentially be a random
combinationofthetwo). Therefore,thecollisionflagisoutputonboth
DuringsleepmodetheRAMautomaticallydeselectsitself.TheRAM
disconnectsitsinternalclockbuffer.Theexternalclockmaycontinuetorun
withoutimpactingtheRAMssleepcurrent(IZZ).Alloutputswillremainin
high-Zstatewhileinsleepmode.Allinputsareallowedtotoggle.TheRAM
will not be selected and will not perform any reads or writes.
ports. Please refer to Truth Table IV for all of the above cases.
The alert flag (COLX) is asserted on the 2nd or 3rd rising clock
edgeoftheaffectedportfollowingthecollision,andremainslowfor
onecycle. PleaserefertoCollisionDetectionTimingtableonPage21.
Duringthatnextcycle,theinternalarbitrationisengagedinresetting
thealertflag(thisavoidsaspecificrequirementonthepartoftheuser
toresetthealertflag). Iftwocollisionsoccuronsubsequentclock
cycles,thesecondcollisionmaynotgeneratetheappropriatealert
6.42
23
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Depth andWidth Expansion
The IDT70T3519/99/89 features dual chip enables (refer to Truth
Table I) in order to facilitate rapid and simple depth expansion with no
requirements for external logic. Figure 4 illustrates how to control the
various chip enables in order to expand two devices in depth.
The IDT70T3519/99/89 can also be used in applications requiring
expandedwidth,asindicatedinFigure4.Throughcombiningthecontrol
signals, the devices can be grouped as necessary to accommodate
applicationsneeding72-bitsorwider.
A18/A17/A16
IDT70T3519/99/89
IDT70T3519/99/89
CE0
CE0
CE1
CE1
V
DD
VDD
Control Inputs
Control Inputs
IDT70T3519/99/89
IDT70T3519/99/89
CE1
CE1
CE0
CE0
BE,
R/W,
Control Inputs
Control Inputs
OE,
CLK,
Figure 4. Depth and Width Expansion with IDT70T3519/99/89
ADS,
REPEAT,
CNTEN
,
5666 drw 23
NOTE:
1. A18 is for IDT70T3519, A17 is for IDT70T3599, A16 is for IDT70T3589.
6.42
24
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
JTAGTimingSpecifications
t
JCYC
t
JR
t
JF
t
JCL
tJCH
TCK
Device Inputs(1)/
TDI/TMS
t
JDC
tJS
tJH
Device Outputs(2)/
TDO
t
JRSR
t
JCD
TRST
,
5666 drw 24
t
JRST
Figure 5. Standard JTAG Timing
NOTES:
1. Device inputs = All device inputs except TDI, TMS, and TRST.
2. Device outputs = All device outputs except TDO.
JTAG AC Electrical
Characteristics(1,2,3,4)
70T3519/99/89
Max. Units
Symbol
Parameter
JTAG Clock Input Period
JTAG Clock HIGH
JTAG Clock Low
JTAG Clock Rise Time
JTAG Clock Fall Time
JTAG Reset
Min.
100
40
____
____
____
t
JCYC
JCH
JCL
JR
JF
JRST
JRSR
JCD
JDC
JS
JH
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
40
3(1)
____
t
3(1)
____
t
____
t
50
____
t
JTAG Reset Recovery
JTAG Data Output
JTAG Data Output Hold
JTAG Setup
50
____
t
25
____
t
0
____
____
t
15
15
t
JTAG Hold
ns
5666 tbl 15
NOTES:
1. Guaranteed by design.
2. 30pF loading on external output signals.
3. Refer to AC Electrical Test Conditions stated earlier in this document.
4. JTAG operations occur at one speed (10MHz). The base device may run at
any speed specified in this datasheet.
6.42
25
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Identification Register Definitions
Instruction Field
Value
Description
Revision Number (31:28)
0x0
Reserved for version number
0x330(1)
0x33
1
IDT Device ID (27:12)
Defines IDT part number
IDT JEDEC ID (11:1)
Allows unique identification of device vendor as IDT
Indicates the presence of an ID register
ID Register Indicator Bit (Bit 0)
5666 tbl 16
NOTE:
1. Device ID for IDT70T3599 is 0x331. Device ID for IDT70T3589 is 0x332.
ScanRegisterSizes
Register Name
Bit Size
Instruction (IR)
Bypass (BYR)
4
1
Identification (IDR)
32
Boundary Scan (BSR)
Note (3)
5666 tbl 17
SystemInterfaceParameters
Instruction
Code
Description
EXTEST
0000
Forces contents of the boundary scan cells onto the device outputs(1).
Places the boundary scan register (BSR) between TDI and TDO.
BYPASS
IDCODE
1111
Places the bypass register (BYR) between TDI and TDO.
0010
Loads the ID register (IDR) with the vendor ID code and places the
register between TDI and TDO.
0100
Places the bypass register (BYR) between TDI and TDO. Forces all
device output drivers to a High-Z state except COLx & INTx outputs.
HIGHZ
Uses BYR. Forces contents of the boundary scan cells onto the device
outputs. Places the bypass register (BYR) between TDI and TDO.
CLAMP
0011
0001
SAMPLE/PRELOAD
Places the boundary scan register (BSR) between TDI and TDO.
SAMPLE allows data from device inputs(2) to be captured in the
boundary scan cells and shifted serially through TDO. PRELOAD allows
data to be input serially into the boundary scan cells via the TDI.
RESERVED
PRIVATE
0101, 0111, 1000, 1001,
1010, 1011, 1100
Several combinations are reserved. Do not use codes other than those
identified above.
0110,1110,1101
For internal use only.
5666 tbl 18
NOTES:
1. Device outputs = All device outputs except TDO.
2. Device inputs = All device inputs except TDI, TMS, and TRST.
3. The Boundary Scan Descriptive Language (BSDL) file for this device is available on the IDT website (www.idt.com), or by contacting your local
IDT sales representative.
6.42
26
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
OrderingInformation
XXXXX
A
999
A
A
IDT
Device
Type
Power Speed
Package
Process/
Temperature
Range
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Blank
I
BC
DR
BF
256-pin BGA (BC-256)
208-pin PQFP (DR-208)
208-pin fpBGA (BF-208)
Commercial Only(2)
200
166
133
Commercial & Industrial(1) Speed in Megahertz
Commercial & Industrial
S
Standard Power
9Mbit (256K x 36) 2.5V Synchronous Dual-Port RAM
4Mbit (128K x 36) 2.5V Synchronous Dual-Port RAM
2Mbit (64K x 36) 2.5V Synchronous Dual-Port RAM
70T3519
70T3599
70T3589
5666 drw 25
NOTES:
1. 166MHz I-Temp is not available in the BF-208 package.
2. 200Mhz is not available in the BF-208 and DR-208 packages.
IDT Clock Solution for IDT70T3519/99/89 Dual-Port
Dual-Port I/O Specitications
Clock Specifications
Input Duty
IDT
PLL
Clock Device
IDT
Non-PLL
Clock Device
IDT Dual-Port
Part Number
Input
Capacitance
Maximum
Jitter
Voltage
2.5
I/O
Cycle
Requirement
Frequency Tolerance
5T9010
5T905, 5T9050
5T907, 5T9070
70T3519/99/89
LVTTL
8pF
40%
200
75ps
5T2010
5666 tbl 19
6.42
27
IDT70T3519/99/89S
High-Speed 2.5V 256/128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
DatasheetDocumentHistory:
01/23/03:
01/30/03:
04/25/03:
InitialDatasheet
Page 1 Corrected 208-pin package from TQFP to PQFP
Page 11 Added Capacitance Derating drawing
Page12ChangedtINS andtINR specsinACElectricalCharacteristicstable
Page10 UpdatedpowernumbersinDCElectricalCharacteristicstable
11/11/03:
Page12 AddedtOFS symbolandparametertoACElectricalCharacteristicstable
Page21 UpdatedCollisionTimingwaveform
Page22 AddedCollisionDetectionTimingtableandfootnotes
Page26 UpdatedHIGHZfunctioninSystemInterfaceParameterstable
Page 27 Added IDT Clock Solution table
03/30/04:
04/22/04:
Page 22 & 23 Clarified Sleep Mode Text and Waveforms
Page 1 & 27 Removed Preliminary status
Page 6 Added another sentence to footnote 4 to recommend that boundary scan not be operated during sleep mode
CORPORATE HEADQUARTERS
2975StenderWay
Santa Clara, CA 95054
for SALES:
for Tech Support:
831-754-4613
DualPortHelp@idt.com
800-345-7015 or 408-727-5166
fax: 408-492-8674
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.42
28
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