IDT70P3519S166BCGI8 [IDT]
SRAM;型号: | IDT70P3519S166BCGI8 |
厂家: | INTEGRATED DEVICE TECHNOLOGY |
描述: | SRAM 静态存储器 |
文件: | 总27页 (文件大小:366K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
HIGH-SPEED 1.8V
256/128K x 36
SYNCHRONOUS
IDT70P3519/99
DUAL-PORT STATIC RAM
WITH 3.3V/2.5V/1.8V INTERFACE
Features:
◆
◆
Counter enable and repeat features
True Dual-Port memory cells which allow simultaneous
◆
◆
Interrupt and Collision Detection Flags
Separate byte controls for multiplexed bus and bus
matching compatibility
Dual Cycle Deselect (DCD) for Pipelined Output Mode
1.8V (±100mV) power supply for core
LVTTL compatible,1.8V to 3.3V power supply for I/Os and
control signals on each port
Industrial temperature range (-40°C to +85°C) is
available at 166MHz
Available in a 256-pin Ball Grid Array (BGA) and 208-pin fine
pitch Ball Grid Array (fpBGA)
Supports JTAG features compliant with IEEE 1149.1
Green parts available, see ordering information
access of the same memory location
Low Power
High-speed data access
◆
◆
◆
◆
◆
– Commercial: 3.4 (200MHz)/3.6ns (166MHz)
– Industrial: 3.6ns (166MHz)
Selectable Pipelined or Flow-Through output mode
◆
◆
Dual chip enables allow for depth expansion without
◆
◆
additional logic
Full synchronous operation on both ports
◆
– 5ns cycle time, 200MHzoperation(14Gbps bandwidth)
– Fast 3.4ns clock to data out
– 1.5ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 200MHz
◆
◆
– Data input, address, byte enable and control registers
– Self-timedwriteallowsfastcycletime
FunctionalBlockDiagram
BE3R
BE3L
BE2L
BE1L
BE0L
BE2R
BE1R
BE0R
FT/PIPE
L
1d 0d
d
1c 0c
c
1b 0b
b
1a 0a
a
FT/PIPER
0a 1a
a
0b 1b
b
0c 1c
c
0d 1d
d
1/0
1/0
R/W
L
R/WR
CE0R
CE0L
1
1
CE1R
CE1L
0
0
B
W
0
B
W
1
B
B
B
W
2
B
B
B
W
3
1/0
1/0
W W
W W
2
L
3
L
1
R
0
R
L
L
R
R
OE
R
OE
L
Dout0-8_L
Dout0-8_R
Dout9-17_L
Dout18-26_L
Dout27-35_L
Dout9-17_R
Dout18-26_R
Dout27-35_R
,
1d 0d 1c 0c
1b 0b 1a 0a
0a 1a 0b 1b
0c 1c 0d 1d
d c b a
0/1
0/1
FT/PIPER
FT/PIPE
L
a bcd
256/128K x 36
MEMORY
ARRAY
I/O0R - I/O35R
I/O0L - I/O35L
Din_L
Din_R
,
CLK
R
CLK
L
(1)
17R
(1)
0L
A
A
17L
Counter/
Address
Reg.
Counter/
Address
Reg.
A
A
0R
REPEAT
ADS
CNTEN
ADDR_R
ADDR_L
REPEAT
L
R
R
ADS
L
R
CNTEN
L
TDI
TCK
TMS
TRST
INTERRUPT
CE
CE1
0
R
CE
0
L
JTAG
COLLISION
DETECTION
LOGIC
R
CE1
TDO
L
R/
W
L
R/W
R
COL
L
COL
R
INT
L
INT
R
(2)
(2)
ZZR
ZZ
ZZL
CONTROL
LOGIC
7144 drw 01
NOTES:
1. Address A17 is a NC for the IDT70P3599.
+. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and the
JUNE 2009
sleep mode pins themselves (ZZx) are not affected during sleep mode.
1
DSC 7144/3
©2009IntegratedDeviceTechnology,Inc.
IDT70P3519/99
High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Description:
TheIDT70P3519/99isahigh-speed256/128Kx36bitsynchronous or bidirectional data flow in bursts. An automatic power down feature,
Dual-Port RAM. The memory array utilizes Dual-Port memory cells to controlledbyCE0 andCE1, permits the on-chipcircuitryofeachportto
allowsimultaneousaccessofanyaddressfrombothports.Registerson enter a very low standby power mode.
control,data,andaddressinputsprovideminimalsetupandholdtimes.
The70P3519/99 cansupportanoperatingvoltageof 3.3V, 2.5Vor
The timing latitude provided by this approach allows systems to be 1.8V on one or both ports. The power supply for the core of the device
designed with very short cycle times. With an input data register, the (VDD) is 1.8V.
IDT70P3519/99hasbeenoptimizedforapplicationshavingunidirectional
6.42
2
FEBRUARY 15, 2008
IDT70P3519/99
High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Pin Configuration (2,3,4)
70P3519/99BC
BC-256(5)
256-Pin BGA
Top View(6)
02/12/08
A1
A2
A3
A6
A7
A8
A9
A11
A12
A13
A14
A4
A5
A10
A15
A16
(1)
NC
TDI
NC
A
11L
A
8L
9L
7L
BE2L CE1L
CNTEN
L
L
A
5L
4L
A
2L
A
0L
A
17L
A
14L
OE
L
NC
NC
B1
B2
B3
B6
B7
B9
CE0L
B11
B12
B13
B4
B5
B8
B10
B14
B15
B16
I/O18L NC TDO
A
12L
10L
A
REPEAT
A
A
1L
NC
A
15L
BE3L
R/W
L
VDD I/O17L NC
C1
C5
C6
C2
C3
C4
C7
C8
C9
C10
C11
C12
C13
C16
C14
C15
I/O18R
A
13L
A
I/O19L
V
SS
A
BE1L BE0L CLK
L
ADS
L
A
6L
A
3L
I/O16L
A
16L
NC I/O17R
D1
D2
D6
D9
D11
D3
D5
D7
D8
D10
D12
D13
D14
D15
D16
D4
I/O20R I/O19R
V
DDQL
V
DDQL
VDDQR
I/O20L
VDDQL
V
DDQR
V
DDQR
V
DDQL
VDDQR
VDD I/O15R I/O15L I/O16R
PIPE/FT
L
E6
E5
E7
E8
E9
E10
E11
E12
E13
E1
E2
E3
E4
E14
E16
E15
V
DD
V
DD
INT
L
V
SS
V
SS
SS
SS
SS
V
SS
V
DD
V
DD
V
DDQR
I/O13L
I/O21R I/O21L I/O22L
V
DDQL
I/O14R
I/O14L
F7
F1 F2 F3
F5
F6
F9
F10
F14
F15
F16
F11
F13
F4
F8
F12
COL
L
VDD
NC
V
VSS
I/O23L I/O22R I/O23R
G1
V
SS
V
DDQR I/O12R I/O13R I/O12L
V
SS
SS
SS
VDD
VDDQL
G5
G2
G4
G6
G8
G9
G3
G7
G10
G12
G13 G14 G15 G16
G11
I/O24R
V
SS
I/O24L
VDDQR
V
SS
SS
V
V
I/O25L
I/O10L I/O11L I/O11R
H16
VSS
VSS
VSS
V
DDQL
V
SS
H11
H12
H13
H7
H8
H9
H10
H14
H15
H3
H4
H5
H6
H1
H2
V
SS
VSS
V
DDQL
I/O10R
V
SS
V
V
V
SS
I/O9R IO9L
V
SS
V
I/O26R
VDDQR
I/O26L I/O25R
J1
J2
J3
J4
J5
J6
J7
J8
J9
J13
J10
J11
J12
J14
J15
J16
I/O27L
I/O28R I/O27R
V
DDQL ZZ
R
V
SS
V
SS
V
SS
V
SS
SS
V
DDQR
I/O8R
V
SS
V
SS
ZZ
L
I/O7R I/O8L
K6
K8
K10
K12
K13
K5
K7
K9
K11
K2
K4
K15
K16
K1
K3
K14
VSS
V
SS
VSS
VSS
V
DDQR
I/O6R
I/O29L
V
DDQL
V
SS
V
SS
V
V
SS
SS
I/O6L I/O7L
I/O29R
I/O28L
L7
L8
L11
L12
L13
L3
L4
L5
L6
L9
L10
L15
L16
L1
L2
L14
COL
R
V
SS
V
VDD
V
DDQL
I/O30R
VDDQR
V
DD
NC
V
SS
V
SS
I/O4R I/O5R
I/O30L I/O31R
I/O5L
M5
M6
M7
M8
M9
M10
M11
M12
M13
M1 M2
M3
M4
M16
M14
M15
V
DD
V
DD INT
R
VSS
V
SS
VSS
V
DD
VDD
V
DDQL
I/O3R I/O3L
I/O32R I/O32L I/O31L
VDDQR
I/O4L
N8
N12
N16
N13
N4
N5
N6
N7
N9
N10
N11
N15
N1
N2
N3
N14
V
DDQL
V
DDQL
V
DD
I/O2R
I/O1R
R VDDQR
P5
V
DDQR
V
DDQL
V
DDQR
V
DDQR
V
DDQL
PIPE/FT
I/O33L I/O34R I/O33R
I/O2L
P1
P2
P3
P4
P7
P8
P9
P10
P11
P12
P14
P15
P16
P6
P13
A
16R
I/O35R I/O34L TMS
A
13R
A
7R BE1R BE0R CLK
R
ADS
R
A
6R
I/O0L I/O0R I/O1L
A
10R
A3R
R5
R6
R7
R8 R9 R10
R11
R16
R1
R2
R3
R4
R12
R13
R14
R15
,
A
15R
A
12R
A
9R
BE3R CE0R R/W
R
REPEAT
R
NC
I/O35L NC TRST NC
A4R
A1R
NC
NC
T2
T3
T4
17R
T1
T5
T8
T9
T15
T16
T6
T7
T10
T11
T12
T13
T14
(1)
A
TCK
NC
NC
A
14R
BE2R CE1R
NC
NC
A
11R
A
8R
OE
R
CNTEN
R
A
5R
A2R
A
0R
NOTES:
1. Pin is a NC for IDT70P3599.
7144 drw 02d
2. All VDD pins must be connected to 1.8V power supply.
3. All VSS pins must be connected to ground supply.
,
4. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
6.42
3
IDT70P3519/99
High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Pin Configuration (2,3,4) (con't.)
02/12/08
A1
A2
A3
A6
A7
A8
A9
BE1L
A11
A12
A13
A14
A17
A4
A10
A15
A16
A5
I/O19L I/O18L
V
SS
A
12L
A
8L
CLK
L
CNTEN
L
A4L
A
0L
V
SS
TDO
A
16L
13L
14L
V
DD
NC I/O17L
COL
L
B1
B2
B3
B6
B7
B9
CE0L
B11
B12
B13
B17
B4
B5
B8
B10
B14
B15
B16
(1)
I/O20R
V
SS I/O18R
A17L
A
A
9L
ADS
L
A
5L
A
1L
I/O15R
TDI
BE2L
VSS
NC
VDDQR I/O16L
C1
C6
C2
C3
C4
C5
C7
C8
C9
C10
C11
C12
C13
C16
C14
C15
C17
VDDQL
A
I/O19R
VDDQR PL/FT
L
INT
L
A
10L BE3L CE1L
V
SS R/W
L
A
6L
A
2L
I/O15L
VDD I/O16R
VSS
D1
D2
D6
D9
D11
D3
D5
D7
D8
D10
D12
D13
D14 D15
D16
D17
D4
I/O22L
V
SS
A
11L
V
DD
REPEATL
I/O21L
A15L
A7L BE0L
OE
L
A3L
VDD I/O17R
V
DDQL I/O14L I/O14R
I/O20L
E1
E2
E3
E4
E14
E16
E17
E15
I/O23L I/O22R
VDDQR I/O21R
I/O12L
VSS I/O13L
I/O13R
F1
F2
F3
F14
F15
F16
F17
F4
VDDQL I/O23R I/O24L
VSS I/O12R I/O11L VDDQR
VSS
G1
G2
G4
G14
G15
G16
G3
G17
I/O26L
V
SS
I/O24R
H4
I/O9L
V
DDQL I/O10L
I/O25L
I/O11R
H3
H1
H2
H16
H17
H14
H15
70P3519/99BF
BF-208(5)
V
DDQR I/O25R
VDD I/O26R
V
SS I/O10R
VDD I/O9R
J1
J2
J3 J4
J14
J15
J16
J17
VDDQL
VDD
VSS
ZZ
R
ZZL
V
DD
VSS
VDDQR
208-Pin fpBGA
Top View(6)
K2
K4
K15
K16
K1
K3
K14
K17
V
SS
V
SS
VDDQL I/O8R
I/O7R
I/O28R
I/O27R
V
SS
L3
L4
L15
L16
L17
L1
L2
L14
V
DDQR I/O27L
I/O7L
V
SS I/O8L
I/O29R I/O28L
I/O6R
M1
M2
M3
M4
M16
M17
M14
M15
V
DDQL I/O29L I/O30R
V
SS
I/O5R
VDDQR
V
SS
I/O6L
N16
N17
N4
N15
N1
N2
N3
N14
I/O4R I/O5L
DDQL
I/O30L
V
I/O31L
V
SS I/O31R
I/O3R
P12
P1
P2
P3
P4
P5
P7
P8
P9
P10
P11
P14
P15
P16
P17
P6
P13
A
16R
I/O32R I/O32L
V
DDQR I/O35R TRST
A12R
A8R BE1R
V
DD CLK
R
CNTEN
R
I/O2L I/O3L
V
SS I/O4L
A
4R
R5
R6
R7
R8
R9
R10
R11
R16
R1
R2
R3
R4
R12
R13
R14
R17
R15
(1)
R
A
17R
A
13R
A
9R
BE2R CE0R
V
SS ADS
R
R
I/O1R
V
SS I/O33L I/O34R TCK
A
5R
A
1R
NC
V
DDQR
V
DDQL
T2
T3
T1
T4
T5
T8
T9
T15
T16
T17
T6
T7
T10
T11
T12
T13
T14
SS
I/O34L
VDDQL
I/O33R
TMS INT
BE3R CE1R
I/O0R
VSS I/O2R
A
14R
A10R
V
SS R/W
A
6R
A
2R
V
U1
U2
U3
U4
U5
U6
U7
U17
U8
BE0R
U9
U10
U12
U13
U14
DD
U16
U15
V
SS I/O35L PL/FT
R
COL
R
A
15R
A
11R
A
7R
I/O1L
V
DD
OE
R
A3R
A
0R
V
I/O0L
NC
7144 drw 02c
NOTES:
1. Pin is a NC for IDT70P3599.
2. All VDD pins must be connected to 1.8V power supply.
3. All VSS pins must be connected to ground supply.
4. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
6.42
4
FEBRUARY 15, 2008
IDT70P3519/99
High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
PinNames
Left Port
Right Port
Names
Chip Enables (Input)(5)
CE0L
R/W
OE
,
CE1L
CE0R
R/W
OE
,
CE1R
L
R
Read/Write Enable (Input)
Output Enable (Input)
Address (Input)
L
R
(4)
(4)
A
0L - A17L
A
0R - A17R
I/O0R - I/O35R
CLK
I/O0L - I/O35L
CLK
Data Input/Output
L
R
Clock (Input)
PL/FT
ADS
CNTEN
REPEAT
BE0L - BE3L
DDQL
L
PL/FT
ADS
CNTEN
REPEAT
BE0R - BE3R
DDQR
R
Pipeline/Flow-Through (Input)
Address Strobe Enable (Input)
Counter Enable (Input)
L
R
L
R
(2)
Counter Repeat
L
R
Byte Enables (9-bit bytes) (Input)(5)
Power (I/O Bus) (3.3V, 2.5V or 1.8V)(1) (Input)
Sleep Mode pin(3) (Input)
Power (1.8V)(1) (Input)
V
V
ZZL
ZZR
V
DD
NOTES:
VSS
Ground (0V) (Input)
1. VDD and VDDQX must be set to appropriate operating levels prior to applying inputs
on the I/Os and controls for that port.
2. When REPEATX is asserted, the counter will reset to the last valid address loaded
via ADSX.
3. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when
asserted. All static inputs, i.e., PL/FTx and the sleep mode pins themselves
(ZZx) are not affected during sleep mode.
4. Address A17x is a NC for the IDT70P3599.
5. Chip Enables and Byte Enables are double buffered when PL/FT = VIH, i.e., the
signals take two cycles to deselect.
TDI
TDO
TCK
TMS
TRST
Test Data Input
Test Data Output
Test Logic Clock (10MHz) (Input)
Test Mode Select (Input)
Reset (Initialize TAP Controller) (Input)
Interrupt Flag (Output)
INTR
INTL
COL
R
COL
L
Collision Alert (Output)
7144 tbl 01
6.42
5
IDT70P3519/99
High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Truth Table I—Read/Write and Enable Control(1,2,3,4)
Byte 3
I/O27-35
Byte 2
I/O18-26
Byte 1
I/O9-17
Byte 0
I/O0-8
CLK
CE
1
R/W
X
X
X
L
ZZ
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
MODE
OE
X
X
X
X
X
X
X
X
X
X
L
CE
0
BE
3
BE
2
BE
1
BE0
↑
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
X
L
X
X
H
H
H
H
L
X
X
H
H
H
L
X
X
H
H
L
X
X
H
L
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z Deselected–Power Down
High-Z Deselected–Power Down
High-Z All Bytes Deselected
↑
↑
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
X
↑
DIN
Write to Byte 0 Only
↑
H
H
H
L
L
DIN
High-Z Write to Byte 1 Only
High-Z Write to Byte 2 Only
High-Z Write to Byte 3 Only
↑
H
H
L
L
DIN
High-Z
High-Z
↑
H
H
L
L
DIN
High-Z
High-Z
↑
H
L
L
High-Z
DIN
DIN
Write to Lower 2 Bytes Only
↑
H
L
H
L
L
DIN
DIN
High-Z
High-Z Write to Upper 2 bytes Only
↑
L
L
L
DIN
DIN
DIN
DIN
Write to All Bytes
Read Byte 0 Only
↑
H
H
H
L
H
H
L
H
L
L
H
H
H
H
H
H
H
X
X
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
DOUT
L
↑
H
H
H
L
DOUT
High-Z Read Byte 1 Only
High-Z Read Byte 2 Only
High-Z Read Byte 3 Only
L
↑
H
H
L
DOUT
High-Z
High-Z
L
↑
H
H
L
DOUT
High-Z
High-Z
L
↑
H
L
High-Z
DOUT
D
OUT
Read Lower 2 Bytes Only
High-Z Read Upper 2 Bytes Only
Read All Bytes
L
↑
H
L
H
L
DOUT
DOUT
High-Z
L
↑
L
L
DOUT
DOUT
DOUT
DOUT
H
X
↑
X
X
X
X
X
X
X
X
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z Outputs Disabled
High-Z Sleep Mode
X
7144 tbl 02
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, REPEAT = X.
3. OE and ZZ are asynchronous input signals.
4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.
TruthTable II—Address Counter Control(1,2)
Previous
Internal
Address
Internal
Address
Used
MODE
(3)
ADS(4) CNTEN(5) REPEAT(4,6)
Address
CLK
↑
I/O
I/O (n) External Address Used
I/O(n+1) Counter Enabled—Internal Address generation
I/O(n+1) External Address Blocked—Counter disabled (An + 1 reused)
DI/O(n) Counter Set to last valid ADS load
An
X
X
An
An
L
X
H
H
H
L
D
An + 1
An + 1
An
↑
H
L
D
X
An + 1
X
↑
H
X
H
X
D
X
↑
7144 tbl 03
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. Read and write operations are controlled by the appropriate setting of R/W, CE0, CE1, BEn and OE.
3. Outputs configured in flow-through output mode: if outputs are in pipelined mode the data out will be delayed by one cycle.
4. ADS and REPEAT are independent of all other memory control signals including CE0, CE1 and BEn
5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE1, BEn.
6. When REPEAT is asserted, the counter will reset to the last valid address loaded via ADS. This value is not set at power-up: a known location should be loaded
via ADS during initialization if desired. Any subsequent ADS access during operations will update the REPEAT address location.
6.42
6
FEBRUARY 15, 2008
IDT70P3519/99
High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
RecommendedOperating
TemperatureandSupplyVoltage(1)
Ambient
Grade
Temperature
0OC to +70OC
-40OC to +85OC
GND
VDD
Commercial
0V
1.8V
1.8V
+
+
100mV
Industrial
0V
100mV
7144 tbl 04
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
RecommendedDCOperating
Conditions with VDDQ at 1.8V
Symbol
Parameter
Core Supply Voltage
I/O Supply Voltage
Ground
Min.
Typ.
Max.
1.9
1.9
0
Unit
V
V
DD
DDQ
SS
IH
1.7
1.8
V
1.7
1.8
V
V
0
0
V
(2)
____
V
Input High Voltage
0.7 VDDQ
VDDQ + 100mV
V
_
Input High Voltage
JTAG
(2)
____
VIH
0.7 VDDQL
V
DDQL + 100mV
V
(3)
Input High Voltage -
ZZ, PIPE/FT
(2)
____
____
____
V
IH
V
DDQ - 0.2V
V
DDQ + 100mV
V
V
V
VIL
Input Low Voltage
-0.3(1)
0.3 VDDQ
0.2
Input Low Voltage -
ZZ, PIPE/FT
VIL
-0.3(1)
7144 tbl 05c
NOTES:
1. VIL (min.) = -0.75V for pulse width less than tCYC/2, or 5ns, whichever is less.
2. VIH (max.) = VDDQ + 0.75V for pulse width less than tCYC/2 or 5ns, whichever is less.
3. JTAG is driven by the left port VDDQL.
RecommendedDCOperating
Conditions with VDDQ at 2.5V
Symbol
Parameter
Core Supply Voltage
I/O Supply Voltage
Ground
Min.
1.7
2.4
0
Typ.
1.8
Max.
1.9
2.6
0
Unit
V
V
DD
DDQ
SS
IH
V
2.5
V
V
0
V
(2)
____
V
Input High Volltage
Input High Voltage _
1.7
V
DDQ + 100mV
V
(2)
____
VIH
1.7
VDDQL + 100mV
V
(3)
JTAG
Input High Voltage -
ZZ, PIPE/FT
(2)
____
____
____
V
IH
V
DDQ - 0.2V
V
DDQ + 100mV
V
V
V
VIL
Input Low Voltage
-0.3(1)
0.7
0.2
Input Low Voltage -
ZZ, PIPE/FT
VIL
-0.3(1)
7144 tbl 05a
NOTES:
1. VIL (min.) = -1.0V for pulse width less than tCYC/2 or 5ns, whichever is less.
2. VIH (max.) = VDDQ + 1.0V for pulse width less than tCYC/2 or 5ns, whichever is less.
3. JTAG is driven by the left port VDDQL.
6.42
7
IDT70P3519/99
High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
RecommendedDCOperating
Conditions with VDDQ at 3.3V
Symbol
Parameter
Core Supply Voltage
I/O Supply Voltage
Ground
Min.
1.7
3.15
0
Typ.
1.8
Max.
1.9
3.45
0
Unit
V
V
DD
DDQ
SS
IH
V
3.3
V
V
0
V
(2)
____
V
Input High Voltage
2.0
VDDQ + 150mV
V
_
Input High Voltage
JTAG
(2)
____
VIH
2.0
V
DDQL + 150mV
V
(3)
Input High Voltage -
ZZ, PIPE/FT
(2)
____
____
____
V
IH
V
DDQ - 0.2V
V
DDQ + 150mV
V
V
V
(1)
VIL
Input Low Voltage
-0.3
0.8
0.2
Input Low Voltage -
ZZ, PIPE/FT
(1)
VIL
-0.3
7144 tbl 05b
NOTES:
1. VIL (min.) = -1.0V for pulse width less than tCYC/2, or 5ns, whichever is less.
2. VIH (max.) = VDDQ + 1.0V for pulse width less than tCYC/2 or 5ns, whichever is less.
3. JTAG is driven by the left port VDDQL.
AbsoluteMaximumRatings(1)
Symbol
Rating
Commercial
& Industrial
Unit
V
V
TERM
VDD Terminal Voltage
- 0.5 to + 2.5
- 0.3 to + 4.2
(VDD
)
with Respect to GND
(2)
TERM
V
VDDQ Te rminal Vo ltag e
V
(VDDQ
)
with Respect to GND
(4)
(2)
TERM
V
Input and I/O Terminal
- 0.3 to min. {VDDQ + 0.3, 4.2}
V
(INPUTS and I/O's)
Voltage with Respect to GND
(3)
T
BIAS
STG
JN
Temperature Under Bias
Storage Temperature
Junction Temperature
-55 to +125
oC
oC
T
-65 to +150
T
+150
50
oC
I
OUT(For VDDQ = 3.3V) DC Output Current
OUT(For VDDQ = 2.5V) DC Output Current
OUT(For VDDQ = 1.8V) DC Output Current
mA
mA
I
40
I
35
mA
7144 tbl 06
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. This is a steady-state DC parameter that applies after the power supply has reached its
nominal operating value. Power sequencing is not necessary; however, the voltage
on any Input or I/O pin cannot exceed VDDQ during power supply ramp up.
3. Ambient Temperature under DC Bias. No AC Conditions. Chip Deselected.
4. VTERM (Inputs and I/O's) -0.3 to min {VDDQ + 0.3, 4.2} means that the range is -0.3V to
either VDDQ +0.3V or 4.2V whichever is less.
6.42
8
FEBRUARY 15, 2008
IDT70P3519/99
High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Capacitance(1)
(TA = +25°C, F = 1.0MHZ)
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions(2)
IN = 3dV
OUT = 3dV
Max. Unit
CIN
V
8
pF
(3)
OUT
C
V
10.5
pF
7144 tbl 07
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch
from 0V to 3V or from 3V to 0V.
3. COUT also references CI/O.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(VDD = 1.8V ± 100mV)
70P3519/99S
Symbol
|ILI
|ILI
|ILO
Parameter
Input Leakage Current
Test Conditions
DDQ = Max., VIN = 0V to VDDQ
DDQL = Max. IN = 0V to VDDQL
Min.
Max.
10
Unit
µA
µA
µA
V
___
___
___
___
|
V
(1)
|
JTAG & ZZ Input Leakage Current
Output Leakage Current(2)
V
,
V
30
|
10
CE
OL = +4mA, VDDQ = Min.
OH = -4mA, VDDQ = Min.
OL = +2mA, VDDQ = Min.
OH = -2mA, VDDQ = Min.
OL = +2mA, VDDQ = Min.
OH = -2mA, VDDQ = Min.
0
= VIH or CE
1
= VIL, VOUT = 0V to VDDQ
V
OL (3.3V) Output Low Voltage
OH (3.3V) Output High Voltage
OL (2.5V) Output Low Voltage
OH (2.5V) Output High Voltage
OL (1.8V) Output Low Voltage
OH (1.8V) Output High Voltage
I
0.4
___
V
I
2.4
V
___
V
I
0.4
V
___
V
I
2.0
V
___
V
I
0.4
V
___
V
I
V
DDQ -0.40
V
7144 tbl 08
NOTES:
1. Applicable only for TMS, TDI and TRST inputs.
2. Outputs tested in tri-state mode.
6.42
9
IDT70P3519/99
High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(3)(VDD = 1.8V ± 100mV)
70P3519/99
S200
70P3519/99
S166
Com'l Only
Com'l & Ind
Symbol
Parameter
Test Condition
Version
COM'L
Typ.(4)
Max.
Typ.(4)
Max.
285
325
170
205
230
270
45
Unit
IDD
Dynamic Operating
Current (Both
Ports Active)
CE
L
and CER= VIL,
S
S
S
S
S
S
S
S
S
S
S
S
226
325
190
190
102
102
148
148
15
mA
Outputs Disabled,
___
___
(1)
IND
f = fMAX
I
SB1(6)
Standby Current
(Both Ports - TTL
Level Inputs)
CEL
= CE
R
= VIH
COM'L
IND
120
195
(1)
mA
mA
mA
mA
f = fMAX
___
___
SB2(6)
Standby Current
(One Port - TTL
Level Inputs)
(5)
I
CE"A" = VIL and CE"B" = VIH
COM'L
IND
176
265
Active Port Outputs Disabled,
___
___
(1)
f=fMAX
ISB3
Full Standby Current
(Both Ports - CMOS
Level Inputs)
Both Ports CE
CE > VDDQ - 0.2V, VIN > VDDQ - 0.2V
or VIN < 0.2V, f = 0(2)
L and
COM'L
IND
15
45
R
___
___
15
60
SB4(6)
Full Standby Current
(One Port - CMOS
Level Inputs)
(5)
I
CE"A" < 0.2V and CE"B" > VDDQ - 0.2V
IN > VDDQ - 0.2V or VIN < 0.2V
Active Port, Outputs Disabled, f = fMAX
COM'L
IND
176
265
148
148
15
230
270
45
V
___
___
(1)
Izz
Sleep Mode Current
(Both Ports - TTL
Level Inputs)
ZZL = ZZR =
f=fMAX
VIH
COM'L
IND
15
45
(1)
mA
___
___
15
60
7144 tbl 09
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS".
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. VDD = 1.8V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 15mA (Typ).
5. CEX = VIL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VDDQ - 0.2V
CEX > VDDQ - 0.2V means CE0X > VDDQ - 0.2V or CE1X - 0.2V
"X" represents "L" for left port or "R" for right port.
6. ISB1, ISB2 and ISB4 will all reach full standby levels (ISB3) on the appropriate port(s) if ZZL and/or ZZR = VIH.
6.42
10
FEBRUARY 15, 2008
IDT70P3519/99
High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
AC Test Conditions (VDDQ - 3.3V/2.5V/1.8V)
Input Pulse Levels (Address & Controls)
Input Pulse Levels (I/Os)
Input Rise/Fall Times
GND to 3.0V/GND to 2.4V/GND to 1.7V
GND to 3.0V/GND to 2.4V/GND to 1.7V
2ns
Input Timing Reference Levels
Output Reference Levels
Output Load
1.5V/1.25V/0.85V
1.5V/1.25V/0.85V
Figure 1
7144 tbl 10
50Ω
50Ω
,
DATAOUT
1.5V/1.25V/0.85V
10pF
(Tester)
7144 drw 03
Figure 1. AC Output Test load.
∆
tCD
(Typical, ns)
7144 drw 04
∆
Capacitance (pF) from AC Test Load
6.42
11
IDT70P3519/99
High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing)(2,3) (VDD = 1.8V ± 100mV, TA = 0°C to +70°C)
70P3519/99
S200
Com'l Only
70P3519/99
S166
Com'l & Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
ns
t
CYC1
CYC2
CH1
CL1
CH2
CL2
SA
HA
SC
HC
SB
HB
SW
HW
SD
HD
SAD
HAD
SCN
HCN
SRPT
HRPT
OE
Clock Cycle Time (Flow-Through)(1)
Clock Cycle Time (Pipelined)(1)
Clock High Time (Flow-Through)(1)
Clock Low Time (Flow-Through)(1)
Clock High Time (Pipelined)(2)
Clock Low Time (Pipelined)(1)
Address Setup Time
15
5
20
6
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
ns
t
6
8
ns
t
6
8
ns
t
2
2.4
2.4
1.7
0.5
1.7
0.5
1.7
0.5
1.7
0.5
1.7
0.5
1.7
0.5
1.7
0.5
1.7
ns
t
2
ns
t
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
ns
t
Address Hold Time
ns
t
Chip Enable Setup Time
Chip Enable Hold Time
Byte Enable Setup Time
Byte Enable Hold Time
R/W Setup Time
ns
t
ns
t
ns
t
ns
t
ns
t
R/W Hold Time
ns
t
Input Data Setup Time
ns
t
Input Data Hold Time
ns
t
ns
ADS Setup Time
t
ns
ADS Hold Time
t
ns
CNTEN Setup Time
t
ns
CNTEN Hold Time
t
ns
REPEAT Setup Time
t
0.5
0.5
ns
REPEAT Hold Time
____
____
t
Output Enable to Data Valid
Output Enable to Output Low-Z
Output Enable to Output High-Z
Clock to Data Valid (Flow-Through)(1)
Clock to Data Valid (Pipelined)(1)
Data Output Hold After Clock High
Clock High to Output High-Z
Clock High to Output Low-Z
Interrupt Flag Set Time
4.4
4.4
ns
(4)
____
____
t
OLZ
1
1
ns
(4)
OHZ
t
1
3.4
10
1
3.6
12
ns
____
____
t
CD1
CD2
DC
ns
____
____
t
3.4
3.6
ns
____
____
t
1
1
1
1
ns
(4)
CKHZ
t
3.4
3.6
ns
(4)
CKLZ
____
____
t
1
1
ns
____
____
t
INS
INR
COLS
COLR
ZZSC
ZZRC
7
7
7
7
ns
____
____
____
____
____
____
t
Interrupt Flag Reset Time
Collision Flag Set Time
Collision Flag Reset Time
Sleep Mode Set Cycles
Sleep Mode Recovery Cycles
ns
t
3.4
3.6
ns
t
3.4
3.6
ns
____
____
t
2
3
2
3
cycles
cycles
____
____
t
Port-to-Port Delay
Clock-to-Clock Offset
____
____
tCO
4
5
ns
Please refer to Collision Detection Timing Table
on Page 21
tOFS
Clock-to-Clock Offset for Collision Detection
7144 tbl 11
NOTES:
1. The Pipelined output parameters (tCYC2, tCD2) apply to either or both left and right ports when PL/FTX = VDD (1.8V). Flow-through parameters (tCYC1, tCD1) apply
when PL/FT = VSS (0V) for that port.
2. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE) and PL/FT. PL/FT should be treated as DC
signals, i.e. steady state during operation.
3. These values are valid for any level of VDDQ (3.3V/2.5V/1.8V).
4. Guaranteed by design (not production tested).
6.42
12
FEBRUARY 15, 2008
IDT70P3519/99
High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle for Pipelined Operation
(1,2)
(FT/PIPE'X' = VIH
)
tCYC2
tCH2
tCL2
CLK
CE
0
t
SC
(3)
tHC
tSC
tHC
CE1
t
SB
tHB
tSB
tHB
(5)
BE
n
R/
W
tHW
tSW
t
SA
tHA
ADDRESS(4)
DATAOUT
An
An + 1
An + 2
Qn
An + 3
(1 Latency)
t
DC
tCD2
Qn + 1
Qn + 2(5)
(1)
t
CKLZ
t
OHZ
tOLZ
(1)
OE
,
tOE
7144 drw 05
Timing Waveform of Read Cycle for Flow-through Output
(1,2,6)
(FT/PIPE"X" = VIL
)
tCYC1
tCH1
tCL1
CLK
CE
0
t
SC
(3)
tHC
t
SC
SB
t
HC
CE1
t
t
HB
t
HB
BEn
tSB
R/W
t
SW
t
HW
HA
t
SA
t
ADDRESS(4)
DATAOUT
An
An + 1
An + 2
An + 3
tDC
tCD1
tCKHZ
Qn
Qn + 1
Qn + 2(5)
t
CKLZ
tDC
t
OHZ
t
OLZ
OE(1)
,
t
OE
7144 drw 06
NOTES:
1. OE is asynchronously controlled; all other inputs depicted in the above waveforms are synchronous to the rising clock edge.
2. ADS = VIL, CNTEN and REPEAT = VIH
.
3. The output is disabled (High-Impedance state) by CE
0
= VIH, CE
1
= VIL, BE
n
= VIH following the next rising edge of the clock. Refer to
Truth Table 1.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
5. If BE
n was HIGH, then the appropriate Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state).
6. "x" denotes Left or Right port. The diagram is with respect to that port.
6.42
13
IDT70P3519/99
High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of a Multi-Device Pipelined Read(1,2)
t
CYC2
t
CH2
t
CL2
CLK
ADDRESS(B1)
CE0(B1)
t
SA
tHA
A
6
A
5
A
4
A
3
A
2
A
0
A
1
t
SC
t
HC
t
SC
tHC
t
CD2
t
CD2
t
CKHZ
t
CD2
Q
0
Q3
Q
1
DATAOUT(B1)
ADDRESS(B2)
t
DC
t
CKLZ
t
DC
tCKHZ
t
SA
t
HA
A
6
A
5
A
4
A3
A
2
A
0
A
1
t
SC
t
HC
CE0(B2)
t
SC
t
HC
t
CD2
t
CKHZ
t
CD2
,
DATAOUT(B2)
Q
4
Q
2
t
CKLZ
t
CKLZ
7144 drw 07
Timing Waveform of a Multi-Device Flow-Through Read(1,2)
t
CYC1
tCH1
tCL1
CLK
t
SA
tH
A
A6
A5
A4
A3
A2
A0
A1
ADDRESS(B1)
t
SC
tHC
CE0(B1)
t
SC
tHC
(1)
tCD1
tCD1
t
CKHZ
t
CD1
(1)
tCD1
D0
D3
D5
D1
DATAOUT(B1)
ADDRESS(B2)
(1)
(1)
tDC
t
CKLZ
tCKLZ
t
DC
t
CKHZ
t
SA
tHA
A6
A5
A4
A3
A2
A
0
A1
t
SC
tHC
CE0(B2)
t
SC
t
HC
(1)
(1)
t
CD1
t
CKHZ
t
CD1
(1)
t
CKHZ
D4
DATAOUT(B2)
D2
(1)
,
t
CKLZ
tCKLZ
7144 drw 08
NOTES:
1. B1 Represents Device #1; B2 Represents Device #2. Each Device consists of one IDT70P3519/99 for this waveform,
and are setup for depth expansion in this example. ADDRESS(B1) = ADDRESS(B2) in this situation.
2. BEn, OE, and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and REPEAT = VIH.
6.42
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FEBRUARY 15, 2008
IDT70P3519/99
High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Left Port Write to Pipelined Right Port Read(1,2,4)
CLK"A"
t
SW
tHW
R/W"A
"
t
SA
MATCH
SD HD
VALID
tHA
NO
MATCH
ADDRESS"A"
DATAIN"A"
t
t
(3)
CO
t
CLK"B"
tCD2
R/W"B"
tSW
tHW
tSA
tHA
NO
MATCH
ADDRESS"B"
DATAOUT"B"
MATCH
VALID
,
t
DC
7144 drw 09
NOTES:
1. CE , BE
2. OE = VIL for Port "B", which is being read from. OE = VIH for Port "A", which is being written to.
3. If tCO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (ie, time from write to valid read on opposite port will be
CO + 2 tCYC2 + tCD2). If tCO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (ie, time from write to valid read on opposite port
0
n
, and ADS = VIL; CE , CNTEN, and REPEAT = VIH.
1
t
will be tCO + tCYC2 + tCD2).
4. All timing is the same for Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite of Port "A"
Timing Waveform with Port-to-Port Flow-Through Read(1,2,4)
CLK "A"
t
SW
tHW
R/W "A"
ADDRESS "A"
DATAIN "A"
CLK "B"
t
SA
MATCH
SD HD
VALID
tHA
NO
MATCH
t
t
(3)
t
CO
t
CD1
R/W "B"
t
HW
HA
t
SW
t
t
SA
NO
MATCH
ADDRESS "B"
DATAOUT "B"
MATCH
tCD1
VALID
VALID
,
t
DC
t
DC
7144 drw 10
NOTES:
1. CE , BEn, and ADS = VIL; CE
2. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
3. If tCO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (i.e., time from write to valid read on opposite port will be
CO + tCYC + tCD1). If tCO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (i.e., time from write to valid read on opposite port will
0
1, CNTEN, and REPEAT = VIH.
t
be tCO + tCD1).
4. All timing is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A".
6.42
15
IDT70P3519/99
High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
(2)
Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL
)
tCYC2
tCH2
tCL2
CLK
CE0
CE1
BEn
t
SC
tHC
tSB
tHB
tSW tHW
R/W
tSW tHW
(3)
An + 3
An + 4
An
An +1
An + 2
An + 2
ADDRESS
t
SA
tHA
t
SD
tHD
DATAIN
Dn + 2
tCD2
t
CD2
(1)
t
CKHZ
(4)
tCKLZ
Qn + 3
Qn
DATAOUT
READ
NOP
WRITE
READ
,
7144 drw 11
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE , BE , and ADS = VIL; CE , CNTEN, and REPEAT = VIH. "NOP" is "No Operation".
0
n
1
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
Timing Waveform of Pipelined Read-to-Write-to-Read(OE Controlled)(2)
t
CYC2
tCH2
tCL2
CLK
CE
0
t
SC
tHC
CE1
tSB
tHB
BE
n
t
SW tHW
R/
W
t
SW tHW
(3)
An + 4
An
An +1
An + 2
An + 3
Dn + 3
An + 5
ADDRESS
t
SA
tHA
t
SD
t
HD
DATAIN
Dn + 2
t
CD2
t
CD2
t
CKLZ
(1)
Qn
Qn + 4
DATAOUT
(4)
tOHZ
OE
READ
WRITE
READ
,
NOTES:
7144 drw 12
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE , BE , and ADS = VIL; CE , CNTEN, and REPEAT = VIH
0
n
1
.
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference
use only.
4. This timing does not meet requirements for fastest speed grade. This waveform indicates how logically it could be done if timing so allows.
6.42
16
FEBRUARY 15, 2008
IDT70P3519/99
High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Flow-Through Read-to-Write-to-Read(OE = VIL)(2)
t
CYC1
tCH1
tCL1
CLK
CE
0
1
t
SC
tHC
CE
t
SB
tHB
BEn
t
SW tHW
R/W
tSW tHW
(3)
An + 4
An
An + 3
An +1
An + 2
An + 2
ADDRESS
t
SA
tHA
t
SD
t
HD
DATAIN
Dn + 2
t
CD1
tCD1
t
CD1
tCD1
(1)
Qn + 3
Qn
READ
Qn + 1
DATAOUT
tDC
t
CKLZ
t
DC
tCKHZ
NOP(5)
,
READ
WRITE
7144 drw 13
Timing Waveform of Flow-Through Read-to-Write-to-Read(OE Controlled)(2)
t
CYC1
t
CH1
tCL1
CLK
CE
0
1
t
SC
tHC
CE
t
SB
tHB
BEn
t
SW tHW
t
SW tHW
R/
W
(3)
An + 5
An
An + 4
An +1
An + 2
An + 3
Dn + 3
ADDRESS
DATAIN
t
SA
tHA
t
SD tHD
Dn + 2
tOE
t
DC
t
CD1
tCD1
t
CD1
(1)
Qn + 4
Qn
DATAOUT
tCKLZ
t
DC
t
OHZ
OE
,
READ
WRITE
READ
7144 drw 14
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for
reference use only.
4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
6.42
17
IDT70P3519/99
High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read with Address Counter Advance(1)
t
CYC2
tCH2
tCL2
CLK
tSA
tHA
An
ADDRESS
t
SAD tHAD
ADS
tSAD tHAD
CNTEN
tSCN tHCN
tCD2
,
Qn + 2(2)
Qx - 1(2)
Qx
Qn + 1
Qn + 3
Qn
DATAOUT
tDC
READ
EXTERNAL
ADDRESS
READ
WITH
COUNTER
COUNTER
HOLD
READ WITH COUNTER
7144 drw 15
TimingWaveformof Flow-ThroughReadwithAddressCounterAdvance(1)
t
CYC1
tCH1
tCL1
CLK
tSA
tHA
An
ADDRESS
t
SAD tHAD
t
SAD
t
HAD
ADS
t
SCN
tHCN
CNTEN
t
CD1
,
Qn + 3(2)
Qx(2)
Qn + 4
Qn + 1
Qn + 2
Qn
DATAOUT
tDC
READ
WITH
COUNTER
READ
EXTERNAL
ADDRESS
READ WITH COUNTER
COUNTER
HOLD
7144 drw 16
NOTES:
1. CE , OE, BEn = VIL; CE , R/W, and REPEAT = VIH.
0
1
2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then
the data output remains constant for subsequent clocks.
6.42
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FEBRUARY 15, 2008
IDT70P3519/99
High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Address Counter Advance
(Flow-through or Pipelined Inputs)(1)
t
CYC2
tCH2
tCL2
CLK
t
SA
tHA
An
ADDRESS
INTERNAL(3)
ADDRESS
An(7)
An + 4
An + 2
An + 1
An + 3
t
SAD tHAD
ADS
t
SCN
t
HC
N
CNTEN
t
SD tHD
Dn + 4
Dn + 1
Dn + 3
Dn
Dn + 1
Dn + 2
DATAIN
WRITE
EXTERNAL
ADDRESS
WRITE
WITH COUNTER
WRITE
COUNTER HOLD
WRITE WITH COUNTER
,
7144 drw 17
Timing Waveform of Counter Repeat(2,6)
tCYC2
CLK
tSA tHA
An
ADDRESS
INTERNAL(3)
ADDRESS
An+2
An+1
An+2
An+2
An
An
An+1
An+2
tSAD tHAD
ADS
tSW tHW
R/
W
t
SCN tHCN
CNTEN
(4)
REPEAT
SRPT tHRPT
t
,
t
SD
t
HD
D3
D2
D0
D1
DATAIN
tCD1
An
An+1
An+2
An+2
HOLD
DATAOUT
,
ADVANCE
COUNTER
WRITE TO
An+2
ADVANCE
COUNTER
WRITE TO
An+1
HOLD
REPEAT
READ LAST
ADS
ADDRESS
An
ADVANCE
COUNTER
READ
WRITE TO
ADS
ADDRESS
An
ADVANCE
COUNTER
READ
COUNTER
WRITE TO
An+2
COUNTER
READ
An+1
An+2
An+2
7144 drw 18
NOTES:
1. CE , BE
CE , BE
0
n
, and R/W = VIL; CE
1
and REPEAT = VIH
.
0
n
= VIL; CE1 = VIH.
2.
3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH
.
4. No dead cycle exists during REPEAT operation. A READ or WRITE cycle may be coincidental with the counter REPEAT cycle: Address loaded by last valid
ADS load will be accessed. For more information on REPEAT function refer to Truth Table II.
5. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is
written to during this cycle.
6. For Pipelined Mode user should add 1 cycle latency for outputs as per timing waveform of read cycle for pipelined operations.
6.42
19
IDT70P3519/99
High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Waveform of Interrupt Timing(2)
CLK
L
t
SW
tHW
R/W
L
t
SA
3FFFF(4)
SC HC
t
HA
ADDRESSL(3)
CEL(1)
t
t
tINS
INT
R
tINR
CLKR
t
SC
tHC
CER(1)
R/WR
t
SW
SA
t
HW
HA
t
t
3FFFF(4)
ADDRESSR(3)
7144 drw 19
NOTES:
1. CE0 = VIL and CE1 = VIH
2. All timing is the same for Left and Right ports.
3. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.
4. For IDT70P3599, the Interrupt Address is 1FFFF.
Truth Table III — Interrupt Flag(1)
Left Port
Right Port
(2)
(2)
(3,4)
(2)
(2)
(3,4)
CLK
L
R/W
L
CE
L
A
17L-A0L
CLK
R
R/W
R
CE
R
A
17R-A0R
Function
Set Right INT Flag
Reset Right INT Flag
Set Left INT Flag
Reset Left INT Flag
INT
L
INTR
↑
↑
↑
↑
L
X
X
H
L
3FFFF
X
X
↑
↑
↑
↑
X
H
L
X
L
L
X
X
L
R
X
X
L
X
3FFFF
3FFFE
X
H
X
X
R
X
L
L
3FFFE
H
X
L
7144 tbl 12
NOTES:
1. INTL and INTR must be initialized at power-up by Resetting the flags.
2. CE0 = VIL and CE1 = VIH. R/W and CE are synchronous with respect to the clock and need valid set-up and hold times.
3. A17X is a NC for IDT70P3599, therefore Interrupt Addresses are 1FFFF and 1FFFE.
4. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.
6.42
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FEBRUARY 15, 2008
IDT70P3519/99
High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Waveform of Collision Timing(1,2)
Both Ports Writing with Left Port Clock Leading
CLK
L
t
OFS
tSA
tHA
ADDRESS (4)
L
A
3
A
1
A2
A
0
t
COLR
tCOLS
COL
L
(3)
tOFS
CLK
R
t
SA
t
HA
(4)
A
DDRESSR
A
3
A2
A
0
A1
t
COLR
tCOLS
COLR
7144 drw 20
NOTES:
1. CE
2. For reading port, OE is a Don't care on the Collision Detection Logic. Please refer to Truth Table IV for specific cases.
3. Leading Port Output flag might output 3tCYC + tCOLS after Address match.
0
= VIL, CE1 = VIH.
2
4. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.
Collision Detection Timing(3,4)
tOFS (ns)
Cycle Time
NOTES:
1. Region 1
Region 1 (ns) (1)
Region 2 (ns) (2)
Both ports show collision after 2nd cycle for Addresses 0, 2, 4 etc.
2. Region 2
Leading port shows collision after 3rd cycle for addresses 0, 3, 6, etc.
while trailing port shows collision after 2nd cycle for addresses 0, 2, 4 etc.
3. All the production units are tested to midpoint of each region.
5ns
6ns
0 - 2.8
2.81 - 4.6
0 - 3.8
0 - 5.3
3.81 - 5.6
5.31 - 7.1
7.5ns
4. These ranges are based on characterization of a typical device.
7144 tbl 13
Truth Table IV — Collision Detection Flag
Left Port
Right Port
(1)
(1)
(2)
(1)
(1)
(2)
CLK
L
R/W
L
CE
L
A
17L-A0L
CLK
R
R/W
R
CE
R
A
17R-A0R
Function
COL
H
L
COL
R
Both ports reading. Not a valid collision.
No flag output on either port.
↑
↑
↑
↑
H
L
MATCH
MATCH
MATCH
MATCH
↑
↑
↑
↑
H
L
MATCH
MATCH
MATCH
MATCH
H
Left port reading, Right port writing.
Valid collision, flag output on Left port.
H
L
L
L
L
L
L
L
H
L
L
L
L
H
Right port reading, Left port writing.
Valid collision, flag output on Right port.
H
L
Both ports writing. Valid collision. Flag
output on both ports.
L
L
7144 tbl 14
NOTES:
1. CE0 = VIL and CE1 = VIH. R/W and CE are synchronous with respect to the clock and need valid set-up and hold times.
2. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.
6.42
21
IDT70P3519/99
High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform - Entering Sleep Mode(1,2)
R/W
(3)
Timing Waveform - Exiting Sleep Mode(1,2)
An
An+1
(5)
R/W
OE
(5)
Dn
Dn+1
DATAOUT
(4)
NOTES:
1. CE1 = VIH.
2. All timing is same for Left and Right ports.
3. CE0 has to be deactivated (CE0 = VIH) three cycles prior to asserting ZZ (ZZx = VIH) and held for two cycles after asserting ZZ (ZZx = VIH).
4. CE0 has to be deactivated (CE0 = VIH) one cycle prior to de-asserting ZZ (ZZx = VIL) and held for three cycles after de-asserting ZZ (ZZx = VIL).
5. The device must be in Read Mode (R/W High) when exiting sleep mode. Outputs are active but data is not valid until the following cycle.
6.42
22
FEBRUARY 15, 2008
IDT70P3519/99
High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
properalertflag.Intheeventthatauserinitiatesaburstaccessonboth
portswiththesamestartingaddressonbothportsandoneorbothports
writing during each access (i.e., imposes a long string of collisions on
contiguousclockcycles),thealertflagwillbeassertedandclearedevery
othercycle. Please refertothe CollisionDetectiontimingwaveformon
Page 21.
FunctionalDescription
The IDT70P3519/99 provides a true synchronous Dual-Port Static
RAM interface.Registeredinputsprovideminimalset-upandholdtimes
onaddress,data,andallcriticalcontrolinputs.Allinternalregistersare
clocked on the rising edge of the clock signal, however, the self-timed
internalwritepulsewidthisindependentofthecycletime.
Collision detection on the IDT70P3519/99 represents an advance in
functionalityoverothersyncmulti-ports,whichhavenosuchcapability.
TheIDT70P3519/99sustainsthekeyfeaturesofbandwidthandflexibility.
Thecollisiondetectionfunctionisveryusefulinthecaseofburstingdata,
orastringofaccessesmadetosequentialaddresses,inthatitindicates
aproblemwithintheburst,givingtheusertheoptionofeitherrepeating
theburstorcontinuingtowatchthealertflagtoseewhetherthenumber
ofcollisionsincreasesaboveanacceptablethresholdvalue.Offeringthis
function on chip also allows users to reduce their need for arbitration
circuits,typicallydoneinCPLD’sorFPGA’s.Thisreducesboardspace
anddesigncomplexity,andgivestheusermoreflexibilityindeveloping
asolution.
An asynchronous output enable is provided to ease asyn-
chronousbusinterfacing.Counterenableinputsarealsoprovidedtostall
the operation of the address counters for fast interleaved
memoryapplications.
AHIGHonCE0oraLOWonCE1foroneclockcyclewillpowerdown
the internal circuitry to reduce static power consumption. Multiple chip
enables allow easier banking of multiple IDT70P3519/99 for depth
expansionconfigurations. Twocycles arerequiredwithCE0 LOWand
CE1HIGHtore-activatetheoutputs.
Interrupts
Iftheuserchoosestheinterruptfunction,amemorylocation(mailbox
ormessagecenter)is assignedtoeachport. Theleftportinterruptflag
(INTL)isassertedwhentherightportwritestomemorylocation3FFFE
(1FFFE for IDT70P3599), where a write is defined as CER = R/WR =
VIL pertheTruthTable.Theleftportclearstheinterruptthroughaccess
of address location 3FFFE (1FFFE for IDT70P3599) when CEL = VIL
andR/WL=VIH.Likewise,therightportinterruptflag(INTR)isasserted
whentheleftportwritestomemorylocation3FFFF(1FFFforIDT70P3599)
andtocleartheinterruptflag(INTR),therightportmustreadthememory
location 3FFFF (1FFFF for IDT70P3599). The message (36 bits) at
3FFFE or 3FFFF (1FFFF or 1FFFE for IDT70P3599) is user-defined
sinceitisanaddressableSRAMlocation.Iftheinterruptfunctionisnotused,
addresslocations3FFFEand3FFFF(1FFFFor1FFFEforIDT70P3599)
arenotusedasmailboxes,butaspartoftherandomaccessmemory.Refer
toTruthTable III forthe interruptoperation.
SleepMode
TheIDT70P3519/99isequippedwithanoptionalsleeporlowpower
modeonbothports.Thesleepmodepinonbothportsisasynchronous
andactivehigh.Duringnormaloperation,theZZpinispulledlow.When
ZZispulledhigh,theportwillentersleepmodewhereitwillmeetlowest
possible power conditions. The sleep mode timing diagram shows the
modes ofoperation:NormalOperation,NoRead/WriteAllowedandSleep
Mode.
Fornormaloperationallinputsmustmeetsetupandholdtimesprior
tosleepand afterrecoveringfromsleep.Clocksmustalsomeetcyclehigh
and low times during these periods. Three cycles prior to asserting ZZ
(ZZx=VIH)andthreecyclesafterde-assertingZZ(ZZx=VIL),thedevice
mustbedisabledviathechipenablepins.Ifawriteorreadoperationoccurs
duringtheseperiods,thememoryarraymaybecorrupted.Validityofdata
outfromtheRAMcannotbeguaranteedimmediatelyafterZZisasserted
(priortobeinginsleep).Whenexitingsleepmode,thedevicemustbein
Read mode (R/Wx = VIH)when chip enable is asserted, and the chip
enablemustbevalidforonefullcyclebeforeareadwillresultintheoutput
ofvaliddata.
DuringsleepmodetheRAMautomaticallydeselectsitself.TheRAM
disconnectsitsinternalclockbuffer.Theexternalclockmaycontinuetorun
withoutimpactingtheRAMssleepcurrent(IZZ).Alloutputswillremainin
high-Zstatewhileinsleepmode.Allinputsareallowedtotoggle.TheRAM
will not be selected and will not perform any reads or writes.
CollisionDetetion
Collisionisdefinedasaccessingthesamememoryaddressfromboth
portsresultinginthepotentialforeitherreadingorwritingincorrectdata
toaspecificaddress. Forthespecificcases:(a)Bothportsreading-no
dataiscorrupted,lost,orincorrectlyoutput,sonocollisionflagisoutputon
eitherport.(b)Oneportwriting,theotherportreading-theendresultof
thewritewillstillbevalid. However,thereadingportmightcapturedata
thatisinastateoftransitionandhencethereadingport’scollisionflagis
output.(c)Bothportswriting-thereisariskthatthetwoportswillinterfere
witheachother,andthedatastoredinmemorywillnotbeavalidwritefrom
either port (it may essentially be a random combination of the two).
Therefore,thecollisionflagisoutputon bothports. PleaserefertoTruth
Table IV for all of the above cases.
Thealertflag (COLx)isassertedonthe2ndor3rdrisingclockedge
oftheaffectedportfollowingthecollision,andremainslowforonecycle.
PleaserefertoCollisionDetectionTimingtableonPage21.Duringthat
nextcycle,theinternalarbitrationisengagedinresettingthealertflag(this
avoidsaspecificrequirementonthepartoftheusertoresetthealertflag).
Iftwocollisionsoccuronsubsequentclockcycles,thesecondcollisionmay
notgeneratetheappropriatealertflag.Athirdcollisionwillgeneratethe
6.42
23
IDT70P3519/99
High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Depth and Width Expansion
The IDT70P3519/99 features dual chip enables (refer to Truth
Table I) in order to facilitate rapid and simple depth expansion with no
requirements for external logic. Figure 4 illustrates how to control the
various chip enables in order to expand two devices in depth.
The IDT70P3519/99 can also be used in applications requiring
expandedwidth,asindicatedinFigure4.Throughcombiningthecontrol
signals, the devices can be grouped as necessary to accommodate
applicationsneeding72-bitsorwider.
A
18/A17
IDT70P3519/99
IDT70P3519/99
CE
0
1
CE
CE
0
1
CE
V
DD
V
DD
Control Inputs
Control Inputs
IDT70P3519/99
IDT70P3519/99
CE
1
CE
1
0
CE0
CE
BE,
R/W,
Control Inputs
Control Inputs
OE,
7144 drw 23
CLK,
ADS,
REPEAT,
CNTEN
Figure 4. Depth and Width Expansion with IDT70P3519/99
,
NOTE:
1. A18 is for IDT70P3519, A17 is for IDT70P3599.
6.42
24
FEBRUARY 15, 2008
IDT70P3519/99
High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
JTAGTimingSpecifications
tJCYC
JR
t
t
JF
tJCL
tJCH
TCK
Device Inputs(1)
TDI/TMS
/
tJDC
tJS
tJH
D
evice Outputs(2)
/
TDO
tJRSR
tJCD
TRST
,
7144 drw 24
tJRST
Figure 5. Standard JTAG Timing
NOTES:
1. Device inputs = All device inputs except TDI, TMS, and TRST.
2. Device outputs = All device outputs except TDO.
JTAG AC Electrical
Characteristics(1,2,3,4)
70P3519/99
Symbol
Parameter
JTAG Clock Input Period
JTAG Clock HIGH
JTAG Clock Low
JTAG Clock Rise Time
JTAG Clock Fall Time
JTAG Reset
Min.
100
40
Max.
Units
ns
____
t
JCYC
JCH
JCL
JR
JF
JRST
JRSR
JCD
JDC
JS
JH
____
____
t
ns
t
40
ns
t
3(1)
ns
____
t
3(1)
ns
____
____
t
50
ns
____
t
JTAG Reset Recovery
JTAG Data Output
JTAG Data Output Hold
JTAG Setup
50
ns
____
t
25
ns
____
t
0
ns
____
____
t
15
15
ns
t
JTAG Hold
ns
7144 tbl 15
NOTES:
1. Guaranteed by design.
2. 30pF loading on external output signals.
3. Refer to AC Electrical Test Conditions stated earlier in this document.
4. JTAG operations occur at one speed (10MHz). The base device may run at
any speed specified in this datasheet.
6.42
25
IDT70P3519/99
High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Identification Register Definitions
Instruction Field
Value
Description
Revision Number (31:28)
0x0
Reserved for version number
0x380(1)
0x33
1
IDT Device ID (27:12)
Defines IDT part number
IDT JEDEC ID (11:1)
Allows unique identification of device vendor as IDT
Indicates the presence of an ID register
ID Register Indicator Bit (Bit 0)
7144 tbl 16
NOTE:
1. Device ID for IDT70P3599 is 0x383.
ScanRegisterSizes
Register Name
Bit Size
Instruction (IR)
4
1
Bypass (BYR)
Identification (IDR)
32
Boundary Scan (BSR)
Note (3)
7144 tbl 17
SystemInterfaceParameters
Instruction
Code
Description
EXTEST
0000
Forces contents of the boundary scan cells onto the device outputs(1).
Places the boundary scan register (BSR) between TDI and TDO.
BYPASS
IDCODE
1111
Places the bypass register (BYR) between TDI and TDO.
0010
Loads the ID register (IDR) with the vendor ID code and places the
register between TDI and TDO.
0100
Places the bypass register (BYR) between TDI and TDO. Forces all
device output drivers to a High-Z state except COLx & INTx outputs.
HIGHZ
Uses BYR. Forces contents of the boundary scan cells onto the device
outputs. Places the bypass register (BYR) between TDI and TDO.
CLAMP
0011
0001
SAMPLE/PRELOAD
Places the boundary scan register (BSR) between TDI and TDO.
SAMPLE allows data from device inputs(2) to be captured in the
boundary scan cells and shifted serially through TDO. PRELOAD allows
data to be input serially into the boundary scan cells via the TDI.
RESERVED
PRIVATE
0101, 0111, 1000, 1001,
1010, 1011, 1100
Several combinations are reserved. Do not use codes other than those
identified above.
0110,1110,1101
For internal use only.
7144 tbl 18
NOTES:
1. Device outputs = All device outputs except TDO.
2. Device inputs = All device inputs except TDI, TMS, and TRST.
3. The Boundary Scan Descriptive Language (BSDL) file for this device is available on the IDT website (www.idt.com), or by contacting your local
IDT sales representative.
6.42
26
FEBRUARY 15, 2008
IDT70P3519/99
High-Speed 1.8V 256/128K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
OrderingInformation
XXXXX
A
999
A
A
A
Device
Type
Power Speed
Package
Process/
Temperature
Range
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Blank
I
Green
G
BC
BF
256-pin BGA (BC-256)
208-pin fpBGA (BF-208)
Commercial Only
Commercial & Industrial
200
166
Speed in Megahertz
Standard Power
S
70P3519
70P3599
9Mbit (256K x 36) 2.5V Synchronous Dual-Port RAM
4Mbit (128K x 36) 2.5V Synchronous Dual-Port RAM
7144 drw 25
IDT Clock Solution for IDT70P3519/99 Dual-Port
Dual-Port I/O Specifications
Clock Specifications
Input Duty
Cycle
IDT
PLL
Clock Device
IDT
Non-PLL
Clock Device
IDT Dual-Port
Part Number
Input
Capacitance
Maximum
Frequency Tolerance
Jitter
Voltage
I/O
Requirement
5T2010
5T9010
5T905, 5T9050
5T907, 5T9070
70P3519/99
2.5
LVTTL
3.5-6pF
40%
200
75ps
7144 tbl 19
DatasheetDocumentHistory:
07/07/08:
01/19/09:
06/08/09:
InitialDatasheet
Page 28 Removed "IDT" from orderable part number
Removedpreliminarystatus
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800-345-7015 or 408-284-8200
fax: 408-284-2775
for Tech Support:
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DualPortHelp@idt.com
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.42
27
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