IDT70825L35PFG [IDT]
Standard SRAM, 8KX16, 35ns, CMOS, PQFP80, TQFP-80;
| 型号： | IDT70825L35PFG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Standard SRAM, 8KX16, 35ns, CMOS, PQFP80, TQFP-80 存储 |
| 文件： | 总21页 (文件大小：319K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT70825S/L
HIGH-SPEED 8K x 16
SEQUENTIAL ACCESS
RANDOM ACCESS MEMORY (SARAM™)
Integrated Device Technology, Inc.
FEATURES:
DESCRIPTION:
• 8K x 16 Sequential Access Random Access Memory
The IDT70825 is a high-speed 8K x 16-bit Sequential
Access Random Access Memory (SARAM). The SARAM
(SARAM™)
- Sequential Access from one port and standard Random offers a single-chip solution to buffer data sequentially on one
Access from the other port
- Separate upper-byte and lower-byte control of the
Random Access Port
port, and be accessed randomly (asynchronously) through
the other port. The device has a Dual-Port RAM based
architecture with a standard SRAM interface for the random
(asynchronous) access port, and a clocked interface with
counter sequencing for the sequential (synchronous) access
port.
• High-speed operation
- 20ns tAA for random access port
- 20ns tCD for sequential port
- 25ns clock cycle time
Fabricated using CMOS high-performance technology,
this memory device typically operates on less than 900mW of
power at maximum high-speed clock-to-data and Random
Access. An automatic power down feature, controlled by CE,
permits the on-chip circuitry of each port to enter a very low
standby power mode.
• Architecture based on Dual-Port RAM cells
• Electrostatic discharge > 2001V, Class II
• Compatible with Intel BMIC and 82430 PCI Set
• Width and Depth Expandable
• Sequential side
- Address based flags for buffer control
- Pointer logic supports two internal buffers
• Battery backup operation—2V data retention
• TTL-compatible, single 5V (±10%) power supply
• Available in 80-pin TQFP and 84-pin PGA
• Military product compliant to MIL-STD-883.
• Industrialtemperaturerange(–40°Cto+85°C)isavailable,
tested to military electrical specifications.
The IDT70825 is packaged in a 80-pin Thin Plastic Quad
Flatpack (TQFP) or 84-pin Ceramic Pin Grid Array (PGA).
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B, making it ideally
suited to military temperature applications demanding the
highest level of performance and reliability.
FUNCTIONAL BLOCK DIAGRAM
13
A
0-12
SCLK
Random
Access
Port
Sequential
Access
Port
Controls
1
R
LSB
2
Controls
MSB
8K X 16
Memory
Array
SR
16
16
16
Data
R
Reg.
13
I/O0-15
Data
L
SI/O0-15
13
Addr
L
Addr
R
13
RST
13
Pointer/
Counter
13
13
Start Address for Buffer #1
End Address for Buffer #1
Start Address for Buffer #2
End Address for Buffer #2
Flow Control Buffer
13
1
2
COMPARATOR
Flag Status
3016 drw 01
The IDT logo is a registered trademark and SARAM is a trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
OCTOBER 1996
©1996 Integrated Device Technology, Inc.
DSC-3016/6
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
6.31
1
IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS(1,2)
INDEX
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
60
SI/O
SI/O
1
0
A
A
A
A
A
A
A
A
A
A
V
V
A
A
CMD
CE
LB
UB
R/W
OE
11
10
9
1
59
58
57
56
55
54
2
GND
N/C
SCE
SR/W
RST
3
8
4
7
5
6
6
5
7
SLD
53
52
51
50
49
48
47
4
8
SSTRT
2
3
9
IDT70825
PN80-1
SSTRT
1
2
10
11
12
13
14
15
16
17
18
19
20
GND
GND
CNTEN
SOE
SCLK
GND
CC
CC
1
TQFP
TOP
(3)
VIEW
0
46
45
44
EOB
2
EOB
1
43
42
41
V
CC
I/O
0
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
3016 drw 02
63
66
61
60
58
55
54
48
46
45
42
51
11
10
09
08
07
06
05
04
03
02
01
CNTEN
SSTRT2
SR/W
V
CC
NC
I/O
1
EOB
1
GND
GND
GND NC
64
62
59
56
49
47
44
43
40
50
I/O
2
NC
EOB
2
SOE RST
SCE SI/O
0
SI/O1
SI/O
3
I/O
0
SLD
67
65
57
53
41
39
52
SSTRT
1
GND
SCLK GND
VCC
I/O
3
SI/O
2
69
68
38
37
I/O
4
VCC
SI/O
4
SI/O
5
72
75
76
71
73
33
35
34
I/O
7
I/O
6
GND
SI/O
8
GND
SI/O
7
IDT70825
G84-3
70
74
32
31
36
I/O
9
I/O
5
I/O
8
SI/O9
SI/O10
29
SI/O
6
84-PIN PGA
TOP VIEW
(3)
77
78
28
30
I/O10 I/O11
V
CC
V
CC
SI/O12
SI/O11
79
80
26
27
I/O12
I/O13
SI/O14
23
SI/O13
81
83
7
11
12
25
CMD
I/O14 NC
V
CC
A2
NC SI/O15
82
1
2
4
5
8
10
14
17
20
22
24
OE
LB
A
4
A
7
A
10
A
12
GND
A
0
1
V
CC
GND
I/O15
84
3
6
9
15
13
16
18
19
21
NC R/W
A8
UB
CE
A
A
5
A
3
A
6
A
9
A11
A
B
C
D
E
F
G
H
J
K
L
3016 drw 03
INDEX
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. This text does not indicate orientation of the actual part-marking.
6.31
2
IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTIONS: RANDOM ACCESS PORT
SYMBOL NAME
I/O(1)
DESCRIPTION
A0-A12
Address Lines
I
I
I
Address inputs to access the 8192-word (16 bit) memory array.
Random access data inputs/outputs for 16-bit wide data.
I/O0-I/O15 Inputs/Outputs
CE
Chip Enable
When CE is LOW, the random access port is enabled. When CE is HIGH, the random access
port is disabled into power-down mode and the I/O outputs are in the high-impedance state. All
data is retained during CE = VIH, unless it is altered by the sequential port. CE and CMD may not
be LOW at the same time.
CMD
R/W
Control Register
Enable
I
I
When CMD is LOW, Address lines A0-A2, R/W, and inputs/outputs I/O0-I/O11, are used to
access the control register, the flag register, and the start and end of buffer registers. CMD and
CE may not be LOW at the same time.
Read/Write Enable
Output Enable
If CEis LOW and CMD is HIGH, data is written into the array when R/W is LOW and read out of the
array when R/W is HIGH. If CE is HIGH and CMD is LOW, R/W is used to access the buffer com-
mand registers. CE and CMD may not be LOW at the same time.
OE
I
I
When OE is LOW and R/W is HIGH, I/O0-I/O15 outputs are enabled. When OE is HIGH, the I/O
outputs are in the high-impedance state.
LB,UB
Lower Byte, Upper
Byte Enables
When LB is LOW, I/O0-I/O7 are accessible for read and write operations. When LB is HIGH, I/O0-
I/O7 are tri-stated and blocked during read and write operations. UB controls access for I/O8-
I/O15 in the same manner and is asynchronous from LB.
VCC
Power Supply
Ground
Seven +5V power supply pins. All Vcc pins must be connected to the same +5V VCC supply.
GND
Ten Ground pins. All Ground pins must be connected to the same Ground supply.
3016 tbl 01
PIN DESCRIPTIONS: SEQUENTIAL ACCESS PORT
SYMBOL
NAME
I/O(1)
I/O Sequential data inputs/outputs for 16-bit wide data.
DESCRIPTION
SI/O0-15 Inputs
SCLK
SCE
Clock
I
I
SI/O0-SI/O15, SCE, SR/W, and SLD are registered on the LOW-to-HIGH transition of SCLK.
Also, the sequential access port address pointer increments by 1 on each LOW-to-HIGH
transition of SCLK when CNTEN is LOW.
Chip Enable
When SCE is LOW, the sequential access port is enabled on the LOW-to-HIGH transition of
SCLK. When SCE is HIGH, the sequential access port is disabled into powered-down mode on
the LOW-to-HIGH transition of SCLK, and the SI/O outputs are in the high-impedance state. All
data is retained, unless altered by the random access port.
CNTEN
SR/W
Counter Enable
I
I
When CNTEN is LOW, the address pointer increments on the LOW-to-HIGH transition of SCLK.
This function is independant of SCE.
Read/Write Enable
When SR/W and SCE are LOW, a write cycle is initiated on the LOW-to-HIGH transition of
SCLK. When SR/W is HIGH, and SCE and SOE are LOW, a read cycle is initiated on the
LOW-to-HIGH transition of SCLK. Termination of a Write cycle is done on the Low-to-High
transistion of SCLK if SR/W or SCE is High.
SLD
Address Pointer
Load Control
I
When SLD is sampled LOW, there is an internal delay of one cycle before the address pointer
changes. When SLD is LOW, data on the inputs SI/O0-SI/O11 is loaded into a data-in register
on the LOW-to-HIGH transition of SCLK. On the cycle following SLD, the address pointer
changes to the address location contained in the data-in register. SSTRT1 and SSTRT2 may
not be LOW while SLD is LOW or during the cycle following SLD.
SSTRT1, Load Start of
SSTRT2 Address Register
I
When SSTRT1 or SSTRT2 is LOW, the start of address register #1 or #2 is loaded into the
address pointer on the LOW-to-HIGH transition of SCLK. The start addresses are stored in
internal registers. SSTRT1 and SSTRT2 may not be LOW while SLD is LOW or during the cycle
following SLD.
EOB1,
EOB2
End of Buffer Flag
O
EOB1 or EOB2 is output LOW when the address pointer is incremented to match the address
stored in the end of buffer registers. The flags can be cleared by either asserting RST LOW or
by writing zero into bit 0 and/or bit 1 of the control register at address 101. EOB1 and EOB2 are
dependent on separate internal registers, and therefore separate match addresses.
SOE
Output Enable
Reset
I
I
SOE controls the data outputs and is independent of SCLK. When SOE is LOW, output buffers
and the sequentially addressed data is output. When SOE is HIGH, the SI/O output bus is in
the high-impedance state. SOE is asynchronous to SCLK.
RST
When RST is LOW, all internal registers are set to their default state, the address pointer is set
to zero and the EOB1 and EOB2 flags are set HIGH. RST is asynchronous to SCLK.
NOTE:
3016 tbl 02
1. "I/O" is bidirectional Input and Output. "I" is Input and "O" is Output.
6.31
3
IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Symbol
Rating
Commercial
Military
Unit
VTERM(2) Terminal Voltage –0.5 to +7.0 –0.5 to +7.0
V
Ambient
Grade
Military
Commercial
Temperature
–55°C to +125°C
0°C to +70°C
GND
0V
VCC
with Respect
to GND
5.0V ± 10%
TA
Operating
Temperature
0 to +70
–55 to +125
°C
°C
0V
5.0V ± 10%
3016 tbl 04
TBIAS
TSTG
IOUT
Temperature
Under Bias
–55 to +125 –65 to +135
–55 to +125 –65 to +150
Storage
Temperature
°C
RECOMMENDED DC OPERATING
CONDITIONS
DC Output
Current
50
50
mA
Symbol
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
Min.
Typ. Max. Unit
VCC
4.5
5.0
0
5.5
V
V
V
V
NOTES:
3016 tbl 03
GND
VIH
0
0
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
onlyandfunctionaloperationofthedeviceattheseoranyotherconditions
abovethoseindicatedintheoperationalsectionsofthisspecificationisnot
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. VTERM must not exceed Vcc + 0.5V for more than 25% of the cycle time
or 10ns maximum, and is limited to < 20mA for the period of VTERM > Vcc
+ 0.5V.
2.2
—
—
6.0(2)
0.8
VIL
–0.5(1)
NOTES:
3016 tbl 05
1. VIL > –1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 0.5V.
CAPACITANCE(1)
(TA = +25°C, F = 1.0MHz)TQFP ONLY
Symbol
CIN
Parameter
Conditions(2) Max. Unit
Input Capacitance
VIN = 3dV
9
pF
pF
COUT
Output
VOUT = 3dV
10
Capacitance
NOTES:
3016 tbl 06
1. This parameter is determined by device characterization, but is not
production tested.
2. 3dV references the interpolated capacitance when the input and output
signals switch from 0V to 3V or from 3V to 0V.
DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE
AND SUPPLY VOLTAGE RANGE (VCC = 5.0V ± 10%)
IDT70825S
IDT70825L
Symbol
Parameter
Input Leakage Current(1)
Output Leakage Current
Test Conditions
Min.
Max.
Min.
Max.
Unit
µA
|ILI|
VCC = Max. VIN = GND to VCC
—
5.0
—
—
1.0
|ILO|
VCC = Max. CE and SCE = VIH
VOUT = GND to VCC
—
5.0
1.0
µA
VOL
Output Low Voltage
Output High Voltage
IOL = 4mA, VCC = Min.
IOH = –4mA, VCC = Min.
—
0.4
—
—
0.4
—
V
VOH
2.4
2.4
V
3016 tbl 07
NOTE:
1. At Vcc ≤ 2.0V input leakages are undefined.
6.31
4
IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE
AND SUPPLY VOLTAGE RANGE(1) (VCC = 5.0V ± 10%)
70825X20
Com'l. Only Com'l. Only
Version Typ.(2) Max. Typ.(2)Max. Typ.(2) Max. Typ.(2) Max. Unit
70825X25
70825X35
70825X45
Test
Condition
Symbol
Parameter
ICC
Dynamic Operating
Current
CE = VIL, Outputs
Open, SCE = VIL(5)
MIL.
S
L
—
—
—
—
—
—
—
—
160
160
400 155
340 155
400 mA
340
(Both Ports Active)
f = fMAX(3)
COM’L. S 180 380
170
170
360
310
160
160
340 155
290 155
340
290
L
180 330
ISB1
ISB2
ISB3
ISB4
Standby Current
(Both Ports - TTL Level CMD = VIH
SCE and CE > VIH(7) MIL.
S
L
—
—
—
—
—
—
—
—
20
20
85
65
16
16
85 mA
65
Inputs)
f = fMAX(3)
COM’L. S
L
25
25
70
50
25
25
70
50
20
20
70
50
16
16
70
50
Standby Current
(One Port - TTL Level Active Port Outputs
CE or SCE = VIH
MIL.
S
L
—
—
——
—
—
—
—
95
95
290
250
90
90
290 mA
250
Input)
Open, f = fMAX(3)
COM’L. S 115 260
105
105
250
220
95
95
240
210
90
90
240
210
L
115 230
Full Standby Current
(Both Ports - CMOS
Both Ports CE and
SCE ≥ VCC - 0.2V(6,7)
MIL.
S
L
—
—
—
—
—
—
—
—
1.0
0.2
30
10
1.0
0.2
30 mA
10
Level Inputs)
VIN ≥ VCC - 0.2V or COM’L. S
VIN ≤ 0.2V, f = 0(4)
1.0
0.2
15
5
1.0
0.2
15
5
1.0
0.2
15
5
1.0
0.2
15
5
L
Full Standby Current
(One Port - CMOS
Level Inputs)
One Port CE or
SCE ≥ VCC - 0.2V(6)
Outputs Open
MIL.
S
L
—
—
—
—
—
—
—
—
90
90
260
215
85
85
260 mA
215
(3)
(Active port), f = fMAX COM’L. S 110 240
100
100
230
190
90
90
220
180
85
85
220
VIN ≥ VCC - 0.2V or
VIN ≤ 0.2V
L
110 200
180
NOTES:
3016 tbl 08
1. "X" in part number indicates power rating (S or L).
2. VCC = 5V, Ta = +25°C; guaranteed by device characterization but not production tested.
3. At f = fMAX, address, control lines (except Output Enable), and SCLK are cycling at the maximum frequency read cycle of 1/tRC.
4. f = 0 means no address or control lines change.
5. SCE may transition, but is Low (SCE=VIL) when clocked in by SCLK.
6. SCE may be ≤ 0.2V, after it is clocked in, since SCLK=VIH must be clocked in prior to powerdown.
7. If one port is enabled (either CE or SCE = Low) then the other port is disabled (SCE or CE = High, respectively). CMOS High > Vcc - 0.2V and
Low < 0.2V, and TTL High = VIH and Low = VIL.
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(L VERSION ONLY) (VLC < 0.2V, VHC > VCC - 0.2V)
Symbol
Parameter
VCC for Data Retention
Data Retention Current
Test Condition
VCC = 2V
CE = VHC
Min.
2.0
—
Typ.(1)
—
Max.
—
Unit
V
VDR
ICCDR
MIL.
100
100
—
4000
1500
—
µA
VIN = VHC or = VLC COM’L.
SCE = VHC(4) when SCLK=
CMD = VHC
—
tCDR(3)
tR(3)
Chip Deselect to Data Retention Time
Operation Recovery Time
0
ns
tRC(2)
—
—
ns
3016 tbl 09
NOTES :
1. TA = +25°C, VCC = 2V; guaranteed by device characterization but not production tested.
2. tRC = Read Cycle Time
3. This parameter is guaranteed by device characterization, but is not production tested.
4. To initiate data retention, SCE = VIH must be clocked in.
6.31
5
IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DATA RETENTION AND POWER DOWN/UP WAVEFORM (RANDOM AND SEQUENTIAL PORT) (1,2)
DATA RETENTION MODE
≥
VDR 2V
4.5V
4.5V
VCC
t
CDR
tR
V
DR
V
IH
CE
V
IH
SCLK
SCE
tPD
tPU
ICC
3016 drw 04
ISB
ISB
NOTES :
1. SCE is synchronized to the sequential clock input.
2. CMD > VCC - 0.2V.
5V
5V
893Ω
893Ω
DATAOUT
DATAOUT
347Ω
30pF
347Ω
5pF
3016 drw 05
3016 drw 06
Figure 2. Output Test Load (for tCLZ, tBLZ, tOLZ, tCHZ,
tBHZ, tOHZ, tWHZ, tCKHZ, and tCKLZ)
Including scope and jig.
Figure 1. AC Output Test Load
8
7
6
tAA/tCD/tEB
(Typical, ns)
5
4
3
2
1
10pF is the I/O
capacitance of
this device, and
30pF is the AC
Test Load
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
3ns Max.
capacitance.
Input Rise/Fall Times
-1
-2
Input Timing Reference Levels
Output Reference Levels
AC Test Load
1.5V
20 40 60 80 100 120 140 160 180 200
1.5V
3016 drw 07
CAPACITANCE (pF)
Figures 1, 2, and 3
-3
3016 tbl 10
Figure 3. Lumped Capacitance Load Typical Derating Curve
6.31
6
IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE I – RANDOM ACCESS READ AND WRITE (1,2)
Inputs/Outputs
MODE
CE CMD R/W OE LB UB
I/O0-I/O7
DATAOUT
DATAOUT
High-Z
I/O8-I/O-
DATAOUT
High-Z
L
H
H
H
H
H
H
H
H
H
L
H
H
H
L
L
L
L
L
L
H
L
Read both Bytes.
L
Read lower Byte only.
Read upper Byte only.
Write to both Bytes.
L
L
H
L
DATAOUT
DATAIN
High-Z
L
H(3)
H(3)
H(3)
X
L
DATAIN
DATAIN
High-Z
L
L
L
H
L
Write to lower Byte only.
Write to upper Byte only.
L
L
H
X
X
H
DATAIN
High-Z
H
X
H
X
L
X
X
H
High-Z
Both Bytes deselected and powered down.
L
H
High-Z
High-Z
Outputs disabled but not powered down.
L
X
High-Z
High-Z
Both Bytes deselected but not powered down.
Write I/O0-I/O12 to the Buffer Command Register.
Read contents of the Buffer Command Register via I/O0-I/O12.
H
H(3) L(4) L(4)
DATAIN
DATAIN
DATAOUT
H
L
H
L
L(4) L(4) DATAOUT
3016 tbl 11
NOTES:
1. H = VIH, L = VIL, X = Don't Care, and High-Z = High-impedance.
2. RST, SCE, CNTEN, SR/W, SLD, SSTRT1, SSTRT2, SCLK, SI/O0-SI/O15, EOB1, EOB2, and SOE are unrelated to the random access port control and
operation.
3. If OE = VIL during write, tWHZ must be added to the tWP or tCW write pulse width to allow the bus to float prior to being driven.
4. Byte operations to control register using UB and LB separately are also allowed.
TRUTH TABLE II – SEQUENTIAL READ (1,2,3,6,8)
Inputs/Outputs
MODE
SCLK SCE CNTEN SR/W EOB1 EOB2 SOE
SI/O
L
L
L
L
L
L
H
L
H
H
H
H
H
LOW LAST
LAST LAST
LAST LOW
LAST LAST
LOW LOW
L
L
L
L
H
[EOB1]
Counter Advanced Sequential Read with EOB1 reached.
[EOB1 - 1] Non-Counter Advanced Sequential Read, without EOB1 reached.
[EOB2] Counter Advanced Sequential Read with EOB2 reached.
[EOB2 - 1] Non-Counter Advanced Sequential Read without EOB2 reached.
H
L
HIGH-Z
Counter Advanced Sequential Non-Read with EOB1 and EOB2
reached.
3016 tbl 12
TRUTH TABLE III – SEQUENTIAL WRITE (1,2,3,4,5,6,7,8)
Inputs/Outputs
MODE
SCLK SCE CNTEN SR/W EOB1 EOB2 SOE SI/O
L
L
H
L
L
L
LAST LAST
LOW LOW
LAST LAST
NEXT NEXT
H
H
X
X
SI/OIN Non-Counter Advanced Sequential Write, without EOB1 or EOB2 reached
SI/OIN Counter Advanced Sequential Write with EOB1 and EOB2 reached.
High-Z No Write or Read due to Sequential port Deselect. No counter advance.
H
H
H
L
X
X
High-Z No Write or Read due to Sequential port Deselect. Conter does advance.
3016 tbl 13
NOTES:
1. H = VIH, L = VIL, X = Don't Care, and High-Z = High-impedance. LOW = VOL.
2. RST, SLD, SSTRT1, SSTRT2 are continuously HIGH during a sequential write access, other than pointer access operations.
3. CE, OE, R/W, CMD, LB, UB, and I/O0-I/O15 are unrelated to the sequential port control and operation except for CMD which must not be used concurrently
with the sequential port operation (due to the counter and register control). CMD should be HIGH (CMD = VIH) during sequential port access.
4. SOEmust be HIGH (SOE=VIH) prior to write conditions only if the previous cycle is a read cycle, since the data being written must be an input at the rising
edge of the clock during the cycle in which SR/W = VIL.
5. SI/OIN refers to SI/O0-SI/O15 inputs.
6. "LAST" refers to the previous value still being output, no change.
7. Termination of a write is done on the Low-to-High transition of SCLK if SR/W or SCE is High.
8. When CLKEN=Low, the address is incremented on the next rising edge before any operation takes place. See the diagrams called "Sequential Counter
Enable Cycle after Reset, Read (and write) Cycle".
6.31
7
IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE IV – SEQUENTIAL ADDRESS POINTER OPERATIONS (1,2,3,4,5)
Inputs/Outputs
SCLK SLD SSTRT1 SSTRT2 SOE
MODE
Start address for Buffer #1 loaded into Address Pointer.
Start address for Buffer #2 loaded into Address Pointer.
H
H
L
L
H
H
H
L
X
X
H
H(6) Data on SI/O0-SI/O12 loaded into Address Pointer.
NOTES:
3016 tbl 14
1. H = VIH, L = VIL, X = Don't Care, and High-Z = High-impedance.
2. RST is continuously HIGH. The conditions of SCE, CNTEN, and SR/W are unrelated to the sequential address pointer operations.
3. CE, OE, R/W, LB, UB, and I/O0-I/O15 are unrelated to the sequential port control and operation, except for CMD which must not be used concurrently with
the sequential port operation (due to the counter and register control). CMD should be HIGH (CMD = VIH) during sequential port access.
4. Address pointer can also change when it reaches an end of buffer address. See Flow Control Bits table.
5. When SLD is sampled LOW, there is an internal delay of one cycle before the address pointer changes. The state of CNTEN is ignored and the address
is not incremented during the two cycles.
6. SOE may be LOW with SCE deselect or in the write mode using SR/W.
ADDRESS POINTER LOAD CONTROL (SLD)
address location contained in the data-in register. SSTRT1,
SSTRT2 may not be low while SLD is LOW, or during the cycle
following SLD. The SSTRT1 and SSTRT2 require only one
clock cycle, since these addresses are pre-loaded in the
registers already.
In SLD mode, there is an internal delay of one cycle before
the address pointer changes in the cycle followingSLD. When
SLD is LOW, data on the inputs SI/O0-SI/O12 is loaded into a
data-in register on the LOW-to-HIGH transition of SCLK. On
the cycle following SLD, the address pointer changes to the
SLD MODE (1)
SLD
(1)
SCLK
B
A
C
ADDRIN
DATAOUT
SI/O0-11
SSTRT1,2
3016 drw 08
NOTE:
1. At SCLK edge (A), SI/O0-SI/O12 data is loaded into a data-in register. At edge (B), contents of the data-in register are loaded into the address pointer (i.e.
address pointer changes). At SCLK edge (A), SSTRT1 and SSTRT2 must be high to ensure for proper sequential address pointer loading. At SCLK edge
(B), SLD and SSTRT1,2 must be high to ensure for proper sequential address pointer loading. For SSTRT1 or SSTRT2, the data to be read will be ready
for edge (B), while data will not be ready at edge (B) when SLD is used, but will be ready at edge (C).
SEQUENTIAL LOAD OF ADDRESS INTO POINTER/COUNTER (1)
15
14
H
13
H
12 ------------------------------------------------------------------------------------------------------------ 0
Address Loaded into Pointer
H
LSB SI/O BITS
MSB
3016 drw 09
NOTE:
1. "H" = VIH for the SI/O intput state.
6.31
8
IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Reset (RST)
Setting RST LOW resets the control state of the SARAM.
RST functions asynchronously of SCLK, (i.e. not registered).
The default states after a reset operation are as follows:
Register
Address Pointer
Contents
0
EOB Flags
Cleared to High state
BUFFER CHAINING
Buffer Flow Mode
Start Address Buffer #1
End Address Buffer #1
Start Address Buffer #2
End Address Buffer #2
Registered State
0
(1)
4095 (4K)
4096 (4K+1)
8191 (8K)
SCE = VIH, SR/W = VIL
3016 tbl 15
BUFFER COMMAND MODE (CMD)
Buffer Command Mode (CMD) allows the random access reading and clearing the status of the EOB flags. Seven
port to control the state of the two buffers. Address pins A0-A2 different CMD cases are available depending on the condi-
and I/O pins I/O0-I/O12 are used to access the start of buffer tions of A0-A2 and R/W. Address bits A3-A12 and data I/O bits
and the end of buffer addresses and to set the flow control I/O13-I/O15 are not used during this operation.
mode of each buffer. The Buffer Command Mode also allows
RANDOM ACCESS PORT CMD MODE(1)
Case #
A2-A0
000
R/W
0 (1)
0 (1)
0 (1)
0 (1)
0 (1)
0
DESCRIPTIONS
Write (read) the start address of Buffer #1 through I/O0-I/O12.
Write (read) the end address of Buffer #1 through I/O0-I/O12.
Write (read) the start address of Buffer #2 through I/O0-I/O12.
Write (read) the end address of Buffer #2 through I/O0-I/O12.
Write (read) flow control register
1
2
3
4
5
6
7
8
001
010
011
100
101
Write only – clear EOB1 and/or EOB2 flag
Read only – flag status register
101
1
110/111
(X)
(Reserved)
3016 tbl 16
NOTE:
1. R/W input "0(1)" indicates a write(0) or read(1) occurring with the same address input.
CASES 1 THROUGH 4: START AND END OF BUFFER REGISTER DESCRIPTION(1,2)
15
H
14
H
13
H
12 ------------------------------------------------------------------------------------------------------------ 0
Address Loaded into Buffer
MSB
LSB I/O BITS
NOTES:
3016 drw 10
1. "H" = VOH for I/O in the output state and "Don't Cares" for I/O in the input state.
2. A write into the buffer occurs when R/W= VIL and a read when R/W= VIH. EOB1/SOB1 and EOB2/SOB2 are chosen through address A0-A2 while CMD
= VIL and CE = VIH.
CASE 5: BUFFER FLOW MODES
of the other buffer. In STOP mode, the address pointer stops
incrementing after it reaches the end of the buffer. In LINEAR
mode, the address pointer ignores the end of buffer address
and increments past it, but sets the EOB flag. MASK mode is
the same as LINEAR mode except EOB flags are not set.
Within the SARAM, the user can designate one of four
buffer flow modes for each buffer. Each buffer flow mode
defines a unique set of actions for the sequential port address
pointerandEOBflags.InBUFFERCHAININGmode,afterthe
address pointer reaches the end of the buffer, it sets the
corresponding EOB flag and continues from the start address
6.31
9
IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FLOW CONTROL REGISTER DESCRIPTION(1,2)
0
15
MSB
H
H
H
H
H
H
H
H
H
H
4
3
2
1
0
H
LSB I/O BITS
Counter Release
(STOP Mode Only)
Buffer #1 flow control
NOTES:
Buffer #2 flow control
3016 drw 11
1. "H" = VOH for I/O in the output state and "Don't Cares"' for I/O in the input state.
2. Writing a 0 into bit 4 releases the address pointer after it is stopped due to the STOP mode and allows sequential write operations to resume. This occurs
asynchronously of SCLK, and therefore caution should be taken. The pointer will be at address EOB+2 on the next rising edge of SCLK that is enabled
by CNTEN. The pointer is also released by RST, SLD, SSTRT1 and SSTRT2 operations.
FLOW CONTROL BITS
Flow Control Bits
Bit 1 & Bit 0
Mode
(Bit 3 & Bit 2)
Functional Description
00
01
BUFFER
CHAINING
EOB1 (EOB2) is asserted (Active Low output) when the pointer matches the end address of Buffer
#1 (Buffer #2). The pointer value is changed to the start address of Buffer #2 (Buffer #1).(1,3)
STOP
EOB1 (EOB2) is asserted when the pointer matches the end address of Buffer #1 (Buffer #2).
The address pointer will stop incrementing when it reaches the next address (EOB address + 1), if
CNTEN is Low on the next clock's rising edge. Otherwise, the address pointer will stop incrementing on
EOB. Sequential write operations are inhibited after the address pointer is stopped. The pointer can be
released by bit 4 of the flow control register. (1,2,4)
10
11
LINEAR
MASK
EOB1 (EOB2) is asserted when the pointer matches the end address of Buffer #1 (Buffer #2).
The pointer keeps incrementing for further operations.(1)
EOB1 (EOB2) is not asserted when the pointer reaches the end address of Buffer #1 (Buffer #2),
although the flag status bits will be set. The pointer keeps incrementing for further operations.
3016 tbl 17
NOTES:
1. EOB1 and EOB2 may be asserted (set) at the same time, if both end addresses have been loaded with the same value.
2. CMD Flow Control bits are unchanged, the count does not continue advancement.
3. If EOB1 and EOB2 are equal, then the pointer will jump to the start of Buffer #1.
4. If counter has stopped at EOBx and was released by bit 4 of the flow control register, CNTEN must be LOW on the next rising edge of SCLK otherwise
the flow control will remain in the STOP mode.
CASES 6 AND 7: FLAG STATUS REGISTER BIT DESCRIPTION(1)
0
0
15
MSB
H
H
H
H
H
H
H
H
H
H
H
H
H
H
1
LSB I/O BITS
End of buffer flag for Buffer #1
End of buffer flag for Buffer #2
NOTE:
1. "H" = VOH for I/O in the output state and "Don't Cares" for I/O in the input state.
3016 drw 12
CASE 6: FLAG STATUS REGISTER WRITE CONDITIONS(1)
Flag Status Bit 0, (Bit 1)
Functional Description
0
Clears Buffer Flag EOB1, (EOB2).
No change to the Buffer Flag.(2)
1
NOTES:
3016 tbl 18
1. Either bit 0 or bit 1, or both bits, may be changed simultaneously. One may be cleared while the second is left alone or cleared.
2. Remains as it was prior to the CMD operation, either HIGH (1) or LOW (0).
CASE 7: FLAG STATUS REGISTER READ CONDITIONS
Flag Status Bit 0, (Bit 1) Functional Description
0
EOB1 (EOB2) flag has not been set, the
Pointer has not reached the End of the
Buffer.
1
EOB1 (EOB2) flag has been set, the
PointerhasreachedtheEndoftheBuffer.
3016 tbl 19
6.31
10
IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
CASES 8 AND 9: (RESERVED)
Illegal operations. All outputs will be HIGH on the I/O bus during a READ.
RANDOM ACCESS PORT: AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (2,3)
IDT70825X20
Com'l. Only
IDT70825X25
Com'l. Only
IDT70825X35 IDT70825X45
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tRC
tAA
Read Cycle Time
Address Access Time
20
—
—
—
—
3
—
20
20
20
10
—
—
—
—
10
10
9
25
—
—
—
—
3
—
25
25
25
10
—
—
—
—
12
12
11
—
25
35
—
—
—
—
3
—
35
35
35
15
—
—
—
—
15
15
15
—
35
45
—
—
—
—
3
—
45
45
45
20
—
—
—
—
15
15
15
—
45
ns
ns
tACE
tBE
Chip Enable Access Time
Byte Enable Access Time
Output Enable Access Time
Output Hold from Address Change
Chip Select Low-Z Time(1)
Byte Enable Low-Z Time(1)
Output Enable Low-Z Time(1)
Chip Select High-Z Time(1)
Byte Enable High-Z Time(1)
Output Enable High-Z Time(1)
Chip Select Power-Up Time
Chip Select Power-Down Time
ns
ns
tOE
ns
tOH
ns
tCLZ
tBLZ
tOLZ
tCHZ
tBHZ
tOHZ
tPU
3
3
3
3
ns
3
3
3
3
ns
2
2
2
2
ns
—
—
—
0
—
—
—
0
—
—
—
0
—
—
—
0
ns
ns
ns
—
20
ns
tPD
—
—
—
—
ns
3016 tbl 20
NOTES:
1. Transition measured at ±200mV from steady state. This parameter is guaranteed with the AC Test Load (Figure 2) by device characterization, but is not
production tested.
2. "X" in part number indicates power rating (S or L).
3. CMD access follows standard timing listed for both read and write accesses, ( CE = VIH when CMD = VIL ) or ( CMD = VIH when CE = VIL ).
RANDOM ACCESS PORT: AC ELECTRICAL CHARACTERISTICS
OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE (2,4)
IDT70825X20
Com'l. Only
IDT70825X25
Com'l. Only
IDT70825X35
IDT70825X45
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max. Unit
WRITE CYCLE
tWC
tCW
Write Cycle Time
20
15
15
0
—
—
—
—
—
—
—
10
—
—
—
25
20
20
0
—
—
—
—
—
—
—
12
—
—
—
35
25
25
0
—
—
—
—
—
—
—
15
—
—
—
45
30
30
0
—
—
—
—
—
—
—
15
—
—
—
ns
ns
Chip Select to End-of-Write
Address Valid to End-of-Write(3)
Address Set-up Time
Write Pulse Width(3)
Byte Enable Pulse Width(3)
tAW
ns
tAS
ns
tWP
13
15
0
20
20
0
25
25
0
30
30
0
ns
tBP
ns
tWR
Write Recovery Time
ns
tWHZ
tDW
Write Enable Output High-Z Time(1)
Data Set-up Time
—
13
0
—
15
0
—
20
0
—
25
0
ns
ns
tDH
Data Hold Time
ns
tOW
Output Active from End-of-Write
3
3
3
3
ns
3016 tbl 21
NOTES:
1. Transition measured at ±200mV from steady state. This parameter is guaranteed with the AC Test Load (Figure 2) by device characterization, but is not
production tested.
2. "X" in part number indicates power rating (S or L).
3. OE is continuously HIGH, OE = VIH. If during the R/W controlled write cycle the OE is LOW, tWP must be greater or equal to tWHZ + tDW to allow the I/O
drivers to turn off and on the data to be placed on the bus for the required tDW. If OEis HIGH during the R/W controlled write cycle, this requirement does
not apply and the minimum write pulse is the specified tWP. For the CE controlled write cycle, OE may be LOW with no degradation to tCW timing.
4. CMD access follows standard timing listed for both read and write accesses, ( CE = VIH when CMD = VIL ) or ( CMD = VIH when CE = VIL ).
6.31
11
IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
RANDOM ACCESS PORT WAVEFORM: READ CYCLES (1,2)
tRC
ADDR
tAA
tOH
(2)
ACS
t
tCHZ
t
CLZ
tBHZ
t
BE
tBLZ
tOE
tOHZ
tOLZ
I/OOUT
Valid Data Out
3016 drw 13
NOTES:
1. R/W is HIGH for Read cycle.
2. Address valid prior to or coincident with CE transition LOW; otherwise tAA is the limiting parameter.
RANDOM ACCESS PORT WAVEFORM: READ CYCLES BUFFER COMMAND MODE
t
RC
ADDR
t
AA
t
OH
(1)
tACS
t
CHZ
t
CLZ
tBHZ
t
BE
t
BLZ
t
OE
tOHZ
t
OLZ
I/OOUT
Valid Data Out
3016 drw 14
NOTE:
1. CE = VIH when CMD = VIL.
6.31
12
IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
RANDOM ACCESS PORT WAVEFORM: WRITE CYCLE NO.1 (R/W CONTROLLED TIMING) (1,6)
tWC
ADDR
tAW
R/W
(3)
(2)
t
WR
tWP
t
AS
(8)
(5)
CE, LB, UB
tDH
tDW
I/OIN
Valid Data In
OE
t
OHZ
tWHZ
Data Out(4)
Data Out(4)
I/OOUT
t
ACS
BE
t
OW
t
3016 drw 15
RANDOM ACCESS PORT WAVEFORM: WRITE CYCLE NO.2
(CE, LB, AND/OR UB CONTROLLED TIMING) (1,6,7)
tWC
ADDR
tAW
(8)
(5)
CE, LB, UB
t
AS
(3)
t
WR
(2)
(2)
t
t
CW
BP
R/W
tDW
tDH
I/OIN
Valid Data
3016 drw 16
NOTES:
1. R/W, CE, or LB and UB must be inactive during all address transitions.
2. A write occurs during the overlap of R/W = VIL, CE = VIL and LB = VIL and/or UB = VIL.
3. tWR is measured from the earlier of CE (and LB and/or UB) or R/W going HIGH to the end of the write cycle.
4. During this period, I/O pins are in the output state and the input signals must not be applied.
5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. OE is continuously HIGH, OE = VIH. If during the R/W controlled write cycle the OE is LOW, tWP must be greater or equal to tWHZ + tDW to allow the I/O
drivers to turn off and on the data to be placed on the bus for the required tDW. If OEis HIGH during the R/Wcontrolled write cycle, this requirement does
not apply and the minimum write pulse is the specified tWP. For the CE controlled write cycle, OE may be LOW with no degregation to tCW timing.
7. I/OOUT is never enabled, therefore the output is in High-Z state during the entire write cycle.
8. CMD access follows the standard CE access described above. If CMD = VIL, then CE must = VIH or, when CE = VIL, CMD must = VIH.
6.31
13
IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SEQUENTIAL PORT: AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(2)
IDT70825X20 IDT70825X25 IDT70825X35 IDT70825X45
Com'l. Only Com'l. Only
Symbol
Parameter
Min.
Max. Min.
Max.
Min.
Max.
Min. Max. Unit
READ CYCLE
tCYC
tCH
Sequential Clock Cycle Time
Clock Pulse High
25
10
10
5
—
—
—
—
—
8
30
12
12
5
—
—
—
—
—
10
—
11
25
14
—
15
40
15
15
6
—
—
—
—
—
15
—
15
35
17
—
18
50
18
18
6
—
—
—
—
—
20
—
15
45
20
—
23
ns
ns
tCL
Clock Pulse Low
ns
tES
Count Enable and Address Pointer Set-up Time
Count Enable and Address Pointer Hold Time
Output Enable to Data Valid
Output Enable Low-Z Time(1)
Output Enable High-Z Time(1)
Clock to Valid Data
ns
tEH
2
—
2
2
2
ns
tSOE
tOLZ
tOHZ
tCD
—
2
—
2
—
2
ns
2
—
9
ns
—
—
—
3
—
—
—
3
—
—
—
3
—
—
—
3
ns
20
12
—
13
ns
tCKHZ
tCKLZ
tEB
Clock High-Z Time(1)
Clock Low-Z Time(1)
ns
ns
Clock to EOB
—
—
—
—
ns
3016 tbl 22
NOTES:
1. Transition measured at ±200mV from steady state. This parameter is guaranteed with the AC Test Load (Figure 2) by device characterization, but is not
production tested.
2. "X" in part numbers indicates power rating (S or L).
SEQUENTIAL PORT: AC ELECTRICAL CHARACTERISTICS
OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE(1)
IDT70825X20
Com'l. Only
IDT70825X25
Com'l. Only
IDT70825X35
IDT70825X45
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max. Unit
WRITE CYCLE
tCYC
tFS
Sequential Clock Cycle Time
Flow Restart Time
25
13
5
—
—
—
—
—
—
30
15
5
—
—
—
—
—
—
40
20
6
—
—
—
—
—
—
50
20
6
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
tWS
Chip Select and Read/Write Set-up Time
Chip Select and Read/Write Hold Time
Input Data Set-up Time
tWH
tDS
2
2
2
2
5
5
6
6
tDH
Input Data Hold Time
2
2
2
2
NOTE:
3016 tbl 23
1. "X" in part numbers indicates power rating (S or L).
SEQUENTIAL PORT: AC ELECTRICAL CHARACTERISTICS
OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE(1)
IDT70825X20
Com'l. Only
IDT70825X25
Com'l. Only
IDT70825X35
IDT70825X45
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
RESET CYCLE
tRSPW
tWERS
tRSRC
tRSFV
Reset Pulse Width
13
10
10
15
—
—
—
—
15
10
10
20
—
—
—
—
20
10
10
25
—
—
—
—
20
10
10
25
—
—
—
—
ns
ns
Write Enable High to Reset High
Reset High to Write Enable Low
Reset High to Flag Valid
ns
ns
NOTE:
3016 tbl 24
1. "X" in part numbers indicates power rating (S or L).
6.31
14
IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SEQUENTIAL PORT WAVEFORM: WRITE, POINTER LOAD, NON-INCREMENTING READ
tCYC
tCH
t
CL
SCLK
CNTEN
SLD
tEH
tES
(2)
(3)
t
EH
(1)
t
ES
t
DS
t
DH
HIGH IMPEDANCE
SI/OIN
Dx
A0
t
t
WS
WS
t
WS
t
WH
t
WH
SR/W
SCE
tWS
tWH
t
WH
t
tCCKSHZZ
tCD
SOE
t
SOE
t
OLZ
tOHZ
SI/OOUT
D0
D0
D0
3016 drw 17
tCKLZ
SEQUENTIAL PORT WAVEFORM: WRITE, POINTER LOAD, BURST READ
t
CYC
t
CH
t
CL
SCLK
tEH
tES
(3)
CNTEN
SLD
(2)
t
EH
(1)
t
ES
t
DS
t
DS
tDH
tDH
HIGH IMPEDANCE
SI/OIN
Dx
A0
D2
tWS
tWS
t
WH
tWH
SR/W
SCE
tWS
WS
t
tWH
t
WH
tCD
SOE
tSOE
t
OHZ
tOLZ
(2)
SI/OOUT
D0
D1
t
CKLZ
3016 drw 18
NOTES:
1. If SLD = VIL, then address will be clocked in on the SCLK's rising edge.
2. If CNTEN = VIH for the SCLK's rising edge, the internal address counter will not advance.
3. Pointer is not incremented on cycle immediately following SLD even if CNTEN is LOW.
6.31
15
IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SEQUENTIAL PORT WAVEFORM: READ STRT/EOB FLAG TIMING
t
CYC
t
CH
tCL
SCLK
t
EH
t
ES
(4)
(2)
CNTEN
t
ES
t
EH
(1)
SSTRT1/2
t
DS
t
DH
HIGH IMPEDANCE
SI/OIN
Dx
D3
t
WS
t
WS
t
t
WH
t
WH
SR/W
SCE
t
WS
t
WS tWH
WH
(3)
t
CD
t
SOE
SOE
t
OHZ
t
OLZ
(2)
(5)
SI/OOUT
D0
D1
D2
tCKLZ
EOB1/2
t
EB
3016 drw 19
NOTES:
1. If SSTRT1 or SSTRT2 = VIL, then address will be clocked in on the SCLK's rising edge.
2. If CNTEN = VIH for the SCLK's rising edge, the internal address counter will not advance.
3. SOE will control the output and should be High on Power-Up. If SCE= VIL and is clocked in while SR/W = VIH, the data addressed will be read out within
that cycle. If SCE = VIL and is clocked in while SR/W= VIL, the data addressed will be written to if the last cycle was a Read. SOEmay be used to control
the bus contention and permit a Write on this cycle.
4. Unlike SLD case, CNTEN is not disabled on cycle immediately following SSTRT.
5. If SR/W = VIL, data would be written to D0 again since CNTEN = VIH.
6. SOE = VIL makes no difference at this point since the SR/W = VIL disables the output until SR/W = VIH is clocked in on the next rising clock edge.
6.31
16
IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SEQUENTIAL PORT WAVEFORM: WRITE CYCLES
tCYC
tCH
tCL
SCLK
t
EH
tEH
(4)
tES
tES
(3)
CNTEN
SLD
t
EH
(1)
tES
t
DS
t
DS
tDS
t
DH
t
DH
tDH
HIGH IMPEDANCE
SI/OIN
Dx
A0
D1
D0
tWS
tWS
tWH
t
WH
(4)
SR/W
SCE
t
WS
tWS
tWH
tWH
tCKHZ
tCD
(5)
SOE
tOHZ
HIGH IMPEDANCE
SI/OOUT
D0
D0
3016 drw 20
t
CKLZ
SEQUENTIAL PORT WAVEFORM: BURST WRITE CYCLES
tCYC
tCH
tCL
SCLK
tEH
tES
(3)
(2)
CNTEN
SLD
tES
tEH
(1)
tDS
t
DS
t
DH
tDH
D1
D0
SI/OIN
Dx
A0
D2
t
WS
t
WS
tWH
tWH
SR/
W
(5)
tWS
tWS
tWH
tWH
SCE
SOE
(5)
tCKLZ
tCD
HIGH IMPEDANCE
SI/OOUT
D2
30916 drw 21
NOTES :
1. If SLD = VIL, then address will be clocked in on the SCLK's rising edge.
2. If CNTEN = VIH for the SCLK's rising edge, the internal address counter will not advance.
3. Pointer is not incrementing on cycle immediately following SLD even if CNTEN is Low.
4. If SR/W = VIL, data would be written to D0 again since CNTEN = VIH.
5. SOE = VIL makes no difference at this point since the SR/W = VIL disables the output until SR/W = VIH is clocked in on the next rising clock edge.
6.31
17
IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SEQUENTIAL PORT WAVEFORM: WRITE CYCLES (STRT/EOB FLAG TIMING)
tCH
tCL
SCLK
tEH
t
ES
(2)
(4)
CNTEN
tES
tEH
(1)
SSTRT1/2
tDS
t
DH
HIGH IMPEDANCE
D0
D1
Dx
D2
D3
SI/OIN
tWS
t
WS
t
WH
tWH
(5)
SR/W
SCE
tWS
tWS
tWH
t
WH
(3)
(6)
tCKLZ
SOE
tCD
HIGH IMPEDANCE
D3
SI/OOUT
t
EB
EOB1/2
3016 drw 22
NOTES:
1. If SSTRT1 or SSTRT2 = VIL, then address will be clocked in on the SCLK's rising edge.
2. If CNTEN = VIH for the SCLK's rising edge, the internal address counter will not advance.
3. SOE will control the output and should be High on Power-Up. If SCE= VIL and is clocked in while SR/W = VIH, the data addressed will be read out within
that cycle. If SCE = VIL and is clocked in while SR/W= VIL, the data addressed will be written to if the last cycle was a Read. SOE may be used to control
the bus contention and permit a Write on this cycle.
4. Unlike SLD case, CNTEN is not disabled on cycle immediately following SSTRT.
5. If SR/W = VIL, data would be written to D0 again since CNTEN = VIH.
6. SOE = VIL makes no difference at this point since the SR/W = VIL disables the output until SR/W = VIH is clocked in on the next rising clock edge.
6.31
18
IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SEQUENTIAL COUNTER ENABLE CYCLE AFTER RESET, WRITE CYCLE(2, 4, 6)
SCLK
(2)
D0
D1
D2
D3
D4
SI/OIN
3016 drw 23
SEQUENTIAL COUNTER ENABLE CYCLE AFTER RESET, READ CYCLE(2, 4)
SCLK
(3)
SR
(5)
D0(5)
D3
D1
D2
SI/OOUT
3016 drw 24
NOTES:
1. 'D0' represents data input for Address=0, 'D1' represents data input for Address=1, etc.
1. If CNTEN=VIL then 'D1' would be written into 'A1' at this point.
3. Data output is available at a tCD after the SR/W=VIH is clocked. The RST sets SR/W=Low internally and therefore disables the output until the next clock.
4. SCE=VIL throughout all cycles.
5. If CNTEN=VIL then 'D1' would be clocked out (read) at this point.
6. SR/W=VIL.
6.31
19
IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
RANDOM ACCESS PORT WAVEFORM: RESET TIMING
t
RSPW
t
RSRC
, S
or
(4)
)
t
WERS
t
RSFV
1/2
Flag Valid
3016 drw 25
RANDOM ACCESS PORT WAVEFORM: RESTART TIMING OF SEQUENTIAL PORT (1)
0.5 x tCYC
tFS
SCLK
R
(2)
2-5ns
6-7ns
CLR(3)
Block
3016 drw 26
(Internal Signal)
NOTES:
1. The sequential port is in the STOP mode and is being restarted from the random port by the Bit 4 Counter Release (see Case 5).
2. "0" is written to Bit 4 from the random port at address [A2 - A0] = 100, when CMD = VIL and CE = VIH. The device is in the Buffer Command Mode
(see Case 5).
3. CLR is an internal signal only and is shown for reference only.
4. Sequential port must also prohibit SR/W or SCE from being low for tWERS and tRSRC periods, or SCLK must not toggle from Low-to-High until after tRSRC.
6.31
20
IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
XXXXX
A
999
A
A
IDT
Device
Type
Power
Speed
Package
Process/
Temperature
Range
Commercial (0°C to +70°C)
Blank
B
Military (–55°C to +125°C)
Compliant to MIL-STD-883, Class B
G
PF
84-pin PGA (G84-3)
80-pin TQFP (PN80-1)
20
25
35
45
Commercial Only
Commercial Only
Speed in nanoseconds
S
L
Standard Power
Low Power
70825 128K (8K x 16) Sequential Access Random Access
Memory
3016 drw 27
6.31
21
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