IDT7025S25GB [IDT]
HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM; 高速8K ×16双口静态RAM
| 型号： | IDT7025S25GB |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM |
| 文件： | 总20页 (文件大小：294K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT7025S/L
HIGH-SPEED
8K x 16 DUAL-PORT
STATIC RAM
Integrated Device Technology, Inc.
more than one device
FEATURES:
• M/S = H for BUSY output flag on Master
M/S = L for BUSY input on Slave
• Busy and Interrupt Flags
• On-chip port arbitration logic
• Full on-chip hardware support of semaphore signaling
between ports
• True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
• High-speed access
— Military: 20/25/35/55/70ns (max.)
— Commercial: 15/17/20/25/35/55ns (max.)
• Low-power operation
• Devices are capable of withstanding greater than 2001V
electrostatic discharge
— IDT7025S
Active: 750mW (typ.)
• Fully asynchronous operation from either port
• Battery backup operation—2V data retention
• TTL-compatible, single 5V (±10%) power supply
• Available in 84-pin PGA, 84-pin quad flatpack, 84-pin
PLCC, and 100-pin Thin Quad Plastic Flatpack
• Industrial temperature range (–40°C to +85°C) is avail-
able, tested to military electrical specifications
Standby: 5mW (typ.)
— IDT7025L
Active: 750mW (typ.)
Standby: 1mW (typ.)
• Separate upper-byte and lower-byte control for
multiplexed bus compatibility
• IDT7025 easily expands data bus width to 32 bits or
more using the Master/Slave select when cascading
FUNCTIONAL BLOCK DIAGRAM
R/
UB
W
L
L
R/
W
R
UB
R
LB
CE
OE
L
LB
CE
OER
R
L
R
L
I/O8L-I/O15L
I/O0L-I/O7L
I/O8R-I/O15R
I/O0R-I/O7R
I/O
Control
I/O
Control
BUSY (1,2)
R
BUSY(1,2)
L
A
12L
0L
A
12R
Address
Decoder
MEMORY
ARRAY
Address
Decoder
A
A
0R
13
13
NOTES:
1. (MASTER):
BUSY is output;
(SLAVE): BUSY
is input.
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
OE
R/ W
L
CE
OE
R/W
R
L
R
L
R
2. BUSY outputs
and INT outputs
are non-tri-stated
push-pull.
SEM
R
SEM
L
INT (2)
R
INT(2)
L
M/S
2683 drw 01
The IDT logo is a registered trademark of Integrated Device Technology Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
OCTOBER 1996
©1996 Integrated Device Technology, Inc.
DSC 2683/6
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
6.16
1
IDT7025S/L
HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Enable ( CE) permits the on-chip circuitry of each port to enter
a very low standby power mode.
DESCRIPTION:
The IDT7025 is a high-speed 8K x 16 Dual-Port Static
RAM. The IDT7025 is designed to be used as a stand-alone
128K-bit Dual-Port RAM or as a combination MASTER/
SLAVE Dual-Port RAM for 32-bit or more word systems.
Using the IDT MASTER/SLAVE Dual-Port RAM approach in
32-bit or wider memory system applications results in full-
speed, error-free operation without the need for additional
discrete logic.
This device provides two independent ports with separate
control, address, and I/O pins that permit independent,
asynchronous access for reads or writes to any location in
memory. AnautomaticpowerdownfeaturecontrolledbyChip
Fabricated using IDT’s CMOS high-performance technol-
ogy, these devices typically operate on only 750mW of power.
Low-power (L) versions offer battery backup data retention
capabilitywithtypical powerconsumptionof500µWfroma2V
battery.
The IDT7025 is packaged in a ceramic 84-pin PGA, an 84-
pin quad flatpack, an 84-pin PLCC, and a 100-pin TQFP.
Military grade product is manufactured in compliance with the
latest revision of MIL-STD-883, Class B, making it ideally
suited to military temperature applications demanding the
highest level of performance and reliability.
PIN CONFIGURATIONS (1,2)
INDEX
11 10
12
9
8
7
6
5
4
3
2
1 84 83 82 81 80 79 78 77 76 75
74
A
A
A
A
A
A
A
A
7L
6L
5L
4L
3L
2L
1L
0L
I/O8L
I/O9L
73
72
71
70
69
68
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
I/O10L
I/O11L
I/O12L
I/O13L
GND
IDT7025
J84-1
F84-2
I/O14L
I/O15L
67
66
65
64
63
62
61
60
59
58
57
56
55
54
INT
L
BUSY
L
V
CC
84-PIN PLCC/
FLATPACK
TOP VIEW
GND
GND
I/O0R
I/O1R
I/O2R
(3)
M/S
BUSY
R
INT
R
V
CC
A
A
A
A
A
A
A
0R
I/O3R
I/O4R
I/O5R
I/O6R
I/O7R
I/O8R
1R
2R
3R
4R
5R
6R
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
2683 drw 02
Index
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
N/C
N/C
N/C
1
N/C
N/C
N/C
N/C
75
2
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
3
N/C
4
I/O10L
I/O11L
I/O12L
I/O13L
GND
5
A
A
A
A
A
A
5L
4L
3L
2L
1L
0L
6
7
8
9
IDT7025
PN100-1
I/O14L
I/O15L
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
INT
BUSY
GND
M/
BUSY
INT
L
100-PIN
TQFP
TOP VIEW
V
CC
L
GND
I/O0R
I/O1R
I/O2R
(3)
S
R
R
V
CC
A
A
A
A
A
0R
I/O3R
I/O4R
I/O5R
I/O6R
N/C
N/C
N/C
N/C
1R
2R
3R
4R
N/C
N/C
N/C
N/C
NOTES:
1. All VCC pins must be connected to power supply.
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
2. All GND pins must be connected to ground supply.
3. This text does not indicate orientation of the actual part-marking.
2683 drw 03
6.16
2
IDT7025S/L
HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS (CONT'D) (1,2)
63
I/O7L
61
I/O5L
60
I/O4L
58
I/O2L
55
I/O0L
54
51
48
46
45
42
11
10
09
08
07
06
05
04
03
02
01
A
11L
A
10L
A
7L
OE
L
SEM
L
LB
L
66
I/O10L
64
I/O8L
62
I/O6L
59
I/O3L
56
I/O1L
49
50
47
44
43
40
A
9L
A
8L
6L
3L
0L
A
5L
A
12L
UB
L
CEL
67
I/O11L
65
I/O9L
68
I/O12L
71
I/O14L
70
57
53
52
41
39
R/W
L
GND
V
CC
A
A
4L
69
I/O13L
38
37
A
A
2L
72
I/O15L
73
33
35
34
BUSY
L
A
VCC
INT
L
IDT7025
G84-3
75
I/O0R
74
32
31
36
GND
84-PIN PGA
TOP VIEW
GND
M/S
GND
A
1L
(3)
76
I/O1R
77
I/O2R
80
I/O4R
83
I/O7R
78
28
29
30
VCC
A
0R
INT
R
BUSY
R
79
I/O3R
26
27
A
2R
A
1R
81
I/O5R
7
11
12
23
25
SEM
R
A
5R
GND
GND
A
3R
82
I/O6R
1
2
5
8
10
14
17
20
18
22
24
I/O9R
I/O10R I/O13R I/O15R R/W
15
R
A
11R
A
8R
A
6R
A
4R
UB
R
84
I/O8R
3
4
6
9
13
16
19
21
I/O11R I/O12R I/O14R
A
10R
A
9R
A
7R
OER
LB
R
CER
A
12R
A
B
C
D
E
F
G
H
J
K
L
2683 drw 04
Index
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. This text does not indicate orientation of the actual part-marking.
PIN NAMES
Left Port
Right Port
CER
Names
Chip Enable
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Ambient
CEL
R/WL
R/WR
Read/Write Enable
Output Enable
Address
OEL
OER
Grade
Military
Commercial
Temperature
–55°C to +125°C
0°C to +70°C
GND
VCC
A0L – A12L
I/O0L – I/O15L
SEML
A0R – A12R
I/O0R – I/O15R
SEMR
0V
5.0V ± 10%
Data Input/Output
Semaphore Enable
Upper Byte Select
Lower Byte Select
Interrupt Flag
Busy Flag
0V
5.0V ± 10%
2683 tbl 02
UBL
UBR
LBL
LBR
INTL
INTR
BUSYL
BUSYR
M/S
VCC
Master or Slave Select
Power
GND
Ground
2683 tbl 01
6.16
3
IDT7025S/L
HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE I – NON-CONTENTION READ/WRITE CONTROL
Inputs(1)
Outputs
CE
R/W
X
OE UB
LB
X
H
H
L
SEM
H
I/O8-15
I/O0-7
Mode
H
X
X
X
X
X
L
X
H
L
High-Z
High-Z
DATAIN
High-Z
High-Z Deselected: Power Down
High-Z Both Bytes Deselected
High-Z Write to Upper Byte Only
DATAIN Write to Lower Byte Only
X
X
H
L
L
H
L
L
H
L
H
L
L
L
H
DATAIN DATAIN Write to Both Bytes
DATAOUT High-Z Read Upper Byte Only
High-Z DATAOUT Read Lower Byte Only
DATAOUT DATAOUT Read Both Bytes
L
H
H
H
X
L
H
L
H
L
L
L
H
L
H
L
L
H
X
H
X
X
X
High-Z
High-Z Outputs Disabled
NOTE:
2683 tbl 03
1. A0L — A12L are not equal to A0R — A12R.
TRUTH TABLE II – SEMAPHORE READ/WRITE CONTROL(1)
Inputs
Outputs
CE
R/W
H
OE
UB
X
LB
X
SEM
I/O8-15
I/O0-7
Mode
H
L
L
L
L
L
L
L
L
DATAOUT DATAOUT Read Semaphore Flag Data Out
DATAOUT DATAOUT Read Semaphore Flag Data Out
DATAIN DATAIN Write I/O0 into Semaphore Flag
DATAIN DATAIN Write I/O0 into Semaphore Flag
X
H
H
X
H
X
H
X
X
X
X
X
H
L
H
X
L
L
X
X
—
—
—
—
Not Allowed
Not Allowed
X
L
NOTE:
2683 tbl 04
1. There are eight semaphore flags written to via I/O0 and read from I/O0 - I/O15. These eight semaphores are addressed by A0 - A2.
ABSOLUTE MAXIMUM RATINGS(1)
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
Rating
Commercial
Military
Unit
Symbol
Parameter
Supply Voltage
Supply Voltage
Min. Typ. Max. Unit
(2)
VTERM
Terminal Voltage –0.5 to +7.0 –0.5 to +7.0
with Respect
to GND
V
VCC
4.5
0
5.0
0
5.5
0
V
V
V
V
GND
6.0(2)
TA
Operating
0 to +70
–55 to +125 °C
VIH
VIL
Input High Voltage
Input Low Voltage
2.2
–0.5(1)
—
—
Temperature
0.8
TBIAS
TSTG
IOUT
Temperature
Under Bias
–55 to +125 –65 to +135 °C
–55 to +125 –65 to +150 °C
NOTES:
2683 tbl 06
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 0.5V.
Storage
Temperature
DC Output
Current
50
50
mA
CAPACITANCE(1)
(TA = +25°C, f = 1.0MHz)TQFP ONLY
NOTES:
2683 tbl 05
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Symbol
CIN
Parameter
Conditions(2) Max. Unit
Input Capacitance
VIN = 3dV
9
pF
pF
COUT
Output
VOUT = 3dV
10
Capacitance
2. VTERM must not exceed Vcc + 0.5V for more than 25% of the cycle time
or 10ns maximum, and is limited to < 20 mA for the period over VTERM
> Vcc + 0.5V.
NOTES:
2683 tbl 07
1. This parameter is determined by device characterization but is not
production tested.
2. 3dV references the interpolated capacitance when the input and output
signals switch from 0V to 3V or from 3V to 0V.
6.16
4
IDT7025S/L
HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (VCC = 5.0V ± 10%)
IDT7025S
IDT7025L
Symbol
Parameter
Input Leakage Current(1)
Output Leakage Current
Output Low Voltage
Test Conditions
VCC = 5.5V, VIN = 0V to VCC
CE = VIH, VOUT = 0V to VCC
IOL = 4mA
Min.
Max.
10
Min.
—
Max.
5
Unit
µA
µA
V
|ILI|
—
—
|ILO|
VOL
VOH
10
—
5
—
0.4
—
—
0.4
—
Output High Voltage
IOH = -4mA
2.4
2.4
V
2683 tbl 08
NOTE:
1. At Vcc < 2.0V input leakages are undefined.
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1) (VCC = 5.0V ± 10%)
7025X15
7025X17
7025X20
7025X25
Test
Com'l. Only
Com'l. Only
Symbol
Parameter
Condition
Version Typ.(2) Max. Typ.(2) Max. Typ.(2) Max.
Typ.(2)Max. Unit
ICC
Dynamic Operating CE"A"=VIL, Outputs Open
MIL
S
L
—
—
—
—
—
—
—
—
160
160
370
320
155
155
340
280
mA
Current
SEM = VIH
(3)
(Both Ports Active) f = fMAX
COM S
L
170
170
310
260
170
170
310 160
260 160
290
240
155
155
265
220
ISB1
ISB2
Standby Current
(Both Ports — TTL SEMR = SEML = VIH
CER = CEL = VIH
MIL
S
L
—
—
—
—
—
—
—
—
20
20
90
70
16
16
80
65
mA
mA
(3)
Level Inputs)
f = fMAX
COM S
L
20
20
60
50
20
20
60
50
20
20
60
50
16
16
60
50
(5)
Standby Current
(One Port — TTL
Level Inputs)
CE"A"=VIL and CE"B"=VIL
MIL
S
L
—
—
—
—
—
—
—
—
95
95
95
95
240
210
180
150
90
90
90
90
215
180
170
140
Active Port Outputs Open
(3)
f = fMAX
COM S
L
105
105
190
160
105
105
190
160
SEMR = SEML = VIH
ISB3
ISB4
Full Standby Current Both Ports CEL and
(Both Ports — All CER >VCC - 0.2V
MIL
S
L
—
—
—
—
—
—
—
—
1.0
0.2
30
10
1.0
0.2
30
10
mA
mA
CMOS Level Inputs) VIN > VCC - 0.2V or
VIN < 0.2V, f = 0(4)
COM S
L
1.0
0.2
15
5
1.0
0.2
15
5
1.0
0.2
15
5
1.0
0.2
15
5
SEMR
= SEML> VCC - 0.2V
Full Standby Current CE"A" < 0.2 and
MIL
S
L
—
—
—
—
—
—
—
—
90
90
225
200
85
85
200
170
(One Port — All
CE"B" > VCC - 0.2V (5)
CMOS Level Inputs) SEMR = SEML> VCC - 0.2V
VIN > VCC - 0.2V or
COM S
L
100
100
170
140
100
100
170
140
90
90
155
130
85
85
145
120
VIN < 0.2V, Active Port
Outputs Open,
(3)
f = fMAX
NOTES:
2683 tbl 09
1. "X" in part numbers indicates power rating (S or L).
2. VCC = 5V, TA = +25°C, and are not production tested. Icc dc = 120mA (typ.)
3. At f = fMAX, address and I/O'S are cycling at the maximum frequency read cycle of 1/ tRC, and using “AC Test Conditions” of input levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
6.16
5
IDT7025S/L
HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1)(Cont'd.) (VCC = 5.0V ± 10%)
7025X35
7025X55
7025X70
Mil. Only
Test
Symbol
Parameter
Condition
Version
MIL.
Typ.(2) Max. Typ.(2) Max. Typ.(2) Max. Unit
ICC
Dynamic Operating
Current
CE = VIL, Outputs Open
SEM = VIH
S
L
150
150
300
250
150
150
300
250
140
140
300 mA
250
(3)
(Both Ports Active)
f = fMAX
COM’L.
MIL.
S
L
150
150
250
210
150
150
250
210
—
—
—
—
ISB1
ISB2
Standby Current
(Both Ports — TTL
CEL = CER = VIH
SEMR = SEML = VIH
S
L
13
13
80
65
13
13
80
65
10
10
80 mA
65
(3)
Level Inputs)
f = fMAX
COM’L.
MIL.
S
L
13
13
60
50
13
13
60
50
—
—
—
—
(5)
Standby Current
(One Port — TTL
Level Inputs)
CE"A"=VIL and CE"B"=VIH
S
L
85
85
85
85
190
160
155
130
85
85
85
85
190
160
155
130
80
80
—
—
190 mA
Active Port Outputs Open
160
—
(3)
f = fMAX
COM’L.
S
L
SEMR = SEML = VIH
—
ISB3
ISB4
Full Standby Current
(Both Ports — All
Both Ports CEL and
CER > VCC - 0.2V
MIL.
S
L
1.0
0.2
30
10
1.0
0.2
30
10
1.0
0.2
30 mA
10
CMOS Level Inputs)
VIN > VCC - 0.2V or
COM’L.
S
L
1.0
0.2
15
5
1.0
0.2
15
5
—
—
—
—
VIN < 0.2V, f = 0(4)
SEMR = SEML > VCC - 0.2V
Full Standby Current
(One Port — All
CE"A" < 0.2 and
MIL.
S
L
80
80
175
150
80
80
175
150
75
75
175 mA
150
CE"B" > VCC - 0.2V(5)
CMOS Level Inputs)
SEMR = SEML > VCC - 0.2V
VIN > VCC - 0.2V or
COM’L.
S
L
80
80
135
110
80
80
135
110
—
—
—
—
VIN < 0.2V,
Active Port Outputs Open,
(3)
f = fMAX
NOTES:
2683 tbl 10
1. "X" in part numbers indicates power rating (S or L).
2. VCC = 5V, TA = +25°C, and are not production tested.
3. At f = fMAX, address and I/O'S are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES (L Version Only)
(VLC = 0.2V, VHC = VCC - 0.2V)(4)
Symbol
VDR
Parameter
VCC for Data Retention
Data Retention Current
Test Condition
VCC = 2V
CE > VHC
Min.
2.0
—
Typ.(1)
—
Max.
—
Unit
V
ICCDR
MIL.
100
100
—
4000
1500
—
µA
VIN > VHC or < VLC COM’L.
SEM > VHC
—
(3)
tCDR
Chip Deselect to Data Retention Time
Operation Recovery Time
0
ns
(3)
(2)
tR
tRC
—
—
ns
NOTES:
2683 tbl 11
1. TA = +25°C, VCC = 2V, and are by characterization but are not production tested.
2. tRC = Read Cycle Time
3. This parameter is guaranteed by device characterization but are not production tested.
4. At Vcc < 2.0V, input leakages are not defined.
DATA RETENTION WAVEFORM
DATA RETENTION MODE
V
DR≥
2V
VCC
4.5V
4.5V
tCDR
tR
VDR
V
IH
VIH
CE
2683 drw 05
6.16
6
IDT7025S/L
HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
5V
5V
AC TEST CONDITIONS
Input Pulse Levels
GND to 3.0V
5ns Max.
1.5V
1250Ω
1250Ω
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
DATAOUT
BUSY
INT
DATAOUT
775Ω
30pF
775Ω
5pF
1.5V
Figures 1 and 2
2683 tbl 12
2683 drw 06
Figure 1. AC Output Test Load
Figure 2. Output Test Load
( for tLZ, tHZ, tWZ, tOW)
*
including scope and jig.
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(4)
IDT7025X15
Com'l. Only
Min. Max.
IDT7025X17
Com'l. Only
IDT7025X20
IDT7025X25
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max. Unit
READ CYCLE
tRC
Read Cycle Time
15
—
—
—
—
3
—
15
15
15
10
—
—
10
—
15
—
15
17
—
—
—
—
3
—
17
17
17
10
—
—
10
—
17
—
17
20
—
—
—
—
3
—
20
20
20
12
—
—
12
—
20
—
20
25
—
—
—
—
3
—
25
25
25
13
—
—
15
—
25
—
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address Access Time
tACE
tABE
tAOE
tOH
tLZ
Chip Enable Access Time(3)
Byte Enable Access Time(3)
Output Enable Access Time
Output Hold from Address Change
Output Low-Z Time(1, 2)
Output High-Z Time(1, 2)
Chip Enable to Power Up Time(1,2)
Chip Disable to Power Down Time(1,2)
3
3
3
3
tHZ
—
0
—
0
—
0
—
0
tPU
tPD
—
—
10
—
—
10
—
—
10
—
tSOP
tSAA
Semaphore Flag Update Pulse (OE or SEM) 10
Semaphore Address Access(3)
—
IDT7025X35
IDT7025X55
IDT7025X70
Mil. Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max. Unit
READ CYCLE
tRC
Read Cycle Time
Address Access Time
Chip Enable Access Time(3)
35
—
—
—
—
3
—
35
35
35
20
—
—
15
—
35
—
35
55
—
—
—
—
3
—
55
55
55
30
—
—
25
—
50
—
55
70
—
—
—
—
3
—
70
70
70
35
—
—
30
—
50
—
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
tACE
tABE
tAOE
tOH
tLZ
Byte Enable Access Time(3)
Output Enable Access Time
Output Hold from Address Change
Output Low-Z Time(1, 2)
Output High-Z Time(1, 2)
Chip Enable to Power Up Time(1,2)
Chip Disable to Power Down Time(1,2)
Semaphore Flag Update Pulse (OE or SEM)
Semaphore Address Access Time(3)
3
3
3
tHZ
—
0
—
0
—
0
tPU
tPD
—
15
—
—
15
—
—
15
—
tSOP
tSAA
NOTES:
2683 tbl 13
1. Transition is measured ±500mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL, UB or LB = VIL, and SEM = VIH. To access semephore, CE = VIH or UB & LB = VIH, and SEM = VIL.
4. "X" in part numbers indicates power rating (S or L).
6.16
7
IDT7025S/L
HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF READ CYCLES(5)
t
RC
ADDR
(4)
t
t
AA
(4)
ACE
CE
OE
(4)
t
AOE
(4)
tABE
UB, LB
R/W
t
OH
(1)
t
LZ
VALID DATA(4)
DATAOUT
BUSYOUT
NOTES:
(2)
tHZ
(3, 4)
2683 drw 07
t
BDD
1. Timing depends on which signal is asserted last, OE, CE, LB, or UB.
2. Timing depends on which signal is de-asserted first, CE, OE, LB, or UB.
3. tBDD delay is required only in case where opposite port is completing a write operation to the same address location for simultaneous read operations
BUSY has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tABE, tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
TIMING OF POWER-UP POWER-DOWN
CE
tPU
tPD
ICC
50%
50%
ISB
2683 drw 08
6.16
8
IDT7025S/L
HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE(5)
IDT7025X15
Com'l. Only
IDT7025X17
Com'l. Only
IDT7025X20
IDT7025X25
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max. Unit
WRITE CYCLE
tWC
tEW
tAW
tAS
Write Cycle Time
Chip Enable to End-of-Write(3)
15
12
12
0
—
—
—
—
—
—
—
10
—
10
—
—
—
17
12
12
0
—
—
—
—
—
—
—
10
—
10
—
—
—
20
15
15
0
—
—
—
—
—
—
—
12
—
12
—
—
—
25
20
20
0
—
—
—
—
—
—
—
15
—
15
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Valid to End-of-Write
Address Set-up Time(3)
tWP
tWR
tDW
tHZ
Write Pulse Width
12
0
12
0
15
0
20
0
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time(1, 2)
Data Hold Time(4)
Write Enable to Output in High-Z(1, 2)
Output Active from End-of-Write(1, 2, 4)
SEM Flag Write to Read Time
SEM Flag Contention Window
10
—
0
10
—
0
15
—
0
15
—
0
tDH
tWZ
tOW
tSWRD
tSPS
—
0
—
0
—
0
—
0
5
5
5
5
5
5
5
5
IDT7025X35
IDT7025X55
IDT7025X70
Mil. Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max. Unit
WRITE CYCLE
tWC
tEW
tAW
tAS
Write Cycle Time
35
30
30
0
—
—
—
—
—
—
—
15
—
15
—
—
—
55
45
45
0
—
—
—
—
—
—
—
25
—
25
—
—
—
70
50
50
0
—
—
—
—
—
—
—
30
—
30
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Enable to End-of-Write(3)
Address Valid to End-of-Write
Address Set-up Time(3)
tWP
tWR
tDW
tHZ
Write Pulse Width
25
0
40
0
50
0
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time(1, 2)
Data Hold Time(4)
Write Enable to Output in High-Z(1, 2)
Output Active from End-of-Write(1, 2, 4)
SEM Flag Write to Read Time
SEM Flag Contention Window
15
—
0
30
—
0
40
—
0
tDH
tWZ
tOW
tSWRD
tSPS
—
0
—
0
—
0
5
5
5
5
5
5
NOTES:
2683 tbl 14
1. Transition is measured ±500mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL. Either condition must be
valid for the entire tEW time.
4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary
over voltage and temperature, the actual tDH will always be smaller than the actual tOW.
5. "X" in part numbers indicates power rating (S or L).
6.16
9
IDT7025S/L
HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/W CONTROLLED TIMING(1,5,8)
tWC
ADDRESS
(7)
t
HZ
OE
t
AW
CE or SEM (9)
UB or LB (9)
R/W
(3)
(2)
(6)
tWR
t
AS
tWP
(7)
tOW
tWZ
(4)
(4)
DATAOUT
DATAIN
t
DW
tDH
2683 drw 09
TIMING WAVEFORM OF WRITE CYCLE NO. 2, CE, UB, LB CONTROLLED TIMING(1,5)
tWC
ADDRESS
CE or SEM(9)
UB or LB (9)
R/W
tAW
(6)
AS
(3)
WR
(2)
EW
t
t
t
tDW
tDH
DATAIN
2683 drw 10
NOTES:
1. R/W or CE or UB & LB must be High during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a Low UB or LB and a Low CE and a Low R/W for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going High to the end-of-write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM Low transition occurs simultaneously with or after the R/W Low transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE, R/W, or byte control.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured +/- 500mV from steady state with Output
Test Load (Figure 2).
8. If OE is Low during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data
to be placed on the bus for the required tDW. If OEis High during an R/W controlled write cycle, this requirement does not apply and the write pulse can
be as short as the specified tWP.
9. To access RAM, CE = VIL, UB or LB = VIL, and SEM = VIH. To access Semaphore, CE = VIH or UB & LB = VIL, and SEM = VIL. tEW must be met
for either condition.
6.16
10
IDT7025S/L
HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING, EITHER SIDE(1)
t
OH
t
SAA
A0-A2
VALID ADDRESS
VALID ADDRESS
t
WR
t
ACE
t
AW
t
EW
SEM
t
SOP
t
DW
DATAIN
VALID
DATAOUT
I/O0
(2)
VALID
t
AS
t
WP
tDH
R/W
tSWRD
tAOE
OE
Write Cycle
Read Cycle
2683 drw 11
NOTES:
1. CE = VIH or UB & LB = VIH for the duration of the above timing (both write and read cycle).
2. "DATAOUT VALID" represents all I/O's (I/O0-I/O15) equal to the semaphore value.
TIMING WAVEFORM OF SEMAPHORE WRITE CONTENTION(1,3,4)
A0"A"-A2"A"
MATCH
SIDE(2)
“A”
R/W"A"
SEM"A"
tSPS
A0"B"-A2"B"
MATCH
SIDE(2)
“B”
R/W"B"
SEM"B"
2683 drw 12
NOTES:
1. DOR = DOL = VIL, CER = CEL = VIH, or both UB & LB = VIH.
2. All timing is the same for left and right port. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
3. This parameter is measured from R/W"A" or SEM"A" going High to R/W"B" or SEM"B" going High.
4. If tSPS is not satisfied, there is no guarantee which side will be granted the semaphore flag.
6.16
11
IDT7025S/L
HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE(6)
IDT7025X15
Com'l Only
IDT7025X17 IDT7025X20 IDT7025X25
Com'l Only
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Min.
Max. Unit
BUSY TIMING (M/S = VIH)
tBAA
tBDA
tBAC
tBDC
tAPS
tBDD
tWH
BUSY Access Time from Address Match
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable Low
BUSY Disable Time from Chip Enable High
Arbitration Priority Set-up Time(2)
BUSY Disable to Valid Data(3
Write Hold After BUSY(5)
—
—
—
—
5
15
15
15
15
—
18
—
—
—
—
—
5
17
17
17
17
—
18
—
—
—
—
—
5
20
20
20
17
—
30
—
—
—
—
—
5
20
20
20
17
—
30
—
ns
ns
ns
ns
ns
ns
ns
—
12
—
13
—
15
—
17
BUSY TIMING (M/S = VIL)
tWB
tWH
BUSY Input to Write(4)
Write Hold After BUSY(5)
0
—
0
—
0
—
—
0
—
ns
12
—
13
—
15
17
—
ns
PORT-TO-PORT DELAY TIMING
tWDD
tDDD
Write Pulse to Data Delay(1)
Write Data Valid to Read Data Delay(1)
—
—
30
25
—
—
30
25
—
—
45
35
—
—
50
35
ns
ns
IDT7025X35
IDT7025X55
IDT7025X70
Mil. Only
Symbol
BUSY TIMING (M/S = VIH)
Parameter
Min.
Max.
Min.
Max.
Min.
Max. Unit
tBAA
tBDA
tBAC
tBDC
tAPS
tBDD
tWH
BUSY Access Time from Address Match
—
—
—
—
5
20
20
20
20
—
35
—
—
—
—
—
5
45
40
40
35
—
40
—
—
—
—
—
5
45
40
40
35
—
45
—
ns
ns
ns
ns
ns
ns
ns
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable Low
BUSY Disable Time from Chip Enable High
Arbitration Priority Set-up Time(2)
BUSY Disable to Valid Data(3)
Write Hold After BUSY(5)
—
25
—
25
—
25
BUSY TIMING (M/S = VIL)
tWB
tWH
BUSY Input to Write(4)
Write Hold After BUSY(5)
0
—
—
0
—
—
0
—
—
ns
ns
25
25
25
PORT-TO-PORT DELAY TIMING
tWDD
tDDD
Write Pulse to Data Delay(1)
Write Data Valid to Read Data Delay(1)
—
—
60
45
—
—
80
65
—
—
95
80
ns
ns
NOTES:
2683 tbl 15
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Read With BUSY (M/S = VIH)" or "Timing Waveform
of Write With Port-To-Port Delay (M/S = VIH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0ns, tWDD – tWP (actual), or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited pn Port "B" during contention with Port "A".
5. To ensure that a write cycle is completed on Port "B" after contention with Port "A".
6. "X" in part numbers indicates power rating (S or L).
6.16
12
IDT7025S/L
HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(2,4,5)
TIMING WAVEFORM OF WRITE PORT-TO-PORT READ AND BUSY (M/S = VIH
)
tWC
MATCH
ADDR"A"
R/W"A"
tWP
tDW
t
DH
VALID
DATAIN "A"
(1)
tAPS
MATCH
ADDR"B"
tBAA
tBDA
tBDD
BUSY"B"
t
WDD
DATAOUT "B"
VALID
(3)
t
DDD
2683 drw 13
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (slave).
2. CEL = CER = VIL.
3. OE = VIL for the reading port.
4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above.
5. All timing is the same for left and right ports. Port "A" may be either the left of right port. Port "B" is the opposite Port from Port "A".
TIMING WAVEFORM OF WRITE WITH BUSY
tWP
R/W"A"
(3)
t
WB
BUSY"B"
(1)
tWH
R/
W"B"
(2)
2683 drw 14
NOTES:
1. tWH must be met for both BUSY input (slave) output master.
2. Busy is asserted on port "B" Blocking R/W"B", until BUSY"B" goes High.
3. tWB is only for the 'Slave' Version.
6.16
13
IDT7025S/L
HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF BUSY ARBITRATION CONTROLLED BY CE TIMING (M/S = VIH)(1)
ADDR"A"
ADDRESSES MATCH
and "B"
CE"A"
(2)
tAPS
CE"B"
t
BAC
t
BDC
BUSY"B"
2683 drw 15
WAVEFORM OF BUSY ARBITRATION CYCLE CONTROLLED BY ADDRESS MATCH TIMING
(M/S = VIH)(1)
ADDRESS "N"
ADDR"A"
ADDR"B"
(2)
t
APS
MATCHING ADDRESS "N"
t
BAA
tBDA
BUSY"B"
2683 drw 16
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. If tAPS is not satisfied, the busy signal will be asserted on one side or another but there is no guarantee on which side busy will be asserted.
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1)
IDT7025X15
Com'l. Only
IDT7025X17
Com'l. Only
IDT7025X20
IDT7025X25
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max. Unit
INTERRUPT TIMING
tAS
Address Set-up Time
0
0
—
—
15
15
0
0
—
—
15
15
0
0
—
—
20
20
0
0
—
—
20
20
ns
ns
ns
ns
tWR
tINS
tINR
Write Recovery Time
Interrupt Set Time
—
—
—
—
—
—
—
—
Interrupt Reset Time
IDT7025X35
IDT7025X55
IDT7025X70
Mil. Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max. Unit
INTERRUPT TIMING
tAS
Address Set-up Time
0
0
—
—
25
25
0
0
—
—
40
40
0
0
—
—
50
50
ns
ns
ns
ns
tWR
tINS
tINR
Write Recovery Time
Interrupt Set Time
—
—
—
—
—
—
Interrupt Reset Time
NOTE:
2683 tbl 16
1. "X" in part numbers indicates power rating (S or L).
6.16
14
IDT7025S/L
HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF INTERRUPT TIMING(1)
tWC
INTERRUPT SET ADDRESS(2)
ADDR"A"
CE"A"
(3)
AS
(4)
t
tWR
R/W"A"
INT"B"
(3)
INS
t
2683 drw 17
t
RC
INTERRUPT CLEAR ADDRESS(2)
ADDR"B"
CE"B"
(3)
t
AS
OE"B"
(3)
INR
t
INT"B"
2683 drw 18
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. See Interrupt Flag truth table.
3. Timing depends on which enable signal ( CE or R/W ) is asserted last.
4. Timing depends on which enable signal ( CE or R/W ) is de-asserted first.
TRUTH TABLES
TRUTH TABLE III — INTERRUPT FLAG(1)
Left Port
Right Port
OER A0R-A12R INTR
R/WL
CEL
L
OEL A0L-A12L INTL
R/WR
CER
X
Function
Set Right INTR Flag
L
X
X
X
L
1FFF
X
X
X
L(3)
H(2)
X
X
L
X
L
X
L(2)
H(3)
X
X
X
L
1FFF
1FFE
X
Reset Right INTR Flag
Set Left INTL Flag
X
X
X
X
L
X
X
L
1FFE
X
X
X
Reset Left INTL Flag
NOTES:
2683 tbl 17
1. Assumes BUSYL = BUSYR = VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
4. INTR and INTL must be initialized at power-up.
6.16
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IDT7025S/L
HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TRUTH TABLE IV —
ADDRESS BUSY ARBITRATION
Inputs
Outputs
A0L-A12L
CER A0R-A12R BUSYL
(1)
(1)
CEL
X
BUSYR
Function
Normal
X
X
H
L
NO MATCH
MATCH
H
H
H
H
H
Normal
X
MATCH
H
H
Normal
Write Inhibit(3)
L
MATCH
(2)
(2)
NOTES:
2683 tbl 18
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. BUSYare inputs when configured as a slave. BUSYx outputs on the
IDT7025 are push pull, not open drain outputs. On slaves the BUSY asserted internally inhibits write.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable
after the address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = Low will result. BUSYL and BUSYR outputs cannot be low
simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving low regardless of actual logic level on the pin. Writes to the right port are
internally ignored when BUSYR outputs are driving low regardless of actual logic level on the pin.
TRUTH TABLE V — EXAMPLE OF SEMAPHORE PROCUREMENT SEQUENCE(1,2)
Functions
D0 - D15 Left
D0 - D15 Right
Status
No Action
1
0
0
1
1
0
1
1
1
0
1
1
1
1
0
0
1
1
0
1
1
1
Semaphore free
Left Port Writes "0" to Semaphore
Right Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "1" to Semaphore
Right Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
NOTES:
2683 tbl 19
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7025.
2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O15). These eight semaphores are addressed by A0 - A2.
FUNCTIONAL DESCRIPTION
writes to memory location 1FFF (HEX) and to clear the
interrupt flag (INTR), the right port must access the memory
location1FFF, Themessage(16bits)at1FFEor1FFFisuser-
defined, since it is an addressable SRAM location. If the
interrupt function is not used, address locations 1FFE and
1FFF are not used as mail boxes, but as part of the random
access memory. Refer to Truth Table for the interrupt opera-
tion.
The IDT7025 provides two ports with separate control,
addressandI/Opinsthatpermitindependentaccessforreads
or writes to any location in memory. The IDT7025 has an
automatic power down feature controlled by CE. The CE
controls on-chip power down circuitry that permits the
respective port to go into a standby mode when not selected
(CE High). When a port is enabled, access to the entire
memory array is permitted.
BUSY LOGIC
INTERRUPTS
Busy Logic provides a hardware indication that both ports
of the RAM have accessed the same location at the same
time. It also allows one of the two accesses to proceed and
signalstheothersidethattheRAMis“Busy”. Thebusypincan
thenbeusedtostalltheaccessuntiltheoperationon theother
side is completed. If a write operation has been attempted
from the side that receives a busy indication, the write signal
is gated internally to prevent the write from proceeding.
If the user chooses to use the interrupt function, a memory
location(mailboxormessagecenter)isassignedtoeachport.
Theleftportinterruptflag(INTL)isassertedwhentherightport
writes to memory location 1FFE (HEX), where a write is
defined as the CER = R/WR = VIL per the Truth Table. The left
port clears the interrupt by an address location 1FFE access
when CEL = OEL = VIL, R/WL is a "don't care". Likewise, the
right port interrupt flag (INTR) is asserted when the left port
6.16
16
IDT7025S/L
HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
MASTER
Dual Port
RAM
BUSY
CE
SLAVE
Dual Port
RAM
BUSY
CE
L
BUSY
R
L
BUSYR
MASTER
Dual Port
RAM
SLAVE
Dual Port
RAM
CE
CE
BUSY
BUSY
R
BUSY
L
BUSYL
BUSY
R
R
BUSY
L
2683 drw 19
Figure 3. Busy and chip enable routing for both width and depth expansion with IDT7025 RAMs.
The use of busy logic is not required or desirable for all can be initiated with either the R/Wsignal or the byte enables.
applications. In some cases it may be useful to logically OR Failure to observe this timing can result in a glitched internal
the busy outputs together and use any busy indication as an write inhibit signal and corrupted data in the slave.
interrupt source to flag the event of an illegal or illogical
operation. If the write inhibit function of busy logic is not
desirable, the busy logic can be disabled by placing the part
SEMAPHORES
The IDT7025 is an extremely fast Dual-Port 8K x 16 CMOS
in slave mode with the M/Spin. Once in slave mode theBUSY
Static RAM with an additional 8 address locations dedicated
pin operates solely as a write inhibit input pin. Normal opera-
tobinarysemaphoreflags. Theseflagsalloweitherprocessor
tion can be programmed by tying the BUSY pins high. If
on the left or right side of the Dual-Port RAM to claim a
desired, unintended write operations can be prevented to a
privilege over the other processor for functions defined by the
system designer’s software. As an example, the semaphore
port by tying the busy pin for that port low.
The busy outputs on the IDT 7025 RAM in master mode,
can be used by one processor to inhibit the other from
are push-pull type outputs and do not require pull up resistors
accessing a portion of the Dual-Port RAM or any other shared
to operate. If these RAMs are being expanded in depth, then
resource.
the busy indication for the resulting array requires the use of
The Dual-Port RAM features a fast access time, and both
ports are completely independent of each other. This means
an external AND gate.
that the activity on the left port in no way slows the access time
oftherightport. Bothportsareidenticalinfunctiontostandard
CMOS Static RAM and can be read from, or written to, at the
WIDTH EXPANSION WITH BUSY LOGIC
MASTER/SLAVE ARRAYS
same time with the only possible conflict arising from the
simultaneous writing of, or a simultaneous READ/WRITE of,
anon-semaphorelocation. Semaphoresareprotectedagainst
such ambiguous situations and may be used by the system
program to avoid any conflicts in the non-semaphore portion
of the Dual-Port RAM. These devices have an automatic
power-down feature controlled by CE, the Dual-Port RAM
enable, and SEM, the semaphore enable. The CE and SEM
pins control on-chip power down circuitry that permits the
respective port to go into standby mode when not selected.
This is the condition which is shown in Truth Table where CE
and SEM are both high.
Systems which can best use the IDT7025 contain multiple
processors or controllers and are typically very high-speed
systems which are software controlled or software intensive.
These systems can benefit from a performance increase
offered by the IDT7025's hardware semaphores, which pro-
vide a lockout mechanism without requiring complex pro-
gramming.
When expanding an IDT7025 RAM array in width while
using busy logic, one master part is used to decide which side
of the RAM array will receive a busy indication, and to output
that indication. Any number of slaves to be addressed in the
same address range as the master, use the busy signal as a
write inhibit signal. Thus on the IDT7025 RAM the busy pin is
an output if the part is used as a master (M/Spin = H), and the
busy pin is an input if the part used as a slave (M/Spin = L) as
shown in Figure 3.
If two or more master parts were used when expanding in
width, a split decision could result with one master indicating
busy on one side of the array and another master indicating
busyononeothersideofthearray. Thiswouldinhibitthewrite
operations from one port for part of a word and inhibit the write
operations from the other port for the other part of the word.
The busy arbitration, on a master, is based on the chip
enable and address signals only. It ignores whether an
access is a read or write. In a master/slave array, both
address and chip enable must be valid long enough for a busy
flag to be output from the master before the actual write pulse
Software handshaking between processors offers the
6.16
17
IDT7025S/L
HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
maximum in system flexibility by permitting shared resources until the semaphore is freed by the first side.
to be allocated in varying configurations. The IDT7025 does
When a semaphore flag is read, its value is spread into all
not use its semaphore flags to control any resources through data bits so that a flag that is a one reads as a one in all data
hardware, thus allowing the system designer total flexibility in bits and a flag containing a zero reads as all zeros. The read
system architecture.
valueislatchedintooneside’soutputregisterwhenthatside's
An advantage of using semaphores rather than the more semaphore select (SEM) and output enable (OE) signals go
common methods of hardware arbitration is that wait states active. This serves to disallow the semaphore from changing
are never incurred in either processor. This can prove to be state in the middle of a read cycle due to a write cycle from the
a major advantage in very high-speed systems.
other side. Because of this latch, a repeated read of a
semaphoreinatestloopmustcauseeithersignal(SEMorOE)
to go inactive or the output will never change.
HOW THE SEMAPHORE FLAGS WORK
A sequence WRITE/READ must be used by the sema-
phore in order to guarantee that no system level contention
will occur. A processor requests access to shared resources
by attempting to write a zero into a semaphore location. If the
semaphore is already in use, the semaphore request latch will
contain a zero, yet the semaphore flag will appear as one, a
fact which the processor will verify by the subsequent read
(see Table III). As an example, assume a processor writes a
zero to the left port at a free semaphore location. On a
subsequent read, the processor will verify that it has written
successfully to that location and will assume control over the
resource in question. Meanwhile, if a processor on the right
side attempts to write a zero to the same semaphore flag it will
fail, as will be verified by the fact that a one will be read from
that semaphore on the right side during subsequent read.
Had a sequence of READ/WRITE been used instead, system
contention problems could have occurred during the gap
between the read and write cycles.
It is important to note that a failed semaphore request must
be followed by either repeated reads or by writing a one into
the same location. The reason for this is easily understood by
looking at the simple logic diagram of the semaphore flag in
Figure 4. Two semaphore request latches feed into a sema-
phore flag. Whichever latch is first to present a zero to the
semaphore flag will force its side of the semaphore flag low
andtheothersidehigh. Thisconditionwillcontinueuntilaone
is written to the same semaphore request latch. Should the
other side’s semaphore request latch have been written to a
zero in the meantime, the semaphore flag will flip over to the
other side as soon as a one is written into the first side’s
request latch. The second side’s flag will now stay low until its
semaphore request latch is written to a one. From this it is
easy to understand that, if a semaphore is requested and the
processor which requested it no longer needs the resource,
the entire system can hang up until a one is written into that
semaphore request latch.
The semaphore logic is a set of eight latches which are
independent of the Dual-Port RAM. These latches can be
used to pass a flag, or token, from one port to the other to
indicate that a shared resource is in use. The semaphores
provideahardwareassistforauseassignmentmethodcalled
“Token Passing Allocation.” In this method, the state of a
semaphore latch is used as a token indicating that shared
resource is in use. If the left processor wants to use this
resource, it requests the token by setting the latch. This
processor then verifies its success in setting the latch by
reading it. If it was successful, it proceeds to assume control
overthesharedresource. Ifitwasnotsuccessfulinsettingthe
latch, it determines that the right side processor has set the
latchfirst, hasthetokenandisusingthesharedresource. The
left processor can then either repeatedly request that
semaphore’s status or remove its request for that semaphore
to perform another task and occasionally attempt again to
gain control of the token via the set and test sequence. Once
the right side has relinquished the token, the left side should
succeed in gaining control.
The semaphore flags are active low. A token is requested
by writing a zero into a semaphore latch and is released when
the same side writes a one to that latch.
The eight semaphore flags reside within the IDT7025 in a
separate memory space from the Dual-Port RAM. This
address space is accessed by placing a low input on the SEM
pin (which acts as a chip select for the semaphore flags) and
using the other control pins (Address, OE, and R/W) as they
would be used in accessing a standard Static RAM. Each of
the flags has a unique address which can be accessed by
eithersidethroughaddresspinsA0–A2. Whenaccessingthe
semaphores, none of the other address pins has any effect.
When writing to a semaphore, only data pin D0 is used. If
a low level is written into an unused semaphore location, that
flagwillbesettoazeroonthatsideandaoneontheotherside
(see Table III). That semaphore can now only be modified by
thesideshowingthezero. Whenaoneiswrittenintothesame
locationfromthesameside,theflagwillbesettoaoneforboth
sides (unless a semaphore request from the other side is
pending) and then can be written to by both sides. The fact
that the side which is able to write a zero into a semaphore
subsequently locks out writes from the other side is what
makes semaphore flags useful in interprocessor communica-
tions. (Athoroughdiscussingontheuseofthisfeaturefollows
shortly.) A zero written into the same location from the other
side will be stored in the semaphore request latch for that side
The critical case of semaphore timing is when both sides
request a single token by attempting to write a zero into it at
the same time. The semaphore logic is specially designed to
resolve this problem. If simultaneous requests are made, the
logic guarantees that only one side receives the token. If one
side is earlier than the other in making the request, the first
side to make the request will receive the token. If both
requests arrive at the same time, the assignment will be
arbitrarily made to one port or the other.
One caution that should be noted when using semaphores
6.16
18
IDT7025S/L
HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
is that semaphores alone do not guarantee that access to a side, the left side could undo its semaphore request and
resource is secure. As with any powerful programming perform other tasks until it was able to write, then read a zero
technique, if semaphores are misused or misinterpreted, a into Semaphore 1. If the right processor performs a similar
software error can easily happen.
task with Semaphore 0, this protocol would allow the two
Initialization of the semaphores is not automatic and must processors to swap 4K blocks of Dual-Port RAM with each
be handled via the initialization program at power-up. Since other.
any semaphore request flag which contains a zero must be
The blocks do not have to be any particular size and can
reset to a one, all semaphores on both sides should have a even be variable, depending upon the complexity of the
one written into them at initialization from both sides to assure software using the semaphore flags. All eight semaphores
that they will be free when needed.
could be used to divide the Dual-Port RAM or other shared
resources into eight parts. Semaphores can even be as-
signed different meanings on different sides rather than being
given a common meaning as was shown in the example
above.
Semaphores are a useful form of arbitration in systems like
disk interfaces where the CPU must be locked out of a section
ofmemoryduringatransferandtheI/Odevicecannottolerate
any wait states. With the use of semaphores, once the two
deviceshasdeterminedwhichmemoryareawas“off-limits”to
the CPU, both the CPU and the I/O devices could access their
assigned portions of memory continuously without any wait
states.
Semaphores are also useful in applications where no
memory “WAIT” state is available on one or both sides. Once
a semaphore handshake has been performed, both proces-
sors can access their assigned RAM segments at full speed.
Another application is in the area of complex data struc-
tures. In this case, block arbitration is very important. For this
applicationoneprocessormayberesponsibleforbuildingand
updating a data structure. The other processor then reads
andinterpretsthatdatastructure. Iftheinterpretingprocessor
reads an incomplete data structure, a major error condition
may exist. Therefore, some sort of arbitration must be used
between the two different processors. The building processor
arbitrates for the block, locks it and then is able to go in and
update the data structure. When the update is completed, the
data structure block is released. This allows the interpreting
processortocomebackandreadthecompletedatastructure,
thereby guaranteeing a consistent data structure.
USING SEMAPHORES—SOME EXAMPLES
Perhaps the simplest application of semaphores is their
application as resource markers for the IDT7025’s Dual-Port
RAM. Say the 8K x 16 RAM was to be divided into two 4K x
16 blocks which were to be dedicated at any one time to
servicing either the left or right port. Semaphore 0 could be
usedtoindicatethesidewhichwouldcontrolthelowersection
of memory, and Semaphore 1 could be defined as the
indicator for the upper section of memory.
To take a resource, in this example the lower 4K of
Dual-Port RAM, the processor on the left port could write and
then read a zero in to Semaphore 0. If this task were
successfully completed (a zero was read back rather than a
one), the left processor would assume control of the lower 4K.
Meanwhile the right processor was attempting to gain control
of the resource after the left processor, it would read back a
one in response to the zero it had attempted to write into
Semaphore 0. At this point, the software could choose to try
and gain control of the second 4K section by writing, then
reading a zero into Semaphore 1. If it succeeded in gaining
control, it would lock out the left side.
Once the left side was finished with its task, it would write
a one to Semaphore 0 and may then try to gain access to
Semaphore 1. If Semaphore 1 was still occupied by the right
L PORT
R PORT
SEMAPHORE
REQUEST FLIP FLOP
SEMAPHORE
REQUEST FLIP FLOP
D0
D0
D
D
Q
Q
WRITE
WRITE
SEMAPHORE
READ
SEMAPHORE
READ
2683 drw 21
Figure 4. IDT7025 Semaphore Logic
6.16
19
IDT7025S/L
HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT XXXXX
A
999
A
A
Device
Type
Power
Speed
Package
Process/
Temperature
Range
Blank
Commercial (0°C to +70°C)
B
Military (–55°C to +125°C)
Compliant to MIL-STD-883, Class B
PF
G
J
100-pin TQFP (PN100-1)
84-pin PGA (G84-3)
84-pin PLCC (J84-1)
84-pin Flatpack (F84-2)
F
15
17
20
25
35
55
70
Commercial Only
Commercial Only
Speed in nanoseconds
Military Only
S
L
Standard Power
Low Power
7025
128K (8K x 16) Dual-Port RAM
2683 drw 21
6.16
20
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