IDT59910A [IDT]
LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.; 低偏移PLL时钟驱动器TURBOCLOCK JR 。型号: | IDT59910A |
厂家: | INTEGRATED DEVICE TECHNOLOGY |
描述: | LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR. |
文件: | 总6页 (文件大小:54K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LOW SKEW
IDT59910A
PLL CLOCK DRIVER
TURBOCLOCK™ JR.
FEATURES:
DESCRIPTION:
• Eight zero delay outputs
The IDT59910A is a high fanout phase lock loop clock driver in-
tended for high performance computing and data-communications appli-
cations. The IDT59910A has eight zero delay TTL outputs.
• Selectable positive or negative edge synchronization
• Synchronous output enable
• Output frequency: 15MHz to 100MHz
• TTL outputs
• 3 skew grades:
IDT59910A-2: tSKEW0<250ps
The IDT59910A maintains Cypress CY7B9910 compatibility while pro-
viding two additional features: Synchronous Output Enable (GND/sOE),
and Positive/Negative Edge Synchronization (VCCQ/PE). When the GND/
sOE pin is held low, all the outputs are synchronously enabled (CY7B9910
compatibility). However, if GND/sOE is held high, all the outputs except
Q2 and Q3 are synchronously disabled.
Furthermore, when the VCCQ/PE is held high, all the outputs are syn-
chronized with the positive edge of the REF clock input (CY7B9910
compatibility). When VCCQ/PE is held low, all the outputs are synchro-
nized with the negative edge of REF.
The FB signal is compared with the input REF signal at the phase
detector in order to drive the VCO. Phase differences cause the VCO of
the PLL to adjust upwards or downwards accordingly.
An internal loop filter moderates the response of the VCO to the
phase detector. The loop filter transfer function has been chosen to
provide minimal jitter (or frequency variation) while still providing accu-
rate responses to input frequency changes.
IDT59910A-5: tSKEW0<500ps
IDT59910A-7: tSKEW0<750ps
• 3-level inputs for PLL range control
• PLL bypass for DC testing
• External feedback, internal loop filter
• 46mA IOL high drive outputs
• Low Jitter: <200ps peak-to-peak
• Outputs drive 50Ω terminated lines
• Pin-compatible with Cypress CY7B9910
• Available in SOIC package
FUNCTIONALBLOCKDIAGRAM
VCCQ/PE
GND/sOE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
FB
PLL
REF
FS
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
SEPTEMBER 2001
1
c
2001 Integrated Device Technology, Inc.
DSC 5845/1
IDT59910A
LOWSKEWPLLCLOCKDRIVERTURBOCLOCKJR.
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
PINCONFIGURATION
ABSOLUTEMAXIMUMRATINGS(1)
Symbol
Description
Supply Voltage to Ground
DC Input Voltage
Max
–0.5 to +7
–0.5 to +7
530
Unit
V
1
2
3
GND
TEST
NC
REF
VCCQ
FS
24
23
22
21
20
19
18
17
16
15
14
13
VI
V
Maximum Power Dissipation (TA = 85°C)
Storage Temperature
mW
°C
TSTG
–65 to +150
GND/sOE
VCCN
Q7
4
5
NC
NOTE:
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
VCCQ/PE
VCCN
Q0
6
7
Q6
8
GND
Q5
Q1
9
GND
Q2
10
11
12
Q4
VCCN
FB
Q3
VCCN
CAPACITANCE(TA = +25°C, f = 1MHz, VIN = 0V)
Parameter Description
Typ.
Max.
Unit
CIN
InputCapacitance
5
7
pF
NOTE:
SOIC
1. Capacitance applies to all inputs except TEST and FS. It is characterized but not
production tested.
TOP VIEW
PINDESCRIPTION
Pin Name
REF
Type
IN
Description
ReferenceClockInput
FeedbackInput
FB
IN
TEST(1)
GND/ sOE(1)
IN
When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Set LOW for normal operation.
IN
Synchronous Output Enable. When HIGH, it stops clock outputs (except Q2 and Q3) in a LOW state - Q2 and Q3 may be used as the
feedbacksignaltomaintainphaselock. SetGND/sOELOWfornormaloperation.
VCCQ/PE
FS(2)
IN
IN
Selectablepositiveornegativeedgecontrol. WhenLOW/HIGHtheoutputsaresynchronizedwiththenegative/positiveedgeofthe
referenceclock.
Frequency range select. 3 level input.
FS = GND: 15 to 35MHz
FS = MID (or open): 25 to 60MHz
FS = VCC: 40 to 100MHz
Q0 - Q7
VCCN
OUT
PWR
PWR
PWR
Eightclockoutput
Powersupplyforoutputbuffers
Powersupplyforphaselockedloopandotherinternalcircuitry
Ground
VCCQ
GND
NOTES:
1. When TEST = MID and GND/sOE = HIGH, PLL remains active.
2. This input is wired to Vcc, GND, or unconnected. Default is MID level. If it is switched in the real time mode, the outputs may glitch, and the PLL may require an additional
lock time before all data sheet limits are achieved.
2
IDT59910A
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
LOWSKEWPLLCLOCKDRIVERTURBOCLOCKJR.
RECOMMENDEDOPERATINGRANGE
IDT59910A-5,-7
(Industrial)
IDT59910A-2
(Commercial)
Symbol
VCC
Description
Min.
Max.
5.5
Min.
Max.
5.25
+70
Unit
V
Power Supply Voltage
AmbientOperatingTemperature
4.5
-40
4.75
0
TA
+85
°C
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Symbol
Parameter
Conditions
Guaranteed Logic HIGH (REF, FB Inputs Only)
Guaranteed Logic LOW (REF, FB Inputs Only)
3-Level Inputs Only
Min.
Max.
Unit
V
VIH
Input HIGH Voltage
2
—
—
VIL
InputLOWVoltage
0.8
V
VIHH
VIMM
VILL
IIN
Input HIGH Voltage(1)
InputMIDVoltage(1)
InputLOWVoltage(1)
InputLeakageCurrent
(REF, FB Inputs Only)
VCC−1
VCC/2−0.5
—
—
V
3-Level Inputs Only
VCC/2+0.5
V
3-Level Inputs Only
1
V
VIN = VCC or GND
—
±5
µA
VCC = Max.
VIN = VCC
HIGH Level
MID Level
LOW Level
—
—
—
—
—
2.4
—
—
—
±200
±50
±200
±100
±100
—
I3
3-Level Input DC Current (TEST, FS)
VIN = VCC/2
µA
VIN = GND
IPU
IPD
Input Pull-Up Current (VCCQ/PE)
Input Pull-Down Current (GND/sOE)
Output HIGH Voltage
VCC = Max., VIN = GND
VCC = Max., VIN = VCC
VCC = Min., IOH = −16mA
VCC = Min., IOH = −40mA
VCC = Min., IOL = 46mA
VCC = Max., VO = GND
µA
µA
V
VOH
—
VOL
IOS
OutputLOWVoltage
OutputShortCircuitCurrent(2)
0.45
−250
V
mA
NOTES:
1. These inputs are normally wired to VCC, GND, or unconnected. Internal termination resistors bias unconnected inputs to VCC/2. If these inputs are switched, the function and
timing of the outputs may be glitched, and the PLL may require an additional tLOCK time before all datasheet limits are achieved.
2. This is to be measured at 25°C with 10:1 duty cycle, one output at a time, and one second maximum.
POWERSUPPLYCHARACTERISTICS
Symbol
Parameter
TestConditions(1)
VCC = Max., TEST = MID, REF = LOW,
GND/sOE = LOW, All outputs unloaded
VCC = Max., VIN = 3.4V
Typ.(2)
Max.
Unit
ICCQ
Quiescent Power Supply Current
10
40
mA
∆ICC
ICCD
ITOT
Power Supply Current per Input HIGH
Dynamic Power Supply Current per Output
TotalPowerSupplyCurrent
0.4
100
53
1.5
160
—
mA
VCC = Max., CL = 0pF
µA/MHz
VCC = 5V, FREF = 25MHz, CL = 240pF(1)
VCC = 5V, FREF = 33MHz, CL = 240pF(1)
VCC = 5V, FREF = 66MHz, CL = 240pF(1)
63
—
mA
117
—
NOTE:
1. For eight outputs, each loaded with 30pF.
3
IDT59910A
LOWSKEWPLLCLOCKDRIVERTURBOCLOCKJR.
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
INPUTTIMINGREQUIREMENTS
Symbol
tR, tF
tPWC
Description(1)
Maximum input rise and fall times, 0.8V to 2V
Input clock pulse, HIGH or LOW
Input duty cycle
Min.
—
Max.
10
Unit
ns/V
ns
3
—
DH
10
90
%
REF
Referenceclockinput
15
100
MHz
NOTE:
1. Where pulse width implied by DH is less than tPWC limit, tPWC limit applies.
SWITCHINGCHARACTERISTICSOVEROPERATINGRANGE
IDT59910A-2
IDT59910A-5
IDT59910A-7
Symbol Parameter
Min.
15
Typ.
—
—
—
—
—
0.1
—
0
Max.
35
Min.
15
Typ.
—
—
—
—
—
0.25
—
0
Max.
35
Min.
15
Typ.
—
—
—
—
—
0.3
—
0
Max.
Unit
FS = LOW
FS = MED
FS = HIGH
35
60
FREF
REFFrequencyRange
25
60
25
60
25
MHz
40
100
—
40
100
—
40
100
—
tRPWH
tRPWL
REF Pulse Width HIGH(1,8)
REF Pulse Width LOW(1,8)
3
3
3
ns
ns
ns
ns
ns
ns
ns
ns
ms
ps
3
—
3
—
3
—
tSKEW0 ZeroOutputSkew(AllOutputs)(1,3,4)
—
0.25
0.75
0.25
1.2
1.2
1.2
0.5
25
—
0.5
1.25
0.5
1.2
1.5
1.5
0.5
25
—
0.75
1.65
0.7
1.2
2.5
2.5
0.5
25
tDEV
tPD
Device-to-Device Skew(1,2,5)
—
—
—
REF Input to FB Propagation Delay(1,7)
Output Duty Cycle Variation from 50%(1)
OutputRiseTime(1)
OutputFallTime(1)
PLLLockTime(1,6)
−0.25
−1.2
0.15
0.15
—
−0.5
−1.2
0.15
0.15
—
−0.7
−1.2
0.15
0.15
—
tODCV
tORISE
tOFALL
tLOCK
tJR
0
0
0
1
1
1.5
1.5
—
—
—
1
1
—
—
—
—
—
—
Cycle-to-CycleOutputJitter(1)
RMS
—
—
—
Peak-to-Peak
—
200
—
200
—
200
NOTES:
1. All timing and jitter tolerances apply for FNOM > 25MHz.
2. Skew is the time between the earliest and the latest output transition among all outputs with the specified load.
3. tSKEW is the skew between all outlets. See AC TEST LOADS.
4. For IDT59910A-2 tSKEW0 is measured with CL = 0pF; for CL = 30pF, tSKEW0 = 0.35ns Max.
5. tDEV is the output-to-output skew between any two devices operating under the same conditions (VCC, ambient temperature, air flow, etc.)
6. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is
measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
7. tPD is measured with REF input rise and fall times (from 0.8V to 2V ) of 1ns.
8. Refer to INPUT TIMING REQUIREMENTS for more detail.
4
IDT59910A
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
LOWSKEWPLLCLOCKDRIVERTURBOCLOCKJR.
AC TEST LOADS AND WAVEFORMS
≤1ns
≤1ns
VCC
3.0V
2.0V
Vth =1.5V
0.8V
130Ω
0V
Output
TTL Input Test Waveform
CL
91Ω
tOFALL
tORISE
CL = 50pF (CL = 30pF for -2 and -5 devices)
Test Load
2.0V
0.8V
TTL Output Waveform
AC TIMING DIAGRAM
tRPWL
tREF
tRPWH
REF
tPD
tODCV
tODCV
FB
tJR
Q
tSKEW
tSKEW
OTHER Q
NOTES:
Skew: The time between the earliest and the latest output transition among all outputs when all are loaded with 50pF (30pF for -2 and -5) and terminated with 50Ω to 2.06V.
tSKEW:
The skew between all outputs.
tDEV:
The output-to-output skew between any two devices operating under the same conditions (VCC, ambient temperature, air flow, etc.)
The deviation of the output from a 50% duty cycle.
tODCV:
tORISE and tOFALL are measured between 0.8V and 2V.
tLOCK:
The time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter
is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
5
IDT59910A
LOWSKEWPLLCLOCKDRIVERTURBOCLOCKJR.
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
ORDERINGINFORMATION
XX
Package Process
XXXXX
IDT
Device Type
X
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Blank
I
Small Outline IC (300-mil)
SO
Low Skew PLL Clock Driver TurboClock Jr.
59910A-2
59910A-5
59910A-7
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
2975StenderWay
Santa Clara, CA 95054
800-345-7015 or 408-727-6116
fax: 408-492-8674
logichelp@idt.com
(408) 654-6459
www.idt.com
6
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