IDT54823CDSOB [IDT]
HIGH PERFORMANCE CMOS BUS INTERFACE REGISTER; 高性能CMOS总线接口寄存器
| 型号： | IDT54823CDSOB |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | HIGH PERFORMANCE CMOS BUS INTERFACE REGISTER |
| 文件： | 总7页 (文件大小：90K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HIGH PERFORMANCE
IDT54/74FCT823A/B/C
CMOS BUS INTERFACE
REGISTER
FEATURES:
DESCRIPTION:
• Equivalent to AMD's Am29823 bipolar registers in pinout/
function, speed, and output drive over full temperature and
voltage supply extremes
The FCT823 series is built using an advanced dual metal CMOS
technology. TheFCT823 businterfaceregistersaredesignedtoeliminate
the extra packages required to buffer existing registers and provide extra
data width for wider address/data paths or buses carrying parity. The
FCT823 is a 9-bit wide buffered register with Clock Enable (EN) and Clear
(CLR)–idealforparitybusinterfacinginhigh-performancemicroprogram-
medsystems.
• IDT54/74FCT823A equivalent to FAST™ speed
• IDT54FCT823B 25% faster than FAST
• IDT74FCT823C 40% faster than FAST
• Buffered common Clock Enable (EN) and Asynchronous Clear
Input (CLR)
• IOL = 48mA (commercial) and 32mA (military)
• Clamp diodes on all inputs for ringing suppression
• CMOS power levels (1mW typ. static)
• TTL input and output compatibility
• CMOS output level compatible
The FCT823 high-performance interface family is designed for high-
capacitance load drive capability, while providing low-capacitance bus
loading at both inputs and outputs. All inputs have clamp diodes and all
outputs are designed for low-capacitance bus loading in high-impedance
state.
• Substantially lower input current levels than AMD's bilopar
Am29800 series (5µAmax.)
• MIlitary product compliant to MIL-STD-883, Class B
• Available in the following packages:
– Commercial: SOIC
– Military: CERDIP, LCC
FUNCTIONALBLOCKDIAGRAM
D0
DN
14
EN
11
CLR
CL
CL
D
Q
Q
D
Q
Q
CP
CP
13
1
CP
OE
Y0
YN
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
JUNE 2002
1
© 2002 Integrated Device Technology, Inc.
DSC-5426/3
IDT54/74FCT823A/B/C
HIGH-PERFORMANCECMOSBUFFER
MILITARYANDCOMMERCIAL TEMPERATURERANGES
PINCONFIGURATION
24
23
22
21
20
19
18
17
16
15
14
13
1
2
OE
D0
VCC
Y0
INDEX
D1
D2
Y1
Y2
3
4
4
3
2
28 27 26
5
D2
25
24
23
22
Y2
1
6
D3
D4
NC
D5
D6
D7
Y3
Y4
D3
D4
D5
Y3
Y4
Y5
5
6
7
8
9
7
8
NC
Y5
9
21
20
19
D6
D7
Y6
Y7
10
Y6
11
Y7
18
12 13 14 15 16 17
D8
Y8
10
11
CLR
EN
CP
GND
12
CERDIP/ SOIC
TOP VIEW
LCC
TOP VIEW
LOGICSYMBOL
ABSOLUTEMAXIMUMRATINGS(1)
9
Symbol Rating
Commercial
Military
Unit
D
D
9
(2)
Q
Y
VTERM
Terminal Voltage
–0.5 to +7
–0.5 to +7
V
with Respect to GND
Terminal Voltage
CP EN CLR
(3)
VTERM
–0.5 to VCC –0.5 to VCC
V
CP
EN
CLR
with Respect to GND
Operating Temperature
Temperature under BIAS
Storage Temperature
Power Dissipation
TA
0 to +70 –55 to +125
°C
°C
°C
W
TBIAS
TSTG
PT
–55 to +125 –65 to +135
–55 to +125 –65 to +150
OE
0.5
0.5
PINDESCRIPTION
IOUT
DC Output Current
120
120
mA
Pin Name
Dx
I/O
Description
D flip-flop data inputs
NOTES:
I
I
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage may exceed
Vcc by +0.5V unless otherwise noted.
CLR
For both inverting and non-inverting registers, when
the clear input is LOW and OE is LOW, the Qx
outputs are LOW. When the clear input is HIGH, data
can be entered into the register.
2. Input and Vcc terminals only.
3. Output and I/O terminals only.
CP
I
Clock Pulse for the Register; enters data into the
register on the LOW-to-HIGH transition.
Y x
O
I
Register 3-state outputs
EN
Clock Enable. When the clock enable is LOW, data
on the DI input is transferred to the QI output on the
LOW-to-HIGH clock transition. When the clock enable
is HIGH, the QI outputs do not change state,
regardless of the data or clock input transitions.
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Symbol
Parameter(1)
Input Capacitance
Output Capacitance
Conditions
Typ.
Max. Unit
CIN
VIN = 0V
6
8
10
12
pF
pF
COUT
VOUT = 0V
OE
I
Output Control. When the OE input is HIGH, the Yx
outputs are in the high impedance state. When the OE
input is LOW, the TRUE register data is present at the
Yx outputs.
NOTE:
1. This parameter is measured at characterization but not tested.
2
IDT54/74FCT823A/B/C
MILITARYANDCOMMERCIAL TEMPERATURERANGES
HIGH-PERFORMANCECMOSBUFFER
FUNCTIONTABLE(1)
Inputs
Internal/
Outputs
OE
H
H
H
L
CLR
H
EN
L
Dx
L
CP
↑
↑
X
Qx
Yx
Z
Function
L
H
High Z
H
L
H
X
X
X
X
L
Z
L
X
X
H
H
L
L
Z
Clear
Hold
Load
L
X
L
L
H
L
H
X
N C
Z
H
X
N C N C
H
H
L
H
↑
↑
↑
↑
L
H
L
Z
Z
L
H
L
H
L
H
L
L
H
L
H
H
H
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance
↑ = LOW-to-HIGH Transition
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:VLC =0.2V;VHC =VCC -0.2V
Commercial: TA = 0°C to +70°C, VCC = 5.0V ±5%, Military: TA = -55°C to +125°C, VCC = 5.0V ±10%
Symbol
VIH
Parameter
Input HIGH Level
Test Conditions(1)
Guaranteed Logic HIGH Level
Min.
2
Typ.(2)
—
Max.
—
Unit
V
VIL
Input LOW Level
Guaranteed Logic LOW Level
—
—
—
—
—
—
0.8
5
V
IIH
Input HIGH Current
VI = VCC
VI = 2.7V
VI = 0.5V
VI = GND
—
(4)
VCC = Max.
—
5
µA
µA
IIL
Input LOW Current
—
–5(4)
—
–5
IOZH
IOZL
VO = VCC
VO = 2.7V
VO = 0.5V
VO = GND
—
—
—
—
—
—
—
10
10(4)
–10(4)
–10
Off State (High Impedance)
Output Current
VCC = Max.
—
—
VIK
IOS
Clamp Diode Voltage
Short Circuit Current
Output HIGH Voltage
VCC = Min., IIN = –18mA
VCC = Max., VO = GND(3)
–0.7
–1.2
V
–75
–120
—
—
—
—
—
mA
VOH
VCC = 3V, VIN = VLC or VHC, IOH = –32µA
VCC = Min
VHC
VHC
2.4
2.4
—
—
—
—
VCC
VCC
4.3
IOH = –300µA
IOH = –15mA MIL
IOH = –24mA COM'L
V
V
VIN = VIH or VIL
4.3
VOL
Output LOWVoltage
VCC = 3V, VIN = VLC or VHC, IOL = 300µA
VCC = Min
GND
GND
0.3
VLC
(4)
IOL = 300µA
IOL = 32mA MIL
IOL = 48mA COM'L
VLC
VIN = VIH or VIL
0.5
0.5
0.3
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient and maximum loading.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. This parameter is guaranteed but not ttested.
3
IDT54/74FCT823A/B/C
HIGH-PERFORMANCECMOSBUFFER
MILITARYANDCOMMERCIAL TEMPERATURERANGES
POWERSUPPLYCHARACTERISTICS
VLC = 0.2V; VHC = VCC - 0.2V
Symbol
Parameter
Test Conditions(1)
Min.
Typ.(2)
Max.
Unit
ICC
Quiescent Power Supply Current
VCC = Max.
—
0.2
1.5
mA
VIN ≥ VHC; VIN ≤ VLC
∆ICC
Quiescent Power Supply Current
TTL Inputs HIGH
VCC = Max.
VIN = 3.4V(3)
—
—
0.5
2
mA
ICCD
Dynamic Power Supply
Current(4)
VCC = Max.
Outputs Open
VIN ≥ VHC
VIN ≤ VLC
0.15
0.25
mA/
MHz
OE = EN = GND
One Input Toggling
50% Duty Cycle
IC
Total Power Supply Current(6)
VCC = Max.
Outputs Open
fCP = 10MHz
VIN ≥ VHC
VIN ≤ VLC
(FCT)
—
—
1.7
2.2
4
6
mA
50% Duty Cycle
OE = EN = GND
One Bit Toggling
at fi = 5MHz
VIN = 3.4V
VIN = GND
50% Duty Cycle
VCC = Max.
Outputs Open
fCP = 10MHz
VIN ≥ VHC
VIN ≤ VLC
(FCT)
—
—
4
7.8(5)
50% Duty Cycle
OE = EN = GND
at fi = 2.5MHz
VIN = 3.4V
VIN = GND
6.2
16.8(5)
Eight Bits Toggling
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of ∆ICC formula. These limits are guaranteed but not tested.
6. IC = IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fiNi)
ICC = Quiescent Current
∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V)
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for register devices (zero for non-register devices)
fi = Input Frequency
Ni = Number of Inputs at fi
All currents are in milliamps and all frequencies are in megahertz.
4
IDT54/74FCT823A/B/C
MILITARYANDCOMMERCIAL TEMPERATURERANGES
HIGH-PERFORMANCECMOSBUFFER
SWITCHINGCHARACTERISTICSOVEROPERATINGRANGE
54/74FCT823A
54FCT823B
Mil.
Min.(2)
74FCT823C
Com'l.
Min.(2) Max.
Com'l.
Min.(2)
Mil.
Symbol
tPLH
Parameter
Condition(1)
CL = 50pF
RL = 500Ω
CL = 300pF(3)
RL = 500Ω
CL = 50pF
RL = 500Ω
CL = 300pF(3)
RL = 500Ω
CL = 5pF(3)
RL = 500Ω
CL = 50pF
RL = 500Ω
CL = 50pF
RL = 500Ω
Max.
Min.(2)
Max.
Max.
Unit
PropagationDelay
CP to Yx (OE = LOW)
—
—
—
—
—
—
4
10
—
—
—
—
—
—
4
11.5
—
—
—
—
—
—
3
8.5
—
—
—
—
—
—
3
6
12.5
7
ns
tPHL
20
12
23
7
20
13
25
8
16
9
tPZH
tPZL
OutputEnableTime,
ns
ns
ns
OE to Yx
16
7
12.5
6.2
6.5
—
tPHZ
tPLZ
OutputDisableTime,
OE to Yx
8
9
8
tSU
Set-up Time HIGH or LOW, Dx to CP
Set-up Time HIGH or LOW, EN to CP
Hold Time HIGH or LOW, Dx to CP
Hold Time HIGH or LOW, EN to CP
Propagation Delay, CLR to Yx
—
—
—
tH
2
2
—
—
14
—
—
—
2
2
—
—
15
—
—
—
1.5
0
—
—
9.5
—
—
—
1.5
0
—
—
8
ns
ns
ns
ns
ns
ns
tH
tPHL
tREM
tW
—
6
—
7
—
6
—
6
Recovery Time, CLR to CP
CP Pulse Width HIGH or LOW
—
—
—
7
7
6
6
tW
CLR Pulse Width HIGH or LOW
6
7
6
6
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. These parameters are guaranteed but not tested.
5
IDT54/74FCT823A/B/C
HIGH-PERFORMANCECMOSBUFFER
MILITARYANDCOMMERCIAL TEMPERATURERANGES
TESTCIRCUITSANDWAVEFORMS
VCC
7.0V
SWITCHPOSITION
500Ω
Test
Switch
Closed
Open
VOUT
VIN
Open Drain
Disable Low
Enable Low
Pulse
Generator
D.U.T
.
50pF
All Other Tests
500Ω
RT
L
C
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Octal link
Test Circuits for All Outputs
3V
DATA
1.5V
0V
INPUT
LOW-HIGH-LOW
PULSE
tH
tSU
1.5V
1.5V
3V
1.5V
0V
TIMING
INPUT
tW
ASYNCHRONOUS CONTROL
tREM
PRESET
3V
1.5V
0V
CLEAR
HIGH-LOW-HIGH
PULSE
ETC.
SYNCHRONOUS CONTROL
PRESET
3V
Octal link
1.5V
0V
CLEAR
tSU
tH
CLOCK ENABLE
ETC.
Pulse Width
Octal link
Set-Up, Hold, and Release Times
ENABLE
DISABLE
3V
1.5V
0V
3V
SAME PHASE
CONTROL
INPUT
1.5V
0V
INPUT TRANSITION
tPLH
tPLH
tPHL
tPHL
tPZL
tPLZ
VOH
1.5V
VOL
OUTPUT
3.5V
1.5V
3.5V
VOL
VOH
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
0.3V
0.3V
3V
1.5V
0V
tPZH
tPHZ
OPPOSITE PHASE
INPUT TRANSITION
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
1.5V
0V
Octal link
0V
Octal link
Propagation Delay
Enable and Disable Times
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; ZO ≤ 50Ω; tF ≤ 2.5ns; tR ≤ 2.5ns.
6
IDT54/74FCT823A/B/C
MILITARYANDCOMMERCIAL TEMPERATURERANGES
HIGH-PERFORMANCECMOSBUFFER
ORDERINGINFORMATION
IDT
XX
FCT
XXXX
XX
X
Temp. Range
Package
Process
Device Type
Blank
B
Commercial
MIL-STD-883, Class B
Commercial Options
Small Outline IC
SO
Military Options
CERDIP
Leadless Chip Carrier
D
L
High Performance CMOS Bus
Interface Register, 9-Bit
823A
823B
823C
54
74
– 55°C to +125°C
– 40°C to +85°C
DATASHEETDOCUMENTHISTORY
6/27/2002 Updated according to PDNs Logic-00-07 and Logic-01-04
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800-345-7015 or 408-727-6116
fax: 408-492-8674
for Tech Support:
logichelp@idt.com
(408) 654-6459
www.idt.com
7
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