IDT100496RL10C [IDT]
Standard SRAM, 16KX4, 10ns, CDIP32;
| 型号： | IDT100496RL10C |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Standard SRAM, 16KX4, 10ns, CDIP32 CD 静态存储器 内存集成电路 |
| 文件： | 总8页 (文件大小：169K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT10496RL
IDT100496RL
IDT101496RL
SELF-TIMED BiCMOS ECL
STATIC RAM
64K (16K x 4-BIT) STRAM
Integrated Device Technology, Inc.
and latches on outputs, and the self-timed write operation,
provide enhanced system performance over conventional
RAMs, providing easier design and improved system level
cycle times.
FEATURES:
• 16,384-words x 4-bit organization
• Self-Timed, with registers on inputs and latches on
outputs
Inputs are captured by the leading edge of an externally
supplied differential clock. The small input valid window re-
quiredmeansmoremarginforsystemskews.Logic-to-memory
propagation delay is included in device cycle time calculation,
allowingthisdevicetodeliverbettersystemperformancethan
asynchronous SRAMs and glue logic.
• Balanced Read/Write cycle time: 10/12/15 ns
• Access time: 10/12/15 ns (max.)
• Fully compatible with ECL logic levels
• Through-hole DIP and surface-mount packages
DESCRIPTION:
Write timing is controlled internally based on the clock.
Write Enable has no special requirements. The device allows
balancedreadandwritecycletimes, andreadsandwritescan
be inserted in any order.
The IDT10496RL, IDT100496RL and IDT101496RL are
65,536-bit high-speed BiCEMOS ECL static random ac-
cess memories organized as 16K x 4, with inputs and outputs
fully compatible with ECL levels. Clocked registers on inputs
FUNCTIONAL BLOCK DIAGRAM
A0
R
E
G
I
65,536-BIT
MEMORY ARRAY
V
V
CC
EE
DECODER
S
T
E
R
REF. VOLTAGE
GENERATOR
V
BB
A13
R
E
G
I
S
T
E
R
D
0
Q
Q
Q
Q
0
1
2
3
L
A
T
C
H
SENSE AMPS
AND READ/WRITE
CONTROL
D1
A
D2
D3
WRITE-PULSE
GENERATOR
*
MUX
B
A/B
L
A
T
C
H
R
E
G
WE
CS
2771 drw 01
CLK
CLK
* *HOLD/OPEN
BiCEMOS is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
AUGUST 1992
1992 Integrated Device Technology, Inc.
1
IDT10496RL, IDT100496RL, IDT101496RL
HIGH SPEED BiCMOS ECL SELF-TIMED STATIC RAM 64K (16K x 4-BIT)
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
CS
D0
D1
D2
D3
Q0
WE
VBB
2
3
CLK
CLK
NC
NC
A13
A12
VEE
A11
A10
A9
A8
A7
A6
A5
4
5
6
Q1
7
Vcc
Vcc
Q2
Q3
A0
A1
A2
A3
8
9
300-Mil-Wide
PLASTIC SOJ PACKAGE
SO32-2
10
11
12
13
400-Mil-Wde
CERAMIC PACKAGE
C32-2
2771 drw 04
2771 drw 03
14
15
16
A4
2771 drw 02
TOP VIEW
PIN DESCRIPTION
Symbol
Pin Name
A0 through A13
D0 through D3
Q0 through Q3
WE
Address Inputs
Data Inputs
Hi-Rel Die
For Hybrid and MCM
Applications
Data Outputs
Write Enable Input
CS
Chip Select Input (Internal pull down)
Differential Clock Inputs
Reference Voltage Output (≈1.32V)
More Negative Supply Voltage
Less Negative Supply Voltage
No Connect - not internally bonded
2771 drw 05
CLK
CLK,
LOGIC SYMBOL
VBB
VEE
VCC
NC
D0 D1 D2 D3
A0
CAPACITANCE (TA=+25°C, f=1.0MHz)
A1
A2
DIP
SOJ
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
Symbol
Parameter
Input
Typ. Max. Typ. Max. Unit
CINCLK
6
4
6
–
–
–
3
3
3
–
–
–
pF
pF
pF
Capacitance
CLK
CLK/
Q0
CIN
Input
Q1
Q2
Q3
Capacitance
except CLK/
CLK
COUT
Output
Capacitance
TRUTH TABLE(1)
(2)
CLK
DataOUT
Function
H
X
H
L
L
Deselected
Read
CLK CLK WE CS
L
L
RAM Data
WRITE Data
Write
16Kx4
STRAM
NOTES:
1. H=High, L=Low, X=Don’t Care
2. DATAOUT initiated by falling edge of CLK.
2771 drw 05
2
IDT10496RL, IDT100496RL, IDT101496RL
HIGH SPEED BiCMOS ECL SELF-TIMED STATIC RAM 64K (16K x 4-BIT)
COMMERCIAL TEMPERATURE RANGE
(1)
ABSOLUTE MAXIMUM RATINGS
AC/DC ELECTRICAL OPERATING RANGES
Symbol
Rating
Value
Unit
I/O
VEE
TA
10K
100K
-5.2V ± 5%
-4.5V ± 5%
0 to +75°C, air flow exceeding 2 m/sec
0 to +85°C, air flow exceeding 2 m/sec
VTERM
Terminal Voltage
With Respect to GND
+0.5 to -7.0
V
TA
Operating
Temperature
10K
100K
101K
0 to +75
0 to +85
0 to +75
°C
101K -4.75V to -5.46V 0 to +75°C, air flow exceeding 2 m/sec
2760 tbl 05
TBIAS
TSTG
Temperature Under Bias
-55 to +125
°C
°C
Storage Ceramic
Temperatuure Plastic
Power Dissipation
-65 to +150
-55 to +125
PT
1.5
-50
W
IOUT
DC Output Current
(Output High)
mA
NOTE:
2760 tbl 04
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
onlyandfunctionaloperationofthedeviceattheseoranyotherconditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect reliability.
(1)
DC ELECTRICAL CHARACTERISTICS
10K
100K/101K
Min.
Symbol
Parameter
Min.
Max.
TA
Max.
Unit
VOH
Output HIGH Voltage
(VIN= VIH(Max) or VIL(Min))
-1000
-960
-900
-840
-810
-720
0°C
25°C
75°C
-1025
-1810
-1035
—
-880
mV
VOL
VOHC
VOLC
VIH
VIL
Output LOW Voltage
(VIN= VIH(Max) or VIL(Min))
-1870
-1850
-1830
-1665
-1650
-1625
0°C
25°C
75°C
-1620
—
mV
mV
mV
mV
mV
Output Threshold HIGH Voltage
(VIN= VIH(Min) or VIL(Max))
-1020
-980
-920
—
—
—
0°C
25°C
75°C
Output Threshold LOW Voltage
(VIN= VIH(Min) or VIL(Max))
—
—
—
-1645
-1630
-1605
0°C
25°C
75°C
-1610
-880
-1475
Input HIGH Voltage
(Guaranteed Input Voltage
High for All Inputs)
-1145
-1105
-1045
-840
-810
-720
0°C
25°C
75°C
-1165
-1810
Input LOW Voltage
(Guaranteed Input Voltage
Low for All Inputs)
-1870
-1850
-1830
-1490
-1475
-1450
0°C
25°C
75°C
IIH
Input HIGH Current
VIN= VIH(Max)
CS
Others
—
—
220
110
—
—
—
—
220
110
µA
µA
IIL
Input LOW Current
VIN= VIL(Min)
CS
Others
0.5
-50
170
90
—
—
0.5
-50
170
90
µA
µA
IEE
Supply Current
-260
—
—
-240 (100K)
-260 (101K)
—
—
mA
NOTE:
1. RL = 50Ω to -2V, air flow exceeding 2 m/sec.
2760 tbl 05
3
IDT10496RL, IDT100496RL, IDT101496RL
HIGH SPEED BiCMOS ECL SELF-TIMED STATIC RAM 64K (16K x 4-BIT)
COMMERCIAL TEMPERATURE RANGE
AC TEST LOAD CONDITION
AC TEST INPUT PULSE
VCC (GND)
-0.9V
-1.7V
80%
20%
DATAOUT
50Ω
30pF*
tR
tF
tR = tF = 1.5ns typ.
Note: All timing measurements are
referenced to 50% input levels.
0.01µF
-2.0V
VEE
* Includes probe and jig
capacitance.
2771 drw 08
2771 drw 07
RISE/FALL TIME
Symbol Parameter
Min.
Typ.
1.5
Max.
—
Unit
tR
tF
Output Rise Time
Output Fall Time
—
—
ns
1.5
—
ns
2771 tbl 06
FUNCTIONAL DESCRIPTION
the outputs. Output data flows out the output latch and is held
into the next cycle.
The IDT10496RL, IDT100496RL and IDT101496RL Self-
Timed BiCMOS ECL static RAMs (STRAM) provide high
speed with low power dissipation typical of BiCMOS ECL.
On-chiplogicadditionallyhelpsimprovesystemperformance.
The ECL-101K meets electrical specifications that combine
the ECL-100K temperature and voltage compensated output
levels with the high-speed of ECL-10K VEE compatibility (-
5.2V).
As can be seen in the Functional Block Diagram on the title
page, this device contains clocked input registers to sample
andholdaddresses, inputdata, andcontrolstatus. Inputsare
sampled on the rising edge of the clock (CLK) input (falling
edge of CLK). In the case of a write cycle, the memory cell is
writtenduringtheclock-hightime, andwritedataconductedto
READ TIMING
In a typical read cycle, the read address is captured by the
rising edge of clock, as at ❶ below. Then, when clock goes
low, thereaddataforthereadaddressclockedinat❶isgated
through the output latch to the output pins. There is a short
delay from falling clock to output ready, called tDR (see Read
Cycle Timing). If the clock-high time (tWH) is shorter than the
inherent access-time of the cell, output is guaranteed valid
after the specified tACC. But if tWH is longer than the cell ac-
cess-time, output data will be valid tDR after clock goes low.
Thus, the time it takes from clock-to-output for any given
FUNCTIONAL DESCRIPTION TIMING EXAMPLE
tCYC
CLK
READ
DESELECT
WRITE
READ
WRITE
WRITE
READ
READ
CS
ADDR
❷
❶
❸
❹
❺
❺
➏
❼
➑
❸
➏
DATAIN
WE
❶
❷
❸
❹
❺
➏
❼
DATAOUT
READ DATA
DESELECT
WRITE DATA
READ DATA
WRITE DATA
WRITE DATA
READ DATA
2771 drw 08
tACC
4
IDT10496RL, IDT100496RL, IDT101496RL
HIGH SPEED BiCMOS ECL SELF-TIMED STATIC RAM 64K (16K x 4-BIT)
COMMERCIAL TEMPERATURE RANGE
address (the latency, or tACC) is
tACC = tACC or (tWH + tDR),
whichever is larger.
WRITE TIMING
Write cycles are identical to read cycles, except that write
enable and write data need also be supplied, with the appro-
The output latch takes some time to change state for the priate setup and hold timing. The device has on-chip timing
nextcycle,butthistimeisveryshort. Therefore,dataholdtime that handles all aspects of writing data into the addressed
from clock low (tDH) is specified as zero minimum hold time. RAM cell without the need for external write-pulse generation.
The timing logic uses the clock-high time as the write pulse,
DESELECT TIMING
and thus determines the minimum clock-high time, tWH.
In addition to writing to the RAM cell, the write data is fed
Because the outputs are latched, they will continue to drive
the output pins until a disable state is clocked through the to the output register by a multiplexer, so that write data is
device. Thedeselectedstateisachievedbyde-assertingchip available on the output pins in the appropriate time slot (i.e.
select (CS high) at rising edge of clock. This case occurs at after tWH + tDR). This function is sometimes called “Transpar-
❷below. Outputsthenattainthedisablestate(low)tACC later. ent Write,” and is useful for write-through cache applications.
Status of other inputs do not effect the disabling of the device Thus the input data sampled at ❸ is available on the output at
when chip select is de-asserted with the proper relation to the end of the cycle.
clock.
There are no restrictions on the order of read cycles and
write cycles.
5
IDT10496RL, IDT100496RL, IDT101496RL
HIGH SPEED BiCMOS ECL SELF-TIMED STATIC RAM 64K (16K x 4-BIT)
COMMERCIAL TEMPERATURE RANGE
10496RL15
AC ELECTRICAL CHARACTERISTICS (Over the AC Operating Range)
10496RL10
100496RL10
101496RL10
10496RL12
100496RL12
101496RL12
100496RL15
101496RL15
Test
Symbol
Read Cycle
tCYC
Parameter(1)
Condition
Min.
Max.
Min. Max.
Min.
Max.
Unit
Cycle Time
–
–
–
–
–
–
–
–
–
–
10
–
12
–
15
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(2)
tACC
Access Time from Clock High
Clock Low Pulse Width
–
5
10
–
–
5
12
–
–
6
15
–
tWL
tWH
Clock High Pulse Width
Setup Time for Chip Select
Setup Time for Address
Hold Time for Chip Select
Hold Time for Address
5
–
5
–
6
–
tSCS
tSA
1
–
1
–
1
–
1
–
1
–
1
–
tHCS
tHA
2.5
2.5
2
–
2.5
2.5
2
–
2.5
2.5
2
–
–
–
–
tDH
Data Hold from Clock Low
Data Ready from Clock Low
–
–
–
tDR
2
5
2
5
2
5
NOTES:
1. Input and Output reference level is 50% point of waveform.
2. Access time is the larger of tACC or tWH + tDR.
READ CYCLE TIMING DIAGRAM
tCYC
OUTPUT LATCH
OUTPUT LATCH
HELD
CLK
OPEN
tWH
tWL
CS
tSCS
tHCS
ADDR
tSA
tHA
DATAOUT
tDH
tDR
tDH
2771 drw 09
tACC
6
IDT10496RL, IDT100496RL, IDT101496RL
HIGH SPEED BiCMOS ECL SELF-TIMED STATIC RAM 64K (16K x 4-BIT)
COMMERCIAL TEMPERATURE RANGE
10496RL15
AC ELECTRICAL CHARACTERISTICS (Over the AC Operating Range)
10496RL10
100496RL10
101496RL10
10496RL12
100496RL12
101496RL12
100496RL15
101496RL15
Test
Symbol
Parameter(1)
Condition
Min.
Max.
Min. Max.
Min.
Max.
Unit
Write Cycle(2)
tSWE
tSD
–
–
–
–
1
–
1
–
1
–
ns
ns
ns
Setup Time for Write Enable
Setup Time for Data In
Hold Time for Write Enable
Hold Time for Data In
1
–
–
–
1
–
–
–
1
–
–
–
tHWE
tHD
2.5
2.5
2.5
2.5
2.5
2.5
ns
2771 tbl 12
NOTES:
1. Input and Output reference level is 50% point of waveform.
2. All Setup, Hold, and Access timing are the same as the Read Cycle with the addition of above requirements. Write Data appears on output pins after falling
edge of clock.
WRITE CYCLE TIMING DIAGRAM
tCYC
OUTPUT LATCH
OPEN
OUTPUT LATCH
HELD
CLK
tWH
tWL
CS
tSCS
tHCS
ADDR
tSA
tHA
DATAIN
WE
tSD
tHD
tSWE
tHWE
DATAOUT
tDH
tDR
tDH
2771 drw 10
tACC
7
IDT10496RL, IDT100496RL, IDT101496RL
HIGH SPEED BiCMOS ECL SELF-TIMED STATIC RAM 64K (16K x 4-BIT)
COMMERCIAL TEMPERATURE RANGE
CLOCK INPUT
The clock input circuit has been designed to accomodate both single-ended and differential mode operation. Differential mode
exhibits better common-mode noise rejection and is obtained by driving both true and complement clock lines with a differential driver,
as shown in Figure (a). Single-ended operation is achieved as either falling-edge-active or rising-edge-active, as shown in Figures (b)
and (c), respectively. VBB is designed to drive clock input only and is not intended to be used for any other purpose.
CLK
CLK
CLK
CLK
CLK
CLK
REF. VOLTAGE
GENERATOR
REF. VOLTAGE
GENERATOR
REF. VOLTAGE
GENERATOR
VBB
VBB
VBB
(a) Differential Mode
(b) Falling-Edge-Active
Single-Ended Mode
(c) Rising-Edge-Active
Single-Ended Mode
2771 drw 11
nnnnn
aa
nn
a
a
IDT
Device Type Architecture
Speed Package
Process/
Temp. Range
Blank
Commercial
C
U(1)
Y
Sidebraze DIP
Hi-Rel Die for MCMs and/or Hybrids
Plastic SOJ
10
12
15
Speed in Nanoseconds
RL
Registered Inputs, Latched Outputs
10496
64K (16K x 4-bits) BiCMOS ECL-10K
Self-Timed Static RAM
100496 64K (16K x 4-bits) BiCMOS ECL-100K
Self-Timed Static RAM
101496 64K (16K x 4-bits) BiCMOS ECL-101K
Self-Timed Static RAM
2771 drw 12
NOTE:
1. Please contact your IDT Sales Representative for more information on
specifications and availability of Die products.
8
相关型号：
©2020 ICPDF网 联系我们和版权申明