ICSSSTUB32872AHLFT [IDT]
D Flip-Flop, 32872 Series, 1-Func, Positive Edge Triggered, 28-Bit, True Output, PBGA96, 5.50 X 13.50 MM, ROHS COMPLIANT, MO-205, LFBGA-96;
| 型号： | ICSSSTUB32872AHLFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | D Flip-Flop, 32872 Series, 1-Func, Positive Edge Triggered, 28-Bit, True Output, PBGA96, 5.50 X 13.50 MM, ROHS COMPLIANT, MO-205, LFBGA-96 逻辑集成电路 触发器 |
| 文件： | 总18页 (文件大小：209K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICSSSTUB32872A
Integrated
Circuit
Advance Information
Systems,Inc.
28-Bit Registered Buffer for DDR2
Pin Configuration
Recommended Application:
1
2
3
4
5
6
•
DDR2 Memory Modules
A
B
C
D
E
F
•
Provides complete DDR DIMM solution with
ICS98ULPA877A, ICS97ULP877, or IDTCSPUA877A
•
Optimized for DDR2 400/533/667 JEDEC 4 Rank
VLP DIMMS
Product Features:
•
28-bit 1:1 registered buffer with parity check
functionality
Supports SSTL_18 JEDEC specification on data
inputs and outputs
Supports LVCMOS switching levels on RESET input
50% more dynamic driver strength than standard
SSTU32864
Low voltage operation
VDD = 1.7V to 1.9V
Available in 96 BGA package
G
H
J
•
K
L
•
•
M
N
P
R
T
•
•
96 Ball BGA
(Top View)
FunctionalityTruthTable
Inputs
Outputs
QCS
L
Dn,
DODTn,
DCKEn
QODT,
QCKE
RESET
DCS0
DCS1
CK
CK
Qn
↓
H
H
H
H
H
H
H
H
H
H
H
H
L
H
X
L
L
L
H
L
L
L
L
L
L
↑
H
↓
L or H
↓
L
↑
L or H
↑
Q0
Q0
Q0
L
L
H
L
L
L
H
H
H
L
↓
H
X
L
H
↑
L or H
↑
L
Q0
Q0
Q0
L or H
↓
L
L
H
H
H
H
H
H
H
L
L
H
H
X
L
H
↓
H
↑
Q0
Q0
Q0
L
L or H
L or H
H
H
H
Q0
Q0
Q0
↓
↓
H
H
L
H
↑
↑
H
X
L or H
L or H
Q0
Q0
X or
floating
X or
floating
X or
floating
X or
floating
X or
floating
L
L
L
L
1222F—3/13/07
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.
ICSSSTUB32872A
Advance Information
Ball Assignments
28 bit 1:1 Register
DCKE0 D0
DCKE1 D1
VDD
GND
VDD
QCKE0 QCKE1
VREF
GND
A
B
C
D
E
F
Q0
Q2
Q1
D2
DODT1 VDD
Q21
DODT0 PTYERR GND
GND
VDD
QODT0 QODT1
D3
D5
D4
D6
VDD
Q3
Q5
Q4
Q6
GND
GND
G
H
J
PAR_IN RESET VDD
VDD
NC
NC
CK
DCS0 GND
GND
QCS0
QCS1
CK
D7
DCS1
D8
VDD
VDD
NC
Q7
NC
Q8
GND
GND
K
L
D9
D10
D12
D14
D16
D18
D20
VDD
GND
VDD
GND
VDD
D21
VDD
GND
VDD
GND
VDD
VDD
Q9
Q10
Q12
Q14
Q16
Q18
Q20
D11
D13
D15
D17
D19
Q11
Q13
Q15
Q17
Q19
M
N
P
R
T
1
2
3
4
5
6
1222F—3/13/07
2
ICSSSTUB32872A
Advance Information
General Description
This 28-bit 1:1 registered buffer with parity is designed for 1.7V to 1.9V VDD operation.
All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are
LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized to drive the DDR2 DIMM load.
The ICSSSTUB32872A operates from a differential clock (CK and CK). Data are registered at the crossing of CK
going high, and CK going low.
The device supports low-power standby operation. When the reset input (RESET) is low, the differential
input receivers are disabled, and undriven (floating) data, clock and reference voltage (VREF) inputs are
allowed. In addition, when RESET is low all registers are reset, and all outputs except PTYERR are forced
low. The LVCMOS RESET input must always be held at a valid logic high or low level.
To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held
in the low state during power up.
In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with respect to CK
and CK. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the
register will be cleared and the outputs will be driven low quickly, relative to the time to disable the
differential input receivers. However, when coming out of reset, the register will become active quickly,
relative to the time to enable the differential input receivers. As long as the data inputs are low, and the
clock is stable during the time from the low-to-high transition of RESET until the input receivers are fully
enabled, the design of the ICSSSTUB32872A must ensure that the outputs will remain low, thus ensuring no
glitches on the output.
The device monitors both DCS0 and DCS1 inputs and will gate the Qn outputs from changing states when
both DCS0 and DCS1 are high. If either DCS0 or DCS1 input is low, the Qn outputs will function
normally. The RESET input has priority over the DCS0 and DCS1 control and will force the Qn outputs
low and the PTYERR output high.
The ICSSSTU32872A includes a parity checking function. The ICSSSTUB32872A accepts a parity bit from the
memory controller at its input pin PARIN, compares it with the data received on the D-inputs and indicates
whether a parity error has occurred on its open-drain PTYERR pin (active LOW).
Package options include 96-ball Thin Profile Fine Pitch BGA (TFBGA, MO-TBD).
Inputs
CK
Output
of inputs = H
(D0-D21)
RESET
DCS0
DCS1
CK
PARIN* PTYERR**
↓
↓
↓
H
H
H
H
H
H
H
H
H
H
Even
Odd
Even
Odd
Even
Odd
Even
Odd
X
L
L
H
L
L
H
H
L
L
L
L
L
H
H
H
↑
↑
↑
H
H
L
L
H
H
H
L
L
↓
↑
↓
↓
↑
↑
L
↓
↓
H
H
X
X
H
H
H
X
L
L
↑
↑
H
PTYERR
PTYERR
↓
H
X
↑
0
L or H
L or H
X
0
X or
floating
X or
floating
X or
floating
X or
floating
X or
floating
L
X or floating
H
* PARIN arrives one clock cycle after the data to which it applies.
** This transition assumes PTYERR is high at the crossing of CK going high and CK going low. If PTYERR
is low, it stays latched low for two clock cycles or until RESET is driven low.
1222F—3/13/07
3
ICSSSTUB32872A
Advance Information
Ball Assignment
Signal Group
Signal Name
Type
Description
Ungated inputs DCKE0, DCKE1, SSTL_18
DODT0, DODT1
DRAM function pins not associated with Chip Select.
DRAM inputs, re-driven only when Chip Select is LOW.
Chip Select
gated inputs
D0 ... D21
SSTL_18
Chip Select
inputs
DCS0, DCS1
SSTL_18
DRAM Chip Select signals. These pins initiate DRAM
address/command decodes, and as such at least one will be
low when a valid address/command is present. The register
can be programmed to re-drive all D-inputs when at least
one Chip Slect input is LOW.
Re-driven
outputs
Q0...Q21,
QCS
0-1,
SSTL_18
Outputs of the register, valid after the specified clock count
and immediately following a rising edge of the clock.
QCKE0-1,
QODT0-1
Parity input
PARIN
SSTL_18
Input parity is received on pin PARIN and should maintain
odd parity across the D0...D20 inputs, at the rising edge of the
clock.
Parity error
output
PTYERR
Open drain
When LOW, this output indicates that a parity error was
identified associated with the address and/or command inputs.
PTYERR will be active for two clock cycles, and delayed by
an additional clock cycle for compatibility with final parity
out timing on the industry-standard DDR-II register with
parity (in JEDEC definition).
Differential master clock input pair to the register. The
register operation is triggered by a rising edge on the positive
clock input (CK).
Clock inputs
CK, CK
SSTL_18
Miscellaneous
inputs
Asynchronous reset input. When LOW, it causes a reset of the
internal latches, thereby forcing the outputs LOW. RESET
also resets the PTYERR signal.
RESET
VREF
1.8 V
LVCMOS
0.9 V nominal Input reference voltage for the SSTL_18 inputs. Two pins
(internally tied together) are used for increased reliability.
1222F—3/13/07
4
ICSSSTUB32872A
Advance Information
Block Diagram
(CS ACTIVE)
VREF
PARITY
GENERATOR
AND
D
R
Q
PARIN
22
PTYERR
Q0
CHECKER
D
R
Q
Q
Q
Q
Q
Q
D0
Q21
D
R
D21
DCS0
D
R
QCS0
QCS1
DCS1
D
R
2
2
2
2
DCKE0,
DCKE1
QCKE0,
QCKE1
D
R
DODT0,
DODT1
QODT0,
QODT1
D
R
RESET
CK
CK
1222F—3/13/07
5
ICSSSTUB32872A
Advance Information
Parity Functionality Block Diagram
21
21
Qn
Dn
D Q
D
D
D
PTYERR
LATCHING AND
RESET FUNCTION
see Note (1)
(1) This function holds the error for two
cycles. See functional description and
timing diagram.
PARIN
CLOCK
002aaa417
1222F—3/13/07
6
ICSSSTUB32872A
Advance Information
RegisterTiming
RESET
DCSn
n
n + 1
n + 2
n + 3
n + 4
CK
CK
t
t
t
ACT
su
h
(1)
Dn
t
, t
PDM PDMSS
CK to Q
Qn
t
t
su
h
PARIN
t
t
, t
PHL
CK to PTYERR
PHL PLH
CK to PTYERR
PTYERR
H or L
H, L, or X
—
Figure 4 RESET switches from L to H
(1) After RESET is switched from LOW to HIGH, all data and PARIN input signals must be set and held LOW for a
minimum time of tACT (max) to avoid false error.
1222F—3/13/07
7
ICSSSTUB32872A
Advance Information
RegisterTiming
RESET
DCSn
n
n + 1
n + 2
n + 3
n + 4
CK
CK
t
t
h
su
(1)
Dn
t
, t
PDM PDMSS
CK to Q
Qn
t
su
t
h
PARIN
t
, t
PHL PLH
CK to PTYERR
PTYERR
002aaa984
Output signal is dependent on the piorr unknown event
Unknown input event
H or L
Figure 5 — RESET being held HIGH
1222F—3/13/07
8
ICSSSTUB32872A
Advance Information
RegisterTiming
RESET
DCSn
t
INACT
(1)
CK
(1)
CK
(1)
Dn
t
RPHL
RESET to Q
Qn
(1)
PARIN
t
RPLH
RESET to PTYERR
PTYERR
H or L
H, L, or X
Figure 6 — RESET switches from H to L
(1) After Reset is switched from HIGH to LOW, all data and clock input signals must be set and held at valid logic
levels (not floating) for a minimum time of t (max)
INACT
1222F—3/13/07
9
ICSSSTUB32872A
Advance Information
Absolute Maximum Ratings
Notes:
Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 2.5V
Input Voltage1, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD +2.5V
Output Voltage1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDDQ + 0.5V
Input Clamp Current . . . . . . . . . . . . . . . . . . . . 50 mA
Output Clamp Current . . . . . . . . . . . . . . . . . . . 50mA
1. The input and output negative voltage
ratings may be excluded if the input
andoutputclampratingsareobserved.
2. This value is limited to 2.5V maximum.
3. The package thermal impedance is
calculated in accordance with
JESD 51.
Continuous Output Current. . . . . . . . . . . . . . . 50mA
VDD or GND Current/Pin . . . . . . . . . . . . . . . . 100mA
Package Thermal Impedance3 . . . . . . . . . . . . . . . 36°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Recommended Operating Conditions
DESCRIPTION
PARAMETER
VDDQ
VREF
VTT
MIN
1.7
TYP
1.8
MAX
1.9
UNITS
I/O Supply Voltage
Reference Voltage
Termination Voltage
0.49 x VDD 0.5 x VDD
0.51 x VDD
VREF + 0.04
VDDQ
VREF - 0.04
0
VREF
VI
Input Voltage
VIH (DC)
VIH (AC)
VIL (DC)
VIL (AC)
VIH
DC Input High Voltage
AC Input High Voltage
DC Input Low Voltage
AC Input Low Voltage
Input High Voltage Level
Input Low Voltage Level
Common mode Input Range
Differential Input Voltage
High-Level Output Current
Low-Level Output Current
VREF + 0.125
VREF + 0.250
Data Inputs
V
VREF - 0.125
VREF - 0.250
0.65 x VDDQ
RESET
CK, CK
VIL
0.35 x VDDQ
1.125
VICR
0.675
0.600
VID
IOH
-8
8
mA
°C
IOL
Operating Free-Air Temperature
TA
0
70
1Guaranteed by design, not 100% tested in production.
Note: Rst and Cn inputs must be helf at valid logic levels (not floating) to ensure proper device operation. The
differential inputs must not be floating unless Rst is low.
1222F—3/13/07
10
ICSSSTUB32872A
Advance Information
Electrical Characteristics - DC
TA = 0 - 70°C; VDD = 2.5 +/-0.2V, VDDQ=2.5 +/-0.2V; (unless otherwise stated)
CONDITIONS
SYMBOL
PARAMETERS
VDDQ
1.7V
1.7V
1.9V
MIN
1.2
TYP MAX
UNITS
V
VOH
VOL
II
IOH = -8mA
IOL = 8mA
0.5
5
200
All Inputs
Standby (Static)
VI = VDD or GND
RESET = GND
VI = VIH(AC) or VIL(AC)
RESET = VDD
µA
µA
IDD
,
1.9V
1.8V
Operating (Static)
mA
150
RESET = VDD
,
Dynamic operating
(clock only)
µA/clock
MHz
VI = VIH(AC) or VIL(AC)
,
TBD
CLK and CLK switching
50% duty cycle.
IO = 0
RESET = VDD
,
IDDD
VI = VIH(AC) or VIL (AC)
,
Dynamic Operating
(per each data
input)
CLK and CLK switching
50% duty cycle. One data
input switching at half
clock frequency, 50%
duty cycle
µA/ clock
MHz/data
TBD
Data Inputs
CLK and CLK
RESET
VI = VREF 350mV
2.5
2
5
3.8
pF
pF
Ci
V
ICR = 1.25V, VI(PP) = 360mV
VI = VDDQ or GND
4.5
Notes:
1 - Guaranteed by design, not 100% tested in production.
Output Buffer Characteristics
Output edge rates over recommended operating free-air temperature range (See figure 7)
V
MIN
1
DD = 1.8V ꢀ.1V
PARAMETER
UNIT
MAX
4
4
1
dV/dt_r
dV/dt_f
V/ns
V/ns
V/ns
1
dV/dt_Δ1
1. Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate)
1222F—3/13/07
11
ICSSSTUB32872A
Advance Information
Timing Requirements
(over recommended operating free-air temperature range, unless otherwise noted)
VDD = 1.8V ꢀ.1V
SYMBOL
PARAMETERS
UNITS
MIN
MAX
fclock
tW
Clock frequency
410
MHz
ns
Pulse duration
1
tACT
Differential inputs active time
10
15
ns
tINACT
tS
Differential inputs inactive time
ns
Data before CK↑,
↓
0.6
0.7
CK
Setup time
ns
,
before CK↑,
DCS0 DSC1
↓, high
CK CSR
, DODT, DCKE and Dn
DCS
after CK↑,
Hold time
Hold time
0.6
0.5
ns
ns
↓
CK
tH
PAR_IN after CK↑,
↓
CK
1 - Guaranteed by design, not 100% tested in production.
2 - For data signal input slew rate of 1V/ns.
Notes:
3 - For data signal input slew rate of 0.5V/ns and < 1V/ns.
4 - CK/
signal input slew rate of 1V/ns.
CK
Switching Characteristics
(over recommended operating free-air temperature range, unless otherwise noted)
Symbol
Parameter
Measurement Conditions
MIN
MAX Units
fmax Max input clock frequency
410
MHz
Propagation delay, single
bit switching
Low to High propagation
delay
High to low propagation
delay
Propagation delay
simultaneous switching
High to low propagation
delay
Low to High propagation
delay
tPDM
CK↑ and
CK↑ and
CK↑ and
↓ to Qn
1.25
1.2
1.9
3
ns
ns
ns
ns
ns
ns
CK
CK
CK
tLH
↓ to
PTYERR
tHL
0.9
3
tPDMSS
↓ to Qn
2
tPHL
↓ to Qn↓
3
RESET
tPLH
T↓ to
RESE
↑
3
PTYERR
1. Guaranteed by design, not 100% tested in production.
1222F—3/13/07
12
ICSSSTUB32872A
Advance Information
V
DD
DUT
RL = 1000Ω
TL=350ps, 50Ω
TL=50Ω
CK
CK
Out
Test Point
CK Inputs
CL = 30 pF
(see Note 1)
RL = 1000Ω
Test Point
RL = 100Ω
LOAD CIRCUIT
Test Point
VCMOS
VDD
0 V
tact
90%
VID
RST
Input
V
DD/2
VDD/2
CK
CK
VICR
VICR
tinact
tPLH
tPHL
IDD
(see
Note 2)
10%
VOH
VOL
Output
VTT
VTT
VOLTAGE AND CURRENT WAVEFORMS
INPUTS ACTIVE AND INACTIVE TIMES
VOLTAGE WAVEFORMS – PROPAGATION DELAY TIMES
VID
tw
Inpu t
VICR
VICR
VOLTAGE WAVEFORMS – PULSE DURATION
VID
LVCMOS
VIH
VIL
VDD/2
RST
Input
CK
VICR
tRPHL
CK
VOH
VOL
th
tsu
Output
VTT
VIH
VIL
Inpu t
VREF
VREF
VOLTAGE WAVEFORMS – PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS – SETUP AND HOLD TIMES
—
Figure 6 Parameter Measurement Information (VDD = 1.8V 0.1V)
Notes: 1. CL incluces probe and jig capacitance.
2. IDD tested with clock and data inputs held at VDD or GND, and Io = 0mA.
3. All input pulses are supplied by generators having the following chareacteristics: PRR ≤10 MHz,
Zo=50Ω, input slew rate = 1 V/ns 20% (unless otherwise specified).
4. The outputs are measured one at a time with one transition per measurement.
5. VREF = VDD/2
6. VIH = VREF + 250 mV (ac voltage levels) for differential inputs. VIH = VDD for LVCMOS input.
7. VIL = VREF - 250 mV (ac voltage levels) for differential inputs. VIL = GND for LVCMOS input.
8. VID = 600 mV
9. tPLH and tPHL are the same as tPDM
.
1222F—3/13/07
13
ICSSSTUB32872A
Advance Information
VDD
DUT
RL = 50Ω
Test Point
Out
CL = 10 pF
(see Note 1)
LOAD CIRCUIT – HIGH-TO-LOW SLEW-RATE MEASUREMENT
Output
VOH
80%
20%
dt_f
VOL
dv_f
VOLTAGE WAVEFORMS – HIGH-TO-LOW SLEW-RATE MEASUREMENT
DUT
Out
Test Point
CL = 10 pF
(see Note 1)
RL = 50Ω
LOAD CIRCUIT – LOW-TO-HIGH SLEW-RATE MEASUREMENT
dt_r
dv_r
VOH
80%
20%
Output
VOL
VOLTAGE WAVEFORMS – LOW-TO-HIGH SLEW-RATE MEASUREMENT
Figure 7 — Output Slew-Rate Measurement Information (V = 1.8V 0.1V)
DD
Notes: 1. CL includes probe and jig capacitance.
2. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10MHz, ZO
50Ω, input slew rate = 1 V/ns 20% (unless otherwise specified).
=
1222F—3/13/07
14
ICSSSTUB32872A
Advance Information
3 Test circuits and switching waveforms (cont’d)
3.3 Error output load circuit and voltage measurement information (V = 1.8 V 0.1 V)
DD
All input pulses are supplied by generators having the following characteristics: PRR 10 MHz;
Z = 50 ; input slew rate = 1 V/ns 20%, unless otherwise specified.
Ω
o
V
DD
DUT
R
= 1KΩ
L
Out
Test Point
C
= 1ꢀ pF
L
(see Note 1)
LOAD CIRCUIT – HIGH-TO-LOW SLEW-RATE MEASUREMENT
(1) C includes probe and jig capacitance.
L
Figure 28 — Load circuit, error output measurements
LVCMOS
RST
V
CC
V
/2
CC
Input
ꢀ V
V
t
PLH
OH
Output
Waveform 2
ꢀ.15 V
_ _ _ _ _ _ _ _ _ _ _
ꢀ V
Voltage waveforms, open-drain output low-to-high transition time with respect to reset input
Figure 29 —
V
I
(PP)
Timing
Inputs
V
V
ICR
ICR
t
PHL
_ _ _ _ _ _ _ _ _ _ _
V
Output
Waveform 1
V
CC
OL
/2
CC
V
Figure 30
—
Voltage waveforms, open-drain output high-to-low transition time with respect to clock inputs
V
I
(PP)
Timing
Inputs
V
ICR
V
ICR
t
PHL
V
ꢀ
OH
V
Output
Waveform 2
ꢀ.15 V
—
Figure 31
Voltage waveforms, open-drain output low-to-high transition time with respect to clock inputs
1222F—3/13/07
15
ICSSSTUB32872A
Advance Information
3 Test circuits and switching waveforms (cont’d)
3.4 Partial-parity-out load circuit and voltage measurement information (V = 1.8 V 0.1 V)
DD
All input pulses are supplied by generators having the following characteristics: PRR 10 MHz;
Ω
Z = 50 ; input slew rate = 1 V/ns 20%, unless otherwise specified.
o
DUT
Out
Test Point
5 pF
C
=
L
R
L
=
1 kΩ
(see Note A)
(1) C includes probe and jig capacitance.
L
Figure 32 — Partial-parity-out load circuit,
CK
V
V
V
ICR
ICR
i(p-p)
V
CK
t
t
PHL
PLH
OH
V
OUTPUT
TT
V
OL
002aaa375
V
= V /2
DD
TT
t
and t
are the same as t
.
PD
PLH
PHL
V
= 600 mV
I(PP)
Figure 33 — Partial-parity-out voltage waveforms; propagation delay times with respect to clock inputs
LVCMOS RST
V
IH
INPUT
V
/2
DD
V
V
V
IL
t
PHL
OH
OL
OUTPUT
V
TT
002aaa376
V
= V /2
DD
TT
t
and t
are the same as t
.
PD
PLH
PHL
V
V
= V
+ 250 mV (AC voltage levels) for differential inputs. V = V for LVCMOS inputs.
IH DD
IH
IL
REF
REF
= V
- 250 mV (AC voltage levels) for differential inputs. V = V for LVCMOS inputs.
IL DD
Figure 34 — Partial-parity-out voltage waveforms; propagation delay times with respect to reset input
1222F—3/13/07
16
ICSSSTUB32872A
Advance Information
C
Seating
Plane
Numeric Designations
for Horizontal Grid
A1
b
REF
T
3 2 1
4
A
B
C
D
Alpha Designations
for Vertical Grid
(Letters I, O, Q & S
not used)
D
d TYP
D1
- e - TYP
TOP VIEW
E
c
REF
TYP
- e -
h
TYP
E1
0.12
C
ALL DIMENSIONS IN MILLIMETERS
----- BALL GRID -----
Max.
REF. DIMENSIONS
D
E
T
e
HORIZ
VERT
TOTAL
d
h
b
c
Min/Max
Min/Max
Min/Max
13.50 Bsc
11.50 Bsc
5.50 Bsc
5.00 Bsc
1.20/1.40
1.00/1.20
0.80 Bsc
0.65 Bsc
6
6
16
16
96
96
0.40/0.50
0.35/0.45
0.25/0.41
0.25/0.35
0.75
0.875
0.75
0.875
Note: Ball grid total indicates maximum ball count for package. Lesser quantity may be used.
* Source Ref.: JEDEC Publication 95, MO-205
10-0055C
Ordering Information
ICSSSTUB32872Az(LF)T
Example:
ICS XXXX y z (LF) T
Designation for tape and reel packaging
Lead Free, RoHS Compliant (Optional)
Package Type
H = LFBGA (reduced size: 5.5 x 13.50)
HM = TFBGA (reduced size: 5.0 x 11.50)
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
1222F—3/13/07
17
ICSSSTUB32872A
Advance Information
Revision History
Rev.
Issue Date Description
Page #
A
5/2/2006 Initial Release.
-
Electrical table, Ci Data input max changed from 3.5 to 5.0, CLK max
changed from 3 to 3.8
Timing table, ts Data before CK changed from 0.5 to 0.7, th DCS after CK
changed from 0.5 to 0.6
B
C
12/12/2006
11
12
12/20/2006
12/21/2006
3/6/2007
Applications, removed "800"; Electrical table, Idd Operating max changed
from 80 to 150, Ci RESET typ changed from 2.5 to 4.5; Timing table, th Hold
Time, changed Q to Dn, Switching table, changed tpdm max from 1.7 to 1.9,
thl min from 1 to 0.9, and tpdmss max from 1.9 to 2.
D
1, 11, 12
12
Timing table, ts Data before CK changed from 0.7 to 0.6; Switching table,
fixed typos.
Page 1, Recc. List, changed 3rd bullet to "Provides complete DDR DIMM
E
F
3/13/2007 solution with ICS98ULPA877A, ICS97ULP877, or IDTCSPUA877A"; page 11, 1, 11
fixed typos.
1222F—3/13/07
18
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ICSSSTUB32872AHT
D Flip-Flop, 32872 Series, 1-Func, Positive Edge Triggered, 28-Bit, True Output, PBGA96, 5.50 X 13.50 MM, MO-205, LFBGA-96
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