ICS9112M-16 [IDT]
Low Skew Clock Driver, 91 Series, 5 True Output(s), 0 Inverted Output(s), PDSO8, 0.150 INCH, SOIC-8;
| 型号： | ICS9112M-16 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, 91 Series, 5 True Output(s), 0 Inverted Output(s), PDSO8, 0.150 INCH, SOIC-8 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总6页 (文件大小：148K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS9112-16
Integrated
Circuit
Systems, Inc.
Preliminary Product Preview
Low Skew Output Buffer
General Description
Features
The ICS9112-16 is a high performance, low skew, low jitter
clock driver. It uses a phase lock loop (PLL) technology to
align, in both phase and frequency, the REF input with the
CLKOUT signal. It is designed to distribute high speed
clocks in PC systems operating at speeds from 25 to
133 MHz.
•
•
•
Zero input - output delay
Frequency range 25 - 133 MHz (3.3V)
High loop filter bandwidth ideal for Spread
Spectrum applications.
Less than 200 ps Jitter between outputs
Skew controlled outputs
Skew less than 250 ps between outputs
Available in 8 pin 150 mil SOIC package
3.3V ±10% operation
•
•
•
•
•
ICS9112-16 is a zero delay buffer that provides
synchronization between the input and output. The
synchronization is established via CLKOUT feed back to the
input of the PLL. Since the skew between the input and
output is less than +/- 350 pS, the part acts as a zero delay
buffer.
The ICS9112-16 comes in an eight pin 150 mil SOIC package.
It has five output clocks. In the absence of REF input, will be
in the power down mode. In this mode, the PLL is turned off
and the output buffers are pulled low. Power down mode
provides the lowest power consumption for a standby
condition.
Block Diagram
Pin Configuration
8 pin SOIC
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.
9112-16RevD4/14/99
ICS9112-16
Preliminary Product Preview
Pin Descriptions
PIN NUMBER
PIN NAME
REF2
TYPE
IN
DESCRIPTION
1
2
3
4
5
6
7
8
Input reference frequency.
Buffered clock output
Buffered clock output
Ground
CLK23
CLK13
GND
OUT
OUT
PWR
OUT
PWR
OUT
OUT
CLK33
Buffered clock output
Power Supply (3.3V)
Buffered clock output
VDD
CLK43
CLKOUT3
Buffered clock output. Internal feedback on this pin
Notes:
1. Guaranteed by design and characterization. Not subject to 100% test.
2. Weak pull-down
3. Weak pull-down on all outputs
2
ICS9112-16
Preliminary Product Preview
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only and functional operation of the device at these or any other conditions above those listed
in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Electrical Characteristics at 3.3V
VDD = 3.0 – 3.6V, TA = 0 –70°C unless otherwise stated
DC Characteristics
PARAMETER
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Output Low Voltage1
Output High Voltage1
SYMBOL
VIL
TEST CONDITIONS
MIN
2.0
TYP
MAX
0.8
UNITS
V
VIH
IIL
V
VIN=0V
19
0.10
0.25
2.9
50.0
100.0
0.4
µA
µA
V
IIH
VIN=VDD
VOL
VOH
IDD
IOL = 8mA
IOH = 8mA
2.4
V
Power Down Supply
Current
REF = 0 MHz
0.3
50.0
40.0
µA
IDD
Unloaded oututs at 66.66 MHz SEL
inputs at VDD or GND
Supply Current
30.0
mA
Notes:
1. Guaranteed by design and characterization. Not subject to 100% test.
2. All Skew specifications are mesured with a 50Ω transmission line, load teminated with 50Ω to 1.4V.
3. Duty cycle measured at 1.4V.
4. Skew measured at 1.4V on rising edges. Loading must be equal on outputs.
3
ICS9112-16
Preliminary Product Preview
Switching Characteristics (3.3V Continued)
PARAMETER
Output period
SYMBOL
t1
CONDITION
With CL=30pF
MIN
TYP
MAX
UNITS
40.00
(25)
10
(100)
ns
(MHz)
40.00
(25)
10
(100)
ns
(MHz)
Input period
t1
With CL=30pF
Duty Cycle1
Duty Cycle1
Dt1
Dt2
Measured at 1.4V; CL=30pF
40.0
45
50
50
60
55
%
%
Measured at VDD/2 Fout <66.6MHz
Measured between 0.8V and 2.0V:
CL=30pF
Rise Time1
Fall Time1
tr1
tf1
1.2
1.2
1.5
1.5
ns
ns
Measured between 2.0V and 0.8V;
CL=30pF
Delay, REF Rising
Edge to CLKOUT
Rising Edge1, 2
Dr1
Measured at 1.4V
0
±350
ps
Output to Output
Skew1
Tskew
Tdsk-Tdsk
Tcyc-Tcyc
tLOCK
Tjabs
All outputs equally loaded, CL=20pF
250
700
200
1.0
ps
ps
ps
ms
ps
ps
Device to Device
Skew1
Measured at VDD/2 on the CLKOUT
pins of devices
0
Measured at 66.66 MHz, loaded
outputs
Cycle to Cycle Jitter1
PLL Lock Time1
Stable power supply, valid clock
presented on REF pin
@ 10,000 cycles
CL=30pF
Jitter; Absolute Jitter1
Jitter; 1 - Sigma1
-100
70
14
100
30
@ 10,000 cycles
CL=30pF
Tj1s
Notes:
1. Guaranteed by design and characterization. Not subject to 100% test.
2. REF input has a threshold voltage of 1.4V
3. All parameters expected with loaded outputs
4
ICS9112-16
Preliminary Product Preview
Output to Output Skew
The skew between CLKOUT and the CLK(1-4) outputs is not dynamically adjusted by the PLL. Since CLKOUT is one of the
inputs to the PLL, zero phase difference is maintained from REF to CLKOUT. If all outputs are equally loaded, zero phase
difference will maintained from REF to all outputs.
If applications requiring zero output-output skew, all the outputs must equally loaded.
If the CLK(1-4) outputs are less loaded than CLKOUT, CLK(1-4) outputs will lead it; and if the CLK(1-4) is more loaded than
CLKOUT, CLK(1-4) will lag the CLKOUT.
Since the CLKOUT and the CLK(1-4) outputs are identical, they all start at the same time, but different loads cause them to
have different rise times and different times crossing the measurement thresholds.
REF input and
all outputs
loaded Equally
REF input and CLK(1-4)
outputs loaded equally, with
CLKOUT loaded More.
REF input and CLK(1_4)
outputs loaded equally, with
CLKOUT loaded Less.
Timing diagrams with different loading configurations
5
ICS9112-16
Preliminary Product Preview
SOIC Package
Ordering Information
ICS9112M-16
Example:
ICS XXXX Y M - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
M=SOIC
Revision Designator
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.
6
相关型号：
ICS9112M-16-T
Low Skew Clock Driver, 5 True Output(s), 0 Inverted Output(s), PDSO8, 0.150 INCH, SOIC-8
IDT
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