ICS87973CYILF [IDT]
PLL Based Clock Driver, 12 True Output(s), 0 Inverted Output(s), PQFP52, 10 X 10 MM, 1.40 MM HEIGHT, LQFP-52;
| 型号： | ICS87973CYILF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PLL Based Clock Driver, 12 True Output(s), 0 Inverted Output(s), PQFP52, 10 X 10 MM, 1.40 MM HEIGHT, LQFP-52 驱动 逻辑集成电路 |
| 文件： | 总15页 (文件大小：141K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS87973I
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-12
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS87973I is a LVCMOS clock generator
• Fully integrated PLL
,&6
and a member of the HiPerClockS™ family of High
• 14 LVCMOS outputs; (12) clock, (1) feedback, (1) sync
• Selectable LVCMOS or LVPECL clock inputs
HiPerClockS™
Performance Clock Solutions from ICS. The
ICS87973I has three selectable inputs and pro-
vides 14 LVCMOS outputs.
• CLK0, CLK1 can accept the following input levels:
LVCMOS or LVTTL
The ICS87973I is a highly flexible device. The three selectable
inputs (1 differential and 2 single ended inputs) are often used
in systems requiring redundant clock sources. Up to three dif-
ferent output frequencies can be generated among the three
output banks.
• PCLK, nPCLK pair supports the following input types:
LVPECL, CML, SSTL
• Output frequency: 125MHz
• Output skew: 550ps (maximum)
• Cycle-to-cycle jitter: ±100ps (typical)
• PLL reference zero delay: TBD
The three output banks and feedback output each have their
own output dividers which allows the device to generate a
multitude of different bank frequency ratios and output-to-input
frequency ratios. In addition, 2 outputs in Bank C (QC2, QC3)
can be selected to be inverting or non-inverting. In all, there
are 1024 possible configurations. The output frequency range is
8.33MHz - 125MHz. The input frequency range is 5MHz - 120MHz.
• Full 3.3V supply voltage
• -40°C to 85°C ambient operating temperature
• Pin compatible with MPC973
The ICS87973I also has a QSYNC output which can by used
for system synchronization purposes. It monitors Bank A and
Bank C outputs and goes low one period prior to coincident
rising edges of Bank A and Bank C clocks. QSYNC then goes
high again when the coincident rising edges of Bank A and
Bank C occur. This feature is used primarily in applications where
Bank A and Bank C are running at different frequencies, and is
particularly useful when they are running at non-integer mul-
tiples of one another.
• Compatible with PowerPC™and Pentium™Microprocessors
PIN ASSIGNMENT
39 38 37 36 35 34 33 32 31 30 29 28 27
Example Applications:
FSEL_B1
FSEL_B0
FSEL_A1
FSEL_A0
QA3
40
41
42
43
44
45
46
47
48
49
50
51
52
26
25
24
23
22
21
20
19
18
17
16
15
14
FSEL_FB1
QSYNC
GNDO
QC0
1. System Clock generator: Use a 16.66MHz reference
clock to generate eight 33.33MHz copies for PCI and
four 100MHz copies for the CPU or PCI-X.
VDDO
2. Line Card Multiplier: Multiply differential 62.5MHz from
a back plane to single-ended 125MHz for the line Card
ASICs and Gigabit Ethernet Serdes.
VDDO
QC1
QA2
FSEL_C0
FSEL_C1
QC2
ICS87973I
GNDO
QA1
3. Zero Delay buffer for Synchronous memory: Fan out
up to twelve 100MHz copies from a memory controller
reference clock to the memory chips on a memory module
with zero delay.
VDDO
VDDO
QA0
QC3
GNDO
VCO_SEL
GNDO
INV_CLK
1
2
3
4
5
6
7
8
9 10 11 12 13
52-Lead LQFP
10mm x 10mm x 1.4mm package body
Y package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
87973CYI
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REV. B JULY 29, 2002
1
PRELIMINARY
ICS87973I
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-12
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
BLOCK DIAGRAM
VCO_SEL
PLL_SEL
REF_SEL
PCLK
1
0
nPCLK
SYNC
FRZ
D
Q
QA0
QA1
QA2
QA3
CLK0
CLK1
0
1
0
1
SYNC
FRZ
PHASE
DETECTOR
VCO
SYNC
FRZ
LPF
CLK_SEL
EXT_FB
SYNC
FRZ
SYNC
FRZ
D
Q
QB0
QB1
QB2
QB3
SYNC
FRZ
SYNC
FRZ
SYNC
FRZ
FSEL_FB2
nMR/OE
D
D
D
Q
Q
Q
QC0
QC1
QC2
QC3
QFB
SYNC
FRZ
÷4, ÷6, ÷8, ÷12
÷4, ÷6, ÷8, ÷10
÷2, ÷4, ÷6, ÷8
SYNC
FRZ
SYNC
FRZ
POWER-ON
RESET
2
2
2
3
0
1
FSEL_A0:1
÷2
FSEL_B0:1
FSEL_C0:1
FSEL_FB0:2
SYNC PULSE
SYNC
SYNC
FRZ
FRZ
D
Q
QSYNC
DATA GENERATOR
FRZ_CLK
OUTPUT DISABLE
CIRCUITRY
12
FRZ_DATA
INV_CLK
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REV. B JULY 29, 2002
2
PRELIMINARY
ICS87973I
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-12
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
SIMPLIFIED BLOCK DIAGRAM
nMR/OE
FSEL_A[0:1]
2
PCLK
1
0
nPCLK
CLK0
FSEL_
A1 A0 QAx
SYNC
FRZ
QA0
QA1
QA2
QA3
0
1
PLL
0
0
1
1
0
1
0
1
÷4
÷6
÷8
CLK1
SYNC
FRZ
VCO RANGE
200MHz - 480MHz
CLK_SEL
REF_SEL
SYNC
FRZ
0
1
÷12
SYNC
FRZ
÷2
÷1
0
1
EXT_FB
FSEL_B[0:1]
2
SYNC
FRZ
FSEL_
B1 B0 QBx
QB0
QB1
QB2
QB3
VCO_SEL
PLL_SEL
0
0
1
1
0
1
0
1
÷4
÷6
÷8
SYNC
FRZ
SYNC
FRZ
÷10
SYNC
FRZ
FSEL_C[0:1]
2
FSEL_
C1 C0 QCx
QC0
QC1
QC2
QC3
0
0
1
1
0
1
0
1
÷2
÷4
÷6
÷8
SYNC
FRZ
SYNC
FRZ
0
1
SYNC
FRZ
INV_CLK
FSEL_FB[0:2]
3
FSEL_
FB2 FB1 FB0 QFB
QFB
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
÷4
÷6
÷8
÷10
÷8
÷12
÷16
÷20
FRZ_CLK
FRZ_DATA
O
UTPUT
D
ISABLE
SYNC
FRZ
CIRCUITRY
QSYNC
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REV. B JULY 29, 2002
3
PRELIMINARY
ICS87973I
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-12
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
GNDI
Power
Input
Power supply ground.
Master reset and output enable. When HIGH, enables the outputs. When
LOW, resets the outputs to tristate and resets output divide circuitry.
Enables and disables all outputs. LVCMOS / LVTTL interface levels.
2
nMR/OE
Pullup
3
4
FRZ_CLK
Input
Input
Pullup
Pullup
Clock input for freeze circuitry.
FRZ_DATA
FSEL_FB2,
Configuration data input for freeze circuitry.
5, 26, 27
FSEL_FB1, Input
FSEL_FB0
Pullup
Select pins control Feedback Divide value.
Selects between the PLL and reference clocks as the input to the output
dividers. When HIGH, selects PLL. When LOW, bypasses the PLL.
LVCMOS / LVTTL interface levels.
Selects between CLK0 and LVPECL clock inputs. When HIGH, selects
LVPECL. When LOW, selects CLK0. LVCMOS / LVTTL interface levels.
Clock select input. Selects between CLK0 or CLK1 as phase detector
reference. When LOW, selects CLK0. When HIGH, selects CLK1.
LVCMOS / LVTTL interface levels.
6
7
PLL_SEL
REF_SEL
CLK_SEL
Input
Input
Input
Input
Pullup
Pullup
Pullup
Pullup
8
CLK0,
CLK1
9, 10
Reference clock inputs. LVCMOS / LVTTL interface levels.
11
12
13
14
PCLK
nPCLK
VDDA
Input Pulldown Non-inverting differential LVPECL clock input.
Input
Power
Input
Pullup
Inverting differential LVPECL clock input.
Analog supply pin.
INV_CLK
Pullup
Inverted clock select for QC2 and QC3 outputs.
15, 24, 30,
35, 39, 47, 51
16, 18,
21, 23
17, 22, 33,
37, 45, 49
GNDO
Power
Output
Power
Power supply ground.
QC3, QC2,
QC1, QC0
Bank C clock outputs. 7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
VDDO
Output supply pins.
25
28
29
31
QSYNC
VDD
Output
Power
Output
Input
See Figure 1, Timing Diagrams.
Positive supply pins.
QFB
Feedback clock output.
EXT_FB
Pullup
Extended feedback. LVCMOS / LVTTL interface levels.
32, 34,
36, 38
QB3, QB2,
QB1, QB0
FSEL_B1,
FSEL_B0
FSEL_A1,
FSEL_A0
QA3, QA2,
QA1, QA0
Bank B clock outputs.7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Output
Input
40, 41
42, 43
Pullup
Pullup
Selects pins for Bank B outputs.
Selects pins for Bank A outputs.
Input
44, 46,
48, 50
Bank A clock outputs.7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
Selects VCO. When HIGH, selects VCO ÷ 1.
When LOW, selects VCO ÷ 2. LVCMOS / LVTTL interface levels.
Output
Input
52
VCO_SEL
Pullup
NOTE: Pullup and Pulldown refer to internal input resistors. See table 2, Pin Characteristics, for typical values.
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REV. B JULY 29, 2002
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PRELIMINARY
ICS87973I
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-12
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum Typical Maximum Units
Input Capacitance
Input Pullup Resistor
4
pF
RPULLUP
51
25
7
KΩ
Power Dissipation Capacitance
(per output)
CPD
V
DDA, VDD, VDDO = 3.465V
pF
ROUT
Output Impedance
Ω
TABLE 3A. OUTPUT BANK CONFIGURATION SELECT FUNCTION TABLE
Inputs
Outputs
QA
Inputs
Outputs
QB
Inputs
Outputs
QC
÷2
FSEL_A1 FSEL_A0
FSEL_B1
FSEL_B0
FSEL_C1
FSEL_C0
0
0
1
1
0
1
0
1
÷4
0
0
1
1
0
1
0
1
÷4
0
0
1
1
0
1
0
1
÷6
÷6
÷4
÷8
÷8
÷6
÷12
÷10
÷8
TABLE 3B. FEEDBACK CONFIGURATION SELECT FUNCTION TABLE
Inputs
Outputs
FSEL_FB2
FSEL_FB1
FSEL_FB0
QFB
÷4
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
÷6
÷8
÷10
÷8
÷12
÷16
÷20
TABLE 3C. CONTROL INPUT SELECT FUNCTION TABLE
Control Pin
VCO_SEL
REF_SEL
CLK_SEL
PLL_SEL
nMR/OE
Logic 0
VCO/2
Logic 1
VCO
CLK0 or CLK1
CLK0
PECL
CLK1
BYPASS PLL
Enable PLL
Enable Outputs
Inverted QC2, QC3
Master Reset/Output Hi Z
Non-Inverted QC2, QC3
INV_CLK
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REV. B JULY 29, 2002
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PRELIMINARY
ICS87973I
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-12
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
fVCO
1:1 MODE
QA
QC
QSYNC
2:1 MODE
3:1 MODE
3:2 MODE
4:1 MODE
4:3 MODE
6:1 MODE
QA
QC
QSYNC
QC(÷2)
QA(÷4)
QSYNC
QC(÷2)
QA(÷8)
QSYNC
QC(÷2)
QA(÷8)
QSYNC
QA(÷6)
QC(÷8)
QSYNC
QA(÷12)
QC(÷2)
QSYNC
FIGURE 1 - TIMING DIAGRAMS
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REV. B JULY 29, 2002
6
PRELIMINARY
ICS87973I
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-12
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDDx
Inputs, VI
4.6V
-0.5V to VDD + 0.5V
-0.5V to VDDO + 0.5V
Outputs, VO
Package Thermal Impedance, θJA
Storage Temperature, TSTG
42.3°C/W (0 lfpm)
-65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended peri-
ods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VDD
VDDA
VDDO
IDD
Positive Supply Voltage
3.135
3.135
3.135
3.3
3.3
3.3
3.465
3.465
3.465
215
V
V
Analog Supply Voltage
Output Supply Voltage
Positive Supply Current
Analog Supply Current
V
All power pins
mA
mA
IDDA
20
NOTE: Special thermal handling may be required in some configurations.
TABLE 4B. DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
2
3.6
0.8
V
V
Input Low Voltage
IIN
Input Current
±120
µA
V
VOH
VOL
VPP
VCMR
Output High Voltage
IOH = -20mA
IOL = 20mA
LVPECL
2.4
Output Low Voltage
0.5
1
V
Peak-to-Peak Input Voltage; NOTE 1, 2
Common Mode Input Voltage; NOTE 1, 2
0.3
V
LVPECL
GND + 1.5
VDD
V
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2. For single ended applications, the maximum input voltage for PCLK and nPCLK is VDD + 0.3V.
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REV. B JULY 29, 2002
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PRELIMINARY
ICS87973I
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-12
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
fIN Input Frequency
CLK0, CLK1,
PCLK, nPCLK; NOTE 1
5
120
20
MHz
MHz
FRZ_CLK
NOTE 1: Input frequency depends on Feedback divide ratio to ensure the clock * Feedback Divide is in the VCO range of
200 - 480MHz.
TABLE 6. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
125
Units
MHz
MHz
MHz
÷2
÷4
÷6
÷8
120
fMAX
Output Frequency
80
60
MHz
ps
CLK0
TBD - 200
TBD - 200
TBD - 200
TBD
TBD
TBD
TBD + 200
TBD + 200
TBD + 200
550
Static Phase Offset;
NOTE 1
t(Ø)
CLK1
QFB ÷8
ps
PCLK, nPCLK
ps
tsk(o)
tjit(cc)
fVCO
tLOCK
tR
Output Skew; NOTE 2, 3
Cycle-to-Cycle Jitter; NOTE 4
PLL VCO Lock Range
PLL Lock Time
ps
±100
ps
200
480
10
MHz
mS
ps
Output Rise Time; NOTE 3
Output Fall Time; NOTE 3
Output Pulse Width
0.8V to 2V
0.8V to 2V
0.15
0.15
1.2
1.2
tF
ps
tPW
tCycle/2 - 750 tCycle/2 ± 750 tCycle/2+ 750
ps
tPZL, tPZH Output Enable Time; NOTE 3
tPLZ, tPHZ Output Disable TIme; NOTE 3
2
2
10
8
ns
ns
All parameters measured at 125MHz unless noted otherwise.
NOTE 1: Defined as the time difference between the input reference clock and the average feedback input signal
when the PLL is locked and the input reference frequency is stable.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDO/2.
NOTE 3: These parameters are guaranteed by characterization. Not tested in production.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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8
PRELIMINARY
ICS87973I
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-12
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
PARAMETER MEASUREMENT INFORMATION
1.65V±5%
SCOPE
VDD
VDDA
VDDO
,
,
Qx
LVCMOS
GND
-1.65V±5%
3.3V OUTPUT LOAD TEST CIRCUIT
VDD
nPCLK
PCLK
VPP
VCMR
Cross Points
GND
DIFFERENTIAL INPUT LEVEL
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PRELIMINARY
ICS87973I
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-12
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
VDDO
2
VDDO
2
VDDO
2
QAx, QBx, QCx,
QFB, QSYNC
➤
➤
tcycle n+1
tcycle n
➤
➤
tjit(cc) = tcycle n –tcycle n+1
1000 Cycles
Cycle-to-Cycle Jitter
VDDO
2
Qx
Qy
VDDO
2
tsk(o)
OUTPUT SKEW
2V
2V
0.8V
0.8V
Clock Inputs
and Outputs
tR
tF
INPUT AND OUTPUT RISE AND FALL TIME
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PRELIMINARY
ICS87973I
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-12
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
VDD
/2
CLK0, CLK1
EXT_FB
VDD
/2
➤
t(Ø)
➤
t(Ø) mean = Static Phase Offset
(where t(Ø) is any random sample, and t(Ø) mean is the average
of the sampled cycles measured on controlled edges)
Static Phase Offset
nPCLK
PCLK
VDD/2
EXT_FB
➤
t(Ø)
➤
t(Ø) mean = Static Phase Offset
(where t(Ø) is any random sample, and t(Ø) mean is the average
of the sampled cycles measured on controlled edges)
Static Phase Offset
VDDO
2
VDDO
2
VDDO
2
QAx, QBx, QCx,
QFB, QSYNC
tPW
tPERIOD
tPW
tPERIOD
odc =
tPW & tPERIOD
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PRELIMINARY
ICS87973I
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-12
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
APPLICATIONS INFORMATION
USING THE OUTPUT FREEZE CIRCUITRY
OVERVIEW
To enable low power states within a system, each output of FRZ_CLK signal. To place an output in the freeze state, a logic
ICS87973I (Except QC0 and QFB) can be individually frozen “0” must be written to the respective freeze enable bit in the shift
(stopped in the logic “0” state) using a simple serial interface register. To unfreeze an output, a logic “1” must be written to the
to a 12 bit shift register. A serial interface was chosen to elimi- respective freeze enable bit. Outputs will not become enabled/
nate the need for each output to have its own Output Enable disabled until all 12 data bits are shifted into the shift register.
pin, which would dramatically increase pin count and package When all 12 data bits are shifted in the register, the next rising
cost. Common sources in a system that can be used to drive edge of FRZ_CLK will enable or disable the outputs. If the bit
the ICS87973I serial interface are FPGA’s and ASICs.
that is following the 12th bit in the register is a logic “0”, it is used
for the start bit of the next cycle; otherwise, the device will wait
and won’t start the next cycle until it sees a logic “0” bit. Freez-
PROTOCOL
The Serial interface consists of two pins, FRZ_Data (Freeze ing and unfreezing of the output clock is synchronous (see the
Data) and FRZ_CLK (Freeze Clock). Each of the outputs which timing diagram below). When going into a frozen state, the out-
can be frozen has its own freeze enable bit in the 12 bit shift put clock will go LOW at the time it would normally go LOW, and
register. The sequence is started by supplying a logic “0” start the freeze logic will keep the output low until unfrozen. Likewise,
bit followed by 12NRZ freeze enable bits. The period of each when coming out of the frozen state, the output will go HIGH
FRZ_DATA bit equals the period of the FRZ_CLK signal. The only when it would normally go HIGH. This logic, therefore, pre-
FRZ_DATAserial transmission should be timed so the ICS87973I vents runt pulses when going into and out of the frozen state.
can sample each FRZ_DATA bit with the rising edge of the
FRZ_DATA
QA0 QA1 QA2 QA3 QB0 QB1 QB2 QB3 QB1 QB2 QB3 QSYNC
FRZ_CLK
FIGURE 2A - FREEZE DATA INPUT PROTOCOL
Qx FREEZE Internal
Qx Internal
Qx Out
FIGURE 2B - OUTPUT DISABLE TIMING
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PRELIMINARY
ICS87973I
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-12
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
58.0°C/W
42.3°C/W
47.1°C/W
36.4°C/W
42.0°C/W
34.0°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS87973I is: 8364
87973CYI
www.icst.com/products/hiperclocks.html
REV. B JULY 29, 2002
13
PRELIMINARY
ICS87973I
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-12
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
PACKAGE OUTLINE - Y SUFFIX
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BCC
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
52
--
--
1.60
0.15
1.45
0.38
0.33
A1
A2
b
0.05
1.35
0.22
0.22
--
1.40
0.32
b1
D
0.30
12.00 BASIC
10.00 BASIC
12.00 BASIC
10.00 BASIC
0.65 BASIC
--
D1
E
E1
e
ccc
ddd
0.45
--
0.10
0.13
--
Reference Document: JEDEC Publication 95, MS-026
87973CYI
www.icst.com/products/hiperclocks.html
REV. B JULY 29, 2002
14
PRELIMINARY
ICS87973I
Integrated
Circuit
Systems, Incꢀ
LOW SKEW, 1-TO-12
LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS87973CYI
Marking
Package
52 Lead LQFP
Count
160 per tray
500
Temperature
-40°C to 85°C
-40°C to 85°C
ICS87973CYI
ICS87973CYI
ICS87973CYIT
52 Lead LQFP on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without
additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices
or critical medical instruments.
87973CYI
www.icst.com/products/hiperclocks.html
REV. B JULY 29, 2002
15
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