ICS8545AGLF [IDT]
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| 型号： | ICS8545AGLF |
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INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 暂无描述 时钟驱动器 逻辑集成电路 光电二极管 |
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LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-LVDS
FANOUT BUFFER
ICS8545
Description
Features
The ICS8545 is a low skew, high performance 1-to-4
LVCMOS/LVTTL-to-LVDS Clock Fanout Buffer and a
member of the HiPerClockS™ family of High
• Four differential LVDS output pairs
S
IC
• Two LVCMOS/LVTTL clock inputs to support redundant
HiPerClockS™
or selectable frequency fanout applications
Performance Clock Solutions from IDT. Utilizing Low
Voltage Differential Signaling (LVDS) the ICS8545
provides a low power, low noise, solution for distributing clock
signals over controlled impedances of 100Ω. The ICS8545
accepts a LVCMOS/LVTTL input level and translates it to 3.3V
LVDS output levels.
• Maximum output frequency: 650MHz
• Translates LVCMOS/LVTTL input signals to LVDS levels
• Output skew: 40ps (maximum)
• Part-to-part skew: 500ps (maximum)
• Propagation delay: 3.6ns (maximum)
• Additive phase jitter, RMS: 0.13ps (typical)
• Full 3.3Vsupply mode
Guaranteed output and part-to-part skew characteristics make the
ICS8545 ideal for those applications demanding well defined
performance and repeatability.
• 0°C to 70°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Pin Assignment
Block Diagram
GND
CLK_EN
CLK_SEL
CLK1
1
2
20 Q0
Pullup
LK_EN
nD
LE
19
Q0
Q
3
4
18
17
VDD
Q1
Pulldown
Pulldown
nc
CLK2
nc
5
6
7
8
9
16 Q1
CLK1
CLK2
Q0
Q0
0
15
14
13
Q2
Q2
GND
1
OE
GND
VDD 10
Q1
Q1
12 Q3
11
Q3
Pulldown
K_SEL
Q2
Q2
ICS8545
Q3
Q3
20-Lead TSSOP
6.5mm x 4.4mm x 0.925mm
package body
Pullup
OE
G Package
Top View
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Table 1. Pin Descriptions
Number
Name
Type
Description
1, 9, 13
GND
Power
Input
Power supply ground.
Synchronizing clock enable. When HIGH, clock outputs follows clock input.
When LOW, Q outputs are forced low, Q outputs are forced high.
LVCMOS / LVTTL interface levels.
2
CLK_EN
Pullup
Clock select input. When HIGH, selects CLK2 input.
When LOW, selects CLK1 input. LVCMOS / LVTTL interface levels.
3
4
CLK_SEL
CLK1
Input
Input
Pulldown
Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels.
5, 7
6
nc
Unused
Input
No connect.
CLK2
Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels.
Output enable. Controls enabling and disabling of outputs Q0/Q0 through
Q3/Q3. LVCMOS/LVTTL interface levels.
8
OE
Input
Pullup
10, 18
11, 12
14, 15
16, 17
19, 20
VDD
Power
Output
Output
Output
Output
Positive supply pins.
Q3, Q3
Q2, Q2
Q1, Q1
Q0, Q0
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
4
RPULLUP
RPULLDOWN
51
51
kΩ
kΩ
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Function Tables
Table 3A. Control Input Function Table
Inputs
Outputs
OE
0
CLK_EN
CLK_SEL
Selected Source
Q0:Q3
Hi-Z
Q0:Q3
Hi-Z
X
0
0
1
1
X
0
1
0
1
1
CLK1
CLK2
CLK1
CLK2
Low
High
1
Low
High
1
Active
Active
Active
Active
1
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLK1 and CLK2 inputs as described in Table 3B.
Enabled
Disabled
CLK1, CLK2
CLK_EN
Q0:Q3
Q0:Q3
Figure 1. CLK_EN Timing Diagram
Table 3B. Clock Input Function Table
Inputs
Outputs
CLK1 or CLK2
Q0:Q3
LOW
Q0:Q3
HIGH
LOW
0
1
HIGH
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Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
Inputs, VI
4.6V
-0.5V to VDD + 0.5V
Outputs, IO
Continuos Current
Surge Current
10mA
15mA
Package Thermal Impedance, θJA
73.2°C/W (0 lfpm)
-65°C to 150°C
Storage Temperature, TSTG
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = 3.3V 5%, TA = 0°C to 70°C
Symbol Parameter
VDD Positive Supply Voltage
IDD Power Supply Current
Test Conditions
Minimum
Typical
Maximum
3.465
50
Units
V
3.135
3.3
mA
Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V 5%, TA = 0°C to 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
VDD + 0.3
1.3
Units
VIH
Input High Voltage
2
V
V
V
CLK1, CLK2
-0.3
-0.3
Input Low
Voltage
VIL
OE, CLK_EN, CLK_SEL
0.8
CLK1, CLK2,
CLK_SEL
VDD = VIN = 3.465V
VDD = VIN = 3.465V
150
5
µA
µA
Input
High Current
IIH
OE, CLK_EN
CLK1, CLK2,
CLK_SEL
VDD = 3.465V, VIN = 0V
VDD = 3.465V, VIN = 0V
-5
µA
µA
Input
Low Current
IIL
OE, CLK_EN
-150
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Table 4C. LVDS DC Characteristics, VDD = 3.3V 5%, TA = 0°C to 70°C
Symbol
VOD
Parameter
Test Conditions
Minimum
Typical
Maximum
360
40
Units
mV
mV
V
Differential Output Voltage
VOD Magnitude Change
Offset Voltage
200
280
∆VOD
VOS
1.125
1.25
5
1.375
25
∆VOS
IOz
VOS Magnitude Change
High Impedance Leakage
Power Off Leakage
mV
µA
µA
mA
mA
V
-10
-20
1
+10
+20
-5
IOFF
IOSD
IOS
1
Differential Output Short Circuit Current
Output Short Circuit Current
Output Voltage High
-3.5
-3.5
1.34
1.06
-5
VOH
1.6
VOL
Output Voltage Low
0.9
V
AC Electrical Characteristics
Table 5. AC Characteristics, VDD = 3.3V 5%, TA = 0°C to 70°C
Parameter Symbol Test Conditions
fMAX Output Frequency
tPD
Minimum Typical Maximum
Units
MHz
ns
650
Propagation Delay; NOTE 1
IJ 650MHz
1.4
3.6
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
156.25MHz, Integration Range:
12kHz – 20MHz
tjit
0.13
ps
tsk(o)
tsk(pp)
tR / tF
odc
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Output Rise/Fall Time
Output Duty Cycle
40
500
600
55
ps
ps
ps
%
20% to 80% @ 50MHz
200
45
400
50
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from VDD/2 of the input to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDD/2 of the input to the differential output crossing point.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions.
Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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Additive Phase Jitter
The spectral purity in a band at a specific offset from the
to the power in the fundamental. When the required offset is
specified, the phase noise is called a dBc value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
fundamental compared to the power of the fundamental is called
the dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz band
Offset Frequency (Hz)
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The device
meets the noise floor of what is shown, but can actually be lower.
The phase noise is dependant on the input source and
measurement equipment.
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Parameter Measurement Information
V
DD
SCOPE
Qx
Q0:Q3
Q0:Q3
V
DD
3.3V 5%
POWER SUPPLY
VOD
Cross Points
+
Float GND –
LVDS
nQx
VOS
GND
-
-
3.3V LVDS Output Load AC Test Circuit
Differential Output Level
Part 1
Qx
Qx
Qx
Qx
Part 1
Qy
Qy
Qy
Qy
tsk(o)
tsk(pp)
Part-to-Part Skew
Output Skew
Q0:Q3
Q0:Q3
CLK1,
CLK2
tPW
tPERIOD
Q0:Q3
tPW
odc =
x 100%
Q0:Q3
tPERIOD
tpLH
Output Duty Cycle/Pulse Width/Period
Propagation Delay
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Parameter Measurement Information, continued
80%
tF
80%
tR
VOD
LVDS
Clock
Outputs
20%
20%
VDD
IOFF
Output Rise/Fall Time
Power Off Leakage Setup
VDD
VDD
➤
out
out
out
out
➤
DC Input
LVDS
LVDS
V
OD/∆ VOD
DC Input
100
➤
VOS/∆ VOS
➤
Offset Voltage Setup
Differential Output Voltage Setup
out
out
VDD
IOZ
out
3.3V 5% POWER SUPPLY
Float GND
DC Inpu
t
LVDS
_
+
IOSD
DC Input
LVDS
IOZ
out
High Impedance Leakage Current Setup
Differential Output Short Circuit Setup
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Parameter Measurement Information, continued
VDD
out
IOS
DC Input
LVDS
IOSB
out
Output Short Circuit Current Setup
Application Information
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
CLK Inputs
LVDS Outputs
For applications not requiring the use of a clock input, it can be left
floating. Though not required, but for additional protection, a 1kΩ
resistor can be tied from the CLK input to ground.
All unused LVDS output pairs can be either left floating or
terminated with 100Ω across. If they are left floating, there should
be no trace attached.
LVCMOS Control Pins
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
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3.3V LVDS Driver Termination
A general LVDS interface is shown in Figure 2. In a 100Ω
differential transmission line environment, LVDS drivers require a
matched load termination of 100Ω across near the receiver input.
For a multiple LVDS outputs buffer, if only partial outputs are used,
it is recommended to terminate the unused outputs.
3.3V
50Ω
3.3V
LVDS Driver
+
–
R1
100Ω
50Ω
100Ω Differential Transmission Line
Figure 2. Typical LVDS Driver Termination
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Power Considerations
This section provides information on power dissipation and junction temperature for the ICS8545.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8545 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 50mA = 173.25mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.
The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate
air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.173W * 66.6°C/W = 81.5°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type
of board (single layer or multi-layer).
Table 6. Thermal Resitance θJA for 20 Lead TSSOP, Forced Convection
θJA by Velocity
Linear Feet per Minute
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
98.0°C/W
66.6°C/W
88.0°C/W
63.5°C/W
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LOW SKEW, 1-TO-4, LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER
Reliability Information
Table 7. θJA vs. Air Flow Table for a 20 Lead TSSOP
θJA by Velocity
Linear Feet per Minute
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
114.5°C/W
73.2°C/W
98.0°C/W
66.6°C/W
88.0°C/W
63.5°C/W
Transistor Count
The transistor count for ICS8545 is: 644
Package Outline and Package Dimension
Package Outline - G Suffix for 20 Lead TSSOP
Table 8. Package Dimensions
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
A
20
1.20
0.15
1.05
0.30
0.20
6.60
A1
A2
b
0.05
0.80
0.19
0.09
6.40
c
D
E
6.40 Basic
E1
e
4.30
4.50
0.65 Basic
L
0.45
0°
0.75
8°
α
aaa
0.10
Reference Document: JEDEC Publication 95, MO-153
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Ordering Information
Table 9. Ordering Information
Part/Order Number
8545BG
8545BGT
8545BGLF
8545BGLFT
Marking
Package
20 Lead TSSOP
20 Lead TSSOP
Shipping Packaging
Tube
2500 Tape & Reel
Tube
Temperature
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
ICS8545BG
ICS8545BG
ICS8545BGLF
ICS8545BGLF
“Lead-Free” 20 Lead TSSOP
“Lead-Free” 20 Lead TSSOP
2500 Tape & Reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for
the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements
are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any
IDT product for use in life support devices or critical medical instruments.
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LOW SKEW, 1-TO-4, LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER
Revision History Sheet
Rev
Table
Page
Description of Change
Date
T4C
4
In the VOL row, 1.06 has been moved to the Typical column from the maximum
column.
A
9/21/01
A
A
3
3
1
Revised Figure 1, CLK_EN Timing Diagram.
Revised Figure 1, CLK_EN Timing Diagram.
10/17/01
11/2/01
Features - deleted bullet ""Designed to meet or exceed the requirements of
ANSI TIA/EIA-644"".
B
9/19/02
4C
T2
4
LVDS Table - changed VOD typical value from 350mV to 280mV.
Updated LVDS diagrams.
8-9
2
4
8
Pin Characteristics - changed CIN 4pF max. to 4pF typical.
Absolute Maximum Ratings - changed Output Rating.
Added LVDS Driver Termination section.
C
C
D
1/5/04
1/17/06
5/31/07
Updated format throughout data sheet.
1
8
Features Section - added Lead-Free bullet.
Added Recommendations for Unused Input and Output Pins.
Ordering Information Table - added lead-free part number, marking and note.
T8
T5
11
1
5
Features Section - added Additive Phase Jitter bullet.
AC Characteristics Table - added Additive Phase Jitter spec.
Added Additive Phase Jitter Plot.
6
11
Added Power Considerations section.
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LOW SKEW, 1-TO-4, LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER
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