ICS844008AKI-46LF [IDT]
Clock Generator, PQCC32;
| 型号： | ICS844008AKI-46LF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, PQCC32 |
| 文件： | 总15页 (文件大小：305K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FEMTOCLOCKS™ CRYSTAL-TO-LVDS
CLOCK GENERATOR
ICS844008I-46
GENERAL DESCRIPTION
FEATURES
• Eight differential LVDS outputs
The ICS844008I-46 is a 10Gb Ethernet Clock
ICS
HiPerClockS™
Generator and a member of the HiPerClocks™ family
of high performance devices from IDT. The
ICS844008I-46 can synthesize 156.25MHz or
100MHz with a 25MHz crystal. It has a total of 8
• Crystal oscillator interface designed for 18pF parallel resonant
crystals
• Supports the following output frequencies:
156.25MHz or 100MHz
LVDS outputs. The ICS844008I-46 has excellent phase jitter
performance and is packaged in a 32 Lead VFQFN package,
making it ideal for use in systems with limited board space.
• VCO frequency: 625MHz or 600MHz
• RMS phase jitter @ 156.25MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.45ps (typical)
• Full 2.5V supply mode
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) packages
FREQUENCY SELECT FUNCTION TABLE
Input
XTAL Frequency
Output Frequency
(MHz)
FREQ_SEL
FB Divider
Output Divider
VCO (MHz)
(MHz)
25
0
÷25
÷4
625
156.25 (default)
25
1
÷24
÷6
600
100
PIN ASSIGNMENT
BLOCK DIAGRAM
Pullup
OE
25MHz
8
8
Q0:Q7
XTAL_IN
OSC
Phase
Detector
VCO
625MHz or
600MHz
÷4
or
nQ0:nQ7
÷6
32 31 30 29 28 27 26 25
XTAL_OUT
Q0
nQ0
GND
Q1
1
2
3
4
5
6
7
8
24
23
22
21
20
nc
OE
FB = ÷25 or ÷24
ICS844008I-46
32-Lead VFQFN
5mm x 5mm x 0.925mm
package body
GND
nQ7
Q7
nQ1
VDDO
Q2
Pulldown
FREQ_SEL
VDDO
nQ6
19
18
17
K Package
Top View
nQ2
Q6
9
10 11 12 13 14 15 16
IDT™ / ICS™ LVDS CLOCK GENERATOR
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FEMTOCLOCKS™ CRYSTAL-TO-LVDS CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
1, 2
Name
Q0, nQ0
GND
Type
Description
Output
Power
Ouput
Power
Output
Output
Output
Output
Output
Output
Differential output pair. LVDS interface levels.
Power supply ground.
3, 11, 22, 32
4, 5
Q1, nQ1
VDDO
Differential output pair. LVDS interface levels.
Output supply pins.
6, 14, 19
7, 8
Q2, nQ2
Q3, nQ3
Q4, nQ4
Q5, nQ5
Q6, nQ6
Q7, nQ7
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
9, 10
12, 13
15, 16
17, 18
20, 21
Output enable pin. When LOW, outputs are disabled. When HIGH.
outputs are enabled. LVCMOS/LVTTL interface levels. See Table 3.
23
OE
Input
Pullup
24, 28, 29
nc
VDDA
Unused
Power
Input
No connect.
25
26
27
Analog supply pin.
FREQ_SEL
VDD
Pulldown Frequency select pin. LVCMOS/LVTTL interface levels.
Core supply pin.
Power
30,
31
XTAL_IN,
XTAL_OUT
Parallel resonant crystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
Input
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
CIN
Input Capacitance
4
pF
kΩ
kΩ
RPULLDOWN Input Pulldown Resistor
RPULLUP Input Pullup Resistor
51
51
TABLE 3. OE FUNCTION TABLE
Inputs
OE
Outputs
Q[0:7]/nQ[0:7]
1
0
Enabled (default)
Hi-Z
IDT™ / ICS™ LVDS CLOCK GENERATOR
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FEMTOCLOCKS™ CRYSTAL-TO-LVDS CLOCK GENERATOR
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Inputs, V
-0.5V to VDD + 0.5V
I
Outputs, IO (LVDS)
Continuous Current
Surge Current
10mA
15mA
Package Thermal Impedance, θ
Storage Temperature, T
37°C/W (0 mps)
-65°C to 150°C
JA
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
2.375
Typical
2.5
Maximum Units
VDD
VDDA
VDDO
IDD
Core Supply Voltage
2.625
VDD
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
VDD – 0.25
2.375
2.5
2.5
2.625
60
V
mA
mA
mA
IDDA
IDDO
25
140
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDO = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
2
VDD + 0.3
V
Input Low Voltage
-0.3
0.8
5
V
OE
V
DD = VIN = 2.625
DD = VIN = 2.625
µA
µA
µA
µA
IIH
Input High Current
FREQ_SEL
OE
V
150
V
DD = 2.625V, VIN = 0V
-150
-5
IIL
Input Low Current
FREQ_SEL
VDD = 2.625V, VIN = 0V
TABLE 4C. LVDS DC CHARACTERISTICS, VDD = VDDO = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VOD
Differential Output Voltage
247
340
454
50
mV
mV
V
Δ VOD
VOS
VOD Magnitude Change
Offset Voltage
1.10
1.25
1.375
50
Δ VOS
VOS Magnitude Change
mV
IDT™ / ICS™ LVDS CLOCK GENERATOR
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FEMTOCLOCKS™ CRYSTAL-TO-LVDS CLOCK GENERATOR
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Fundamental
25
Typical Maximum Units
Mode of Oscillation
Frequency
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
50
7
pF
300
µW
NOTE: Characterized using an 18pF parallel resonant crystal.
TABLE 6. AC CHARACTERISTICS, VDD = VDDO = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
FREQ_SEL = 0
FREQ_SEL = 1
Minimum Typical Maximum Units
156.25
100
MHz
MHz
ps
fOUT
Output Frequency
tsk(o)
tjit(cc)
Output Skew; NOTE 1, 2
Cycle-to-Cycle Jitter
75
20
ps
156.25MHz (1.875MHz - 20MHz)
100MHz (1.875MHz - 20MHz)
20ꢀ to 80ꢀ
0.45
0.52
ps
RMS Phase Jitter (Random);
NOTE 3
tjit(Ø)
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
300
48
700
52
ps
ꢀ
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at the differential cross points.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
IDT™ / ICS™ LVDS CLOCK GENERATOR
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TYPICAL PHASE NOISE AT 156.25MHZ
Ethernet Filter
156.25MHz
RMS Phase Jitter (Random)
1.875Mhz to 20MHz = 0.45ps (typical)
Raw Phase Noise Data
Phase Noise Result by adding
Ethernet Filter to raw data
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE AT 100MHZ
10Gb Ethernet Filter
100MHz
RMS Phase Jitter (Random)
1.875Mhz to 20MHz = 0.52ps (typical)
Raw Phase Noise Data
Phase Noise Result by adding a
10Gb Ethernet Filter to raw data
OFFSET FREQUENCY (HZ)
IDT™ / ICS™ LVDS CLOCK GENERATOR
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PARAMETER MEASUREMENT INFORMATION
Phase Noise Plot
SCOPE
Qx
VDD,
2.5V 5ꢀ
POWER SUPPLY
VDDO
VDDA
Phase Noise Mask
+
Float GND –
LVDS
nQx
Offset Frequency
f1
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
2.5V LVDS OUTPUT LOAD AC TEST CIRCUIT
RMS PHASE JITTER
nQ0:nQ7
Q0:nQ7
nQx
Qx
➤
➤
tcycle n
tcycle n+1
➤
➤
nQy
Qy
tjit(cc) = tcycle n – tcycle n+1
1000 Cycles
tsk(o)
CYCLE-TO-CYCLE JITTER
OUTPUT SKEW
nQ0:nQ7
nQ0:nQ7
Q0:Q7
80ꢀ
tF
80ꢀ
VOD
tPW
20ꢀ
20ꢀ
tPERIOD
Q0:Q7
tR
tPW
odc =
x 100ꢀ
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT RISE/FALL TIME
IDT™ / ICS™ LVDS CLOCK GENERATOR
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FEMTOCLOCKS™ CRYSTAL-TO-LVDS CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION, CONTINUED
VDD
VDD
out
out
➤
out
out
➤
DC Input
LVDS
LVDS
DC Input
100
V
OD/Δ VOD
➤
VOS/Δ VOS
➤
OFFSET VOLTAGE SETUP
DIFFERENTIAL OUTPUT VOLTAGE SETUP
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter perfor-
mance, power supply isolation is required. The ICS844008I-46
provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VDD, VDDA, and VDDO
should be individually connected to the power supply
plane through vias, and 0.01µF bypass capacitors should be used
for each pin. Figure 1 illustrates this for a generic VCC pin and
also shows that VDDA requires that an additional 10Ω resistor
along with a 10µF bypass capacitor be connected to the VDDA
pin.
2.5V
VDD
.01μF
.01μF
10Ω
VDDA
10μF
FIGURE 1. POWER SUPPLY FILTERING
IDT™ / ICS™ LVDS CLOCK GENERATOR
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RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
LVDS OUTPUTS
LVCMOS CONTROL PINS
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
All unused LVDS output pairs can be either left floating or
terminated with 100Ω across. If they are left floating, there should
be no trace attached.
CRYSTAL INPUT INTERFACE
The ICS844008I-46 has been characterized with an 18pF
parallel resonant crystals. The capacitor values shown in
Figure 2 below were determined using a 25MHz parallel
resonant crystal and were chosen to minimize the ppm error.
XTAL_IN
C1
27p
X1
18pF Parallel Crystal
XTAL_OUT
C2
27p
FIGURE 2. CRYSTAL INPUt INTERFACE
LVCMOS TO XTAL INTERFACE
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance.In addition, matched termination
at the crystal input will attenuate the signal in half. This can be
done in one of two ways. First, R1 and R2 in parallel should equal
the transmission line impedance. For most 50Ω applications, R1
and R2 can be 100Ω.This can also be accomplished by removing
R1 and making R2 50Ω.
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 3. The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs, it is
recommended that the amplitude be reduced from full swing to
half swing in order to prevent signal interference with the power
rail and to reduce noise.This configuration requires that the output
VDD
VDD
R1
.1uf
Ro
Rs
Zo = 50
XTAL_I N
R2
Zo = Ro + Rs
XTAL_OUT
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
IDT™ / ICS™ LVDS CLOCK GENERATOR
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FEMTOCLOCKS™ CRYSTAL-TO-LVDS CLOCK GENERATOR
VFQFN EPADTHERMAL RELEASE PATH
In order to maximize both the removal of heat from the package
and the electrical performance, a land pattern must be
incorporated on the Printed Circuit Board (PCB) within the footprint
of the package corresponding to the exposed metal pad or
exposed heat slug on the package, as shown in Figure 4. The
solderable area on the PCB, as defined by the solder mask, should
be at least the same size/shape as the exposed pad/slug area on
the package to maximize the thermal/electrical performance.
Sufficient clearance should be designed on the PCB between the
outer edges of the land pattern and the inner edges of pad pattern
for the leads to avoid any shorts.
are application specific and dependent upon the package power
dissipation as well as electrical conductivity requirements. Thus,
thermal and electrical analysis and/or testing are recommended
to determine the minimum number needed. Maximum thermal
and electrical performance is achieved when an array of vias is
incorporated in the land pattern. It is recommended to use as
many vias connected to ground as possible. It is also
recommended that the via diameter should be 12 to 13mils (0.30
to 0.33mm) with 1oz copper via barrel plating. This is desirable to
avoid any solder wicking inside the via during the soldering process
which may result in voids in solder between the exposed pad/
slug and the thermal land. Precautions should be taken to
eliminate any solder voids between the exposed heat slug and
the land pattern. Note: These recommendations are to be used
as a guideline only. For further information, refer to the Application
Note on the Surface Mount Assembly of Amkor’s Thermally/
Electrically Enhance Leadfame Base Package, Amkor Technology.
While the land pattern on the PCB provides a means of heat
transfer and electrical grounding from the package to the board
through a solder joint, thermal vias are necessary to effectively
conduct from the surface of the PCB to the ground plane(s). The
land pattern must be connected to ground through these vias.
The vias act as “heat pipes”. The number of vias (i.e.“heat pipes”)
SOLDER
SOLDER
PIN
PIN
EXPOSED HEAT SLUG
PIN PAD
GROUND PLANE
LAND PATTERN
(GROUND PAD)
PIN PAD
THERMAL VIA
FIGURE 4. P.C.ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH –SIDE VIEW (DRAWING NOT TO SCALE)
2.5V LVDS DRIVER TERMINATION
Figure 5 shows a typical termination for LVDS driver in
characteristic impedance of 100Ω differential (50Ω single)
transmission line environment.
2.5V
2.5V
LVDS_Driv er
+
-
R1
100
100Ω DifferentialTransmission Line
FIGURE 5. TYPICAL LVDS DRIVER TERMINATION
IDT™ / ICS™ LVDS CLOCK GENERATOR
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SCHEMATIC LAYOUT
Figure 6 shows an example of ICS844008I-46 application
schematic. In this example, the device is operated at
for frequency accuracy. For different board layout, the C1
and C2 may be slightly adjusted for optimizing frequency
accuracy. Two examples of LVDS for receiver without built-
in termination are shown in this schematic.
V = V = 3.3V. The 18pF parallel resonant 25MHz crystal
DDO
isDDused. The C1 = 27pF and C2 = 27pF are recommended
VDD
C5
0.1uF
VDD
VDDA
X1
25MHz
18pF
C3
0.01u
R1
10
GND
C2
27pF
C4
10uF
FREQ_SEL
Zo = 50 Ohm
Zo = 50 Ohm
Q7
C1
27pF
+
-
R2
100
U1
nQ7
Q0
1
24
Q0
nc
23
nQ0
OE
2
3
4
5
6
7
8
nQ0
GND
Q1
nQ1
VDDO
Q2
OE
22
VDDO
GND
21
Q1
nQ1
nQ7
Q7
VDDO
nQ7
20
Q7
19
VDDO
18
Q2
nQ2
nQ6
Q6
nQ6
17
C6
0.1uF
nQ2
Q6
C7
0.1uF
VDD= VDDO=3.3V
ICS844008I-46
Zo = 50 Ohm
Q6
VDDO
Logic Control Input Examples
R3
50
C8
0.1uF
Set Logic
Input to
'1'
Set Logic
Input to
'0'
+
-
VDD
VDD
C9
0.1uF
R4
50
RU1
1K
RU2
Not Install
Zo = 50 Ohm
nQ6
To Logic
Input
To Logic
Input
pins
pins
RD1
RD2
1K
Alternate
LVDS
Termination
Not Install
FIGURE 6. ICS844008I-46 SCHEMATIC LAYOUT
IDT™ / ICS™ LVDS CLOCK GENERATOR
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FEMTOCLOCKS™ CRYSTAL-TO-LVDS CLOCK GENERATOR
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS844008I-46.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS844008I-46 is the sum of the core power plus the analog power plus the power dissipated in
the load(s). The following is the power dissipation for V = 2.5V + 5ꢀ = 2.625V, which gives worst case results.
DD
•
Power (core) = V
* (I
+ I
+ I
) = 2.625V * (60mA + 25mA + 140mA) = 590.625mW
DDO_MAX
MAX
DD_MAX
DD_MAX
DDA_MAX
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
TM
device. The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θ
= Junction-to-Ambient Thermal Resistance
JA
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ must be used. Assuming no air
JA
flow and a multi-layer board, the appropriate value is 37°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.591W * 37°C/W = 106.8°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and
the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE θ FOR 32-LEAD VFQFN, FORCED CONVECTION
JA
θ vs. Air Flow (Meters per Second)
JA
0
1
2.5
29.0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
37.0°C/W
32.4°C/W
IDT™ / ICS™ LVDS CLOCK GENERATOR
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RELIABILITY INFORMATION
TABLE 8. θ VS. AIR FLOW TABLE FOR 32 LEAD VFQFN
JA
θ vs. Air Flow (Meters per Second)
JA
0
1
2.5
29.0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
37.0°C/W
32.4°C/W
TRANSISTOR COUNT
The transistor count for ICS844008I-46 is: 2993
IDT™ / ICS™ LVDS CLOCK GENERATOR
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PACKAGE OUTLINE - K SUFFIX FOR 32 LEAD VFQFN
NOTE: The following package mechanical drawing is a generic
drawing that applies to any pin count VFQFN package.This draw-
ing is not intended to convey the actual pin count or pin layout of
this device.The pin count and pinout are shown on the front page.
The package dimensions are in Table 9 below.
TABLE 9. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS (VHHD -2/ -4)
SYMBOL
Minimum
Maximum
N
A
32
0.80
0
1.0
A1
A3
b
0.05
0.25 Reference
0.18
0.30
e
0.50 BASIC
ND
8
8
NE
D, E
D2, E2
L
5.0 BASIC
3.0
3.3
0.30
0.50
Reference Document: JEDEC Publication 95, MO-220
IDT™ / ICS™ LVDS CLOCK GENERATOR
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TABLE 10. ORDERING INFORMATION
Part/Order Number
844008AKI-46LF
844008AKI-46LFT
Marking
Package
Shipping Packaging
Tray
Temperature
-40°C to 85°C
-40°C to 85°C
ICS008AI46L
ICS008AI46L
32 Lead "Lead-Free" VFQFN
32 Lead "Lead-Free" VFQFN
1000 Tape & Reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and
industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT
reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT™ / ICS™ LVDS CLOCK GENERATOR
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FEMTOCLOCKS™ CRYSTAL-TO-LVDS CLOCK GENERATOR
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
For Tech Support
Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
Fax: 408-284-2775
netcom@idt.com
+480-763-2056
www.IDT.com/go/contactIDT
United States
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
© 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be
trademarks or registered trademarks used to identify products or services of their respective owners.
Printed in USA
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IDT
ICS844008BYI-15LFT
Clock Generator, 125MHz, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, MS-026BBA, LQFP-32
IDT
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